Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/init.h>
37#include <linux/delay.h>
38#include <linux/sched.h>
39#include <linux/pci.h>
40#include <linux/mc146818rtc.h>
41#include <linux/compiler.h>
42#include <linux/acpi.h>
43#include <linux/export.h>
44#include <linux/syscore_ops.h>
45#include <linux/freezer.h>
46#include <linux/kthread.h>
47#include <linux/jiffies.h> /* time_after() */
48#include <linux/slab.h>
49#include <linux/bootmem.h>
50
51#include <asm/irqdomain.h>
52#include <asm/io.h>
53#include <asm/smp.h>
54#include <asm/cpu.h>
55#include <asm/desc.h>
56#include <asm/proto.h>
57#include <asm/acpi.h>
58#include <asm/dma.h>
59#include <asm/timer.h>
60#include <asm/i8259.h>
61#include <asm/setup.h>
62#include <asm/irq_remapping.h>
63#include <asm/hw_irq.h>
64
65#include <asm/apic.h>
66
67#define for_each_ioapic(idx) \
68 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
69#define for_each_ioapic_reverse(idx) \
70 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
71#define for_each_pin(idx, pin) \
72 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73#define for_each_ioapic_pin(idx, pin) \
74 for_each_ioapic((idx)) \
75 for_each_pin((idx), (pin))
76#define for_each_irq_pin(entry, head) \
77 list_for_each_entry(entry, &head, list)
78
79static DEFINE_RAW_SPINLOCK(ioapic_lock);
80static DEFINE_MUTEX(ioapic_mutex);
81static unsigned int ioapic_dynirq_base;
82static int ioapic_initialized;
83
84struct irq_pin_list {
85 struct list_head list;
86 int apic, pin;
87};
88
89struct mp_chip_data {
90 struct list_head irq_2_pin;
91 struct IO_APIC_route_entry entry;
92 int trigger;
93 int polarity;
94 u32 count;
95 bool isa_irq;
96};
97
98struct mp_ioapic_gsi {
99 u32 gsi_base;
100 u32 gsi_end;
101};
102
103static struct ioapic {
104 /*
105 * # of IRQ routing registers
106 */
107 int nr_registers;
108 /*
109 * Saved state during suspend/resume, or while enabling intr-remap.
110 */
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119} ioapics[MAX_IO_APICS];
120
121#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
122
123int mpc_ioapic_id(int ioapic_idx)
124{
125 return ioapics[ioapic_idx].mp_config.apicid;
126}
127
128unsigned int mpc_ioapic_addr(int ioapic_idx)
129{
130 return ioapics[ioapic_idx].mp_config.apicaddr;
131}
132
133static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134{
135 return &ioapics[ioapic_idx].gsi_config;
136}
137
138static inline int mp_ioapic_pin_count(int ioapic)
139{
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143}
144
145static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146{
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148}
149
150static inline bool mp_is_legacy_irq(int irq)
151{
152 return irq >= 0 && irq < nr_legacy_irqs();
153}
154
155/*
156 * Initialize all legacy IRQs and all pins on the first IOAPIC
157 * if we have legacy interrupt controller. Kernel boot option "pirq="
158 * may rely on non-legacy pins on the first IOAPIC.
159 */
160static inline int mp_init_irq_at_boot(int ioapic, int irq)
161{
162 if (!nr_legacy_irqs())
163 return 0;
164
165 return ioapic == 0 || mp_is_legacy_irq(irq);
166}
167
168static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
169{
170 return ioapics[ioapic].irqdomain;
171}
172
173int nr_ioapics;
174
175/* The one past the highest gsi number used */
176u32 gsi_top;
177
178/* MP IRQ source entries */
179struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
180
181/* # of MP IRQ source entries */
182int mp_irq_entries;
183
184#ifdef CONFIG_EISA
185int mp_bus_id_to_type[MAX_MP_BUSSES];
186#endif
187
188DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
189
190int skip_ioapic_setup;
191
192/**
193 * disable_ioapic_support() - disables ioapic support at runtime
194 */
195void disable_ioapic_support(void)
196{
197#ifdef CONFIG_PCI
198 noioapicquirk = 1;
199 noioapicreroute = -1;
200#endif
201 skip_ioapic_setup = 1;
202}
203
204static int __init parse_noapic(char *str)
205{
206 /* disable IO-APIC */
207 disable_ioapic_support();
208 return 0;
209}
210early_param("noapic", parse_noapic);
211
212/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213void mp_save_irq(struct mpc_intsrc *m)
214{
215 int i;
216
217 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 m->srcbusirq, m->dstapic, m->dstirq);
221
222 for (i = 0; i < mp_irq_entries; i++) {
223 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
224 return;
225 }
226
227 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 panic("Max # of irq sources exceeded!!\n");
230}
231
232static void alloc_ioapic_saved_registers(int idx)
233{
234 size_t size;
235
236 if (ioapics[idx].saved_registers)
237 return;
238
239 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
240 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
241 if (!ioapics[idx].saved_registers)
242 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
243}
244
245static void free_ioapic_saved_registers(int idx)
246{
247 kfree(ioapics[idx].saved_registers);
248 ioapics[idx].saved_registers = NULL;
249}
250
251int __init arch_early_ioapic_init(void)
252{
253 int i;
254
255 if (!nr_legacy_irqs())
256 io_apic_irqs = ~0UL;
257
258 for_each_ioapic(i)
259 alloc_ioapic_saved_registers(i);
260
261 return 0;
262}
263
264struct io_apic {
265 unsigned int index;
266 unsigned int unused[3];
267 unsigned int data;
268 unsigned int unused2[11];
269 unsigned int eoi;
270};
271
272static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
273{
274 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
275 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
276}
277
278static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
279{
280 struct io_apic __iomem *io_apic = io_apic_base(apic);
281 writel(vector, &io_apic->eoi);
282}
283
284unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
285{
286 struct io_apic __iomem *io_apic = io_apic_base(apic);
287 writel(reg, &io_apic->index);
288 return readl(&io_apic->data);
289}
290
291static void io_apic_write(unsigned int apic, unsigned int reg,
292 unsigned int value)
293{
294 struct io_apic __iomem *io_apic = io_apic_base(apic);
295
296 writel(reg, &io_apic->index);
297 writel(value, &io_apic->data);
298}
299
300union entry_union {
301 struct { u32 w1, w2; };
302 struct IO_APIC_route_entry entry;
303};
304
305static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
306{
307 union entry_union eu;
308
309 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
310 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
311
312 return eu.entry;
313}
314
315static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
316{
317 union entry_union eu;
318 unsigned long flags;
319
320 raw_spin_lock_irqsave(&ioapic_lock, flags);
321 eu.entry = __ioapic_read_entry(apic, pin);
322 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
323
324 return eu.entry;
325}
326
327/*
328 * When we write a new IO APIC routing entry, we need to write the high
329 * word first! If the mask bit in the low word is clear, we will enable
330 * the interrupt, and we need to make sure the entry is fully populated
331 * before that happens.
332 */
333static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
334{
335 union entry_union eu = {{0, 0}};
336
337 eu.entry = e;
338 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
339 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
340}
341
342static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
343{
344 unsigned long flags;
345
346 raw_spin_lock_irqsave(&ioapic_lock, flags);
347 __ioapic_write_entry(apic, pin, e);
348 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
349}
350
351/*
352 * When we mask an IO APIC routing entry, we need to write the low
353 * word first, in order to set the mask bit before we change the
354 * high bits!
355 */
356static void ioapic_mask_entry(int apic, int pin)
357{
358 unsigned long flags;
359 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
360
361 raw_spin_lock_irqsave(&ioapic_lock, flags);
362 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
363 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
364 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
365}
366
367/*
368 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
369 * shared ISA-space IRQs, so we have to support them. We are super
370 * fast in the common case, and fast for shared ISA-space IRQs.
371 */
372static int __add_pin_to_irq_node(struct mp_chip_data *data,
373 int node, int apic, int pin)
374{
375 struct irq_pin_list *entry;
376
377 /* don't allow duplicates */
378 for_each_irq_pin(entry, data->irq_2_pin)
379 if (entry->apic == apic && entry->pin == pin)
380 return 0;
381
382 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
383 if (!entry) {
384 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
385 node, apic, pin);
386 return -ENOMEM;
387 }
388 entry->apic = apic;
389 entry->pin = pin;
390 list_add_tail(&entry->list, &data->irq_2_pin);
391
392 return 0;
393}
394
395static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
396{
397 struct irq_pin_list *tmp, *entry;
398
399 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
400 if (entry->apic == apic && entry->pin == pin) {
401 list_del(&entry->list);
402 kfree(entry);
403 return;
404 }
405}
406
407static void add_pin_to_irq_node(struct mp_chip_data *data,
408 int node, int apic, int pin)
409{
410 if (__add_pin_to_irq_node(data, node, apic, pin))
411 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
412}
413
414/*
415 * Reroute an IRQ to a different pin.
416 */
417static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
418 int oldapic, int oldpin,
419 int newapic, int newpin)
420{
421 struct irq_pin_list *entry;
422
423 for_each_irq_pin(entry, data->irq_2_pin) {
424 if (entry->apic == oldapic && entry->pin == oldpin) {
425 entry->apic = newapic;
426 entry->pin = newpin;
427 /* every one is different, right? */
428 return;
429 }
430 }
431
432 /* old apic/pin didn't exist, so just add new ones */
433 add_pin_to_irq_node(data, node, newapic, newpin);
434}
435
436static void io_apic_modify_irq(struct mp_chip_data *data,
437 int mask_and, int mask_or,
438 void (*final)(struct irq_pin_list *entry))
439{
440 union entry_union eu;
441 struct irq_pin_list *entry;
442
443 eu.entry = data->entry;
444 eu.w1 &= mask_and;
445 eu.w1 |= mask_or;
446 data->entry = eu.entry;
447
448 for_each_irq_pin(entry, data->irq_2_pin) {
449 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
450 if (final)
451 final(entry);
452 }
453}
454
455static void io_apic_sync(struct irq_pin_list *entry)
456{
457 /*
458 * Synchronize the IO-APIC and the CPU by doing
459 * a dummy read from the IO-APIC
460 */
461 struct io_apic __iomem *io_apic;
462
463 io_apic = io_apic_base(entry->apic);
464 readl(&io_apic->data);
465}
466
467static void mask_ioapic_irq(struct irq_data *irq_data)
468{
469 struct mp_chip_data *data = irq_data->chip_data;
470 unsigned long flags;
471
472 raw_spin_lock_irqsave(&ioapic_lock, flags);
473 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
474 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
475}
476
477static void __unmask_ioapic(struct mp_chip_data *data)
478{
479 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
480}
481
482static void unmask_ioapic_irq(struct irq_data *irq_data)
483{
484 struct mp_chip_data *data = irq_data->chip_data;
485 unsigned long flags;
486
487 raw_spin_lock_irqsave(&ioapic_lock, flags);
488 __unmask_ioapic(data);
489 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
490}
491
492/*
493 * IO-APIC versions below 0x20 don't support EOI register.
494 * For the record, here is the information about various versions:
495 * 0Xh 82489DX
496 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
497 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
498 * 30h-FFh Reserved
499 *
500 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
501 * version as 0x2. This is an error with documentation and these ICH chips
502 * use io-apic's of version 0x20.
503 *
504 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
505 * Otherwise, we simulate the EOI message manually by changing the trigger
506 * mode to edge and then back to level, with RTE being masked during this.
507 */
508static void __eoi_ioapic_pin(int apic, int pin, int vector)
509{
510 if (mpc_ioapic_ver(apic) >= 0x20) {
511 io_apic_eoi(apic, vector);
512 } else {
513 struct IO_APIC_route_entry entry, entry1;
514
515 entry = entry1 = __ioapic_read_entry(apic, pin);
516
517 /*
518 * Mask the entry and change the trigger mode to edge.
519 */
520 entry1.mask = IOAPIC_MASKED;
521 entry1.trigger = IOAPIC_EDGE;
522
523 __ioapic_write_entry(apic, pin, entry1);
524
525 /*
526 * Restore the previous level triggered entry.
527 */
528 __ioapic_write_entry(apic, pin, entry);
529 }
530}
531
532static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
533{
534 unsigned long flags;
535 struct irq_pin_list *entry;
536
537 raw_spin_lock_irqsave(&ioapic_lock, flags);
538 for_each_irq_pin(entry, data->irq_2_pin)
539 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
541}
542
543static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
544{
545 struct IO_APIC_route_entry entry;
546
547 /* Check delivery_mode to be sure we're not clearing an SMI pin */
548 entry = ioapic_read_entry(apic, pin);
549 if (entry.delivery_mode == dest_SMI)
550 return;
551
552 /*
553 * Make sure the entry is masked and re-read the contents to check
554 * if it is a level triggered pin and if the remote-IRR is set.
555 */
556 if (entry.mask == IOAPIC_UNMASKED) {
557 entry.mask = IOAPIC_MASKED;
558 ioapic_write_entry(apic, pin, entry);
559 entry = ioapic_read_entry(apic, pin);
560 }
561
562 if (entry.irr) {
563 unsigned long flags;
564
565 /*
566 * Make sure the trigger mode is set to level. Explicit EOI
567 * doesn't clear the remote-IRR if the trigger mode is not
568 * set to level.
569 */
570 if (entry.trigger == IOAPIC_EDGE) {
571 entry.trigger = IOAPIC_LEVEL;
572 ioapic_write_entry(apic, pin, entry);
573 }
574 raw_spin_lock_irqsave(&ioapic_lock, flags);
575 __eoi_ioapic_pin(apic, pin, entry.vector);
576 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
577 }
578
579 /*
580 * Clear the rest of the bits in the IO-APIC RTE except for the mask
581 * bit.
582 */
583 ioapic_mask_entry(apic, pin);
584 entry = ioapic_read_entry(apic, pin);
585 if (entry.irr)
586 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
587 mpc_ioapic_id(apic), pin);
588}
589
590void clear_IO_APIC (void)
591{
592 int apic, pin;
593
594 for_each_ioapic_pin(apic, pin)
595 clear_IO_APIC_pin(apic, pin);
596}
597
598#ifdef CONFIG_X86_32
599/*
600 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
601 * specific CPU-side IRQs.
602 */
603
604#define MAX_PIRQS 8
605static int pirq_entries[MAX_PIRQS] = {
606 [0 ... MAX_PIRQS - 1] = -1
607};
608
609static int __init ioapic_pirq_setup(char *str)
610{
611 int i, max;
612 int ints[MAX_PIRQS+1];
613
614 get_options(str, ARRAY_SIZE(ints), ints);
615
616 apic_printk(APIC_VERBOSE, KERN_INFO
617 "PIRQ redirection, working around broken MP-BIOS.\n");
618 max = MAX_PIRQS;
619 if (ints[0] < MAX_PIRQS)
620 max = ints[0];
621
622 for (i = 0; i < max; i++) {
623 apic_printk(APIC_VERBOSE, KERN_DEBUG
624 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
625 /*
626 * PIRQs are mapped upside down, usually.
627 */
628 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
629 }
630 return 1;
631}
632
633__setup("pirq=", ioapic_pirq_setup);
634#endif /* CONFIG_X86_32 */
635
636/*
637 * Saves all the IO-APIC RTE's
638 */
639int save_ioapic_entries(void)
640{
641 int apic, pin;
642 int err = 0;
643
644 for_each_ioapic(apic) {
645 if (!ioapics[apic].saved_registers) {
646 err = -ENOMEM;
647 continue;
648 }
649
650 for_each_pin(apic, pin)
651 ioapics[apic].saved_registers[pin] =
652 ioapic_read_entry(apic, pin);
653 }
654
655 return err;
656}
657
658/*
659 * Mask all IO APIC entries.
660 */
661void mask_ioapic_entries(void)
662{
663 int apic, pin;
664
665 for_each_ioapic(apic) {
666 if (!ioapics[apic].saved_registers)
667 continue;
668
669 for_each_pin(apic, pin) {
670 struct IO_APIC_route_entry entry;
671
672 entry = ioapics[apic].saved_registers[pin];
673 if (entry.mask == IOAPIC_UNMASKED) {
674 entry.mask = IOAPIC_MASKED;
675 ioapic_write_entry(apic, pin, entry);
676 }
677 }
678 }
679}
680
681/*
682 * Restore IO APIC entries which was saved in the ioapic structure.
683 */
684int restore_ioapic_entries(void)
685{
686 int apic, pin;
687
688 for_each_ioapic(apic) {
689 if (!ioapics[apic].saved_registers)
690 continue;
691
692 for_each_pin(apic, pin)
693 ioapic_write_entry(apic, pin,
694 ioapics[apic].saved_registers[pin]);
695 }
696 return 0;
697}
698
699/*
700 * Find the IRQ entry number of a certain pin.
701 */
702static int find_irq_entry(int ioapic_idx, int pin, int type)
703{
704 int i;
705
706 for (i = 0; i < mp_irq_entries; i++)
707 if (mp_irqs[i].irqtype == type &&
708 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
709 mp_irqs[i].dstapic == MP_APIC_ALL) &&
710 mp_irqs[i].dstirq == pin)
711 return i;
712
713 return -1;
714}
715
716/*
717 * Find the pin to which IRQ[irq] (ISA) is connected
718 */
719static int __init find_isa_irq_pin(int irq, int type)
720{
721 int i;
722
723 for (i = 0; i < mp_irq_entries; i++) {
724 int lbus = mp_irqs[i].srcbus;
725
726 if (test_bit(lbus, mp_bus_not_pci) &&
727 (mp_irqs[i].irqtype == type) &&
728 (mp_irqs[i].srcbusirq == irq))
729
730 return mp_irqs[i].dstirq;
731 }
732 return -1;
733}
734
735static int __init find_isa_irq_apic(int irq, int type)
736{
737 int i;
738
739 for (i = 0; i < mp_irq_entries; i++) {
740 int lbus = mp_irqs[i].srcbus;
741
742 if (test_bit(lbus, mp_bus_not_pci) &&
743 (mp_irqs[i].irqtype == type) &&
744 (mp_irqs[i].srcbusirq == irq))
745 break;
746 }
747
748 if (i < mp_irq_entries) {
749 int ioapic_idx;
750
751 for_each_ioapic(ioapic_idx)
752 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
753 return ioapic_idx;
754 }
755
756 return -1;
757}
758
759#ifdef CONFIG_EISA
760/*
761 * EISA Edge/Level control register, ELCR
762 */
763static int EISA_ELCR(unsigned int irq)
764{
765 if (irq < nr_legacy_irqs()) {
766 unsigned int port = 0x4d0 + (irq >> 3);
767 return (inb(port) >> (irq & 7)) & 1;
768 }
769 apic_printk(APIC_VERBOSE, KERN_INFO
770 "Broken MPtable reports ISA irq %d\n", irq);
771 return 0;
772}
773
774#endif
775
776/* ISA interrupts are always active high edge triggered,
777 * when listed as conforming in the MP table. */
778
779#define default_ISA_trigger(idx) (IOAPIC_EDGE)
780#define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
781
782/* EISA interrupts are always polarity zero and can be edge or level
783 * trigger depending on the ELCR value. If an interrupt is listed as
784 * EISA conforming in the MP table, that means its trigger type must
785 * be read in from the ELCR */
786
787#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
788#define default_EISA_polarity(idx) default_ISA_polarity(idx)
789
790/* PCI interrupts are always active low level triggered,
791 * when listed as conforming in the MP table. */
792
793#define default_PCI_trigger(idx) (IOAPIC_LEVEL)
794#define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
795
796static int irq_polarity(int idx)
797{
798 int bus = mp_irqs[idx].srcbus;
799
800 /*
801 * Determine IRQ line polarity (high active or low active):
802 */
803 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
804 case MP_IRQPOL_DEFAULT:
805 /* conforms to spec, ie. bus-type dependent polarity */
806 if (test_bit(bus, mp_bus_not_pci))
807 return default_ISA_polarity(idx);
808 else
809 return default_PCI_polarity(idx);
810 case MP_IRQPOL_ACTIVE_HIGH:
811 return IOAPIC_POL_HIGH;
812 case MP_IRQPOL_RESERVED:
813 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
814 case MP_IRQPOL_ACTIVE_LOW:
815 default: /* Pointless default required due to do gcc stupidity */
816 return IOAPIC_POL_LOW;
817 }
818}
819
820#ifdef CONFIG_EISA
821static int eisa_irq_trigger(int idx, int bus, int trigger)
822{
823 switch (mp_bus_id_to_type[bus]) {
824 case MP_BUS_PCI:
825 case MP_BUS_ISA:
826 return trigger;
827 case MP_BUS_EISA:
828 return default_EISA_trigger(idx);
829 }
830 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
831 return IOAPIC_LEVEL;
832}
833#else
834static inline int eisa_irq_trigger(int idx, int bus, int trigger)
835{
836 return trigger;
837}
838#endif
839
840static int irq_trigger(int idx)
841{
842 int bus = mp_irqs[idx].srcbus;
843 int trigger;
844
845 /*
846 * Determine IRQ trigger mode (edge or level sensitive):
847 */
848 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
849 case MP_IRQTRIG_DEFAULT:
850 /* conforms to spec, ie. bus-type dependent trigger mode */
851 if (test_bit(bus, mp_bus_not_pci))
852 trigger = default_ISA_trigger(idx);
853 else
854 trigger = default_PCI_trigger(idx);
855 /* Take EISA into account */
856 return eisa_irq_trigger(idx, bus, trigger);
857 case MP_IRQTRIG_EDGE:
858 return IOAPIC_EDGE;
859 case MP_IRQTRIG_RESERVED:
860 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
861 case MP_IRQTRIG_LEVEL:
862 default: /* Pointless default required due to do gcc stupidity */
863 return IOAPIC_LEVEL;
864 }
865}
866
867void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
868 int trigger, int polarity)
869{
870 init_irq_alloc_info(info, NULL);
871 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
872 info->ioapic_node = node;
873 info->ioapic_trigger = trigger;
874 info->ioapic_polarity = polarity;
875 info->ioapic_valid = 1;
876}
877
878#ifndef CONFIG_ACPI
879int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
880#endif
881
882static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
883 struct irq_alloc_info *src,
884 u32 gsi, int ioapic_idx, int pin)
885{
886 int trigger, polarity;
887
888 copy_irq_alloc_info(dst, src);
889 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
890 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
891 dst->ioapic_pin = pin;
892 dst->ioapic_valid = 1;
893 if (src && src->ioapic_valid) {
894 dst->ioapic_node = src->ioapic_node;
895 dst->ioapic_trigger = src->ioapic_trigger;
896 dst->ioapic_polarity = src->ioapic_polarity;
897 } else {
898 dst->ioapic_node = NUMA_NO_NODE;
899 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
900 dst->ioapic_trigger = trigger;
901 dst->ioapic_polarity = polarity;
902 } else {
903 /*
904 * PCI interrupts are always active low level
905 * triggered.
906 */
907 dst->ioapic_trigger = IOAPIC_LEVEL;
908 dst->ioapic_polarity = IOAPIC_POL_LOW;
909 }
910 }
911}
912
913static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
914{
915 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
916}
917
918static void mp_register_handler(unsigned int irq, unsigned long trigger)
919{
920 irq_flow_handler_t hdl;
921 bool fasteoi;
922
923 if (trigger) {
924 irq_set_status_flags(irq, IRQ_LEVEL);
925 fasteoi = true;
926 } else {
927 irq_clear_status_flags(irq, IRQ_LEVEL);
928 fasteoi = false;
929 }
930
931 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
932 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
933}
934
935static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
936{
937 struct mp_chip_data *data = irq_get_chip_data(irq);
938
939 /*
940 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
941 * and polarity attirbutes. So allow the first user to reprogram the
942 * pin with real trigger and polarity attributes.
943 */
944 if (irq < nr_legacy_irqs() && data->count == 1) {
945 if (info->ioapic_trigger != data->trigger)
946 mp_register_handler(irq, info->ioapic_trigger);
947 data->entry.trigger = data->trigger = info->ioapic_trigger;
948 data->entry.polarity = data->polarity = info->ioapic_polarity;
949 }
950
951 return data->trigger == info->ioapic_trigger &&
952 data->polarity == info->ioapic_polarity;
953}
954
955static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
956 struct irq_alloc_info *info)
957{
958 bool legacy = false;
959 int irq = -1;
960 int type = ioapics[ioapic].irqdomain_cfg.type;
961
962 switch (type) {
963 case IOAPIC_DOMAIN_LEGACY:
964 /*
965 * Dynamically allocate IRQ number for non-ISA IRQs in the first
966 * 16 GSIs on some weird platforms.
967 */
968 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
969 irq = gsi;
970 legacy = mp_is_legacy_irq(irq);
971 break;
972 case IOAPIC_DOMAIN_STRICT:
973 irq = gsi;
974 break;
975 case IOAPIC_DOMAIN_DYNAMIC:
976 break;
977 default:
978 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
979 return -1;
980 }
981
982 return __irq_domain_alloc_irqs(domain, irq, 1,
983 ioapic_alloc_attr_node(info),
984 info, legacy, NULL);
985}
986
987/*
988 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
989 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
990 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
991 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
992 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
993 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
994 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
995 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
996 */
997static int alloc_isa_irq_from_domain(struct irq_domain *domain,
998 int irq, int ioapic, int pin,
999 struct irq_alloc_info *info)
1000{
1001 struct mp_chip_data *data;
1002 struct irq_data *irq_data = irq_get_irq_data(irq);
1003 int node = ioapic_alloc_attr_node(info);
1004
1005 /*
1006 * Legacy ISA IRQ has already been allocated, just add pin to
1007 * the pin list assoicated with this IRQ and program the IOAPIC
1008 * entry. The IOAPIC entry
1009 */
1010 if (irq_data && irq_data->parent_data) {
1011 if (!mp_check_pin_attr(irq, info))
1012 return -EBUSY;
1013 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1014 info->ioapic_pin))
1015 return -ENOMEM;
1016 } else {
1017 info->flags |= X86_IRQ_ALLOC_LEGACY;
1018 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1019 NULL);
1020 if (irq >= 0) {
1021 irq_data = irq_domain_get_irq_data(domain, irq);
1022 data = irq_data->chip_data;
1023 data->isa_irq = true;
1024 }
1025 }
1026
1027 return irq;
1028}
1029
1030static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1031 unsigned int flags, struct irq_alloc_info *info)
1032{
1033 int irq;
1034 bool legacy = false;
1035 struct irq_alloc_info tmp;
1036 struct mp_chip_data *data;
1037 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1038
1039 if (!domain)
1040 return -ENOSYS;
1041
1042 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1043 irq = mp_irqs[idx].srcbusirq;
1044 legacy = mp_is_legacy_irq(irq);
1045 }
1046
1047 mutex_lock(&ioapic_mutex);
1048 if (!(flags & IOAPIC_MAP_ALLOC)) {
1049 if (!legacy) {
1050 irq = irq_find_mapping(domain, pin);
1051 if (irq == 0)
1052 irq = -ENOENT;
1053 }
1054 } else {
1055 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1056 if (legacy)
1057 irq = alloc_isa_irq_from_domain(domain, irq,
1058 ioapic, pin, &tmp);
1059 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1060 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1061 else if (!mp_check_pin_attr(irq, &tmp))
1062 irq = -EBUSY;
1063 if (irq >= 0) {
1064 data = irq_get_chip_data(irq);
1065 data->count++;
1066 }
1067 }
1068 mutex_unlock(&ioapic_mutex);
1069
1070 return irq;
1071}
1072
1073static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1074{
1075 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1076
1077 /*
1078 * Debugging check, we are in big trouble if this message pops up!
1079 */
1080 if (mp_irqs[idx].dstirq != pin)
1081 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1082
1083#ifdef CONFIG_X86_32
1084 /*
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086 */
1087 if ((pin >= 16) && (pin <= 23)) {
1088 if (pirq_entries[pin-16] != -1) {
1089 if (!pirq_entries[pin-16]) {
1090 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin-16);
1092 } else {
1093 int irq = pirq_entries[pin-16];
1094 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1096 pin-16, irq);
1097 return irq;
1098 }
1099 }
1100 }
1101#endif
1102
1103 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1104}
1105
1106int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1107{
1108 int ioapic, pin, idx;
1109
1110 ioapic = mp_find_ioapic(gsi);
1111 if (ioapic < 0)
1112 return -ENODEV;
1113
1114 pin = mp_find_ioapic_pin(ioapic, gsi);
1115 idx = find_irq_entry(ioapic, pin, mp_INT);
1116 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1117 return -ENODEV;
1118
1119 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1120}
1121
1122void mp_unmap_irq(int irq)
1123{
1124 struct irq_data *irq_data = irq_get_irq_data(irq);
1125 struct mp_chip_data *data;
1126
1127 if (!irq_data || !irq_data->domain)
1128 return;
1129
1130 data = irq_data->chip_data;
1131 if (!data || data->isa_irq)
1132 return;
1133
1134 mutex_lock(&ioapic_mutex);
1135 if (--data->count == 0)
1136 irq_domain_free_irqs(irq, 1);
1137 mutex_unlock(&ioapic_mutex);
1138}
1139
1140/*
1141 * Find a specific PCI IRQ entry.
1142 * Not an __init, possibly needed by modules
1143 */
1144int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1145{
1146 int irq, i, best_ioapic = -1, best_idx = -1;
1147
1148 apic_printk(APIC_DEBUG,
1149 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1150 bus, slot, pin);
1151 if (test_bit(bus, mp_bus_not_pci)) {
1152 apic_printk(APIC_VERBOSE,
1153 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1154 return -1;
1155 }
1156
1157 for (i = 0; i < mp_irq_entries; i++) {
1158 int lbus = mp_irqs[i].srcbus;
1159 int ioapic_idx, found = 0;
1160
1161 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1162 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1163 continue;
1164
1165 for_each_ioapic(ioapic_idx)
1166 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1167 mp_irqs[i].dstapic == MP_APIC_ALL) {
1168 found = 1;
1169 break;
1170 }
1171 if (!found)
1172 continue;
1173
1174 /* Skip ISA IRQs */
1175 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1176 if (irq > 0 && !IO_APIC_IRQ(irq))
1177 continue;
1178
1179 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1180 best_idx = i;
1181 best_ioapic = ioapic_idx;
1182 goto out;
1183 }
1184
1185 /*
1186 * Use the first all-but-pin matching entry as a
1187 * best-guess fuzzy result for broken mptables.
1188 */
1189 if (best_idx < 0) {
1190 best_idx = i;
1191 best_ioapic = ioapic_idx;
1192 }
1193 }
1194 if (best_idx < 0)
1195 return -1;
1196
1197out:
1198 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1199 IOAPIC_MAP_ALLOC);
1200}
1201EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1202
1203static struct irq_chip ioapic_chip, ioapic_ir_chip;
1204
1205static void __init setup_IO_APIC_irqs(void)
1206{
1207 unsigned int ioapic, pin;
1208 int idx;
1209
1210 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211
1212 for_each_ioapic_pin(ioapic, pin) {
1213 idx = find_irq_entry(ioapic, pin, mp_INT);
1214 if (idx < 0)
1215 apic_printk(APIC_VERBOSE,
1216 KERN_DEBUG " apic %d pin %d not connected\n",
1217 mpc_ioapic_id(ioapic), pin);
1218 else
1219 pin_2_irq(idx, ioapic, pin,
1220 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1221 }
1222}
1223
1224void ioapic_zap_locks(void)
1225{
1226 raw_spin_lock_init(&ioapic_lock);
1227}
1228
1229static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1230{
1231 int i;
1232 char buf[256];
1233 struct IO_APIC_route_entry entry;
1234 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1235
1236 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1237 for (i = 0; i <= nr_entries; i++) {
1238 entry = ioapic_read_entry(apic, i);
1239 snprintf(buf, sizeof(buf),
1240 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1241 i,
1242 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1243 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1244 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1245 entry.vector, entry.irr, entry.delivery_status);
1246 if (ir_entry->format)
1247 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1248 buf, (ir_entry->index2 << 15) | ir_entry->index,
1249 ir_entry->zero);
1250 else
1251 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1252 buf,
1253 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1254 "logical " : "physical",
1255 entry.dest, entry.delivery_mode);
1256 }
1257}
1258
1259static void __init print_IO_APIC(int ioapic_idx)
1260{
1261 union IO_APIC_reg_00 reg_00;
1262 union IO_APIC_reg_01 reg_01;
1263 union IO_APIC_reg_02 reg_02;
1264 union IO_APIC_reg_03 reg_03;
1265 unsigned long flags;
1266
1267 raw_spin_lock_irqsave(&ioapic_lock, flags);
1268 reg_00.raw = io_apic_read(ioapic_idx, 0);
1269 reg_01.raw = io_apic_read(ioapic_idx, 1);
1270 if (reg_01.bits.version >= 0x10)
1271 reg_02.raw = io_apic_read(ioapic_idx, 2);
1272 if (reg_01.bits.version >= 0x20)
1273 reg_03.raw = io_apic_read(ioapic_idx, 3);
1274 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1275
1276 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1277 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1278 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1279 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1280 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1281
1282 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1283 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1284 reg_01.bits.entries);
1285
1286 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1287 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1288 reg_01.bits.version);
1289
1290 /*
1291 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1292 * but the value of reg_02 is read as the previous read register
1293 * value, so ignore it if reg_02 == reg_01.
1294 */
1295 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1296 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1297 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1298 }
1299
1300 /*
1301 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1302 * or reg_03, but the value of reg_0[23] is read as the previous read
1303 * register value, so ignore it if reg_03 == reg_0[12].
1304 */
1305 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1306 reg_03.raw != reg_01.raw) {
1307 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1308 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1309 }
1310
1311 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1312 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1313}
1314
1315void __init print_IO_APICs(void)
1316{
1317 int ioapic_idx;
1318 unsigned int irq;
1319
1320 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321 for_each_ioapic(ioapic_idx)
1322 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323 mpc_ioapic_id(ioapic_idx),
1324 ioapics[ioapic_idx].nr_registers);
1325
1326 /*
1327 * We are a bit conservative about what we expect. We have to
1328 * know about every hardware change ASAP.
1329 */
1330 printk(KERN_INFO "testing the IO APIC.......................\n");
1331
1332 for_each_ioapic(ioapic_idx)
1333 print_IO_APIC(ioapic_idx);
1334
1335 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1336 for_each_active_irq(irq) {
1337 struct irq_pin_list *entry;
1338 struct irq_chip *chip;
1339 struct mp_chip_data *data;
1340
1341 chip = irq_get_chip(irq);
1342 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1343 continue;
1344 data = irq_get_chip_data(irq);
1345 if (!data)
1346 continue;
1347 if (list_empty(&data->irq_2_pin))
1348 continue;
1349
1350 printk(KERN_DEBUG "IRQ%d ", irq);
1351 for_each_irq_pin(entry, data->irq_2_pin)
1352 pr_cont("-> %d:%d", entry->apic, entry->pin);
1353 pr_cont("\n");
1354 }
1355
1356 printk(KERN_INFO ".................................... done.\n");
1357}
1358
1359/* Where if anywhere is the i8259 connect in external int mode */
1360static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1361
1362void __init enable_IO_APIC(void)
1363{
1364 int i8259_apic, i8259_pin;
1365 int apic, pin;
1366
1367 if (skip_ioapic_setup)
1368 nr_ioapics = 0;
1369
1370 if (!nr_legacy_irqs() || !nr_ioapics)
1371 return;
1372
1373 for_each_ioapic_pin(apic, pin) {
1374 /* See if any of the pins is in ExtINT mode */
1375 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1376
1377 /* If the interrupt line is enabled and in ExtInt mode
1378 * I have found the pin where the i8259 is connected.
1379 */
1380 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1381 ioapic_i8259.apic = apic;
1382 ioapic_i8259.pin = pin;
1383 goto found_i8259;
1384 }
1385 }
1386 found_i8259:
1387 /* Look to see what if the MP table has reported the ExtINT */
1388 /* If we could not find the appropriate pin by looking at the ioapic
1389 * the i8259 probably is not connected the ioapic but give the
1390 * mptable a chance anyway.
1391 */
1392 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1393 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1394 /* Trust the MP table if nothing is setup in the hardware */
1395 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1396 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1397 ioapic_i8259.pin = i8259_pin;
1398 ioapic_i8259.apic = i8259_apic;
1399 }
1400 /* Complain if the MP table and the hardware disagree */
1401 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1402 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1403 {
1404 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1405 }
1406
1407 /*
1408 * Do not trust the IO-APIC being empty at bootup
1409 */
1410 clear_IO_APIC();
1411}
1412
1413void native_restore_boot_irq_mode(void)
1414{
1415 /*
1416 * If the i8259 is routed through an IOAPIC
1417 * Put that IOAPIC in virtual wire mode
1418 * so legacy interrupts can be delivered.
1419 */
1420 if (ioapic_i8259.pin != -1) {
1421 struct IO_APIC_route_entry entry;
1422
1423 memset(&entry, 0, sizeof(entry));
1424 entry.mask = IOAPIC_UNMASKED;
1425 entry.trigger = IOAPIC_EDGE;
1426 entry.polarity = IOAPIC_POL_HIGH;
1427 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1428 entry.delivery_mode = dest_ExtINT;
1429 entry.dest = read_apic_id();
1430
1431 /*
1432 * Add it to the IO-APIC irq-routing table:
1433 */
1434 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1435 }
1436
1437 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1438 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1439}
1440
1441void restore_boot_irq_mode(void)
1442{
1443 if (!nr_legacy_irqs())
1444 return;
1445
1446 x86_apic_ops.restore();
1447}
1448
1449#ifdef CONFIG_X86_32
1450/*
1451 * function to set the IO-APIC physical IDs based on the
1452 * values stored in the MPC table.
1453 *
1454 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1455 */
1456void __init setup_ioapic_ids_from_mpc_nocheck(void)
1457{
1458 union IO_APIC_reg_00 reg_00;
1459 physid_mask_t phys_id_present_map;
1460 int ioapic_idx;
1461 int i;
1462 unsigned char old_id;
1463 unsigned long flags;
1464
1465 /*
1466 * This is broken; anything with a real cpu count has to
1467 * circumvent this idiocy regardless.
1468 */
1469 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1470
1471 /*
1472 * Set the IOAPIC ID to the value stored in the MPC table.
1473 */
1474 for_each_ioapic(ioapic_idx) {
1475 /* Read the register 0 value */
1476 raw_spin_lock_irqsave(&ioapic_lock, flags);
1477 reg_00.raw = io_apic_read(ioapic_idx, 0);
1478 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1479
1480 old_id = mpc_ioapic_id(ioapic_idx);
1481
1482 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1483 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1484 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1485 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1486 reg_00.bits.ID);
1487 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1488 }
1489
1490 /*
1491 * Sanity check, is the ID really free? Every APIC in a
1492 * system must have a unique ID or we get lots of nice
1493 * 'stuck on smp_invalidate_needed IPI wait' messages.
1494 */
1495 if (apic->check_apicid_used(&phys_id_present_map,
1496 mpc_ioapic_id(ioapic_idx))) {
1497 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1498 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1499 for (i = 0; i < get_physical_broadcast(); i++)
1500 if (!physid_isset(i, phys_id_present_map))
1501 break;
1502 if (i >= get_physical_broadcast())
1503 panic("Max APIC ID exceeded!\n");
1504 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1505 i);
1506 physid_set(i, phys_id_present_map);
1507 ioapics[ioapic_idx].mp_config.apicid = i;
1508 } else {
1509 physid_mask_t tmp;
1510 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1511 &tmp);
1512 apic_printk(APIC_VERBOSE, "Setting %d in the "
1513 "phys_id_present_map\n",
1514 mpc_ioapic_id(ioapic_idx));
1515 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1516 }
1517
1518 /*
1519 * We need to adjust the IRQ routing table
1520 * if the ID changed.
1521 */
1522 if (old_id != mpc_ioapic_id(ioapic_idx))
1523 for (i = 0; i < mp_irq_entries; i++)
1524 if (mp_irqs[i].dstapic == old_id)
1525 mp_irqs[i].dstapic
1526 = mpc_ioapic_id(ioapic_idx);
1527
1528 /*
1529 * Update the ID register according to the right value
1530 * from the MPC table if they are different.
1531 */
1532 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1533 continue;
1534
1535 apic_printk(APIC_VERBOSE, KERN_INFO
1536 "...changing IO-APIC physical APIC ID to %d ...",
1537 mpc_ioapic_id(ioapic_idx));
1538
1539 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1540 raw_spin_lock_irqsave(&ioapic_lock, flags);
1541 io_apic_write(ioapic_idx, 0, reg_00.raw);
1542 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1543
1544 /*
1545 * Sanity check
1546 */
1547 raw_spin_lock_irqsave(&ioapic_lock, flags);
1548 reg_00.raw = io_apic_read(ioapic_idx, 0);
1549 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1550 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1551 pr_cont("could not set ID!\n");
1552 else
1553 apic_printk(APIC_VERBOSE, " ok.\n");
1554 }
1555}
1556
1557void __init setup_ioapic_ids_from_mpc(void)
1558{
1559
1560 if (acpi_ioapic)
1561 return;
1562 /*
1563 * Don't check I/O APIC IDs for xAPIC systems. They have
1564 * no meaning without the serial APIC bus.
1565 */
1566 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1567 || APIC_XAPIC(boot_cpu_apic_version))
1568 return;
1569 setup_ioapic_ids_from_mpc_nocheck();
1570}
1571#endif
1572
1573int no_timer_check __initdata;
1574
1575static int __init notimercheck(char *s)
1576{
1577 no_timer_check = 1;
1578 return 1;
1579}
1580__setup("no_timer_check", notimercheck);
1581
1582static void __init delay_with_tsc(void)
1583{
1584 unsigned long long start, now;
1585 unsigned long end = jiffies + 4;
1586
1587 start = rdtsc();
1588
1589 /*
1590 * We don't know the TSC frequency yet, but waiting for
1591 * 40000000000/HZ TSC cycles is safe:
1592 * 4 GHz == 10 jiffies
1593 * 1 GHz == 40 jiffies
1594 */
1595 do {
1596 rep_nop();
1597 now = rdtsc();
1598 } while ((now - start) < 40000000000ULL / HZ &&
1599 time_before_eq(jiffies, end));
1600}
1601
1602static void __init delay_without_tsc(void)
1603{
1604 unsigned long end = jiffies + 4;
1605 int band = 1;
1606
1607 /*
1608 * We don't know any frequency yet, but waiting for
1609 * 40940000000/HZ cycles is safe:
1610 * 4 GHz == 10 jiffies
1611 * 1 GHz == 40 jiffies
1612 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1613 */
1614 do {
1615 __delay(((1U << band++) * 10000000UL) / HZ);
1616 } while (band < 12 && time_before_eq(jiffies, end));
1617}
1618
1619/*
1620 * There is a nasty bug in some older SMP boards, their mptable lies
1621 * about the timer IRQ. We do the following to work around the situation:
1622 *
1623 * - timer IRQ defaults to IO-APIC IRQ
1624 * - if this function detects that timer IRQs are defunct, then we fall
1625 * back to ISA timer IRQs
1626 */
1627static int __init timer_irq_works(void)
1628{
1629 unsigned long t1 = jiffies;
1630 unsigned long flags;
1631
1632 if (no_timer_check)
1633 return 1;
1634
1635 local_save_flags(flags);
1636 local_irq_enable();
1637
1638 if (boot_cpu_has(X86_FEATURE_TSC))
1639 delay_with_tsc();
1640 else
1641 delay_without_tsc();
1642
1643 local_irq_restore(flags);
1644
1645 /*
1646 * Expect a few ticks at least, to be sure some possible
1647 * glue logic does not lock up after one or two first
1648 * ticks in a non-ExtINT mode. Also the local APIC
1649 * might have cached one ExtINT interrupt. Finally, at
1650 * least one tick may be lost due to delays.
1651 */
1652
1653 /* jiffies wrap? */
1654 if (time_after(jiffies, t1 + 4))
1655 return 1;
1656 return 0;
1657}
1658
1659/*
1660 * In the SMP+IOAPIC case it might happen that there are an unspecified
1661 * number of pending IRQ events unhandled. These cases are very rare,
1662 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1663 * better to do it this way as thus we do not have to be aware of
1664 * 'pending' interrupts in the IRQ path, except at this point.
1665 */
1666/*
1667 * Edge triggered needs to resend any interrupt
1668 * that was delayed but this is now handled in the device
1669 * independent code.
1670 */
1671
1672/*
1673 * Starting up a edge-triggered IO-APIC interrupt is
1674 * nasty - we need to make sure that we get the edge.
1675 * If it is already asserted for some reason, we need
1676 * return 1 to indicate that is was pending.
1677 *
1678 * This is not complete - we should be able to fake
1679 * an edge even if it isn't on the 8259A...
1680 */
1681static unsigned int startup_ioapic_irq(struct irq_data *data)
1682{
1683 int was_pending = 0, irq = data->irq;
1684 unsigned long flags;
1685
1686 raw_spin_lock_irqsave(&ioapic_lock, flags);
1687 if (irq < nr_legacy_irqs()) {
1688 legacy_pic->mask(irq);
1689 if (legacy_pic->irq_pending(irq))
1690 was_pending = 1;
1691 }
1692 __unmask_ioapic(data->chip_data);
1693 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1694
1695 return was_pending;
1696}
1697
1698atomic_t irq_mis_count;
1699
1700#ifdef CONFIG_GENERIC_PENDING_IRQ
1701static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1702{
1703 struct irq_pin_list *entry;
1704 unsigned long flags;
1705
1706 raw_spin_lock_irqsave(&ioapic_lock, flags);
1707 for_each_irq_pin(entry, data->irq_2_pin) {
1708 unsigned int reg;
1709 int pin;
1710
1711 pin = entry->pin;
1712 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1713 /* Is the remote IRR bit set? */
1714 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1715 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1716 return true;
1717 }
1718 }
1719 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1720
1721 return false;
1722}
1723
1724static inline bool ioapic_irqd_mask(struct irq_data *data)
1725{
1726 /* If we are moving the irq we need to mask it */
1727 if (unlikely(irqd_is_setaffinity_pending(data))) {
1728 mask_ioapic_irq(data);
1729 return true;
1730 }
1731 return false;
1732}
1733
1734static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1735{
1736 if (unlikely(masked)) {
1737 /* Only migrate the irq if the ack has been received.
1738 *
1739 * On rare occasions the broadcast level triggered ack gets
1740 * delayed going to ioapics, and if we reprogram the
1741 * vector while Remote IRR is still set the irq will never
1742 * fire again.
1743 *
1744 * To prevent this scenario we read the Remote IRR bit
1745 * of the ioapic. This has two effects.
1746 * - On any sane system the read of the ioapic will
1747 * flush writes (and acks) going to the ioapic from
1748 * this cpu.
1749 * - We get to see if the ACK has actually been delivered.
1750 *
1751 * Based on failed experiments of reprogramming the
1752 * ioapic entry from outside of irq context starting
1753 * with masking the ioapic entry and then polling until
1754 * Remote IRR was clear before reprogramming the
1755 * ioapic I don't trust the Remote IRR bit to be
1756 * completey accurate.
1757 *
1758 * However there appears to be no other way to plug
1759 * this race, so if the Remote IRR bit is not
1760 * accurate and is causing problems then it is a hardware bug
1761 * and you can go talk to the chipset vendor about it.
1762 */
1763 if (!io_apic_level_ack_pending(data->chip_data))
1764 irq_move_masked_irq(data);
1765 unmask_ioapic_irq(data);
1766 }
1767}
1768#else
1769static inline bool ioapic_irqd_mask(struct irq_data *data)
1770{
1771 return false;
1772}
1773static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1774{
1775}
1776#endif
1777
1778static void ioapic_ack_level(struct irq_data *irq_data)
1779{
1780 struct irq_cfg *cfg = irqd_cfg(irq_data);
1781 unsigned long v;
1782 bool masked;
1783 int i;
1784
1785 irq_complete_move(cfg);
1786 masked = ioapic_irqd_mask(irq_data);
1787
1788 /*
1789 * It appears there is an erratum which affects at least version 0x11
1790 * of I/O APIC (that's the 82093AA and cores integrated into various
1791 * chipsets). Under certain conditions a level-triggered interrupt is
1792 * erroneously delivered as edge-triggered one but the respective IRR
1793 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1794 * message but it will never arrive and further interrupts are blocked
1795 * from the source. The exact reason is so far unknown, but the
1796 * phenomenon was observed when two consecutive interrupt requests
1797 * from a given source get delivered to the same CPU and the source is
1798 * temporarily disabled in between.
1799 *
1800 * A workaround is to simulate an EOI message manually. We achieve it
1801 * by setting the trigger mode to edge and then to level when the edge
1802 * trigger mode gets detected in the TMR of a local APIC for a
1803 * level-triggered interrupt. We mask the source for the time of the
1804 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1805 * The idea is from Manfred Spraul. --macro
1806 *
1807 * Also in the case when cpu goes offline, fixup_irqs() will forward
1808 * any unhandled interrupt on the offlined cpu to the new cpu
1809 * destination that is handling the corresponding interrupt. This
1810 * interrupt forwarding is done via IPI's. Hence, in this case also
1811 * level-triggered io-apic interrupt will be seen as an edge
1812 * interrupt in the IRR. And we can't rely on the cpu's EOI
1813 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1814 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1815 * supporting EOI register, we do an explicit EOI to clear the
1816 * remote IRR and on IO-APIC's which don't have an EOI register,
1817 * we use the above logic (mask+edge followed by unmask+level) from
1818 * Manfred Spraul to clear the remote IRR.
1819 */
1820 i = cfg->vector;
1821 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1822
1823 /*
1824 * We must acknowledge the irq before we move it or the acknowledge will
1825 * not propagate properly.
1826 */
1827 ack_APIC_irq();
1828
1829 /*
1830 * Tail end of clearing remote IRR bit (either by delivering the EOI
1831 * message via io-apic EOI register write or simulating it using
1832 * mask+edge followed by unnask+level logic) manually when the
1833 * level triggered interrupt is seen as the edge triggered interrupt
1834 * at the cpu.
1835 */
1836 if (!(v & (1 << (i & 0x1f)))) {
1837 atomic_inc(&irq_mis_count);
1838 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1839 }
1840
1841 ioapic_irqd_unmask(irq_data, masked);
1842}
1843
1844static void ioapic_ir_ack_level(struct irq_data *irq_data)
1845{
1846 struct mp_chip_data *data = irq_data->chip_data;
1847
1848 /*
1849 * Intr-remapping uses pin number as the virtual vector
1850 * in the RTE. Actual vector is programmed in
1851 * intr-remapping table entry. Hence for the io-apic
1852 * EOI we use the pin number.
1853 */
1854 ack_APIC_irq();
1855 eoi_ioapic_pin(data->entry.vector, data);
1856}
1857
1858static void ioapic_configure_entry(struct irq_data *irqd)
1859{
1860 struct mp_chip_data *mpd = irqd->chip_data;
1861 struct irq_cfg *cfg = irqd_cfg(irqd);
1862 struct irq_pin_list *entry;
1863
1864 /*
1865 * Only update when the parent is the vector domain, don't touch it
1866 * if the parent is the remapping domain. Check the installed
1867 * ioapic chip to verify that.
1868 */
1869 if (irqd->chip == &ioapic_chip) {
1870 mpd->entry.dest = cfg->dest_apicid;
1871 mpd->entry.vector = cfg->vector;
1872 }
1873 for_each_irq_pin(entry, mpd->irq_2_pin)
1874 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1875}
1876
1877static int ioapic_set_affinity(struct irq_data *irq_data,
1878 const struct cpumask *mask, bool force)
1879{
1880 struct irq_data *parent = irq_data->parent_data;
1881 unsigned long flags;
1882 int ret;
1883
1884 ret = parent->chip->irq_set_affinity(parent, mask, force);
1885 raw_spin_lock_irqsave(&ioapic_lock, flags);
1886 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1887 ioapic_configure_entry(irq_data);
1888 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1889
1890 return ret;
1891}
1892
1893static struct irq_chip ioapic_chip __read_mostly = {
1894 .name = "IO-APIC",
1895 .irq_startup = startup_ioapic_irq,
1896 .irq_mask = mask_ioapic_irq,
1897 .irq_unmask = unmask_ioapic_irq,
1898 .irq_ack = irq_chip_ack_parent,
1899 .irq_eoi = ioapic_ack_level,
1900 .irq_set_affinity = ioapic_set_affinity,
1901 .irq_retrigger = irq_chip_retrigger_hierarchy,
1902 .flags = IRQCHIP_SKIP_SET_WAKE,
1903};
1904
1905static struct irq_chip ioapic_ir_chip __read_mostly = {
1906 .name = "IR-IO-APIC",
1907 .irq_startup = startup_ioapic_irq,
1908 .irq_mask = mask_ioapic_irq,
1909 .irq_unmask = unmask_ioapic_irq,
1910 .irq_ack = irq_chip_ack_parent,
1911 .irq_eoi = ioapic_ir_ack_level,
1912 .irq_set_affinity = ioapic_set_affinity,
1913 .irq_retrigger = irq_chip_retrigger_hierarchy,
1914 .flags = IRQCHIP_SKIP_SET_WAKE,
1915};
1916
1917static inline void init_IO_APIC_traps(void)
1918{
1919 struct irq_cfg *cfg;
1920 unsigned int irq;
1921
1922 for_each_active_irq(irq) {
1923 cfg = irq_cfg(irq);
1924 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1925 /*
1926 * Hmm.. We don't have an entry for this,
1927 * so default to an old-fashioned 8259
1928 * interrupt if we can..
1929 */
1930 if (irq < nr_legacy_irqs())
1931 legacy_pic->make_irq(irq);
1932 else
1933 /* Strange. Oh, well.. */
1934 irq_set_chip(irq, &no_irq_chip);
1935 }
1936 }
1937}
1938
1939/*
1940 * The local APIC irq-chip implementation:
1941 */
1942
1943static void mask_lapic_irq(struct irq_data *data)
1944{
1945 unsigned long v;
1946
1947 v = apic_read(APIC_LVT0);
1948 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1949}
1950
1951static void unmask_lapic_irq(struct irq_data *data)
1952{
1953 unsigned long v;
1954
1955 v = apic_read(APIC_LVT0);
1956 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1957}
1958
1959static void ack_lapic_irq(struct irq_data *data)
1960{
1961 ack_APIC_irq();
1962}
1963
1964static struct irq_chip lapic_chip __read_mostly = {
1965 .name = "local-APIC",
1966 .irq_mask = mask_lapic_irq,
1967 .irq_unmask = unmask_lapic_irq,
1968 .irq_ack = ack_lapic_irq,
1969};
1970
1971static void lapic_register_intr(int irq)
1972{
1973 irq_clear_status_flags(irq, IRQ_LEVEL);
1974 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1975 "edge");
1976}
1977
1978/*
1979 * This looks a bit hackish but it's about the only one way of sending
1980 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1981 * not support the ExtINT mode, unfortunately. We need to send these
1982 * cycles as some i82489DX-based boards have glue logic that keeps the
1983 * 8259A interrupt line asserted until INTA. --macro
1984 */
1985static inline void __init unlock_ExtINT_logic(void)
1986{
1987 int apic, pin, i;
1988 struct IO_APIC_route_entry entry0, entry1;
1989 unsigned char save_control, save_freq_select;
1990
1991 pin = find_isa_irq_pin(8, mp_INT);
1992 if (pin == -1) {
1993 WARN_ON_ONCE(1);
1994 return;
1995 }
1996 apic = find_isa_irq_apic(8, mp_INT);
1997 if (apic == -1) {
1998 WARN_ON_ONCE(1);
1999 return;
2000 }
2001
2002 entry0 = ioapic_read_entry(apic, pin);
2003 clear_IO_APIC_pin(apic, pin);
2004
2005 memset(&entry1, 0, sizeof(entry1));
2006
2007 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2008 entry1.mask = IOAPIC_UNMASKED;
2009 entry1.dest = hard_smp_processor_id();
2010 entry1.delivery_mode = dest_ExtINT;
2011 entry1.polarity = entry0.polarity;
2012 entry1.trigger = IOAPIC_EDGE;
2013 entry1.vector = 0;
2014
2015 ioapic_write_entry(apic, pin, entry1);
2016
2017 save_control = CMOS_READ(RTC_CONTROL);
2018 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2019 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2020 RTC_FREQ_SELECT);
2021 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2022
2023 i = 100;
2024 while (i-- > 0) {
2025 mdelay(10);
2026 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2027 i -= 10;
2028 }
2029
2030 CMOS_WRITE(save_control, RTC_CONTROL);
2031 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2032 clear_IO_APIC_pin(apic, pin);
2033
2034 ioapic_write_entry(apic, pin, entry0);
2035}
2036
2037static int disable_timer_pin_1 __initdata;
2038/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2039static int __init disable_timer_pin_setup(char *arg)
2040{
2041 disable_timer_pin_1 = 1;
2042 return 0;
2043}
2044early_param("disable_timer_pin_1", disable_timer_pin_setup);
2045
2046static int mp_alloc_timer_irq(int ioapic, int pin)
2047{
2048 int irq = -1;
2049 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2050
2051 if (domain) {
2052 struct irq_alloc_info info;
2053
2054 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2055 info.ioapic_id = mpc_ioapic_id(ioapic);
2056 info.ioapic_pin = pin;
2057 mutex_lock(&ioapic_mutex);
2058 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2059 mutex_unlock(&ioapic_mutex);
2060 }
2061
2062 return irq;
2063}
2064
2065/*
2066 * This code may look a bit paranoid, but it's supposed to cooperate with
2067 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2068 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2069 * fanatically on his truly buggy board.
2070 *
2071 * FIXME: really need to revamp this for all platforms.
2072 */
2073static inline void __init check_timer(void)
2074{
2075 struct irq_data *irq_data = irq_get_irq_data(0);
2076 struct mp_chip_data *data = irq_data->chip_data;
2077 struct irq_cfg *cfg = irqd_cfg(irq_data);
2078 int node = cpu_to_node(0);
2079 int apic1, pin1, apic2, pin2;
2080 unsigned long flags;
2081 int no_pin1 = 0;
2082
2083 local_irq_save(flags);
2084
2085 /*
2086 * get/set the timer IRQ vector:
2087 */
2088 legacy_pic->mask(0);
2089
2090 /*
2091 * As IRQ0 is to be enabled in the 8259A, the virtual
2092 * wire has to be disabled in the local APIC. Also
2093 * timer interrupts need to be acknowledged manually in
2094 * the 8259A for the i82489DX when using the NMI
2095 * watchdog as that APIC treats NMIs as level-triggered.
2096 * The AEOI mode will finish them in the 8259A
2097 * automatically.
2098 */
2099 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2100 legacy_pic->init(1);
2101
2102 pin1 = find_isa_irq_pin(0, mp_INT);
2103 apic1 = find_isa_irq_apic(0, mp_INT);
2104 pin2 = ioapic_i8259.pin;
2105 apic2 = ioapic_i8259.apic;
2106
2107 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2108 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2109 cfg->vector, apic1, pin1, apic2, pin2);
2110
2111 /*
2112 * Some BIOS writers are clueless and report the ExtINTA
2113 * I/O APIC input from the cascaded 8259A as the timer
2114 * interrupt input. So just in case, if only one pin
2115 * was found above, try it both directly and through the
2116 * 8259A.
2117 */
2118 if (pin1 == -1) {
2119 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2120 pin1 = pin2;
2121 apic1 = apic2;
2122 no_pin1 = 1;
2123 } else if (pin2 == -1) {
2124 pin2 = pin1;
2125 apic2 = apic1;
2126 }
2127
2128 if (pin1 != -1) {
2129 /* Ok, does IRQ0 through the IOAPIC work? */
2130 if (no_pin1) {
2131 mp_alloc_timer_irq(apic1, pin1);
2132 } else {
2133 /*
2134 * for edge trigger, it's already unmasked,
2135 * so only need to unmask if it is level-trigger
2136 * do we really have level trigger timer?
2137 */
2138 int idx;
2139 idx = find_irq_entry(apic1, pin1, mp_INT);
2140 if (idx != -1 && irq_trigger(idx))
2141 unmask_ioapic_irq(irq_get_irq_data(0));
2142 }
2143 irq_domain_deactivate_irq(irq_data);
2144 irq_domain_activate_irq(irq_data, false);
2145 if (timer_irq_works()) {
2146 if (disable_timer_pin_1 > 0)
2147 clear_IO_APIC_pin(0, pin1);
2148 goto out;
2149 }
2150 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2151 local_irq_disable();
2152 clear_IO_APIC_pin(apic1, pin1);
2153 if (!no_pin1)
2154 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2155 "8254 timer not connected to IO-APIC\n");
2156
2157 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2158 "(IRQ0) through the 8259A ...\n");
2159 apic_printk(APIC_QUIET, KERN_INFO
2160 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2161 /*
2162 * legacy devices should be connected to IO APIC #0
2163 */
2164 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2165 irq_domain_deactivate_irq(irq_data);
2166 irq_domain_activate_irq(irq_data, false);
2167 legacy_pic->unmask(0);
2168 if (timer_irq_works()) {
2169 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2170 goto out;
2171 }
2172 /*
2173 * Cleanup, just in case ...
2174 */
2175 local_irq_disable();
2176 legacy_pic->mask(0);
2177 clear_IO_APIC_pin(apic2, pin2);
2178 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2179 }
2180
2181 apic_printk(APIC_QUIET, KERN_INFO
2182 "...trying to set up timer as Virtual Wire IRQ...\n");
2183
2184 lapic_register_intr(0);
2185 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2186 legacy_pic->unmask(0);
2187
2188 if (timer_irq_works()) {
2189 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2190 goto out;
2191 }
2192 local_irq_disable();
2193 legacy_pic->mask(0);
2194 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2195 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2196
2197 apic_printk(APIC_QUIET, KERN_INFO
2198 "...trying to set up timer as ExtINT IRQ...\n");
2199
2200 legacy_pic->init(0);
2201 legacy_pic->make_irq(0);
2202 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2203
2204 unlock_ExtINT_logic();
2205
2206 if (timer_irq_works()) {
2207 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2208 goto out;
2209 }
2210 local_irq_disable();
2211 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2212 if (apic_is_x2apic_enabled())
2213 apic_printk(APIC_QUIET, KERN_INFO
2214 "Perhaps problem with the pre-enabled x2apic mode\n"
2215 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2216 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2217 "report. Then try booting with the 'noapic' option.\n");
2218out:
2219 local_irq_restore(flags);
2220}
2221
2222/*
2223 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2224 * to devices. However there may be an I/O APIC pin available for
2225 * this interrupt regardless. The pin may be left unconnected, but
2226 * typically it will be reused as an ExtINT cascade interrupt for
2227 * the master 8259A. In the MPS case such a pin will normally be
2228 * reported as an ExtINT interrupt in the MP table. With ACPI
2229 * there is no provision for ExtINT interrupts, and in the absence
2230 * of an override it would be treated as an ordinary ISA I/O APIC
2231 * interrupt, that is edge-triggered and unmasked by default. We
2232 * used to do this, but it caused problems on some systems because
2233 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2234 * the same ExtINT cascade interrupt to drive the local APIC of the
2235 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2236 * the I/O APIC in all cases now. No actual device should request
2237 * it anyway. --macro
2238 */
2239#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2240
2241static int mp_irqdomain_create(int ioapic)
2242{
2243 struct irq_alloc_info info;
2244 struct irq_domain *parent;
2245 int hwirqs = mp_ioapic_pin_count(ioapic);
2246 struct ioapic *ip = &ioapics[ioapic];
2247 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2248 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2249 struct fwnode_handle *fn;
2250 char *name = "IO-APIC";
2251
2252 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2253 return 0;
2254
2255 init_irq_alloc_info(&info, NULL);
2256 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2257 info.ioapic_id = mpc_ioapic_id(ioapic);
2258 parent = irq_remapping_get_ir_irq_domain(&info);
2259 if (!parent)
2260 parent = x86_vector_domain;
2261 else
2262 name = "IO-APIC-IR";
2263
2264 /* Handle device tree enumerated APICs proper */
2265 if (cfg->dev) {
2266 fn = of_node_to_fwnode(cfg->dev);
2267 } else {
2268 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2269 if (!fn)
2270 return -ENOMEM;
2271 }
2272
2273 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2274 (void *)(long)ioapic);
2275
2276 /* Release fw handle if it was allocated above */
2277 if (!cfg->dev)
2278 irq_domain_free_fwnode(fn);
2279
2280 if (!ip->irqdomain)
2281 return -ENOMEM;
2282
2283 ip->irqdomain->parent = parent;
2284
2285 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2286 cfg->type == IOAPIC_DOMAIN_STRICT)
2287 ioapic_dynirq_base = max(ioapic_dynirq_base,
2288 gsi_cfg->gsi_end + 1);
2289
2290 return 0;
2291}
2292
2293static void ioapic_destroy_irqdomain(int idx)
2294{
2295 if (ioapics[idx].irqdomain) {
2296 irq_domain_remove(ioapics[idx].irqdomain);
2297 ioapics[idx].irqdomain = NULL;
2298 }
2299}
2300
2301void __init setup_IO_APIC(void)
2302{
2303 int ioapic;
2304
2305 if (skip_ioapic_setup || !nr_ioapics)
2306 return;
2307
2308 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2309
2310 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2311 for_each_ioapic(ioapic)
2312 BUG_ON(mp_irqdomain_create(ioapic));
2313
2314 /*
2315 * Set up IO-APIC IRQ routing.
2316 */
2317 x86_init.mpparse.setup_ioapic_ids();
2318
2319 sync_Arb_IDs();
2320 setup_IO_APIC_irqs();
2321 init_IO_APIC_traps();
2322 if (nr_legacy_irqs())
2323 check_timer();
2324
2325 ioapic_initialized = 1;
2326}
2327
2328static void resume_ioapic_id(int ioapic_idx)
2329{
2330 unsigned long flags;
2331 union IO_APIC_reg_00 reg_00;
2332
2333 raw_spin_lock_irqsave(&ioapic_lock, flags);
2334 reg_00.raw = io_apic_read(ioapic_idx, 0);
2335 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2336 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2337 io_apic_write(ioapic_idx, 0, reg_00.raw);
2338 }
2339 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2340}
2341
2342static void ioapic_resume(void)
2343{
2344 int ioapic_idx;
2345
2346 for_each_ioapic_reverse(ioapic_idx)
2347 resume_ioapic_id(ioapic_idx);
2348
2349 restore_ioapic_entries();
2350}
2351
2352static struct syscore_ops ioapic_syscore_ops = {
2353 .suspend = save_ioapic_entries,
2354 .resume = ioapic_resume,
2355};
2356
2357static int __init ioapic_init_ops(void)
2358{
2359 register_syscore_ops(&ioapic_syscore_ops);
2360
2361 return 0;
2362}
2363
2364device_initcall(ioapic_init_ops);
2365
2366static int io_apic_get_redir_entries(int ioapic)
2367{
2368 union IO_APIC_reg_01 reg_01;
2369 unsigned long flags;
2370
2371 raw_spin_lock_irqsave(&ioapic_lock, flags);
2372 reg_01.raw = io_apic_read(ioapic, 1);
2373 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2374
2375 /* The register returns the maximum index redir index
2376 * supported, which is one less than the total number of redir
2377 * entries.
2378 */
2379 return reg_01.bits.entries + 1;
2380}
2381
2382unsigned int arch_dynirq_lower_bound(unsigned int from)
2383{
2384 /*
2385 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2386 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2387 */
2388 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2389}
2390
2391#ifdef CONFIG_X86_32
2392static int io_apic_get_unique_id(int ioapic, int apic_id)
2393{
2394 union IO_APIC_reg_00 reg_00;
2395 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2396 physid_mask_t tmp;
2397 unsigned long flags;
2398 int i = 0;
2399
2400 /*
2401 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2402 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2403 * supports up to 16 on one shared APIC bus.
2404 *
2405 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2406 * advantage of new APIC bus architecture.
2407 */
2408
2409 if (physids_empty(apic_id_map))
2410 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2411
2412 raw_spin_lock_irqsave(&ioapic_lock, flags);
2413 reg_00.raw = io_apic_read(ioapic, 0);
2414 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2415
2416 if (apic_id >= get_physical_broadcast()) {
2417 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2418 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2419 apic_id = reg_00.bits.ID;
2420 }
2421
2422 /*
2423 * Every APIC in a system must have a unique ID or we get lots of nice
2424 * 'stuck on smp_invalidate_needed IPI wait' messages.
2425 */
2426 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2427
2428 for (i = 0; i < get_physical_broadcast(); i++) {
2429 if (!apic->check_apicid_used(&apic_id_map, i))
2430 break;
2431 }
2432
2433 if (i == get_physical_broadcast())
2434 panic("Max apic_id exceeded!\n");
2435
2436 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2437 "trying %d\n", ioapic, apic_id, i);
2438
2439 apic_id = i;
2440 }
2441
2442 apic->apicid_to_cpu_present(apic_id, &tmp);
2443 physids_or(apic_id_map, apic_id_map, tmp);
2444
2445 if (reg_00.bits.ID != apic_id) {
2446 reg_00.bits.ID = apic_id;
2447
2448 raw_spin_lock_irqsave(&ioapic_lock, flags);
2449 io_apic_write(ioapic, 0, reg_00.raw);
2450 reg_00.raw = io_apic_read(ioapic, 0);
2451 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2452
2453 /* Sanity check */
2454 if (reg_00.bits.ID != apic_id) {
2455 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2456 ioapic);
2457 return -1;
2458 }
2459 }
2460
2461 apic_printk(APIC_VERBOSE, KERN_INFO
2462 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2463
2464 return apic_id;
2465}
2466
2467static u8 io_apic_unique_id(int idx, u8 id)
2468{
2469 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2470 !APIC_XAPIC(boot_cpu_apic_version))
2471 return io_apic_get_unique_id(idx, id);
2472 else
2473 return id;
2474}
2475#else
2476static u8 io_apic_unique_id(int idx, u8 id)
2477{
2478 union IO_APIC_reg_00 reg_00;
2479 DECLARE_BITMAP(used, 256);
2480 unsigned long flags;
2481 u8 new_id;
2482 int i;
2483
2484 bitmap_zero(used, 256);
2485 for_each_ioapic(i)
2486 __set_bit(mpc_ioapic_id(i), used);
2487
2488 /* Hand out the requested id if available */
2489 if (!test_bit(id, used))
2490 return id;
2491
2492 /*
2493 * Read the current id from the ioapic and keep it if
2494 * available.
2495 */
2496 raw_spin_lock_irqsave(&ioapic_lock, flags);
2497 reg_00.raw = io_apic_read(idx, 0);
2498 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2499 new_id = reg_00.bits.ID;
2500 if (!test_bit(new_id, used)) {
2501 apic_printk(APIC_VERBOSE, KERN_INFO
2502 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2503 idx, new_id, id);
2504 return new_id;
2505 }
2506
2507 /*
2508 * Get the next free id and write it to the ioapic.
2509 */
2510 new_id = find_first_zero_bit(used, 256);
2511 reg_00.bits.ID = new_id;
2512 raw_spin_lock_irqsave(&ioapic_lock, flags);
2513 io_apic_write(idx, 0, reg_00.raw);
2514 reg_00.raw = io_apic_read(idx, 0);
2515 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2516 /* Sanity check */
2517 BUG_ON(reg_00.bits.ID != new_id);
2518
2519 return new_id;
2520}
2521#endif
2522
2523static int io_apic_get_version(int ioapic)
2524{
2525 union IO_APIC_reg_01 reg_01;
2526 unsigned long flags;
2527
2528 raw_spin_lock_irqsave(&ioapic_lock, flags);
2529 reg_01.raw = io_apic_read(ioapic, 1);
2530 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2531
2532 return reg_01.bits.version;
2533}
2534
2535int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2536{
2537 int ioapic, pin, idx;
2538
2539 if (skip_ioapic_setup)
2540 return -1;
2541
2542 ioapic = mp_find_ioapic(gsi);
2543 if (ioapic < 0)
2544 return -1;
2545
2546 pin = mp_find_ioapic_pin(ioapic, gsi);
2547 if (pin < 0)
2548 return -1;
2549
2550 idx = find_irq_entry(ioapic, pin, mp_INT);
2551 if (idx < 0)
2552 return -1;
2553
2554 *trigger = irq_trigger(idx);
2555 *polarity = irq_polarity(idx);
2556 return 0;
2557}
2558
2559/*
2560 * This function updates target affinity of IOAPIC interrupts to include
2561 * the CPUs which came online during SMP bringup.
2562 */
2563#define IOAPIC_RESOURCE_NAME_SIZE 11
2564
2565static struct resource *ioapic_resources;
2566
2567static struct resource * __init ioapic_setup_resources(void)
2568{
2569 unsigned long n;
2570 struct resource *res;
2571 char *mem;
2572 int i;
2573
2574 if (nr_ioapics == 0)
2575 return NULL;
2576
2577 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2578 n *= nr_ioapics;
2579
2580 mem = alloc_bootmem(n);
2581 res = (void *)mem;
2582
2583 mem += sizeof(struct resource) * nr_ioapics;
2584
2585 for_each_ioapic(i) {
2586 res[i].name = mem;
2587 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2588 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2589 mem += IOAPIC_RESOURCE_NAME_SIZE;
2590 ioapics[i].iomem_res = &res[i];
2591 }
2592
2593 ioapic_resources = res;
2594
2595 return res;
2596}
2597
2598void __init io_apic_init_mappings(void)
2599{
2600 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2601 struct resource *ioapic_res;
2602 int i;
2603
2604 ioapic_res = ioapic_setup_resources();
2605 for_each_ioapic(i) {
2606 if (smp_found_config) {
2607 ioapic_phys = mpc_ioapic_addr(i);
2608#ifdef CONFIG_X86_32
2609 if (!ioapic_phys) {
2610 printk(KERN_ERR
2611 "WARNING: bogus zero IO-APIC "
2612 "address found in MPTABLE, "
2613 "disabling IO/APIC support!\n");
2614 smp_found_config = 0;
2615 skip_ioapic_setup = 1;
2616 goto fake_ioapic_page;
2617 }
2618#endif
2619 } else {
2620#ifdef CONFIG_X86_32
2621fake_ioapic_page:
2622#endif
2623 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2624 ioapic_phys = __pa(ioapic_phys);
2625 }
2626 set_fixmap_nocache(idx, ioapic_phys);
2627 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2628 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2629 ioapic_phys);
2630 idx++;
2631
2632 ioapic_res->start = ioapic_phys;
2633 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2634 ioapic_res++;
2635 }
2636}
2637
2638void __init ioapic_insert_resources(void)
2639{
2640 int i;
2641 struct resource *r = ioapic_resources;
2642
2643 if (!r) {
2644 if (nr_ioapics > 0)
2645 printk(KERN_ERR
2646 "IO APIC resources couldn't be allocated.\n");
2647 return;
2648 }
2649
2650 for_each_ioapic(i) {
2651 insert_resource(&iomem_resource, r);
2652 r++;
2653 }
2654}
2655
2656int mp_find_ioapic(u32 gsi)
2657{
2658 int i;
2659
2660 if (nr_ioapics == 0)
2661 return -1;
2662
2663 /* Find the IOAPIC that manages this GSI. */
2664 for_each_ioapic(i) {
2665 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2666 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2667 return i;
2668 }
2669
2670 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2671 return -1;
2672}
2673
2674int mp_find_ioapic_pin(int ioapic, u32 gsi)
2675{
2676 struct mp_ioapic_gsi *gsi_cfg;
2677
2678 if (WARN_ON(ioapic < 0))
2679 return -1;
2680
2681 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2682 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2683 return -1;
2684
2685 return gsi - gsi_cfg->gsi_base;
2686}
2687
2688static int bad_ioapic_register(int idx)
2689{
2690 union IO_APIC_reg_00 reg_00;
2691 union IO_APIC_reg_01 reg_01;
2692 union IO_APIC_reg_02 reg_02;
2693
2694 reg_00.raw = io_apic_read(idx, 0);
2695 reg_01.raw = io_apic_read(idx, 1);
2696 reg_02.raw = io_apic_read(idx, 2);
2697
2698 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2699 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2700 mpc_ioapic_addr(idx));
2701 return 1;
2702 }
2703
2704 return 0;
2705}
2706
2707static int find_free_ioapic_entry(void)
2708{
2709 int idx;
2710
2711 for (idx = 0; idx < MAX_IO_APICS; idx++)
2712 if (ioapics[idx].nr_registers == 0)
2713 return idx;
2714
2715 return MAX_IO_APICS;
2716}
2717
2718/**
2719 * mp_register_ioapic - Register an IOAPIC device
2720 * @id: hardware IOAPIC ID
2721 * @address: physical address of IOAPIC register area
2722 * @gsi_base: base of GSI associated with the IOAPIC
2723 * @cfg: configuration information for the IOAPIC
2724 */
2725int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2726 struct ioapic_domain_cfg *cfg)
2727{
2728 bool hotplug = !!ioapic_initialized;
2729 struct mp_ioapic_gsi *gsi_cfg;
2730 int idx, ioapic, entries;
2731 u32 gsi_end;
2732
2733 if (!address) {
2734 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2735 return -EINVAL;
2736 }
2737 for_each_ioapic(ioapic)
2738 if (ioapics[ioapic].mp_config.apicaddr == address) {
2739 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2740 address, ioapic);
2741 return -EEXIST;
2742 }
2743
2744 idx = find_free_ioapic_entry();
2745 if (idx >= MAX_IO_APICS) {
2746 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2747 MAX_IO_APICS, idx);
2748 return -ENOSPC;
2749 }
2750
2751 ioapics[idx].mp_config.type = MP_IOAPIC;
2752 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2753 ioapics[idx].mp_config.apicaddr = address;
2754
2755 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2756 if (bad_ioapic_register(idx)) {
2757 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2758 return -ENODEV;
2759 }
2760
2761 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2762 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2763
2764 /*
2765 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2766 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2767 */
2768 entries = io_apic_get_redir_entries(idx);
2769 gsi_end = gsi_base + entries - 1;
2770 for_each_ioapic(ioapic) {
2771 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2772 if ((gsi_base >= gsi_cfg->gsi_base &&
2773 gsi_base <= gsi_cfg->gsi_end) ||
2774 (gsi_end >= gsi_cfg->gsi_base &&
2775 gsi_end <= gsi_cfg->gsi_end)) {
2776 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2777 gsi_base, gsi_end,
2778 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2779 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2780 return -ENOSPC;
2781 }
2782 }
2783 gsi_cfg = mp_ioapic_gsi_routing(idx);
2784 gsi_cfg->gsi_base = gsi_base;
2785 gsi_cfg->gsi_end = gsi_end;
2786
2787 ioapics[idx].irqdomain = NULL;
2788 ioapics[idx].irqdomain_cfg = *cfg;
2789
2790 /*
2791 * If mp_register_ioapic() is called during early boot stage when
2792 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2793 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2794 */
2795 if (hotplug) {
2796 if (mp_irqdomain_create(idx)) {
2797 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2798 return -ENOMEM;
2799 }
2800 alloc_ioapic_saved_registers(idx);
2801 }
2802
2803 if (gsi_cfg->gsi_end >= gsi_top)
2804 gsi_top = gsi_cfg->gsi_end + 1;
2805 if (nr_ioapics <= idx)
2806 nr_ioapics = idx + 1;
2807
2808 /* Set nr_registers to mark entry present */
2809 ioapics[idx].nr_registers = entries;
2810
2811 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2812 idx, mpc_ioapic_id(idx),
2813 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2814 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2815
2816 return 0;
2817}
2818
2819int mp_unregister_ioapic(u32 gsi_base)
2820{
2821 int ioapic, pin;
2822 int found = 0;
2823
2824 for_each_ioapic(ioapic)
2825 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2826 found = 1;
2827 break;
2828 }
2829 if (!found) {
2830 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2831 return -ENODEV;
2832 }
2833
2834 for_each_pin(ioapic, pin) {
2835 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2836 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2837 struct mp_chip_data *data;
2838
2839 if (irq >= 0) {
2840 data = irq_get_chip_data(irq);
2841 if (data && data->count) {
2842 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2843 pin, ioapic);
2844 return -EBUSY;
2845 }
2846 }
2847 }
2848
2849 /* Mark entry not present */
2850 ioapics[ioapic].nr_registers = 0;
2851 ioapic_destroy_irqdomain(ioapic);
2852 free_ioapic_saved_registers(ioapic);
2853 if (ioapics[ioapic].iomem_res)
2854 release_resource(ioapics[ioapic].iomem_res);
2855 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2856 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2857
2858 return 0;
2859}
2860
2861int mp_ioapic_registered(u32 gsi_base)
2862{
2863 int ioapic;
2864
2865 for_each_ioapic(ioapic)
2866 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2867 return 1;
2868
2869 return 0;
2870}
2871
2872static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2873 struct irq_alloc_info *info)
2874{
2875 if (info && info->ioapic_valid) {
2876 data->trigger = info->ioapic_trigger;
2877 data->polarity = info->ioapic_polarity;
2878 } else if (acpi_get_override_irq(gsi, &data->trigger,
2879 &data->polarity) < 0) {
2880 /* PCI interrupts are always active low level triggered. */
2881 data->trigger = IOAPIC_LEVEL;
2882 data->polarity = IOAPIC_POL_LOW;
2883 }
2884}
2885
2886static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2887 struct IO_APIC_route_entry *entry)
2888{
2889 memset(entry, 0, sizeof(*entry));
2890 entry->delivery_mode = apic->irq_delivery_mode;
2891 entry->dest_mode = apic->irq_dest_mode;
2892 entry->dest = cfg->dest_apicid;
2893 entry->vector = cfg->vector;
2894 entry->trigger = data->trigger;
2895 entry->polarity = data->polarity;
2896 /*
2897 * Mask level triggered irqs. Edge triggered irqs are masked
2898 * by the irq core code in case they fire.
2899 */
2900 if (data->trigger == IOAPIC_LEVEL)
2901 entry->mask = IOAPIC_MASKED;
2902 else
2903 entry->mask = IOAPIC_UNMASKED;
2904}
2905
2906int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2907 unsigned int nr_irqs, void *arg)
2908{
2909 int ret, ioapic, pin;
2910 struct irq_cfg *cfg;
2911 struct irq_data *irq_data;
2912 struct mp_chip_data *data;
2913 struct irq_alloc_info *info = arg;
2914 unsigned long flags;
2915
2916 if (!info || nr_irqs > 1)
2917 return -EINVAL;
2918 irq_data = irq_domain_get_irq_data(domain, virq);
2919 if (!irq_data)
2920 return -EINVAL;
2921
2922 ioapic = mp_irqdomain_ioapic_idx(domain);
2923 pin = info->ioapic_pin;
2924 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2925 return -EEXIST;
2926
2927 data = kzalloc(sizeof(*data), GFP_KERNEL);
2928 if (!data)
2929 return -ENOMEM;
2930
2931 info->ioapic_entry = &data->entry;
2932 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2933 if (ret < 0) {
2934 kfree(data);
2935 return ret;
2936 }
2937
2938 INIT_LIST_HEAD(&data->irq_2_pin);
2939 irq_data->hwirq = info->ioapic_pin;
2940 irq_data->chip = (domain->parent == x86_vector_domain) ?
2941 &ioapic_chip : &ioapic_ir_chip;
2942 irq_data->chip_data = data;
2943 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2944
2945 cfg = irqd_cfg(irq_data);
2946 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2947
2948 local_irq_save(flags);
2949 if (info->ioapic_entry)
2950 mp_setup_entry(cfg, data, info->ioapic_entry);
2951 mp_register_handler(virq, data->trigger);
2952 if (virq < nr_legacy_irqs())
2953 legacy_pic->mask(virq);
2954 local_irq_restore(flags);
2955
2956 apic_printk(APIC_VERBOSE, KERN_DEBUG
2957 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2958 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2959 virq, data->trigger, data->polarity, cfg->dest_apicid);
2960
2961 return 0;
2962}
2963
2964void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2965 unsigned int nr_irqs)
2966{
2967 struct irq_data *irq_data;
2968 struct mp_chip_data *data;
2969
2970 BUG_ON(nr_irqs != 1);
2971 irq_data = irq_domain_get_irq_data(domain, virq);
2972 if (irq_data && irq_data->chip_data) {
2973 data = irq_data->chip_data;
2974 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2975 (int)irq_data->hwirq);
2976 WARN_ON(!list_empty(&data->irq_2_pin));
2977 kfree(irq_data->chip_data);
2978 }
2979 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2980}
2981
2982int mp_irqdomain_activate(struct irq_domain *domain,
2983 struct irq_data *irq_data, bool reserve)
2984{
2985 unsigned long flags;
2986
2987 raw_spin_lock_irqsave(&ioapic_lock, flags);
2988 ioapic_configure_entry(irq_data);
2989 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2990 return 0;
2991}
2992
2993void mp_irqdomain_deactivate(struct irq_domain *domain,
2994 struct irq_data *irq_data)
2995{
2996 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2997 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
2998 (int)irq_data->hwirq);
2999}
3000
3001int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3002{
3003 return (int)(long)domain->host_data;
3004}
3005
3006const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3007 .alloc = mp_irqdomain_alloc,
3008 .free = mp_irqdomain_free,
3009 .activate = mp_irqdomain_activate,
3010 .deactivate = mp_irqdomain_deactivate,
3011};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51#include <linux/msi.h>
52
53#include <asm/irqdomain.h>
54#include <asm/io.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/desc.h>
58#include <asm/proto.h>
59#include <asm/acpi.h>
60#include <asm/dma.h>
61#include <asm/timer.h>
62#include <asm/time.h>
63#include <asm/i8259.h>
64#include <asm/setup.h>
65#include <asm/irq_remapping.h>
66#include <asm/hw_irq.h>
67#include <asm/apic.h>
68
69#define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71#define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73#define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75#define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78#define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
80
81static DEFINE_RAW_SPINLOCK(ioapic_lock);
82static DEFINE_MUTEX(ioapic_mutex);
83static unsigned int ioapic_dynirq_base;
84static int ioapic_initialized;
85
86struct irq_pin_list {
87 struct list_head list;
88 int apic, pin;
89};
90
91struct mp_chip_data {
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
94 bool is_level;
95 bool active_low;
96 bool isa_irq;
97 u32 count;
98};
99
100struct mp_ioapic_gsi {
101 u32 gsi_base;
102 u32 gsi_end;
103};
104
105static struct ioapic {
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_registers;
110 /*
111 * Saved state during suspend/resume, or while enabling intr-remap.
112 */
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121} ioapics[MAX_IO_APICS];
122
123#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124
125int mpc_ioapic_id(int ioapic_idx)
126{
127 return ioapics[ioapic_idx].mp_config.apicid;
128}
129
130unsigned int mpc_ioapic_addr(int ioapic_idx)
131{
132 return ioapics[ioapic_idx].mp_config.apicaddr;
133}
134
135static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136{
137 return &ioapics[ioapic_idx].gsi_config;
138}
139
140static inline int mp_ioapic_pin_count(int ioapic)
141{
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145}
146
147static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148{
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150}
151
152static inline bool mp_is_legacy_irq(int irq)
153{
154 return irq >= 0 && irq < nr_legacy_irqs();
155}
156
157static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
158{
159 return ioapics[ioapic].irqdomain;
160}
161
162int nr_ioapics;
163
164/* The one past the highest gsi number used */
165u32 gsi_top;
166
167/* MP IRQ source entries */
168struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
169
170/* # of MP IRQ source entries */
171int mp_irq_entries;
172
173#ifdef CONFIG_EISA
174int mp_bus_id_to_type[MAX_MP_BUSSES];
175#endif
176
177DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
178
179int skip_ioapic_setup;
180
181/**
182 * disable_ioapic_support() - disables ioapic support at runtime
183 */
184void disable_ioapic_support(void)
185{
186#ifdef CONFIG_PCI
187 noioapicquirk = 1;
188 noioapicreroute = -1;
189#endif
190 skip_ioapic_setup = 1;
191}
192
193static int __init parse_noapic(char *str)
194{
195 /* disable IO-APIC */
196 disable_ioapic_support();
197 return 0;
198}
199early_param("noapic", parse_noapic);
200
201/* Will be called in mpparse/ACPI codes for saving IRQ info */
202void mp_save_irq(struct mpc_intsrc *m)
203{
204 int i;
205
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
210
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
213 return;
214 }
215
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
219}
220
221static void alloc_ioapic_saved_registers(int idx)
222{
223 size_t size;
224
225 if (ioapics[idx].saved_registers)
226 return;
227
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
232}
233
234static void free_ioapic_saved_registers(int idx)
235{
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
238}
239
240int __init arch_early_ioapic_init(void)
241{
242 int i;
243
244 if (!nr_legacy_irqs())
245 io_apic_irqs = ~0UL;
246
247 for_each_ioapic(i)
248 alloc_ioapic_saved_registers(i);
249
250 return 0;
251}
252
253struct io_apic {
254 unsigned int index;
255 unsigned int unused[3];
256 unsigned int data;
257 unsigned int unused2[11];
258 unsigned int eoi;
259};
260
261static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
262{
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
265}
266
267static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
268{
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
271}
272
273unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
274{
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
278}
279
280static void io_apic_write(unsigned int apic, unsigned int reg,
281 unsigned int value)
282{
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
284
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
287}
288
289static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
290{
291 struct IO_APIC_route_entry entry;
292
293 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
294 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
295
296 return entry;
297}
298
299static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
300{
301 struct IO_APIC_route_entry entry;
302 unsigned long flags;
303
304 raw_spin_lock_irqsave(&ioapic_lock, flags);
305 entry = __ioapic_read_entry(apic, pin);
306 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
307
308 return entry;
309}
310
311/*
312 * When we write a new IO APIC routing entry, we need to write the high
313 * word first! If the mask bit in the low word is clear, we will enable
314 * the interrupt, and we need to make sure the entry is fully populated
315 * before that happens.
316 */
317static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
318{
319 io_apic_write(apic, 0x11 + 2*pin, e.w2);
320 io_apic_write(apic, 0x10 + 2*pin, e.w1);
321}
322
323static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
324{
325 unsigned long flags;
326
327 raw_spin_lock_irqsave(&ioapic_lock, flags);
328 __ioapic_write_entry(apic, pin, e);
329 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
330}
331
332/*
333 * When we mask an IO APIC routing entry, we need to write the low
334 * word first, in order to set the mask bit before we change the
335 * high bits!
336 */
337static void ioapic_mask_entry(int apic, int pin)
338{
339 struct IO_APIC_route_entry e = { .masked = true };
340 unsigned long flags;
341
342 raw_spin_lock_irqsave(&ioapic_lock, flags);
343 io_apic_write(apic, 0x10 + 2*pin, e.w1);
344 io_apic_write(apic, 0x11 + 2*pin, e.w2);
345 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
346}
347
348/*
349 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
350 * shared ISA-space IRQs, so we have to support them. We are super
351 * fast in the common case, and fast for shared ISA-space IRQs.
352 */
353static int __add_pin_to_irq_node(struct mp_chip_data *data,
354 int node, int apic, int pin)
355{
356 struct irq_pin_list *entry;
357
358 /* don't allow duplicates */
359 for_each_irq_pin(entry, data->irq_2_pin)
360 if (entry->apic == apic && entry->pin == pin)
361 return 0;
362
363 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
364 if (!entry) {
365 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
366 node, apic, pin);
367 return -ENOMEM;
368 }
369 entry->apic = apic;
370 entry->pin = pin;
371 list_add_tail(&entry->list, &data->irq_2_pin);
372
373 return 0;
374}
375
376static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
377{
378 struct irq_pin_list *tmp, *entry;
379
380 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
381 if (entry->apic == apic && entry->pin == pin) {
382 list_del(&entry->list);
383 kfree(entry);
384 return;
385 }
386}
387
388static void add_pin_to_irq_node(struct mp_chip_data *data,
389 int node, int apic, int pin)
390{
391 if (__add_pin_to_irq_node(data, node, apic, pin))
392 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
393}
394
395/*
396 * Reroute an IRQ to a different pin.
397 */
398static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
399 int oldapic, int oldpin,
400 int newapic, int newpin)
401{
402 struct irq_pin_list *entry;
403
404 for_each_irq_pin(entry, data->irq_2_pin) {
405 if (entry->apic == oldapic && entry->pin == oldpin) {
406 entry->apic = newapic;
407 entry->pin = newpin;
408 /* every one is different, right? */
409 return;
410 }
411 }
412
413 /* old apic/pin didn't exist, so just add new ones */
414 add_pin_to_irq_node(data, node, newapic, newpin);
415}
416
417static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
418 void (*final)(struct irq_pin_list *entry))
419{
420 struct irq_pin_list *entry;
421
422 data->entry.masked = masked;
423
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
426 if (final)
427 final(entry);
428 }
429}
430
431static void io_apic_sync(struct irq_pin_list *entry)
432{
433 /*
434 * Synchronize the IO-APIC and the CPU by doing
435 * a dummy read from the IO-APIC
436 */
437 struct io_apic __iomem *io_apic;
438
439 io_apic = io_apic_base(entry->apic);
440 readl(&io_apic->data);
441}
442
443static void mask_ioapic_irq(struct irq_data *irq_data)
444{
445 struct mp_chip_data *data = irq_data->chip_data;
446 unsigned long flags;
447
448 raw_spin_lock_irqsave(&ioapic_lock, flags);
449 io_apic_modify_irq(data, true, &io_apic_sync);
450 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
451}
452
453static void __unmask_ioapic(struct mp_chip_data *data)
454{
455 io_apic_modify_irq(data, false, NULL);
456}
457
458static void unmask_ioapic_irq(struct irq_data *irq_data)
459{
460 struct mp_chip_data *data = irq_data->chip_data;
461 unsigned long flags;
462
463 raw_spin_lock_irqsave(&ioapic_lock, flags);
464 __unmask_ioapic(data);
465 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
466}
467
468/*
469 * IO-APIC versions below 0x20 don't support EOI register.
470 * For the record, here is the information about various versions:
471 * 0Xh 82489DX
472 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
473 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
474 * 30h-FFh Reserved
475 *
476 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
477 * version as 0x2. This is an error with documentation and these ICH chips
478 * use io-apic's of version 0x20.
479 *
480 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
481 * Otherwise, we simulate the EOI message manually by changing the trigger
482 * mode to edge and then back to level, with RTE being masked during this.
483 */
484static void __eoi_ioapic_pin(int apic, int pin, int vector)
485{
486 if (mpc_ioapic_ver(apic) >= 0x20) {
487 io_apic_eoi(apic, vector);
488 } else {
489 struct IO_APIC_route_entry entry, entry1;
490
491 entry = entry1 = __ioapic_read_entry(apic, pin);
492
493 /*
494 * Mask the entry and change the trigger mode to edge.
495 */
496 entry1.masked = true;
497 entry1.is_level = false;
498
499 __ioapic_write_entry(apic, pin, entry1);
500
501 /*
502 * Restore the previous level triggered entry.
503 */
504 __ioapic_write_entry(apic, pin, entry);
505 }
506}
507
508static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
509{
510 unsigned long flags;
511 struct irq_pin_list *entry;
512
513 raw_spin_lock_irqsave(&ioapic_lock, flags);
514 for_each_irq_pin(entry, data->irq_2_pin)
515 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
516 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
517}
518
519static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
520{
521 struct IO_APIC_route_entry entry;
522
523 /* Check delivery_mode to be sure we're not clearing an SMI pin */
524 entry = ioapic_read_entry(apic, pin);
525 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
526 return;
527
528 /*
529 * Make sure the entry is masked and re-read the contents to check
530 * if it is a level triggered pin and if the remote-IRR is set.
531 */
532 if (!entry.masked) {
533 entry.masked = true;
534 ioapic_write_entry(apic, pin, entry);
535 entry = ioapic_read_entry(apic, pin);
536 }
537
538 if (entry.irr) {
539 unsigned long flags;
540
541 /*
542 * Make sure the trigger mode is set to level. Explicit EOI
543 * doesn't clear the remote-IRR if the trigger mode is not
544 * set to level.
545 */
546 if (!entry.is_level) {
547 entry.is_level = true;
548 ioapic_write_entry(apic, pin, entry);
549 }
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __eoi_ioapic_pin(apic, pin, entry.vector);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
553 }
554
555 /*
556 * Clear the rest of the bits in the IO-APIC RTE except for the mask
557 * bit.
558 */
559 ioapic_mask_entry(apic, pin);
560 entry = ioapic_read_entry(apic, pin);
561 if (entry.irr)
562 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
563 mpc_ioapic_id(apic), pin);
564}
565
566void clear_IO_APIC (void)
567{
568 int apic, pin;
569
570 for_each_ioapic_pin(apic, pin)
571 clear_IO_APIC_pin(apic, pin);
572}
573
574#ifdef CONFIG_X86_32
575/*
576 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
577 * specific CPU-side IRQs.
578 */
579
580#define MAX_PIRQS 8
581static int pirq_entries[MAX_PIRQS] = {
582 [0 ... MAX_PIRQS - 1] = -1
583};
584
585static int __init ioapic_pirq_setup(char *str)
586{
587 int i, max;
588 int ints[MAX_PIRQS+1];
589
590 get_options(str, ARRAY_SIZE(ints), ints);
591
592 apic_printk(APIC_VERBOSE, KERN_INFO
593 "PIRQ redirection, working around broken MP-BIOS.\n");
594 max = MAX_PIRQS;
595 if (ints[0] < MAX_PIRQS)
596 max = ints[0];
597
598 for (i = 0; i < max; i++) {
599 apic_printk(APIC_VERBOSE, KERN_DEBUG
600 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
601 /*
602 * PIRQs are mapped upside down, usually.
603 */
604 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
605 }
606 return 1;
607}
608
609__setup("pirq=", ioapic_pirq_setup);
610#endif /* CONFIG_X86_32 */
611
612/*
613 * Saves all the IO-APIC RTE's
614 */
615int save_ioapic_entries(void)
616{
617 int apic, pin;
618 int err = 0;
619
620 for_each_ioapic(apic) {
621 if (!ioapics[apic].saved_registers) {
622 err = -ENOMEM;
623 continue;
624 }
625
626 for_each_pin(apic, pin)
627 ioapics[apic].saved_registers[pin] =
628 ioapic_read_entry(apic, pin);
629 }
630
631 return err;
632}
633
634/*
635 * Mask all IO APIC entries.
636 */
637void mask_ioapic_entries(void)
638{
639 int apic, pin;
640
641 for_each_ioapic(apic) {
642 if (!ioapics[apic].saved_registers)
643 continue;
644
645 for_each_pin(apic, pin) {
646 struct IO_APIC_route_entry entry;
647
648 entry = ioapics[apic].saved_registers[pin];
649 if (!entry.masked) {
650 entry.masked = true;
651 ioapic_write_entry(apic, pin, entry);
652 }
653 }
654 }
655}
656
657/*
658 * Restore IO APIC entries which was saved in the ioapic structure.
659 */
660int restore_ioapic_entries(void)
661{
662 int apic, pin;
663
664 for_each_ioapic(apic) {
665 if (!ioapics[apic].saved_registers)
666 continue;
667
668 for_each_pin(apic, pin)
669 ioapic_write_entry(apic, pin,
670 ioapics[apic].saved_registers[pin]);
671 }
672 return 0;
673}
674
675/*
676 * Find the IRQ entry number of a certain pin.
677 */
678static int find_irq_entry(int ioapic_idx, int pin, int type)
679{
680 int i;
681
682 for (i = 0; i < mp_irq_entries; i++)
683 if (mp_irqs[i].irqtype == type &&
684 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
685 mp_irqs[i].dstapic == MP_APIC_ALL) &&
686 mp_irqs[i].dstirq == pin)
687 return i;
688
689 return -1;
690}
691
692/*
693 * Find the pin to which IRQ[irq] (ISA) is connected
694 */
695static int __init find_isa_irq_pin(int irq, int type)
696{
697 int i;
698
699 for (i = 0; i < mp_irq_entries; i++) {
700 int lbus = mp_irqs[i].srcbus;
701
702 if (test_bit(lbus, mp_bus_not_pci) &&
703 (mp_irqs[i].irqtype == type) &&
704 (mp_irqs[i].srcbusirq == irq))
705
706 return mp_irqs[i].dstirq;
707 }
708 return -1;
709}
710
711static int __init find_isa_irq_apic(int irq, int type)
712{
713 int i;
714
715 for (i = 0; i < mp_irq_entries; i++) {
716 int lbus = mp_irqs[i].srcbus;
717
718 if (test_bit(lbus, mp_bus_not_pci) &&
719 (mp_irqs[i].irqtype == type) &&
720 (mp_irqs[i].srcbusirq == irq))
721 break;
722 }
723
724 if (i < mp_irq_entries) {
725 int ioapic_idx;
726
727 for_each_ioapic(ioapic_idx)
728 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
729 return ioapic_idx;
730 }
731
732 return -1;
733}
734
735static bool irq_active_low(int idx)
736{
737 int bus = mp_irqs[idx].srcbus;
738
739 /*
740 * Determine IRQ line polarity (high active or low active):
741 */
742 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
743 case MP_IRQPOL_DEFAULT:
744 /*
745 * Conforms to spec, ie. bus-type dependent polarity. PCI
746 * defaults to low active. [E]ISA defaults to high active.
747 */
748 return !test_bit(bus, mp_bus_not_pci);
749 case MP_IRQPOL_ACTIVE_HIGH:
750 return false;
751 case MP_IRQPOL_RESERVED:
752 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
753 fallthrough;
754 case MP_IRQPOL_ACTIVE_LOW:
755 default: /* Pointless default required due to do gcc stupidity */
756 return true;
757 }
758}
759
760#ifdef CONFIG_EISA
761/*
762 * EISA Edge/Level control register, ELCR
763 */
764static bool EISA_ELCR(unsigned int irq)
765{
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = 0x4d0 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
769 }
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
772 return false;
773}
774
775/*
776 * EISA interrupts are always active high and can be edge or level
777 * triggered depending on the ELCR value. If an interrupt is listed as
778 * EISA conforming in the MP table, that means its trigger type must be
779 * read in from the ELCR.
780 */
781static bool eisa_irq_is_level(int idx, int bus, bool level)
782{
783 switch (mp_bus_id_to_type[bus]) {
784 case MP_BUS_PCI:
785 case MP_BUS_ISA:
786 return level;
787 case MP_BUS_EISA:
788 return EISA_ELCR(mp_irqs[idx].srcbusirq);
789 }
790 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
791 return true;
792}
793#else
794static inline int eisa_irq_is_level(int idx, int bus, bool level)
795{
796 return level;
797}
798#endif
799
800static bool irq_is_level(int idx)
801{
802 int bus = mp_irqs[idx].srcbus;
803 bool level;
804
805 /*
806 * Determine IRQ trigger mode (edge or level sensitive):
807 */
808 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
809 case MP_IRQTRIG_DEFAULT:
810 /*
811 * Conforms to spec, ie. bus-type dependent trigger
812 * mode. PCI defaults to level, ISA to edge.
813 */
814 level = !test_bit(bus, mp_bus_not_pci);
815 /* Take EISA into account */
816 return eisa_irq_is_level(idx, bus, level);
817 case MP_IRQTRIG_EDGE:
818 return false;
819 case MP_IRQTRIG_RESERVED:
820 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
821 fallthrough;
822 case MP_IRQTRIG_LEVEL:
823 default: /* Pointless default required due to do gcc stupidity */
824 return true;
825 }
826}
827
828static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
829{
830 int ioapic, pin, idx;
831
832 if (skip_ioapic_setup)
833 return -1;
834
835 ioapic = mp_find_ioapic(gsi);
836 if (ioapic < 0)
837 return -1;
838
839 pin = mp_find_ioapic_pin(ioapic, gsi);
840 if (pin < 0)
841 return -1;
842
843 idx = find_irq_entry(ioapic, pin, mp_INT);
844 if (idx < 0)
845 return -1;
846
847 *trigger = irq_is_level(idx);
848 *polarity = irq_active_low(idx);
849 return 0;
850}
851
852#ifdef CONFIG_ACPI
853int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
854{
855 *is_level = *active_low = 0;
856 return __acpi_get_override_irq(gsi, (bool *)is_level,
857 (bool *)active_low);
858}
859#endif
860
861void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
862 int trigger, int polarity)
863{
864 init_irq_alloc_info(info, NULL);
865 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
866 info->ioapic.node = node;
867 info->ioapic.is_level = trigger;
868 info->ioapic.active_low = polarity;
869 info->ioapic.valid = 1;
870}
871
872static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
873 struct irq_alloc_info *src,
874 u32 gsi, int ioapic_idx, int pin)
875{
876 bool level, pol_low;
877
878 copy_irq_alloc_info(dst, src);
879 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
880 dst->devid = mpc_ioapic_id(ioapic_idx);
881 dst->ioapic.pin = pin;
882 dst->ioapic.valid = 1;
883 if (src && src->ioapic.valid) {
884 dst->ioapic.node = src->ioapic.node;
885 dst->ioapic.is_level = src->ioapic.is_level;
886 dst->ioapic.active_low = src->ioapic.active_low;
887 } else {
888 dst->ioapic.node = NUMA_NO_NODE;
889 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
890 dst->ioapic.is_level = level;
891 dst->ioapic.active_low = pol_low;
892 } else {
893 /*
894 * PCI interrupts are always active low level
895 * triggered.
896 */
897 dst->ioapic.is_level = true;
898 dst->ioapic.active_low = true;
899 }
900 }
901}
902
903static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
904{
905 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
906}
907
908static void mp_register_handler(unsigned int irq, bool level)
909{
910 irq_flow_handler_t hdl;
911 bool fasteoi;
912
913 if (level) {
914 irq_set_status_flags(irq, IRQ_LEVEL);
915 fasteoi = true;
916 } else {
917 irq_clear_status_flags(irq, IRQ_LEVEL);
918 fasteoi = false;
919 }
920
921 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
922 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
923}
924
925static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
926{
927 struct mp_chip_data *data = irq_get_chip_data(irq);
928
929 /*
930 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
931 * and polarity attributes. So allow the first user to reprogram the
932 * pin with real trigger and polarity attributes.
933 */
934 if (irq < nr_legacy_irqs() && data->count == 1) {
935 if (info->ioapic.is_level != data->is_level)
936 mp_register_handler(irq, info->ioapic.is_level);
937 data->entry.is_level = data->is_level = info->ioapic.is_level;
938 data->entry.active_low = data->active_low = info->ioapic.active_low;
939 }
940
941 return data->is_level == info->ioapic.is_level &&
942 data->active_low == info->ioapic.active_low;
943}
944
945static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
946 struct irq_alloc_info *info)
947{
948 bool legacy = false;
949 int irq = -1;
950 int type = ioapics[ioapic].irqdomain_cfg.type;
951
952 switch (type) {
953 case IOAPIC_DOMAIN_LEGACY:
954 /*
955 * Dynamically allocate IRQ number for non-ISA IRQs in the first
956 * 16 GSIs on some weird platforms.
957 */
958 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
959 irq = gsi;
960 legacy = mp_is_legacy_irq(irq);
961 break;
962 case IOAPIC_DOMAIN_STRICT:
963 irq = gsi;
964 break;
965 case IOAPIC_DOMAIN_DYNAMIC:
966 break;
967 default:
968 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
969 return -1;
970 }
971
972 return __irq_domain_alloc_irqs(domain, irq, 1,
973 ioapic_alloc_attr_node(info),
974 info, legacy, NULL);
975}
976
977/*
978 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
979 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
980 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
981 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
982 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
983 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
984 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
985 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
986 */
987static int alloc_isa_irq_from_domain(struct irq_domain *domain,
988 int irq, int ioapic, int pin,
989 struct irq_alloc_info *info)
990{
991 struct mp_chip_data *data;
992 struct irq_data *irq_data = irq_get_irq_data(irq);
993 int node = ioapic_alloc_attr_node(info);
994
995 /*
996 * Legacy ISA IRQ has already been allocated, just add pin to
997 * the pin list associated with this IRQ and program the IOAPIC
998 * entry. The IOAPIC entry
999 */
1000 if (irq_data && irq_data->parent_data) {
1001 if (!mp_check_pin_attr(irq, info))
1002 return -EBUSY;
1003 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1004 info->ioapic.pin))
1005 return -ENOMEM;
1006 } else {
1007 info->flags |= X86_IRQ_ALLOC_LEGACY;
1008 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1009 NULL);
1010 if (irq >= 0) {
1011 irq_data = irq_domain_get_irq_data(domain, irq);
1012 data = irq_data->chip_data;
1013 data->isa_irq = true;
1014 }
1015 }
1016
1017 return irq;
1018}
1019
1020static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1021 unsigned int flags, struct irq_alloc_info *info)
1022{
1023 int irq;
1024 bool legacy = false;
1025 struct irq_alloc_info tmp;
1026 struct mp_chip_data *data;
1027 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1028
1029 if (!domain)
1030 return -ENOSYS;
1031
1032 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1033 irq = mp_irqs[idx].srcbusirq;
1034 legacy = mp_is_legacy_irq(irq);
1035 /*
1036 * IRQ2 is unusable for historical reasons on systems which
1037 * have a legacy PIC. See the comment vs. IRQ2 further down.
1038 *
1039 * If this gets removed at some point then the related code
1040 * in lapic_assign_system_vectors() needs to be adjusted as
1041 * well.
1042 */
1043 if (legacy && irq == PIC_CASCADE_IR)
1044 return -EINVAL;
1045 }
1046
1047 mutex_lock(&ioapic_mutex);
1048 if (!(flags & IOAPIC_MAP_ALLOC)) {
1049 if (!legacy) {
1050 irq = irq_find_mapping(domain, pin);
1051 if (irq == 0)
1052 irq = -ENOENT;
1053 }
1054 } else {
1055 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1056 if (legacy)
1057 irq = alloc_isa_irq_from_domain(domain, irq,
1058 ioapic, pin, &tmp);
1059 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1060 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1061 else if (!mp_check_pin_attr(irq, &tmp))
1062 irq = -EBUSY;
1063 if (irq >= 0) {
1064 data = irq_get_chip_data(irq);
1065 data->count++;
1066 }
1067 }
1068 mutex_unlock(&ioapic_mutex);
1069
1070 return irq;
1071}
1072
1073static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1074{
1075 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1076
1077 /*
1078 * Debugging check, we are in big trouble if this message pops up!
1079 */
1080 if (mp_irqs[idx].dstirq != pin)
1081 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1082
1083#ifdef CONFIG_X86_32
1084 /*
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086 */
1087 if ((pin >= 16) && (pin <= 23)) {
1088 if (pirq_entries[pin-16] != -1) {
1089 if (!pirq_entries[pin-16]) {
1090 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin-16);
1092 } else {
1093 int irq = pirq_entries[pin-16];
1094 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1096 pin-16, irq);
1097 return irq;
1098 }
1099 }
1100 }
1101#endif
1102
1103 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1104}
1105
1106int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1107{
1108 int ioapic, pin, idx;
1109
1110 ioapic = mp_find_ioapic(gsi);
1111 if (ioapic < 0)
1112 return -ENODEV;
1113
1114 pin = mp_find_ioapic_pin(ioapic, gsi);
1115 idx = find_irq_entry(ioapic, pin, mp_INT);
1116 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1117 return -ENODEV;
1118
1119 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1120}
1121
1122void mp_unmap_irq(int irq)
1123{
1124 struct irq_data *irq_data = irq_get_irq_data(irq);
1125 struct mp_chip_data *data;
1126
1127 if (!irq_data || !irq_data->domain)
1128 return;
1129
1130 data = irq_data->chip_data;
1131 if (!data || data->isa_irq)
1132 return;
1133
1134 mutex_lock(&ioapic_mutex);
1135 if (--data->count == 0)
1136 irq_domain_free_irqs(irq, 1);
1137 mutex_unlock(&ioapic_mutex);
1138}
1139
1140/*
1141 * Find a specific PCI IRQ entry.
1142 * Not an __init, possibly needed by modules
1143 */
1144int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1145{
1146 int irq, i, best_ioapic = -1, best_idx = -1;
1147
1148 apic_printk(APIC_DEBUG,
1149 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1150 bus, slot, pin);
1151 if (test_bit(bus, mp_bus_not_pci)) {
1152 apic_printk(APIC_VERBOSE,
1153 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1154 return -1;
1155 }
1156
1157 for (i = 0; i < mp_irq_entries; i++) {
1158 int lbus = mp_irqs[i].srcbus;
1159 int ioapic_idx, found = 0;
1160
1161 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1162 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1163 continue;
1164
1165 for_each_ioapic(ioapic_idx)
1166 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1167 mp_irqs[i].dstapic == MP_APIC_ALL) {
1168 found = 1;
1169 break;
1170 }
1171 if (!found)
1172 continue;
1173
1174 /* Skip ISA IRQs */
1175 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1176 if (irq > 0 && !IO_APIC_IRQ(irq))
1177 continue;
1178
1179 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1180 best_idx = i;
1181 best_ioapic = ioapic_idx;
1182 goto out;
1183 }
1184
1185 /*
1186 * Use the first all-but-pin matching entry as a
1187 * best-guess fuzzy result for broken mptables.
1188 */
1189 if (best_idx < 0) {
1190 best_idx = i;
1191 best_ioapic = ioapic_idx;
1192 }
1193 }
1194 if (best_idx < 0)
1195 return -1;
1196
1197out:
1198 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1199 IOAPIC_MAP_ALLOC);
1200}
1201EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1202
1203static struct irq_chip ioapic_chip, ioapic_ir_chip;
1204
1205static void __init setup_IO_APIC_irqs(void)
1206{
1207 unsigned int ioapic, pin;
1208 int idx;
1209
1210 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211
1212 for_each_ioapic_pin(ioapic, pin) {
1213 idx = find_irq_entry(ioapic, pin, mp_INT);
1214 if (idx < 0)
1215 apic_printk(APIC_VERBOSE,
1216 KERN_DEBUG " apic %d pin %d not connected\n",
1217 mpc_ioapic_id(ioapic), pin);
1218 else
1219 pin_2_irq(idx, ioapic, pin,
1220 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1221 }
1222}
1223
1224void ioapic_zap_locks(void)
1225{
1226 raw_spin_lock_init(&ioapic_lock);
1227}
1228
1229static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1230{
1231 struct IO_APIC_route_entry entry;
1232 char buf[256];
1233 int i;
1234
1235 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1236 for (i = 0; i <= nr_entries; i++) {
1237 entry = ioapic_read_entry(apic, i);
1238 snprintf(buf, sizeof(buf),
1239 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1240 i,
1241 entry.masked ? "disabled" : "enabled ",
1242 entry.is_level ? "level" : "edge ",
1243 entry.active_low ? "low " : "high",
1244 entry.vector, entry.irr, entry.delivery_status);
1245 if (entry.ir_format) {
1246 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1247 buf,
1248 (entry.ir_index_15 << 15) | entry.ir_index_0_14,
1249 entry.ir_zero);
1250 } else {
1251 printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf,
1252 entry.dest_mode_logical ? "logical " : "physical",
1253 entry.virt_destid_8_14, entry.destid_0_7,
1254 entry.delivery_mode);
1255 }
1256 }
1257}
1258
1259static void __init print_IO_APIC(int ioapic_idx)
1260{
1261 union IO_APIC_reg_00 reg_00;
1262 union IO_APIC_reg_01 reg_01;
1263 union IO_APIC_reg_02 reg_02;
1264 union IO_APIC_reg_03 reg_03;
1265 unsigned long flags;
1266
1267 raw_spin_lock_irqsave(&ioapic_lock, flags);
1268 reg_00.raw = io_apic_read(ioapic_idx, 0);
1269 reg_01.raw = io_apic_read(ioapic_idx, 1);
1270 if (reg_01.bits.version >= 0x10)
1271 reg_02.raw = io_apic_read(ioapic_idx, 2);
1272 if (reg_01.bits.version >= 0x20)
1273 reg_03.raw = io_apic_read(ioapic_idx, 3);
1274 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1275
1276 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1277 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1278 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1279 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1280 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1281
1282 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1283 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1284 reg_01.bits.entries);
1285
1286 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1287 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1288 reg_01.bits.version);
1289
1290 /*
1291 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1292 * but the value of reg_02 is read as the previous read register
1293 * value, so ignore it if reg_02 == reg_01.
1294 */
1295 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1296 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1297 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1298 }
1299
1300 /*
1301 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1302 * or reg_03, but the value of reg_0[23] is read as the previous read
1303 * register value, so ignore it if reg_03 == reg_0[12].
1304 */
1305 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1306 reg_03.raw != reg_01.raw) {
1307 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1308 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1309 }
1310
1311 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1312 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1313}
1314
1315void __init print_IO_APICs(void)
1316{
1317 int ioapic_idx;
1318 unsigned int irq;
1319
1320 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321 for_each_ioapic(ioapic_idx)
1322 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323 mpc_ioapic_id(ioapic_idx),
1324 ioapics[ioapic_idx].nr_registers);
1325
1326 /*
1327 * We are a bit conservative about what we expect. We have to
1328 * know about every hardware change ASAP.
1329 */
1330 printk(KERN_INFO "testing the IO APIC.......................\n");
1331
1332 for_each_ioapic(ioapic_idx)
1333 print_IO_APIC(ioapic_idx);
1334
1335 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1336 for_each_active_irq(irq) {
1337 struct irq_pin_list *entry;
1338 struct irq_chip *chip;
1339 struct mp_chip_data *data;
1340
1341 chip = irq_get_chip(irq);
1342 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1343 continue;
1344 data = irq_get_chip_data(irq);
1345 if (!data)
1346 continue;
1347 if (list_empty(&data->irq_2_pin))
1348 continue;
1349
1350 printk(KERN_DEBUG "IRQ%d ", irq);
1351 for_each_irq_pin(entry, data->irq_2_pin)
1352 pr_cont("-> %d:%d", entry->apic, entry->pin);
1353 pr_cont("\n");
1354 }
1355
1356 printk(KERN_INFO ".................................... done.\n");
1357}
1358
1359/* Where if anywhere is the i8259 connect in external int mode */
1360static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1361
1362void __init enable_IO_APIC(void)
1363{
1364 int i8259_apic, i8259_pin;
1365 int apic, pin;
1366
1367 if (skip_ioapic_setup)
1368 nr_ioapics = 0;
1369
1370 if (!nr_legacy_irqs() || !nr_ioapics)
1371 return;
1372
1373 for_each_ioapic_pin(apic, pin) {
1374 /* See if any of the pins is in ExtINT mode */
1375 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1376
1377 /* If the interrupt line is enabled and in ExtInt mode
1378 * I have found the pin where the i8259 is connected.
1379 */
1380 if (!entry.masked &&
1381 entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1382 ioapic_i8259.apic = apic;
1383 ioapic_i8259.pin = pin;
1384 goto found_i8259;
1385 }
1386 }
1387 found_i8259:
1388 /* Look to see what if the MP table has reported the ExtINT */
1389 /* If we could not find the appropriate pin by looking at the ioapic
1390 * the i8259 probably is not connected the ioapic but give the
1391 * mptable a chance anyway.
1392 */
1393 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1394 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1397 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259.pin = i8259_pin;
1399 ioapic_i8259.apic = i8259_apic;
1400 }
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1403 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1404 {
1405 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1406 }
1407
1408 /*
1409 * Do not trust the IO-APIC being empty at bootup
1410 */
1411 clear_IO_APIC();
1412}
1413
1414void native_restore_boot_irq_mode(void)
1415{
1416 /*
1417 * If the i8259 is routed through an IOAPIC
1418 * Put that IOAPIC in virtual wire mode
1419 * so legacy interrupts can be delivered.
1420 */
1421 if (ioapic_i8259.pin != -1) {
1422 struct IO_APIC_route_entry entry;
1423 u32 apic_id = read_apic_id();
1424
1425 memset(&entry, 0, sizeof(entry));
1426 entry.masked = false;
1427 entry.is_level = false;
1428 entry.active_low = false;
1429 entry.dest_mode_logical = false;
1430 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1431 entry.destid_0_7 = apic_id & 0xFF;
1432 entry.virt_destid_8_14 = apic_id >> 8;
1433
1434 /*
1435 * Add it to the IO-APIC irq-routing table:
1436 */
1437 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1438 }
1439
1440 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1441 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1442}
1443
1444void restore_boot_irq_mode(void)
1445{
1446 if (!nr_legacy_irqs())
1447 return;
1448
1449 x86_apic_ops.restore();
1450}
1451
1452#ifdef CONFIG_X86_32
1453/*
1454 * function to set the IO-APIC physical IDs based on the
1455 * values stored in the MPC table.
1456 *
1457 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1458 */
1459void __init setup_ioapic_ids_from_mpc_nocheck(void)
1460{
1461 union IO_APIC_reg_00 reg_00;
1462 physid_mask_t phys_id_present_map;
1463 int ioapic_idx;
1464 int i;
1465 unsigned char old_id;
1466 unsigned long flags;
1467
1468 /*
1469 * This is broken; anything with a real cpu count has to
1470 * circumvent this idiocy regardless.
1471 */
1472 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1473
1474 /*
1475 * Set the IOAPIC ID to the value stored in the MPC table.
1476 */
1477 for_each_ioapic(ioapic_idx) {
1478 /* Read the register 0 value */
1479 raw_spin_lock_irqsave(&ioapic_lock, flags);
1480 reg_00.raw = io_apic_read(ioapic_idx, 0);
1481 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1482
1483 old_id = mpc_ioapic_id(ioapic_idx);
1484
1485 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1486 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1487 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1488 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1489 reg_00.bits.ID);
1490 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1491 }
1492
1493 /*
1494 * Sanity check, is the ID really free? Every APIC in a
1495 * system must have a unique ID or we get lots of nice
1496 * 'stuck on smp_invalidate_needed IPI wait' messages.
1497 */
1498 if (apic->check_apicid_used(&phys_id_present_map,
1499 mpc_ioapic_id(ioapic_idx))) {
1500 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1501 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1502 for (i = 0; i < get_physical_broadcast(); i++)
1503 if (!physid_isset(i, phys_id_present_map))
1504 break;
1505 if (i >= get_physical_broadcast())
1506 panic("Max APIC ID exceeded!\n");
1507 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1508 i);
1509 physid_set(i, phys_id_present_map);
1510 ioapics[ioapic_idx].mp_config.apicid = i;
1511 } else {
1512 physid_mask_t tmp;
1513 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1514 &tmp);
1515 apic_printk(APIC_VERBOSE, "Setting %d in the "
1516 "phys_id_present_map\n",
1517 mpc_ioapic_id(ioapic_idx));
1518 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1519 }
1520
1521 /*
1522 * We need to adjust the IRQ routing table
1523 * if the ID changed.
1524 */
1525 if (old_id != mpc_ioapic_id(ioapic_idx))
1526 for (i = 0; i < mp_irq_entries; i++)
1527 if (mp_irqs[i].dstapic == old_id)
1528 mp_irqs[i].dstapic
1529 = mpc_ioapic_id(ioapic_idx);
1530
1531 /*
1532 * Update the ID register according to the right value
1533 * from the MPC table if they are different.
1534 */
1535 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1536 continue;
1537
1538 apic_printk(APIC_VERBOSE, KERN_INFO
1539 "...changing IO-APIC physical APIC ID to %d ...",
1540 mpc_ioapic_id(ioapic_idx));
1541
1542 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1543 raw_spin_lock_irqsave(&ioapic_lock, flags);
1544 io_apic_write(ioapic_idx, 0, reg_00.raw);
1545 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1546
1547 /*
1548 * Sanity check
1549 */
1550 raw_spin_lock_irqsave(&ioapic_lock, flags);
1551 reg_00.raw = io_apic_read(ioapic_idx, 0);
1552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1553 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1554 pr_cont("could not set ID!\n");
1555 else
1556 apic_printk(APIC_VERBOSE, " ok.\n");
1557 }
1558}
1559
1560void __init setup_ioapic_ids_from_mpc(void)
1561{
1562
1563 if (acpi_ioapic)
1564 return;
1565 /*
1566 * Don't check I/O APIC IDs for xAPIC systems. They have
1567 * no meaning without the serial APIC bus.
1568 */
1569 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1570 || APIC_XAPIC(boot_cpu_apic_version))
1571 return;
1572 setup_ioapic_ids_from_mpc_nocheck();
1573}
1574#endif
1575
1576int no_timer_check __initdata;
1577
1578static int __init notimercheck(char *s)
1579{
1580 no_timer_check = 1;
1581 return 1;
1582}
1583__setup("no_timer_check", notimercheck);
1584
1585static void __init delay_with_tsc(void)
1586{
1587 unsigned long long start, now;
1588 unsigned long end = jiffies + 4;
1589
1590 start = rdtsc();
1591
1592 /*
1593 * We don't know the TSC frequency yet, but waiting for
1594 * 40000000000/HZ TSC cycles is safe:
1595 * 4 GHz == 10 jiffies
1596 * 1 GHz == 40 jiffies
1597 */
1598 do {
1599 rep_nop();
1600 now = rdtsc();
1601 } while ((now - start) < 40000000000ULL / HZ &&
1602 time_before_eq(jiffies, end));
1603}
1604
1605static void __init delay_without_tsc(void)
1606{
1607 unsigned long end = jiffies + 4;
1608 int band = 1;
1609
1610 /*
1611 * We don't know any frequency yet, but waiting for
1612 * 40940000000/HZ cycles is safe:
1613 * 4 GHz == 10 jiffies
1614 * 1 GHz == 40 jiffies
1615 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1616 */
1617 do {
1618 __delay(((1U << band++) * 10000000UL) / HZ);
1619 } while (band < 12 && time_before_eq(jiffies, end));
1620}
1621
1622/*
1623 * There is a nasty bug in some older SMP boards, their mptable lies
1624 * about the timer IRQ. We do the following to work around the situation:
1625 *
1626 * - timer IRQ defaults to IO-APIC IRQ
1627 * - if this function detects that timer IRQs are defunct, then we fall
1628 * back to ISA timer IRQs
1629 */
1630static int __init timer_irq_works(void)
1631{
1632 unsigned long t1 = jiffies;
1633
1634 if (no_timer_check)
1635 return 1;
1636
1637 local_irq_enable();
1638 if (boot_cpu_has(X86_FEATURE_TSC))
1639 delay_with_tsc();
1640 else
1641 delay_without_tsc();
1642
1643 /*
1644 * Expect a few ticks at least, to be sure some possible
1645 * glue logic does not lock up after one or two first
1646 * ticks in a non-ExtINT mode. Also the local APIC
1647 * might have cached one ExtINT interrupt. Finally, at
1648 * least one tick may be lost due to delays.
1649 */
1650
1651 local_irq_disable();
1652
1653 /* Did jiffies advance? */
1654 return time_after(jiffies, t1 + 4);
1655}
1656
1657/*
1658 * In the SMP+IOAPIC case it might happen that there are an unspecified
1659 * number of pending IRQ events unhandled. These cases are very rare,
1660 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1661 * better to do it this way as thus we do not have to be aware of
1662 * 'pending' interrupts in the IRQ path, except at this point.
1663 */
1664/*
1665 * Edge triggered needs to resend any interrupt
1666 * that was delayed but this is now handled in the device
1667 * independent code.
1668 */
1669
1670/*
1671 * Starting up a edge-triggered IO-APIC interrupt is
1672 * nasty - we need to make sure that we get the edge.
1673 * If it is already asserted for some reason, we need
1674 * return 1 to indicate that is was pending.
1675 *
1676 * This is not complete - we should be able to fake
1677 * an edge even if it isn't on the 8259A...
1678 */
1679static unsigned int startup_ioapic_irq(struct irq_data *data)
1680{
1681 int was_pending = 0, irq = data->irq;
1682 unsigned long flags;
1683
1684 raw_spin_lock_irqsave(&ioapic_lock, flags);
1685 if (irq < nr_legacy_irqs()) {
1686 legacy_pic->mask(irq);
1687 if (legacy_pic->irq_pending(irq))
1688 was_pending = 1;
1689 }
1690 __unmask_ioapic(data->chip_data);
1691 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1692
1693 return was_pending;
1694}
1695
1696atomic_t irq_mis_count;
1697
1698#ifdef CONFIG_GENERIC_PENDING_IRQ
1699static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1700{
1701 struct irq_pin_list *entry;
1702 unsigned long flags;
1703
1704 raw_spin_lock_irqsave(&ioapic_lock, flags);
1705 for_each_irq_pin(entry, data->irq_2_pin) {
1706 struct IO_APIC_route_entry e;
1707 int pin;
1708
1709 pin = entry->pin;
1710 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1711 /* Is the remote IRR bit set? */
1712 if (e.irr) {
1713 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1714 return true;
1715 }
1716 }
1717 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1718
1719 return false;
1720}
1721
1722static inline bool ioapic_prepare_move(struct irq_data *data)
1723{
1724 /* If we are moving the IRQ we need to mask it */
1725 if (unlikely(irqd_is_setaffinity_pending(data))) {
1726 if (!irqd_irq_masked(data))
1727 mask_ioapic_irq(data);
1728 return true;
1729 }
1730 return false;
1731}
1732
1733static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1734{
1735 if (unlikely(moveit)) {
1736 /* Only migrate the irq if the ack has been received.
1737 *
1738 * On rare occasions the broadcast level triggered ack gets
1739 * delayed going to ioapics, and if we reprogram the
1740 * vector while Remote IRR is still set the irq will never
1741 * fire again.
1742 *
1743 * To prevent this scenario we read the Remote IRR bit
1744 * of the ioapic. This has two effects.
1745 * - On any sane system the read of the ioapic will
1746 * flush writes (and acks) going to the ioapic from
1747 * this cpu.
1748 * - We get to see if the ACK has actually been delivered.
1749 *
1750 * Based on failed experiments of reprogramming the
1751 * ioapic entry from outside of irq context starting
1752 * with masking the ioapic entry and then polling until
1753 * Remote IRR was clear before reprogramming the
1754 * ioapic I don't trust the Remote IRR bit to be
1755 * completely accurate.
1756 *
1757 * However there appears to be no other way to plug
1758 * this race, so if the Remote IRR bit is not
1759 * accurate and is causing problems then it is a hardware bug
1760 * and you can go talk to the chipset vendor about it.
1761 */
1762 if (!io_apic_level_ack_pending(data->chip_data))
1763 irq_move_masked_irq(data);
1764 /* If the IRQ is masked in the core, leave it: */
1765 if (!irqd_irq_masked(data))
1766 unmask_ioapic_irq(data);
1767 }
1768}
1769#else
1770static inline bool ioapic_prepare_move(struct irq_data *data)
1771{
1772 return false;
1773}
1774static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1775{
1776}
1777#endif
1778
1779static void ioapic_ack_level(struct irq_data *irq_data)
1780{
1781 struct irq_cfg *cfg = irqd_cfg(irq_data);
1782 unsigned long v;
1783 bool moveit;
1784 int i;
1785
1786 irq_complete_move(cfg);
1787 moveit = ioapic_prepare_move(irq_data);
1788
1789 /*
1790 * It appears there is an erratum which affects at least version 0x11
1791 * of I/O APIC (that's the 82093AA and cores integrated into various
1792 * chipsets). Under certain conditions a level-triggered interrupt is
1793 * erroneously delivered as edge-triggered one but the respective IRR
1794 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1795 * message but it will never arrive and further interrupts are blocked
1796 * from the source. The exact reason is so far unknown, but the
1797 * phenomenon was observed when two consecutive interrupt requests
1798 * from a given source get delivered to the same CPU and the source is
1799 * temporarily disabled in between.
1800 *
1801 * A workaround is to simulate an EOI message manually. We achieve it
1802 * by setting the trigger mode to edge and then to level when the edge
1803 * trigger mode gets detected in the TMR of a local APIC for a
1804 * level-triggered interrupt. We mask the source for the time of the
1805 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1806 * The idea is from Manfred Spraul. --macro
1807 *
1808 * Also in the case when cpu goes offline, fixup_irqs() will forward
1809 * any unhandled interrupt on the offlined cpu to the new cpu
1810 * destination that is handling the corresponding interrupt. This
1811 * interrupt forwarding is done via IPI's. Hence, in this case also
1812 * level-triggered io-apic interrupt will be seen as an edge
1813 * interrupt in the IRR. And we can't rely on the cpu's EOI
1814 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1815 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1816 * supporting EOI register, we do an explicit EOI to clear the
1817 * remote IRR and on IO-APIC's which don't have an EOI register,
1818 * we use the above logic (mask+edge followed by unmask+level) from
1819 * Manfred Spraul to clear the remote IRR.
1820 */
1821 i = cfg->vector;
1822 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1823
1824 /*
1825 * We must acknowledge the irq before we move it or the acknowledge will
1826 * not propagate properly.
1827 */
1828 ack_APIC_irq();
1829
1830 /*
1831 * Tail end of clearing remote IRR bit (either by delivering the EOI
1832 * message via io-apic EOI register write or simulating it using
1833 * mask+edge followed by unmask+level logic) manually when the
1834 * level triggered interrupt is seen as the edge triggered interrupt
1835 * at the cpu.
1836 */
1837 if (!(v & (1 << (i & 0x1f)))) {
1838 atomic_inc(&irq_mis_count);
1839 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1840 }
1841
1842 ioapic_finish_move(irq_data, moveit);
1843}
1844
1845static void ioapic_ir_ack_level(struct irq_data *irq_data)
1846{
1847 struct mp_chip_data *data = irq_data->chip_data;
1848
1849 /*
1850 * Intr-remapping uses pin number as the virtual vector
1851 * in the RTE. Actual vector is programmed in
1852 * intr-remapping table entry. Hence for the io-apic
1853 * EOI we use the pin number.
1854 */
1855 apic_ack_irq(irq_data);
1856 eoi_ioapic_pin(data->entry.vector, data);
1857}
1858
1859/*
1860 * The I/OAPIC is just a device for generating MSI messages from legacy
1861 * interrupt pins. Various fields of the RTE translate into bits of the
1862 * resulting MSI which had a historical meaning.
1863 *
1864 * With interrupt remapping, many of those bits have different meanings
1865 * in the underlying MSI, but the way that the I/OAPIC transforms them
1866 * from its RTE to the MSI message is the same. This function allows
1867 * the parent IRQ domain to compose the MSI message, then takes the
1868 * relevant bits to put them in the appropriate places in the RTE in
1869 * order to generate that message when the IRQ happens.
1870 *
1871 * The setup here relies on a preconfigured route entry (is_level,
1872 * active_low, masked) because the parent domain is merely composing the
1873 * generic message routing information which is used for the MSI.
1874 */
1875static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1876 struct IO_APIC_route_entry *entry)
1877{
1878 struct msi_msg msg;
1879
1880 /* Let the parent domain compose the MSI message */
1881 irq_chip_compose_msi_msg(irq_data, &msg);
1882
1883 /*
1884 * - Real vector
1885 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1886 * - AMD/IR: 8bit IRTE index
1887 */
1888 entry->vector = msg.arch_data.vector;
1889 /* Delivery mode (for DMAR/IR all 0) */
1890 entry->delivery_mode = msg.arch_data.delivery_mode;
1891 /* Destination mode or DMAR/IR index bit 15 */
1892 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1893 /* DMAR/IR: 1, 0 for all other modes */
1894 entry->ir_format = msg.arch_addr_lo.dmar_format;
1895 /*
1896 * - DMAR/IR: index bit 0-14.
1897 *
1898 * - Virt: If the host supports x2apic without a virtualized IR
1899 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1900 * 8-14 of the destination id.
1901 *
1902 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1903 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1904 */
1905 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1906}
1907
1908static void ioapic_configure_entry(struct irq_data *irqd)
1909{
1910 struct mp_chip_data *mpd = irqd->chip_data;
1911 struct irq_pin_list *entry;
1912
1913 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1914
1915 for_each_irq_pin(entry, mpd->irq_2_pin)
1916 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1917}
1918
1919static int ioapic_set_affinity(struct irq_data *irq_data,
1920 const struct cpumask *mask, bool force)
1921{
1922 struct irq_data *parent = irq_data->parent_data;
1923 unsigned long flags;
1924 int ret;
1925
1926 ret = parent->chip->irq_set_affinity(parent, mask, force);
1927 raw_spin_lock_irqsave(&ioapic_lock, flags);
1928 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1929 ioapic_configure_entry(irq_data);
1930 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1931
1932 return ret;
1933}
1934
1935/*
1936 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1937 * be in flight, but not yet serviced by the target CPU. That means
1938 * __synchronize_hardirq() would return and claim that everything is calmed
1939 * down. So free_irq() would proceed and deactivate the interrupt and free
1940 * resources.
1941 *
1942 * Once the target CPU comes around to service it it will find a cleared
1943 * vector and complain. While the spurious interrupt is harmless, the full
1944 * release of resources might prevent the interrupt from being acknowledged
1945 * which keeps the hardware in a weird state.
1946 *
1947 * Verify that the corresponding Remote-IRR bits are clear.
1948 */
1949static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1950 enum irqchip_irq_state which,
1951 bool *state)
1952{
1953 struct mp_chip_data *mcd = irqd->chip_data;
1954 struct IO_APIC_route_entry rentry;
1955 struct irq_pin_list *p;
1956
1957 if (which != IRQCHIP_STATE_ACTIVE)
1958 return -EINVAL;
1959
1960 *state = false;
1961 raw_spin_lock(&ioapic_lock);
1962 for_each_irq_pin(p, mcd->irq_2_pin) {
1963 rentry = __ioapic_read_entry(p->apic, p->pin);
1964 /*
1965 * The remote IRR is only valid in level trigger mode. It's
1966 * meaning is undefined for edge triggered interrupts and
1967 * irrelevant because the IO-APIC treats them as fire and
1968 * forget.
1969 */
1970 if (rentry.irr && rentry.is_level) {
1971 *state = true;
1972 break;
1973 }
1974 }
1975 raw_spin_unlock(&ioapic_lock);
1976 return 0;
1977}
1978
1979static struct irq_chip ioapic_chip __read_mostly = {
1980 .name = "IO-APIC",
1981 .irq_startup = startup_ioapic_irq,
1982 .irq_mask = mask_ioapic_irq,
1983 .irq_unmask = unmask_ioapic_irq,
1984 .irq_ack = irq_chip_ack_parent,
1985 .irq_eoi = ioapic_ack_level,
1986 .irq_set_affinity = ioapic_set_affinity,
1987 .irq_retrigger = irq_chip_retrigger_hierarchy,
1988 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1989 .flags = IRQCHIP_SKIP_SET_WAKE |
1990 IRQCHIP_AFFINITY_PRE_STARTUP,
1991};
1992
1993static struct irq_chip ioapic_ir_chip __read_mostly = {
1994 .name = "IR-IO-APIC",
1995 .irq_startup = startup_ioapic_irq,
1996 .irq_mask = mask_ioapic_irq,
1997 .irq_unmask = unmask_ioapic_irq,
1998 .irq_ack = irq_chip_ack_parent,
1999 .irq_eoi = ioapic_ir_ack_level,
2000 .irq_set_affinity = ioapic_set_affinity,
2001 .irq_retrigger = irq_chip_retrigger_hierarchy,
2002 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
2003 .flags = IRQCHIP_SKIP_SET_WAKE |
2004 IRQCHIP_AFFINITY_PRE_STARTUP,
2005};
2006
2007static inline void init_IO_APIC_traps(void)
2008{
2009 struct irq_cfg *cfg;
2010 unsigned int irq;
2011
2012 for_each_active_irq(irq) {
2013 cfg = irq_cfg(irq);
2014 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2015 /*
2016 * Hmm.. We don't have an entry for this,
2017 * so default to an old-fashioned 8259
2018 * interrupt if we can..
2019 */
2020 if (irq < nr_legacy_irqs())
2021 legacy_pic->make_irq(irq);
2022 else
2023 /* Strange. Oh, well.. */
2024 irq_set_chip(irq, &no_irq_chip);
2025 }
2026 }
2027}
2028
2029/*
2030 * The local APIC irq-chip implementation:
2031 */
2032
2033static void mask_lapic_irq(struct irq_data *data)
2034{
2035 unsigned long v;
2036
2037 v = apic_read(APIC_LVT0);
2038 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2039}
2040
2041static void unmask_lapic_irq(struct irq_data *data)
2042{
2043 unsigned long v;
2044
2045 v = apic_read(APIC_LVT0);
2046 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2047}
2048
2049static void ack_lapic_irq(struct irq_data *data)
2050{
2051 ack_APIC_irq();
2052}
2053
2054static struct irq_chip lapic_chip __read_mostly = {
2055 .name = "local-APIC",
2056 .irq_mask = mask_lapic_irq,
2057 .irq_unmask = unmask_lapic_irq,
2058 .irq_ack = ack_lapic_irq,
2059};
2060
2061static void lapic_register_intr(int irq)
2062{
2063 irq_clear_status_flags(irq, IRQ_LEVEL);
2064 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2065 "edge");
2066}
2067
2068/*
2069 * This looks a bit hackish but it's about the only one way of sending
2070 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2071 * not support the ExtINT mode, unfortunately. We need to send these
2072 * cycles as some i82489DX-based boards have glue logic that keeps the
2073 * 8259A interrupt line asserted until INTA. --macro
2074 */
2075static inline void __init unlock_ExtINT_logic(void)
2076{
2077 int apic, pin, i;
2078 struct IO_APIC_route_entry entry0, entry1;
2079 unsigned char save_control, save_freq_select;
2080 u32 apic_id;
2081
2082 pin = find_isa_irq_pin(8, mp_INT);
2083 if (pin == -1) {
2084 WARN_ON_ONCE(1);
2085 return;
2086 }
2087 apic = find_isa_irq_apic(8, mp_INT);
2088 if (apic == -1) {
2089 WARN_ON_ONCE(1);
2090 return;
2091 }
2092
2093 entry0 = ioapic_read_entry(apic, pin);
2094 clear_IO_APIC_pin(apic, pin);
2095
2096 apic_id = hard_smp_processor_id();
2097 memset(&entry1, 0, sizeof(entry1));
2098
2099 entry1.dest_mode_logical = true;
2100 entry1.masked = false;
2101 entry1.destid_0_7 = apic_id & 0xFF;
2102 entry1.virt_destid_8_14 = apic_id >> 8;
2103 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
2104 entry1.active_low = entry0.active_low;
2105 entry1.is_level = false;
2106 entry1.vector = 0;
2107
2108 ioapic_write_entry(apic, pin, entry1);
2109
2110 save_control = CMOS_READ(RTC_CONTROL);
2111 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2113 RTC_FREQ_SELECT);
2114 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2115
2116 i = 100;
2117 while (i-- > 0) {
2118 mdelay(10);
2119 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2120 i -= 10;
2121 }
2122
2123 CMOS_WRITE(save_control, RTC_CONTROL);
2124 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125 clear_IO_APIC_pin(apic, pin);
2126
2127 ioapic_write_entry(apic, pin, entry0);
2128}
2129
2130static int disable_timer_pin_1 __initdata;
2131/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2132static int __init disable_timer_pin_setup(char *arg)
2133{
2134 disable_timer_pin_1 = 1;
2135 return 0;
2136}
2137early_param("disable_timer_pin_1", disable_timer_pin_setup);
2138
2139static int mp_alloc_timer_irq(int ioapic, int pin)
2140{
2141 int irq = -1;
2142 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2143
2144 if (domain) {
2145 struct irq_alloc_info info;
2146
2147 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2148 info.devid = mpc_ioapic_id(ioapic);
2149 info.ioapic.pin = pin;
2150 mutex_lock(&ioapic_mutex);
2151 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2152 mutex_unlock(&ioapic_mutex);
2153 }
2154
2155 return irq;
2156}
2157
2158/*
2159 * This code may look a bit paranoid, but it's supposed to cooperate with
2160 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2161 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2162 * fanatically on his truly buggy board.
2163 *
2164 * FIXME: really need to revamp this for all platforms.
2165 */
2166static inline void __init check_timer(void)
2167{
2168 struct irq_data *irq_data = irq_get_irq_data(0);
2169 struct mp_chip_data *data = irq_data->chip_data;
2170 struct irq_cfg *cfg = irqd_cfg(irq_data);
2171 int node = cpu_to_node(0);
2172 int apic1, pin1, apic2, pin2;
2173 int no_pin1 = 0;
2174
2175 if (!global_clock_event)
2176 return;
2177
2178 local_irq_disable();
2179
2180 /*
2181 * get/set the timer IRQ vector:
2182 */
2183 legacy_pic->mask(0);
2184
2185 /*
2186 * As IRQ0 is to be enabled in the 8259A, the virtual
2187 * wire has to be disabled in the local APIC. Also
2188 * timer interrupts need to be acknowledged manually in
2189 * the 8259A for the i82489DX when using the NMI
2190 * watchdog as that APIC treats NMIs as level-triggered.
2191 * The AEOI mode will finish them in the 8259A
2192 * automatically.
2193 */
2194 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2195 legacy_pic->init(1);
2196
2197 pin1 = find_isa_irq_pin(0, mp_INT);
2198 apic1 = find_isa_irq_apic(0, mp_INT);
2199 pin2 = ioapic_i8259.pin;
2200 apic2 = ioapic_i8259.apic;
2201
2202 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2203 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2204 cfg->vector, apic1, pin1, apic2, pin2);
2205
2206 /*
2207 * Some BIOS writers are clueless and report the ExtINTA
2208 * I/O APIC input from the cascaded 8259A as the timer
2209 * interrupt input. So just in case, if only one pin
2210 * was found above, try it both directly and through the
2211 * 8259A.
2212 */
2213 if (pin1 == -1) {
2214 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2215 pin1 = pin2;
2216 apic1 = apic2;
2217 no_pin1 = 1;
2218 } else if (pin2 == -1) {
2219 pin2 = pin1;
2220 apic2 = apic1;
2221 }
2222
2223 if (pin1 != -1) {
2224 /* Ok, does IRQ0 through the IOAPIC work? */
2225 if (no_pin1) {
2226 mp_alloc_timer_irq(apic1, pin1);
2227 } else {
2228 /*
2229 * for edge trigger, it's already unmasked,
2230 * so only need to unmask if it is level-trigger
2231 * do we really have level trigger timer?
2232 */
2233 int idx = find_irq_entry(apic1, pin1, mp_INT);
2234
2235 if (idx != -1 && irq_is_level(idx))
2236 unmask_ioapic_irq(irq_get_irq_data(0));
2237 }
2238 irq_domain_deactivate_irq(irq_data);
2239 irq_domain_activate_irq(irq_data, false);
2240 if (timer_irq_works()) {
2241 if (disable_timer_pin_1 > 0)
2242 clear_IO_APIC_pin(0, pin1);
2243 goto out;
2244 }
2245 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2246 clear_IO_APIC_pin(apic1, pin1);
2247 if (!no_pin1)
2248 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2249 "8254 timer not connected to IO-APIC\n");
2250
2251 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2252 "(IRQ0) through the 8259A ...\n");
2253 apic_printk(APIC_QUIET, KERN_INFO
2254 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2255 /*
2256 * legacy devices should be connected to IO APIC #0
2257 */
2258 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2259 irq_domain_deactivate_irq(irq_data);
2260 irq_domain_activate_irq(irq_data, false);
2261 legacy_pic->unmask(0);
2262 if (timer_irq_works()) {
2263 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2264 goto out;
2265 }
2266 /*
2267 * Cleanup, just in case ...
2268 */
2269 legacy_pic->mask(0);
2270 clear_IO_APIC_pin(apic2, pin2);
2271 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2272 }
2273
2274 apic_printk(APIC_QUIET, KERN_INFO
2275 "...trying to set up timer as Virtual Wire IRQ...\n");
2276
2277 lapic_register_intr(0);
2278 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2279 legacy_pic->unmask(0);
2280
2281 if (timer_irq_works()) {
2282 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2283 goto out;
2284 }
2285 legacy_pic->mask(0);
2286 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2287 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2288
2289 apic_printk(APIC_QUIET, KERN_INFO
2290 "...trying to set up timer as ExtINT IRQ...\n");
2291
2292 legacy_pic->init(0);
2293 legacy_pic->make_irq(0);
2294 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2295 legacy_pic->unmask(0);
2296
2297 unlock_ExtINT_logic();
2298
2299 if (timer_irq_works()) {
2300 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2301 goto out;
2302 }
2303 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2304 if (apic_is_x2apic_enabled())
2305 apic_printk(APIC_QUIET, KERN_INFO
2306 "Perhaps problem with the pre-enabled x2apic mode\n"
2307 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2308 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2309 "report. Then try booting with the 'noapic' option.\n");
2310out:
2311 local_irq_enable();
2312}
2313
2314/*
2315 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2316 * to devices. However there may be an I/O APIC pin available for
2317 * this interrupt regardless. The pin may be left unconnected, but
2318 * typically it will be reused as an ExtINT cascade interrupt for
2319 * the master 8259A. In the MPS case such a pin will normally be
2320 * reported as an ExtINT interrupt in the MP table. With ACPI
2321 * there is no provision for ExtINT interrupts, and in the absence
2322 * of an override it would be treated as an ordinary ISA I/O APIC
2323 * interrupt, that is edge-triggered and unmasked by default. We
2324 * used to do this, but it caused problems on some systems because
2325 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2326 * the same ExtINT cascade interrupt to drive the local APIC of the
2327 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2328 * the I/O APIC in all cases now. No actual device should request
2329 * it anyway. --macro
2330 */
2331#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2332
2333static int mp_irqdomain_create(int ioapic)
2334{
2335 struct irq_domain *parent;
2336 int hwirqs = mp_ioapic_pin_count(ioapic);
2337 struct ioapic *ip = &ioapics[ioapic];
2338 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2339 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2340 struct fwnode_handle *fn;
2341 struct irq_fwspec fwspec;
2342
2343 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2344 return 0;
2345
2346 /* Handle device tree enumerated APICs proper */
2347 if (cfg->dev) {
2348 fn = of_node_to_fwnode(cfg->dev);
2349 } else {
2350 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2351 if (!fn)
2352 return -ENOMEM;
2353 }
2354
2355 fwspec.fwnode = fn;
2356 fwspec.param_count = 1;
2357 fwspec.param[0] = mpc_ioapic_id(ioapic);
2358
2359 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
2360 if (!parent) {
2361 if (!cfg->dev)
2362 irq_domain_free_fwnode(fn);
2363 return -ENODEV;
2364 }
2365
2366 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2367 (void *)(long)ioapic);
2368
2369 if (!ip->irqdomain) {
2370 /* Release fw handle if it was allocated above */
2371 if (!cfg->dev)
2372 irq_domain_free_fwnode(fn);
2373 return -ENOMEM;
2374 }
2375
2376 ip->irqdomain->parent = parent;
2377
2378 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2379 cfg->type == IOAPIC_DOMAIN_STRICT)
2380 ioapic_dynirq_base = max(ioapic_dynirq_base,
2381 gsi_cfg->gsi_end + 1);
2382
2383 return 0;
2384}
2385
2386static void ioapic_destroy_irqdomain(int idx)
2387{
2388 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2389 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2390
2391 if (ioapics[idx].irqdomain) {
2392 irq_domain_remove(ioapics[idx].irqdomain);
2393 if (!cfg->dev)
2394 irq_domain_free_fwnode(fn);
2395 ioapics[idx].irqdomain = NULL;
2396 }
2397}
2398
2399void __init setup_IO_APIC(void)
2400{
2401 int ioapic;
2402
2403 if (skip_ioapic_setup || !nr_ioapics)
2404 return;
2405
2406 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2407
2408 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2409 for_each_ioapic(ioapic)
2410 BUG_ON(mp_irqdomain_create(ioapic));
2411
2412 /*
2413 * Set up IO-APIC IRQ routing.
2414 */
2415 x86_init.mpparse.setup_ioapic_ids();
2416
2417 sync_Arb_IDs();
2418 setup_IO_APIC_irqs();
2419 init_IO_APIC_traps();
2420 if (nr_legacy_irqs())
2421 check_timer();
2422
2423 ioapic_initialized = 1;
2424}
2425
2426static void resume_ioapic_id(int ioapic_idx)
2427{
2428 unsigned long flags;
2429 union IO_APIC_reg_00 reg_00;
2430
2431 raw_spin_lock_irqsave(&ioapic_lock, flags);
2432 reg_00.raw = io_apic_read(ioapic_idx, 0);
2433 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2434 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2435 io_apic_write(ioapic_idx, 0, reg_00.raw);
2436 }
2437 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2438}
2439
2440static void ioapic_resume(void)
2441{
2442 int ioapic_idx;
2443
2444 for_each_ioapic_reverse(ioapic_idx)
2445 resume_ioapic_id(ioapic_idx);
2446
2447 restore_ioapic_entries();
2448}
2449
2450static struct syscore_ops ioapic_syscore_ops = {
2451 .suspend = save_ioapic_entries,
2452 .resume = ioapic_resume,
2453};
2454
2455static int __init ioapic_init_ops(void)
2456{
2457 register_syscore_ops(&ioapic_syscore_ops);
2458
2459 return 0;
2460}
2461
2462device_initcall(ioapic_init_ops);
2463
2464static int io_apic_get_redir_entries(int ioapic)
2465{
2466 union IO_APIC_reg_01 reg_01;
2467 unsigned long flags;
2468
2469 raw_spin_lock_irqsave(&ioapic_lock, flags);
2470 reg_01.raw = io_apic_read(ioapic, 1);
2471 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2472
2473 /* The register returns the maximum index redir index
2474 * supported, which is one less than the total number of redir
2475 * entries.
2476 */
2477 return reg_01.bits.entries + 1;
2478}
2479
2480unsigned int arch_dynirq_lower_bound(unsigned int from)
2481{
2482 /*
2483 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2484 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2485 */
2486 if (!ioapic_initialized)
2487 return gsi_top;
2488 /*
2489 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2490 * updated. So simply return @from if ioapic_dynirq_base == 0.
2491 */
2492 return ioapic_dynirq_base ? : from;
2493}
2494
2495#ifdef CONFIG_X86_32
2496static int io_apic_get_unique_id(int ioapic, int apic_id)
2497{
2498 union IO_APIC_reg_00 reg_00;
2499 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2500 physid_mask_t tmp;
2501 unsigned long flags;
2502 int i = 0;
2503
2504 /*
2505 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2506 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2507 * supports up to 16 on one shared APIC bus.
2508 *
2509 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2510 * advantage of new APIC bus architecture.
2511 */
2512
2513 if (physids_empty(apic_id_map))
2514 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2515
2516 raw_spin_lock_irqsave(&ioapic_lock, flags);
2517 reg_00.raw = io_apic_read(ioapic, 0);
2518 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2519
2520 if (apic_id >= get_physical_broadcast()) {
2521 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2522 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2523 apic_id = reg_00.bits.ID;
2524 }
2525
2526 /*
2527 * Every APIC in a system must have a unique ID or we get lots of nice
2528 * 'stuck on smp_invalidate_needed IPI wait' messages.
2529 */
2530 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2531
2532 for (i = 0; i < get_physical_broadcast(); i++) {
2533 if (!apic->check_apicid_used(&apic_id_map, i))
2534 break;
2535 }
2536
2537 if (i == get_physical_broadcast())
2538 panic("Max apic_id exceeded!\n");
2539
2540 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2541 "trying %d\n", ioapic, apic_id, i);
2542
2543 apic_id = i;
2544 }
2545
2546 apic->apicid_to_cpu_present(apic_id, &tmp);
2547 physids_or(apic_id_map, apic_id_map, tmp);
2548
2549 if (reg_00.bits.ID != apic_id) {
2550 reg_00.bits.ID = apic_id;
2551
2552 raw_spin_lock_irqsave(&ioapic_lock, flags);
2553 io_apic_write(ioapic, 0, reg_00.raw);
2554 reg_00.raw = io_apic_read(ioapic, 0);
2555 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2556
2557 /* Sanity check */
2558 if (reg_00.bits.ID != apic_id) {
2559 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2560 ioapic);
2561 return -1;
2562 }
2563 }
2564
2565 apic_printk(APIC_VERBOSE, KERN_INFO
2566 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2567
2568 return apic_id;
2569}
2570
2571static u8 io_apic_unique_id(int idx, u8 id)
2572{
2573 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2574 !APIC_XAPIC(boot_cpu_apic_version))
2575 return io_apic_get_unique_id(idx, id);
2576 else
2577 return id;
2578}
2579#else
2580static u8 io_apic_unique_id(int idx, u8 id)
2581{
2582 union IO_APIC_reg_00 reg_00;
2583 DECLARE_BITMAP(used, 256);
2584 unsigned long flags;
2585 u8 new_id;
2586 int i;
2587
2588 bitmap_zero(used, 256);
2589 for_each_ioapic(i)
2590 __set_bit(mpc_ioapic_id(i), used);
2591
2592 /* Hand out the requested id if available */
2593 if (!test_bit(id, used))
2594 return id;
2595
2596 /*
2597 * Read the current id from the ioapic and keep it if
2598 * available.
2599 */
2600 raw_spin_lock_irqsave(&ioapic_lock, flags);
2601 reg_00.raw = io_apic_read(idx, 0);
2602 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2603 new_id = reg_00.bits.ID;
2604 if (!test_bit(new_id, used)) {
2605 apic_printk(APIC_VERBOSE, KERN_INFO
2606 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2607 idx, new_id, id);
2608 return new_id;
2609 }
2610
2611 /*
2612 * Get the next free id and write it to the ioapic.
2613 */
2614 new_id = find_first_zero_bit(used, 256);
2615 reg_00.bits.ID = new_id;
2616 raw_spin_lock_irqsave(&ioapic_lock, flags);
2617 io_apic_write(idx, 0, reg_00.raw);
2618 reg_00.raw = io_apic_read(idx, 0);
2619 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2620 /* Sanity check */
2621 BUG_ON(reg_00.bits.ID != new_id);
2622
2623 return new_id;
2624}
2625#endif
2626
2627static int io_apic_get_version(int ioapic)
2628{
2629 union IO_APIC_reg_01 reg_01;
2630 unsigned long flags;
2631
2632 raw_spin_lock_irqsave(&ioapic_lock, flags);
2633 reg_01.raw = io_apic_read(ioapic, 1);
2634 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2635
2636 return reg_01.bits.version;
2637}
2638
2639/*
2640 * This function updates target affinity of IOAPIC interrupts to include
2641 * the CPUs which came online during SMP bringup.
2642 */
2643#define IOAPIC_RESOURCE_NAME_SIZE 11
2644
2645static struct resource *ioapic_resources;
2646
2647static struct resource * __init ioapic_setup_resources(void)
2648{
2649 unsigned long n;
2650 struct resource *res;
2651 char *mem;
2652 int i;
2653
2654 if (nr_ioapics == 0)
2655 return NULL;
2656
2657 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2658 n *= nr_ioapics;
2659
2660 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2661 if (!mem)
2662 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2663 res = (void *)mem;
2664
2665 mem += sizeof(struct resource) * nr_ioapics;
2666
2667 for_each_ioapic(i) {
2668 res[i].name = mem;
2669 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2670 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2671 mem += IOAPIC_RESOURCE_NAME_SIZE;
2672 ioapics[i].iomem_res = &res[i];
2673 }
2674
2675 ioapic_resources = res;
2676
2677 return res;
2678}
2679
2680void __init io_apic_init_mappings(void)
2681{
2682 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2683 struct resource *ioapic_res;
2684 int i;
2685
2686 ioapic_res = ioapic_setup_resources();
2687 for_each_ioapic(i) {
2688 if (smp_found_config) {
2689 ioapic_phys = mpc_ioapic_addr(i);
2690#ifdef CONFIG_X86_32
2691 if (!ioapic_phys) {
2692 printk(KERN_ERR
2693 "WARNING: bogus zero IO-APIC "
2694 "address found in MPTABLE, "
2695 "disabling IO/APIC support!\n");
2696 smp_found_config = 0;
2697 skip_ioapic_setup = 1;
2698 goto fake_ioapic_page;
2699 }
2700#endif
2701 } else {
2702#ifdef CONFIG_X86_32
2703fake_ioapic_page:
2704#endif
2705 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2706 PAGE_SIZE);
2707 if (!ioapic_phys)
2708 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2709 __func__, PAGE_SIZE, PAGE_SIZE);
2710 ioapic_phys = __pa(ioapic_phys);
2711 }
2712 set_fixmap_nocache(idx, ioapic_phys);
2713 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2714 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2715 ioapic_phys);
2716 idx++;
2717
2718 ioapic_res->start = ioapic_phys;
2719 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2720 ioapic_res++;
2721 }
2722}
2723
2724void __init ioapic_insert_resources(void)
2725{
2726 int i;
2727 struct resource *r = ioapic_resources;
2728
2729 if (!r) {
2730 if (nr_ioapics > 0)
2731 printk(KERN_ERR
2732 "IO APIC resources couldn't be allocated.\n");
2733 return;
2734 }
2735
2736 for_each_ioapic(i) {
2737 insert_resource(&iomem_resource, r);
2738 r++;
2739 }
2740}
2741
2742int mp_find_ioapic(u32 gsi)
2743{
2744 int i;
2745
2746 if (nr_ioapics == 0)
2747 return -1;
2748
2749 /* Find the IOAPIC that manages this GSI. */
2750 for_each_ioapic(i) {
2751 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2752 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2753 return i;
2754 }
2755
2756 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2757 return -1;
2758}
2759
2760int mp_find_ioapic_pin(int ioapic, u32 gsi)
2761{
2762 struct mp_ioapic_gsi *gsi_cfg;
2763
2764 if (WARN_ON(ioapic < 0))
2765 return -1;
2766
2767 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2768 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2769 return -1;
2770
2771 return gsi - gsi_cfg->gsi_base;
2772}
2773
2774static int bad_ioapic_register(int idx)
2775{
2776 union IO_APIC_reg_00 reg_00;
2777 union IO_APIC_reg_01 reg_01;
2778 union IO_APIC_reg_02 reg_02;
2779
2780 reg_00.raw = io_apic_read(idx, 0);
2781 reg_01.raw = io_apic_read(idx, 1);
2782 reg_02.raw = io_apic_read(idx, 2);
2783
2784 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2785 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2786 mpc_ioapic_addr(idx));
2787 return 1;
2788 }
2789
2790 return 0;
2791}
2792
2793static int find_free_ioapic_entry(void)
2794{
2795 int idx;
2796
2797 for (idx = 0; idx < MAX_IO_APICS; idx++)
2798 if (ioapics[idx].nr_registers == 0)
2799 return idx;
2800
2801 return MAX_IO_APICS;
2802}
2803
2804/**
2805 * mp_register_ioapic - Register an IOAPIC device
2806 * @id: hardware IOAPIC ID
2807 * @address: physical address of IOAPIC register area
2808 * @gsi_base: base of GSI associated with the IOAPIC
2809 * @cfg: configuration information for the IOAPIC
2810 */
2811int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2812 struct ioapic_domain_cfg *cfg)
2813{
2814 bool hotplug = !!ioapic_initialized;
2815 struct mp_ioapic_gsi *gsi_cfg;
2816 int idx, ioapic, entries;
2817 u32 gsi_end;
2818
2819 if (!address) {
2820 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2821 return -EINVAL;
2822 }
2823 for_each_ioapic(ioapic)
2824 if (ioapics[ioapic].mp_config.apicaddr == address) {
2825 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2826 address, ioapic);
2827 return -EEXIST;
2828 }
2829
2830 idx = find_free_ioapic_entry();
2831 if (idx >= MAX_IO_APICS) {
2832 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2833 MAX_IO_APICS, idx);
2834 return -ENOSPC;
2835 }
2836
2837 ioapics[idx].mp_config.type = MP_IOAPIC;
2838 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2839 ioapics[idx].mp_config.apicaddr = address;
2840
2841 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2842 if (bad_ioapic_register(idx)) {
2843 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2844 return -ENODEV;
2845 }
2846
2847 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2848 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2849
2850 /*
2851 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2852 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2853 */
2854 entries = io_apic_get_redir_entries(idx);
2855 gsi_end = gsi_base + entries - 1;
2856 for_each_ioapic(ioapic) {
2857 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2858 if ((gsi_base >= gsi_cfg->gsi_base &&
2859 gsi_base <= gsi_cfg->gsi_end) ||
2860 (gsi_end >= gsi_cfg->gsi_base &&
2861 gsi_end <= gsi_cfg->gsi_end)) {
2862 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2863 gsi_base, gsi_end,
2864 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2865 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2866 return -ENOSPC;
2867 }
2868 }
2869 gsi_cfg = mp_ioapic_gsi_routing(idx);
2870 gsi_cfg->gsi_base = gsi_base;
2871 gsi_cfg->gsi_end = gsi_end;
2872
2873 ioapics[idx].irqdomain = NULL;
2874 ioapics[idx].irqdomain_cfg = *cfg;
2875
2876 /*
2877 * If mp_register_ioapic() is called during early boot stage when
2878 * walking ACPI/DT tables, it's too early to create irqdomain,
2879 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2880 */
2881 if (hotplug) {
2882 if (mp_irqdomain_create(idx)) {
2883 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2884 return -ENOMEM;
2885 }
2886 alloc_ioapic_saved_registers(idx);
2887 }
2888
2889 if (gsi_cfg->gsi_end >= gsi_top)
2890 gsi_top = gsi_cfg->gsi_end + 1;
2891 if (nr_ioapics <= idx)
2892 nr_ioapics = idx + 1;
2893
2894 /* Set nr_registers to mark entry present */
2895 ioapics[idx].nr_registers = entries;
2896
2897 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2898 idx, mpc_ioapic_id(idx),
2899 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2900 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2901
2902 return 0;
2903}
2904
2905int mp_unregister_ioapic(u32 gsi_base)
2906{
2907 int ioapic, pin;
2908 int found = 0;
2909
2910 for_each_ioapic(ioapic)
2911 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2912 found = 1;
2913 break;
2914 }
2915 if (!found) {
2916 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2917 return -ENODEV;
2918 }
2919
2920 for_each_pin(ioapic, pin) {
2921 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2922 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2923 struct mp_chip_data *data;
2924
2925 if (irq >= 0) {
2926 data = irq_get_chip_data(irq);
2927 if (data && data->count) {
2928 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2929 pin, ioapic);
2930 return -EBUSY;
2931 }
2932 }
2933 }
2934
2935 /* Mark entry not present */
2936 ioapics[ioapic].nr_registers = 0;
2937 ioapic_destroy_irqdomain(ioapic);
2938 free_ioapic_saved_registers(ioapic);
2939 if (ioapics[ioapic].iomem_res)
2940 release_resource(ioapics[ioapic].iomem_res);
2941 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2942 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2943
2944 return 0;
2945}
2946
2947int mp_ioapic_registered(u32 gsi_base)
2948{
2949 int ioapic;
2950
2951 for_each_ioapic(ioapic)
2952 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2953 return 1;
2954
2955 return 0;
2956}
2957
2958static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2959 struct irq_alloc_info *info)
2960{
2961 if (info && info->ioapic.valid) {
2962 data->is_level = info->ioapic.is_level;
2963 data->active_low = info->ioapic.active_low;
2964 } else if (__acpi_get_override_irq(gsi, &data->is_level,
2965 &data->active_low) < 0) {
2966 /* PCI interrupts are always active low level triggered. */
2967 data->is_level = true;
2968 data->active_low = true;
2969 }
2970}
2971
2972/*
2973 * Configure the I/O-APIC specific fields in the routing entry.
2974 *
2975 * This is important to setup the I/O-APIC specific bits (is_level,
2976 * active_low, masked) because the underlying parent domain will only
2977 * provide the routing information and is oblivious of the I/O-APIC
2978 * specific bits.
2979 *
2980 * The entry is just preconfigured at this point and not written into the
2981 * RTE. This happens later during activation which will fill in the actual
2982 * routing information.
2983 */
2984static void mp_preconfigure_entry(struct mp_chip_data *data)
2985{
2986 struct IO_APIC_route_entry *entry = &data->entry;
2987
2988 memset(entry, 0, sizeof(*entry));
2989 entry->is_level = data->is_level;
2990 entry->active_low = data->active_low;
2991 /*
2992 * Mask level triggered irqs. Edge triggered irqs are masked
2993 * by the irq core code in case they fire.
2994 */
2995 entry->masked = data->is_level;
2996}
2997
2998int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2999 unsigned int nr_irqs, void *arg)
3000{
3001 struct irq_alloc_info *info = arg;
3002 struct mp_chip_data *data;
3003 struct irq_data *irq_data;
3004 int ret, ioapic, pin;
3005 unsigned long flags;
3006
3007 if (!info || nr_irqs > 1)
3008 return -EINVAL;
3009 irq_data = irq_domain_get_irq_data(domain, virq);
3010 if (!irq_data)
3011 return -EINVAL;
3012
3013 ioapic = mp_irqdomain_ioapic_idx(domain);
3014 pin = info->ioapic.pin;
3015 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3016 return -EEXIST;
3017
3018 data = kzalloc(sizeof(*data), GFP_KERNEL);
3019 if (!data)
3020 return -ENOMEM;
3021
3022 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3023 if (ret < 0) {
3024 kfree(data);
3025 return ret;
3026 }
3027
3028 INIT_LIST_HEAD(&data->irq_2_pin);
3029 irq_data->hwirq = info->ioapic.pin;
3030 irq_data->chip = (domain->parent == x86_vector_domain) ?
3031 &ioapic_chip : &ioapic_ir_chip;
3032 irq_data->chip_data = data;
3033 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3034
3035 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3036
3037 mp_preconfigure_entry(data);
3038 mp_register_handler(virq, data->is_level);
3039
3040 local_irq_save(flags);
3041 if (virq < nr_legacy_irqs())
3042 legacy_pic->mask(virq);
3043 local_irq_restore(flags);
3044
3045 apic_printk(APIC_VERBOSE, KERN_DEBUG
3046 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
3047 ioapic, mpc_ioapic_id(ioapic), pin, virq,
3048 data->is_level, data->active_low);
3049 return 0;
3050}
3051
3052void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3053 unsigned int nr_irqs)
3054{
3055 struct irq_data *irq_data;
3056 struct mp_chip_data *data;
3057
3058 BUG_ON(nr_irqs != 1);
3059 irq_data = irq_domain_get_irq_data(domain, virq);
3060 if (irq_data && irq_data->chip_data) {
3061 data = irq_data->chip_data;
3062 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3063 (int)irq_data->hwirq);
3064 WARN_ON(!list_empty(&data->irq_2_pin));
3065 kfree(irq_data->chip_data);
3066 }
3067 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3068}
3069
3070int mp_irqdomain_activate(struct irq_domain *domain,
3071 struct irq_data *irq_data, bool reserve)
3072{
3073 unsigned long flags;
3074
3075 raw_spin_lock_irqsave(&ioapic_lock, flags);
3076 ioapic_configure_entry(irq_data);
3077 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3078 return 0;
3079}
3080
3081void mp_irqdomain_deactivate(struct irq_domain *domain,
3082 struct irq_data *irq_data)
3083{
3084 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3085 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3086 (int)irq_data->hwirq);
3087}
3088
3089int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3090{
3091 return (int)(long)domain->host_data;
3092}
3093
3094const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3095 .alloc = mp_irqdomain_alloc,
3096 .free = mp_irqdomain_free,
3097 .activate = mp_irqdomain_activate,
3098 .deactivate = mp_irqdomain_deactivate,
3099};