Loading...
1/*
2 * arch/arm/mm/proc-v7-2level.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define TTB_S (1 << 1)
12#define TTB_RGN_NC (0 << 3)
13#define TTB_RGN_OC_WBWA (1 << 3)
14#define TTB_RGN_OC_WT (2 << 3)
15#define TTB_RGN_OC_WB (3 << 3)
16#define TTB_NOS (1 << 5)
17#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
18#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
19#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
20#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
21
22/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
23#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
24#define PMD_FLAGS_UP PMD_SECT_WB
25
26/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
27#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
28#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
29
30/*
31 * cpu_v7_switch_mm(pgd_phys, tsk)
32 *
33 * Set the translation table base pointer to be pgd_phys
34 *
35 * - pgd_phys - physical address of new TTB
36 *
37 * It is assumed that:
38 * - we are not using split page tables
39 *
40 * Note that we always need to flush BTAC/BTB if IBE is set
41 * even on Cortex-A8 revisions not affected by 430973.
42 * If IBE is not set, the flush BTAC/BTB won't do anything.
43 */
44ENTRY(cpu_ca8_switch_mm)
45#ifdef CONFIG_MMU
46 mov r2, #0
47 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
48#endif
49ENTRY(cpu_v7_switch_mm)
50#ifdef CONFIG_MMU
51 mmid r1, r1 @ get mm->context.id
52 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
53 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
54#ifdef CONFIG_PID_IN_CONTEXTIDR
55 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
56 lsr r2, r2, #8 @ extract the PID
57 bfi r1, r2, #8, #24 @ insert into new context ID
58#endif
59#ifdef CONFIG_ARM_ERRATA_754322
60 dsb
61#endif
62 mcr p15, 0, r1, c13, c0, 1 @ set context ID
63 isb
64 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
65 isb
66#endif
67 bx lr
68ENDPROC(cpu_v7_switch_mm)
69ENDPROC(cpu_ca8_switch_mm)
70
71/*
72 * cpu_v7_set_pte_ext(ptep, pte)
73 *
74 * Set a level 2 translation table entry.
75 *
76 * - ptep - pointer to level 2 translation table entry
77 * (hardware version is stored at +2048 bytes)
78 * - pte - PTE value to store
79 * - ext - value for extended PTE bits
80 */
81ENTRY(cpu_v7_set_pte_ext)
82#ifdef CONFIG_MMU
83 str r1, [r0] @ linux version
84
85 bic r3, r1, #0x000003f0
86 bic r3, r3, #PTE_TYPE_MASK
87 orr r3, r3, r2
88 orr r3, r3, #PTE_EXT_AP0 | 2
89
90 tst r1, #1 << 4
91 orrne r3, r3, #PTE_EXT_TEX(1)
92
93 eor r1, r1, #L_PTE_DIRTY
94 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
95 orrne r3, r3, #PTE_EXT_APX
96
97 tst r1, #L_PTE_USER
98 orrne r3, r3, #PTE_EXT_AP1
99
100 tst r1, #L_PTE_XN
101 orrne r3, r3, #PTE_EXT_XN
102
103 tst r1, #L_PTE_YOUNG
104 tstne r1, #L_PTE_VALID
105 eorne r1, r1, #L_PTE_NONE
106 tstne r1, #L_PTE_NONE
107 moveq r3, #0
108
109 ARM( str r3, [r0, #2048]! )
110 THUMB( add r0, r0, #2048 )
111 THUMB( str r3, [r0] )
112 ALT_SMP(W(nop))
113 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
114#endif
115 bx lr
116ENDPROC(cpu_v7_set_pte_ext)
117
118 /*
119 * Memory region attributes with SCTLR.TRE=1
120 *
121 * n = TEX[0],C,B
122 * TR = PRRR[2n+1:2n] - memory type
123 * IR = NMRR[2n+1:2n] - inner cacheable property
124 * OR = NMRR[2n+17:2n+16] - outer cacheable property
125 *
126 * n TR IR OR
127 * UNCACHED 000 00
128 * BUFFERABLE 001 10 00 00
129 * WRITETHROUGH 010 10 10 10
130 * WRITEBACK 011 10 11 11
131 * reserved 110
132 * WRITEALLOC 111 10 01 01
133 * DEV_SHARED 100 01
134 * DEV_NONSHARED 100 01
135 * DEV_WC 001 10
136 * DEV_CACHED 011 10
137 *
138 * Other attributes:
139 *
140 * DS0 = PRRR[16] = 0 - device shareable property
141 * DS1 = PRRR[17] = 1 - device shareable property
142 * NS0 = PRRR[18] = 0 - normal shareable property
143 * NS1 = PRRR[19] = 1 - normal shareable property
144 * NOS = PRRR[24+n] = 1 - not outer shareable
145 */
146.equ PRRR, 0xff0a81a8
147.equ NMRR, 0x40e040e0
148
149 /*
150 * Macro for setting up the TTBRx and TTBCR registers.
151 * - \ttb0 and \ttb1 updated with the corresponding flags.
152 */
153 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
154 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
155 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
156 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
157 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
158 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
159 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
160 .endm
161
162 /* AT
163 * TFR EV X F I D LR S
164 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
165 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
166 * 01 0 110 0011 1100 .111 1101 < we want
167 */
168 .align 2
169 .type v7_crval, #object
170v7_crval:
171 crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/mm/proc-v7-2level.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 */
7
8#define TTB_S (1 << 1)
9#define TTB_RGN_NC (0 << 3)
10#define TTB_RGN_OC_WBWA (1 << 3)
11#define TTB_RGN_OC_WT (2 << 3)
12#define TTB_RGN_OC_WB (3 << 3)
13#define TTB_NOS (1 << 5)
14#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
15#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
16#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
17#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
18
19/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
20#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
21#define PMD_FLAGS_UP PMD_SECT_WB
22
23/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
24#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
25#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
26
27/*
28 * cpu_v7_switch_mm(pgd_phys, tsk)
29 *
30 * Set the translation table base pointer to be pgd_phys
31 *
32 * - pgd_phys - physical address of new TTB
33 *
34 * It is assumed that:
35 * - we are not using split page tables
36 *
37 * Note that we always need to flush BTAC/BTB if IBE is set
38 * even on Cortex-A8 revisions not affected by 430973.
39 * If IBE is not set, the flush BTAC/BTB won't do anything.
40 */
41ENTRY(cpu_v7_switch_mm)
42#ifdef CONFIG_MMU
43 mmid r1, r1 @ get mm->context.id
44 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
45 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
46#ifdef CONFIG_PID_IN_CONTEXTIDR
47 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
48 lsr r2, r2, #8 @ extract the PID
49 bfi r1, r2, #8, #24 @ insert into new context ID
50#endif
51#ifdef CONFIG_ARM_ERRATA_754322
52 dsb
53#endif
54 mcr p15, 0, r1, c13, c0, 1 @ set context ID
55 isb
56 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
57 isb
58#endif
59 bx lr
60ENDPROC(cpu_v7_switch_mm)
61
62/*
63 * cpu_v7_set_pte_ext(ptep, pte)
64 *
65 * Set a level 2 translation table entry.
66 *
67 * - ptep - pointer to level 2 translation table entry
68 * (hardware version is stored at +2048 bytes)
69 * - pte - PTE value to store
70 * - ext - value for extended PTE bits
71 */
72ENTRY(cpu_v7_set_pte_ext)
73#ifdef CONFIG_MMU
74 str r1, [r0] @ linux version
75
76 bic r3, r1, #0x000003f0
77 bic r3, r3, #PTE_TYPE_MASK
78 orr r3, r3, r2
79 orr r3, r3, #PTE_EXT_AP0 | 2
80
81 tst r1, #1 << 4
82 orrne r3, r3, #PTE_EXT_TEX(1)
83
84 eor r1, r1, #L_PTE_DIRTY
85 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
86 orrne r3, r3, #PTE_EXT_APX
87
88 tst r1, #L_PTE_USER
89 orrne r3, r3, #PTE_EXT_AP1
90
91 tst r1, #L_PTE_XN
92 orrne r3, r3, #PTE_EXT_XN
93
94 tst r1, #L_PTE_YOUNG
95 tstne r1, #L_PTE_VALID
96 eorne r1, r1, #L_PTE_NONE
97 tstne r1, #L_PTE_NONE
98 moveq r3, #0
99
100 ARM( str r3, [r0, #2048]! )
101 THUMB( add r0, r0, #2048 )
102 THUMB( str r3, [r0] )
103 ALT_SMP(W(nop))
104 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
105#endif
106 bx lr
107ENDPROC(cpu_v7_set_pte_ext)
108
109 /*
110 * Memory region attributes with SCTLR.TRE=1
111 *
112 * n = TEX[0],C,B
113 * TR = PRRR[2n+1:2n] - memory type
114 * IR = NMRR[2n+1:2n] - inner cacheable property
115 * OR = NMRR[2n+17:2n+16] - outer cacheable property
116 *
117 * n TR IR OR
118 * UNCACHED 000 00
119 * BUFFERABLE 001 10 00 00
120 * WRITETHROUGH 010 10 10 10
121 * WRITEBACK 011 10 11 11
122 * reserved 110
123 * WRITEALLOC 111 10 01 01
124 * DEV_SHARED 100 01
125 * DEV_NONSHARED 100 01
126 * DEV_WC 001 10
127 * DEV_CACHED 011 10
128 *
129 * Other attributes:
130 *
131 * DS0 = PRRR[16] = 0 - device shareable property
132 * DS1 = PRRR[17] = 1 - device shareable property
133 * NS0 = PRRR[18] = 0 - normal shareable property
134 * NS1 = PRRR[19] = 1 - normal shareable property
135 * NOS = PRRR[24+n] = 1 - not outer shareable
136 */
137.equ PRRR, 0xff0a81a8
138.equ NMRR, 0x40e040e0
139
140 /*
141 * Macro for setting up the TTBRx and TTBCR registers.
142 * - \ttb0 and \ttb1 updated with the corresponding flags.
143 */
144 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
145 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
146 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
147 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
148 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
149 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
150 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
151 .endm
152
153 /* AT
154 * TFR EV X F I D LR S
155 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
156 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
157 * 01 0 110 0011 1100 .111 1101 < we want
158 */
159 .align 2
160 .type v7_crval, #object
161v7_crval:
162 crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c