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1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef XILINX_LL_TEMAC_H
4#define XILINX_LL_TEMAC_H
5
6#include <linux/netdevice.h>
7#include <linux/of.h>
8#include <linux/spinlock.h>
9
10#ifdef CONFIG_PPC_DCR
11#include <asm/dcr.h>
12#include <asm/dcr-regs.h>
13#endif
14
15/* packet size info */
16#define XTE_HDR_SIZE 14 /* size of Ethernet header */
17#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
18#define XTE_JUMBO_MTU 9000
19#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
20
21/* Configuration options */
22
23/* Accept all incoming packets.
24 * This option defaults to disabled (cleared) */
25#define XTE_OPTION_PROMISC (1 << 0)
26/* Jumbo frame support for Tx & Rx.
27 * This option defaults to disabled (cleared) */
28#define XTE_OPTION_JUMBO (1 << 1)
29/* VLAN Rx & Tx frame support.
30 * This option defaults to disabled (cleared) */
31#define XTE_OPTION_VLAN (1 << 2)
32/* Enable recognition of flow control frames on Rx
33 * This option defaults to enabled (set) */
34#define XTE_OPTION_FLOW_CONTROL (1 << 4)
35/* Strip FCS and PAD from incoming frames.
36 * Note: PAD from VLAN frames is not stripped.
37 * This option defaults to disabled (set) */
38#define XTE_OPTION_FCS_STRIP (1 << 5)
39/* Generate FCS field and add PAD automatically for outgoing frames.
40 * This option defaults to enabled (set) */
41#define XTE_OPTION_FCS_INSERT (1 << 6)
42/* Enable Length/Type error checking for incoming frames. When this option is
43set, the MAC will filter frames that have a mismatched type/length field
44and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
45types of frames are encountered. When this option is cleared, the MAC will
46allow these types of frames to be received.
47This option defaults to enabled (set) */
48#define XTE_OPTION_LENTYPE_ERR (1 << 7)
49/* Enable the transmitter.
50 * This option defaults to enabled (set) */
51#define XTE_OPTION_TXEN (1 << 11)
52/* Enable the receiver
53* This option defaults to enabled (set) */
54#define XTE_OPTION_RXEN (1 << 12)
55
56/* Default options set when device is initialized or reset */
57#define XTE_OPTION_DEFAULTS \
58 (XTE_OPTION_TXEN | \
59 XTE_OPTION_FLOW_CONTROL | \
60 XTE_OPTION_RXEN)
61
62/* XPS_LL_TEMAC SDMA registers definition */
63
64#define TX_NXTDESC_PTR 0x00 /* r */
65#define TX_CURBUF_ADDR 0x01 /* r */
66#define TX_CURBUF_LENGTH 0x02 /* r */
67#define TX_CURDESC_PTR 0x03 /* rw */
68#define TX_TAILDESC_PTR 0x04 /* rw */
69#define TX_CHNL_CTRL 0x05 /* rw */
70/*
71 0:7 24:31 IRQTimeout
72 8:15 16:23 IRQCount
73 16:20 11:15 Reserved
74 21 10 0
75 22 9 UseIntOnEnd
76 23 8 LdIRQCnt
77 24 7 IRQEn
78 25:28 3:6 Reserved
79 29 2 IrqErrEn
80 30 1 IrqDlyEn
81 31 0 IrqCoalEn
82*/
83#define CHNL_CTRL_IRQ_IOE (1 << 9)
84#define CHNL_CTRL_IRQ_EN (1 << 7)
85#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
86#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)
87#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
88#define TX_IRQ_REG 0x06 /* rw */
89/*
90 0:7 24:31 DltTmrValue
91 8:15 16:23 ClscCntrValue
92 16:17 14:15 Reserved
93 18:21 10:13 ClscCnt
94 22:23 8:9 DlyCnt
95 24:28 3::7 Reserved
96 29 2 ErrIrq
97 30 1 DlyIrq
98 31 0 CoalIrq
99 */
100#define TX_CHNL_STS 0x07 /* r */
101/*
102 0:9 22:31 Reserved
103 10 21 TailPErr
104 11 20 CmpErr
105 12 19 AddrErr
106 13 18 NxtPErr
107 14 17 CurPErr
108 15 16 BsyWr
109 16:23 8:15 Reserved
110 24 7 Error
111 25 6 IOE
112 26 5 SOE
113 27 4 Cmplt
114 28 3 SOP
115 29 2 EOP
116 30 1 EngBusy
117 31 0 Reserved
118*/
119
120#define RX_NXTDESC_PTR 0x08 /* r */
121#define RX_CURBUF_ADDR 0x09 /* r */
122#define RX_CURBUF_LENGTH 0x0a /* r */
123#define RX_CURDESC_PTR 0x0b /* rw */
124#define RX_TAILDESC_PTR 0x0c /* rw */
125#define RX_CHNL_CTRL 0x0d /* rw */
126/*
127 0:7 24:31 IRQTimeout
128 8:15 16:23 IRQCount
129 16:20 11:15 Reserved
130 21 10 0
131 22 9 UseIntOnEnd
132 23 8 LdIRQCnt
133 24 7 IRQEn
134 25:28 3:6 Reserved
135 29 2 IrqErrEn
136 30 1 IrqDlyEn
137 31 0 IrqCoalEn
138 */
139#define RX_IRQ_REG 0x0e /* rw */
140#define IRQ_COAL (1 << 0)
141#define IRQ_DLY (1 << 1)
142#define IRQ_ERR (1 << 2)
143#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
144/*
145 0:7 24:31 DltTmrValue
146 8:15 16:23 ClscCntrValue
147 16:17 14:15 Reserved
148 18:21 10:13 ClscCnt
149 22:23 8:9 DlyCnt
150 24:28 3::7 Reserved
151*/
152#define RX_CHNL_STS 0x0f /* r */
153#define CHNL_STS_ENGBUSY (1 << 1)
154#define CHNL_STS_EOP (1 << 2)
155#define CHNL_STS_SOP (1 << 3)
156#define CHNL_STS_CMPLT (1 << 4)
157#define CHNL_STS_SOE (1 << 5)
158#define CHNL_STS_IOE (1 << 6)
159#define CHNL_STS_ERR (1 << 7)
160
161#define CHNL_STS_BSYWR (1 << 16)
162#define CHNL_STS_CURPERR (1 << 17)
163#define CHNL_STS_NXTPERR (1 << 18)
164#define CHNL_STS_ADDRERR (1 << 19)
165#define CHNL_STS_CMPERR (1 << 20)
166#define CHNL_STS_TAILERR (1 << 21)
167/*
168 0:9 22:31 Reserved
169 10 21 TailPErr
170 11 20 CmpErr
171 12 19 AddrErr
172 13 18 NxtPErr
173 14 17 CurPErr
174 15 16 BsyWr
175 16:23 8:15 Reserved
176 24 7 Error
177 25 6 IOE
178 26 5 SOE
179 27 4 Cmplt
180 28 3 SOP
181 29 2 EOP
182 30 1 EngBusy
183 31 0 Reserved
184*/
185
186#define DMA_CONTROL_REG 0x10 /* rw */
187#define DMA_CONTROL_RST (1 << 0)
188#define DMA_TAIL_ENABLE (1 << 2)
189
190/* XPS_LL_TEMAC direct registers definition */
191
192#define XTE_RAF0_OFFSET 0x00
193#define RAF0_RST (1 << 0)
194#define RAF0_MCSTREJ (1 << 1)
195#define RAF0_BCSTREJ (1 << 2)
196#define XTE_TPF0_OFFSET 0x04
197#define XTE_IFGP0_OFFSET 0x08
198#define XTE_ISR0_OFFSET 0x0c
199#define ISR0_HARDACSCMPLT (1 << 0)
200#define ISR0_AUTONEG (1 << 1)
201#define ISR0_RXCMPLT (1 << 2)
202#define ISR0_RXREJ (1 << 3)
203#define ISR0_RXFIFOOVR (1 << 4)
204#define ISR0_TXCMPLT (1 << 5)
205#define ISR0_RXDCMLCK (1 << 6)
206
207#define XTE_IPR0_OFFSET 0x10
208#define XTE_IER0_OFFSET 0x14
209
210#define XTE_MSW0_OFFSET 0x20
211#define XTE_LSW0_OFFSET 0x24
212#define XTE_CTL0_OFFSET 0x28
213#define XTE_RDY0_OFFSET 0x2c
214
215#define XTE_RSE_MIIM_RR_MASK 0x0002
216#define XTE_RSE_MIIM_WR_MASK 0x0004
217#define XTE_RSE_CFG_RR_MASK 0x0020
218#define XTE_RSE_CFG_WR_MASK 0x0040
219#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)
220
221/* XPS_LL_TEMAC indirect registers offset definition */
222
223#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */
224#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */
225#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */
226#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */
227#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */
228#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */
229#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */
230#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */
231#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */
232
233#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */
234#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */
235#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */
236#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */
237#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */
238#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */
239#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */
240
241#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */
242#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */
243#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */
244
245#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */
246#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */
247#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */
248#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */
249#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */
250#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */
251
252#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */
253#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */
254#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */
255#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */
256
257#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */
258#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */
259#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */
260#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */
261
262/* Interrupt Request status */
263#define XTE_TIS_OFFSET 0x000003A0
264#define TIS_FRIS (1 << 0)
265#define TIS_MRIS (1 << 1)
266#define TIS_MWIS (1 << 2)
267#define TIS_ARIS (1 << 3)
268#define TIS_AWIS (1 << 4)
269#define TIS_CRIS (1 << 5)
270#define TIS_CWIS (1 << 6)
271
272#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */
273
274/** MII Mamagement Control register (MGTCR) */
275#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */
276#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */
277
278#define CNTLREG_WRITE_ENABLE_MASK 0x8000
279#define CNTLREG_EMAC1SEL_MASK 0x0400
280#define CNTLREG_ADDRESSCODE_MASK 0x03ff
281
282/* CDMAC descriptor status bit definitions */
283
284#define STS_CTRL_APP0_ERR (1 << 31)
285#define STS_CTRL_APP0_IRQONEND (1 << 30)
286/* undoccumented */
287#define STS_CTRL_APP0_STOPONEND (1 << 29)
288#define STS_CTRL_APP0_CMPLT (1 << 28)
289#define STS_CTRL_APP0_SOP (1 << 27)
290#define STS_CTRL_APP0_EOP (1 << 26)
291#define STS_CTRL_APP0_ENGBUSY (1 << 25)
292/* undocumented */
293#define STS_CTRL_APP0_ENGRST (1 << 24)
294
295#define TX_CONTROL_CALC_CSUM_MASK 1
296
297#define MULTICAST_CAM_TABLE_NUM 4
298
299/* TEMAC Synthesis features */
300#define TEMAC_FEATURE_RX_CSUM (1 << 0)
301#define TEMAC_FEATURE_TX_CSUM (1 << 1)
302
303/* TX/RX CURDESC_PTR points to first descriptor */
304/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
305
306/**
307 * struct cdmac_bd - LocalLink buffer descriptor format
308 *
309 * app0 bits:
310 * 0 Error
311 * 1 IrqOnEnd generate an interrupt at completion of DMA op
312 * 2 reserved
313 * 3 completed Current descriptor completed
314 * 4 SOP TX - marks first desc/ RX marks first desct
315 * 5 EOP TX marks last desc/RX marks last desc
316 * 6 EngBusy DMA is processing
317 * 7 reserved
318 * 8:31 application specific
319 */
320struct cdmac_bd {
321 u32 next; /* Physical address of next buffer descriptor */
322 u32 phys;
323 u32 len;
324 u32 app0;
325 u32 app1; /* TX start << 16 | insert */
326 u32 app2; /* TX csum */
327 u32 app3;
328 u32 app4; /* skb for TX length for RX */
329};
330
331struct temac_local {
332 struct net_device *ndev;
333 struct device *dev;
334
335 /* Connection to PHY device */
336 struct device_node *phy_node;
337
338 /* MDIO bus data */
339 struct mii_bus *mii_bus; /* MII bus reference */
340
341 /* IO registers, dma functions and IRQs */
342 void __iomem *regs;
343 void __iomem *sdma_regs;
344#ifdef CONFIG_PPC_DCR
345 dcr_host_t sdma_dcrs;
346#endif
347 u32 (*dma_in)(struct temac_local *, int);
348 void (*dma_out)(struct temac_local *, int, u32);
349
350 int tx_irq;
351 int rx_irq;
352 int emac_num;
353
354 struct sk_buff **rx_skb;
355 spinlock_t rx_lock;
356 struct mutex indirect_mutex;
357 u32 options; /* Current options word */
358 int last_link;
359 unsigned int temac_features;
360
361 /* Buffer descriptors */
362 struct cdmac_bd *tx_bd_v;
363 dma_addr_t tx_bd_p;
364 struct cdmac_bd *rx_bd_v;
365 dma_addr_t rx_bd_p;
366 int tx_bd_ci;
367 int tx_bd_next;
368 int tx_bd_tail;
369 int rx_bd_ci;
370};
371
372/* xilinx_temac.c */
373u32 temac_ior(struct temac_local *lp, int offset);
374void temac_iow(struct temac_local *lp, int offset, u32 value);
375int temac_indirect_busywait(struct temac_local *lp);
376u32 temac_indirect_in32(struct temac_local *lp, int reg);
377void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
378
379
380/* xilinx_temac_mdio.c */
381int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
382void temac_mdio_teardown(struct temac_local *lp);
383
384#endif /* XILINX_LL_TEMAC_H */
1
2#ifndef XILINX_LL_TEMAC_H
3#define XILINX_LL_TEMAC_H
4
5#include <linux/netdevice.h>
6#include <linux/of.h>
7#include <linux/spinlock.h>
8
9#ifdef CONFIG_PPC_DCR
10#include <asm/dcr.h>
11#include <asm/dcr-regs.h>
12#endif
13
14/* packet size info */
15#define XTE_HDR_SIZE 14 /* size of Ethernet header */
16#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
17#define XTE_JUMBO_MTU 9000
18#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
19
20/* Configuration options */
21
22/* Accept all incoming packets.
23 * This option defaults to disabled (cleared) */
24#define XTE_OPTION_PROMISC (1 << 0)
25/* Jumbo frame support for Tx & Rx.
26 * This option defaults to disabled (cleared) */
27#define XTE_OPTION_JUMBO (1 << 1)
28/* VLAN Rx & Tx frame support.
29 * This option defaults to disabled (cleared) */
30#define XTE_OPTION_VLAN (1 << 2)
31/* Enable recognition of flow control frames on Rx
32 * This option defaults to enabled (set) */
33#define XTE_OPTION_FLOW_CONTROL (1 << 4)
34/* Strip FCS and PAD from incoming frames.
35 * Note: PAD from VLAN frames is not stripped.
36 * This option defaults to disabled (set) */
37#define XTE_OPTION_FCS_STRIP (1 << 5)
38/* Generate FCS field and add PAD automatically for outgoing frames.
39 * This option defaults to enabled (set) */
40#define XTE_OPTION_FCS_INSERT (1 << 6)
41/* Enable Length/Type error checking for incoming frames. When this option is
42set, the MAC will filter frames that have a mismatched type/length field
43and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
44types of frames are encountered. When this option is cleared, the MAC will
45allow these types of frames to be received.
46This option defaults to enabled (set) */
47#define XTE_OPTION_LENTYPE_ERR (1 << 7)
48/* Enable the transmitter.
49 * This option defaults to enabled (set) */
50#define XTE_OPTION_TXEN (1 << 11)
51/* Enable the receiver
52* This option defaults to enabled (set) */
53#define XTE_OPTION_RXEN (1 << 12)
54
55/* Default options set when device is initialized or reset */
56#define XTE_OPTION_DEFAULTS \
57 (XTE_OPTION_TXEN | \
58 XTE_OPTION_FLOW_CONTROL | \
59 XTE_OPTION_RXEN)
60
61/* XPS_LL_TEMAC SDMA registers definition */
62
63#define TX_NXTDESC_PTR 0x00 /* r */
64#define TX_CURBUF_ADDR 0x01 /* r */
65#define TX_CURBUF_LENGTH 0x02 /* r */
66#define TX_CURDESC_PTR 0x03 /* rw */
67#define TX_TAILDESC_PTR 0x04 /* rw */
68#define TX_CHNL_CTRL 0x05 /* rw */
69/*
70 0:7 24:31 IRQTimeout
71 8:15 16:23 IRQCount
72 16:20 11:15 Reserved
73 21 10 0
74 22 9 UseIntOnEnd
75 23 8 LdIRQCnt
76 24 7 IRQEn
77 25:28 3:6 Reserved
78 29 2 IrqErrEn
79 30 1 IrqDlyEn
80 31 0 IrqCoalEn
81*/
82#define CHNL_CTRL_IRQ_IOE (1 << 9)
83#define CHNL_CTRL_IRQ_EN (1 << 7)
84#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
85#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)
86#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
87#define TX_IRQ_REG 0x06 /* rw */
88/*
89 0:7 24:31 DltTmrValue
90 8:15 16:23 ClscCntrValue
91 16:17 14:15 Reserved
92 18:21 10:13 ClscCnt
93 22:23 8:9 DlyCnt
94 24:28 3::7 Reserved
95 29 2 ErrIrq
96 30 1 DlyIrq
97 31 0 CoalIrq
98 */
99#define TX_CHNL_STS 0x07 /* r */
100/*
101 0:9 22:31 Reserved
102 10 21 TailPErr
103 11 20 CmpErr
104 12 19 AddrErr
105 13 18 NxtPErr
106 14 17 CurPErr
107 15 16 BsyWr
108 16:23 8:15 Reserved
109 24 7 Error
110 25 6 IOE
111 26 5 SOE
112 27 4 Cmplt
113 28 3 SOP
114 29 2 EOP
115 30 1 EngBusy
116 31 0 Reserved
117*/
118
119#define RX_NXTDESC_PTR 0x08 /* r */
120#define RX_CURBUF_ADDR 0x09 /* r */
121#define RX_CURBUF_LENGTH 0x0a /* r */
122#define RX_CURDESC_PTR 0x0b /* rw */
123#define RX_TAILDESC_PTR 0x0c /* rw */
124#define RX_CHNL_CTRL 0x0d /* rw */
125/*
126 0:7 24:31 IRQTimeout
127 8:15 16:23 IRQCount
128 16:20 11:15 Reserved
129 21 10 0
130 22 9 UseIntOnEnd
131 23 8 LdIRQCnt
132 24 7 IRQEn
133 25:28 3:6 Reserved
134 29 2 IrqErrEn
135 30 1 IrqDlyEn
136 31 0 IrqCoalEn
137 */
138#define RX_IRQ_REG 0x0e /* rw */
139#define IRQ_COAL (1 << 0)
140#define IRQ_DLY (1 << 1)
141#define IRQ_ERR (1 << 2)
142#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
143/*
144 0:7 24:31 DltTmrValue
145 8:15 16:23 ClscCntrValue
146 16:17 14:15 Reserved
147 18:21 10:13 ClscCnt
148 22:23 8:9 DlyCnt
149 24:28 3::7 Reserved
150*/
151#define RX_CHNL_STS 0x0f /* r */
152#define CHNL_STS_ENGBUSY (1 << 1)
153#define CHNL_STS_EOP (1 << 2)
154#define CHNL_STS_SOP (1 << 3)
155#define CHNL_STS_CMPLT (1 << 4)
156#define CHNL_STS_SOE (1 << 5)
157#define CHNL_STS_IOE (1 << 6)
158#define CHNL_STS_ERR (1 << 7)
159
160#define CHNL_STS_BSYWR (1 << 16)
161#define CHNL_STS_CURPERR (1 << 17)
162#define CHNL_STS_NXTPERR (1 << 18)
163#define CHNL_STS_ADDRERR (1 << 19)
164#define CHNL_STS_CMPERR (1 << 20)
165#define CHNL_STS_TAILERR (1 << 21)
166/*
167 0:9 22:31 Reserved
168 10 21 TailPErr
169 11 20 CmpErr
170 12 19 AddrErr
171 13 18 NxtPErr
172 14 17 CurPErr
173 15 16 BsyWr
174 16:23 8:15 Reserved
175 24 7 Error
176 25 6 IOE
177 26 5 SOE
178 27 4 Cmplt
179 28 3 SOP
180 29 2 EOP
181 30 1 EngBusy
182 31 0 Reserved
183*/
184
185#define DMA_CONTROL_REG 0x10 /* rw */
186#define DMA_CONTROL_RST (1 << 0)
187#define DMA_TAIL_ENABLE (1 << 2)
188
189/* XPS_LL_TEMAC direct registers definition */
190
191#define XTE_RAF0_OFFSET 0x00
192#define RAF0_RST (1 << 0)
193#define RAF0_MCSTREJ (1 << 1)
194#define RAF0_BCSTREJ (1 << 2)
195#define XTE_TPF0_OFFSET 0x04
196#define XTE_IFGP0_OFFSET 0x08
197#define XTE_ISR0_OFFSET 0x0c
198#define ISR0_HARDACSCMPLT (1 << 0)
199#define ISR0_AUTONEG (1 << 1)
200#define ISR0_RXCMPLT (1 << 2)
201#define ISR0_RXREJ (1 << 3)
202#define ISR0_RXFIFOOVR (1 << 4)
203#define ISR0_TXCMPLT (1 << 5)
204#define ISR0_RXDCMLCK (1 << 6)
205
206#define XTE_IPR0_OFFSET 0x10
207#define XTE_IER0_OFFSET 0x14
208
209#define XTE_MSW0_OFFSET 0x20
210#define XTE_LSW0_OFFSET 0x24
211#define XTE_CTL0_OFFSET 0x28
212#define XTE_RDY0_OFFSET 0x2c
213
214#define XTE_RSE_MIIM_RR_MASK 0x0002
215#define XTE_RSE_MIIM_WR_MASK 0x0004
216#define XTE_RSE_CFG_RR_MASK 0x0020
217#define XTE_RSE_CFG_WR_MASK 0x0040
218#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)
219
220/* XPS_LL_TEMAC indirect registers offset definition */
221
222#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */
223#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */
224#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */
225#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */
226#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */
227#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */
228#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */
229#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */
230#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */
231
232#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */
233#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */
234#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */
235#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */
236#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */
237#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */
238#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */
239
240#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */
241#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */
242#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */
243
244#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */
245#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */
246#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */
247#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */
248#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */
249#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */
250
251#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */
252#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */
253#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */
254#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */
255
256#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */
257#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */
258#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */
259#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */
260
261/* Interrupt Request status */
262#define XTE_TIS_OFFSET 0x000003A0
263#define TIS_FRIS (1 << 0)
264#define TIS_MRIS (1 << 1)
265#define TIS_MWIS (1 << 2)
266#define TIS_ARIS (1 << 3)
267#define TIS_AWIS (1 << 4)
268#define TIS_CRIS (1 << 5)
269#define TIS_CWIS (1 << 6)
270
271#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */
272
273/** MII Mamagement Control register (MGTCR) */
274#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */
275#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */
276
277#define CNTLREG_WRITE_ENABLE_MASK 0x8000
278#define CNTLREG_EMAC1SEL_MASK 0x0400
279#define CNTLREG_ADDRESSCODE_MASK 0x03ff
280
281/* CDMAC descriptor status bit definitions */
282
283#define STS_CTRL_APP0_ERR (1 << 31)
284#define STS_CTRL_APP0_IRQONEND (1 << 30)
285/* undoccumented */
286#define STS_CTRL_APP0_STOPONEND (1 << 29)
287#define STS_CTRL_APP0_CMPLT (1 << 28)
288#define STS_CTRL_APP0_SOP (1 << 27)
289#define STS_CTRL_APP0_EOP (1 << 26)
290#define STS_CTRL_APP0_ENGBUSY (1 << 25)
291/* undocumented */
292#define STS_CTRL_APP0_ENGRST (1 << 24)
293
294#define TX_CONTROL_CALC_CSUM_MASK 1
295
296#define MULTICAST_CAM_TABLE_NUM 4
297
298/* TEMAC Synthesis features */
299#define TEMAC_FEATURE_RX_CSUM (1 << 0)
300#define TEMAC_FEATURE_TX_CSUM (1 << 1)
301
302/* TX/RX CURDESC_PTR points to first descriptor */
303/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
304
305/**
306 * struct cdmac_bd - LocalLink buffer descriptor format
307 *
308 * app0 bits:
309 * 0 Error
310 * 1 IrqOnEnd generate an interrupt at completion of DMA op
311 * 2 reserved
312 * 3 completed Current descriptor completed
313 * 4 SOP TX - marks first desc/ RX marks first desct
314 * 5 EOP TX marks last desc/RX marks last desc
315 * 6 EngBusy DMA is processing
316 * 7 reserved
317 * 8:31 application specific
318 */
319struct cdmac_bd {
320 u32 next; /* Physical address of next buffer descriptor */
321 u32 phys;
322 u32 len;
323 u32 app0;
324 u32 app1; /* TX start << 16 | insert */
325 u32 app2; /* TX csum */
326 u32 app3;
327 u32 app4; /* skb for TX length for RX */
328};
329
330struct temac_local {
331 struct net_device *ndev;
332 struct device *dev;
333
334 /* Connection to PHY device */
335 struct phy_device *phy_dev; /* Pointer to PHY device */
336 struct device_node *phy_node;
337
338 /* MDIO bus data */
339 struct mii_bus *mii_bus; /* MII bus reference */
340
341 /* IO registers, dma functions and IRQs */
342 void __iomem *regs;
343 void __iomem *sdma_regs;
344#ifdef CONFIG_PPC_DCR
345 dcr_host_t sdma_dcrs;
346#endif
347 u32 (*dma_in)(struct temac_local *, int);
348 void (*dma_out)(struct temac_local *, int, u32);
349
350 int tx_irq;
351 int rx_irq;
352 int emac_num;
353
354 struct sk_buff **rx_skb;
355 spinlock_t rx_lock;
356 struct mutex indirect_mutex;
357 u32 options; /* Current options word */
358 int last_link;
359 unsigned int temac_features;
360
361 /* Buffer descriptors */
362 struct cdmac_bd *tx_bd_v;
363 dma_addr_t tx_bd_p;
364 struct cdmac_bd *rx_bd_v;
365 dma_addr_t rx_bd_p;
366 int tx_bd_ci;
367 int tx_bd_next;
368 int tx_bd_tail;
369 int rx_bd_ci;
370};
371
372/* xilinx_temac.c */
373u32 temac_ior(struct temac_local *lp, int offset);
374void temac_iow(struct temac_local *lp, int offset, u32 value);
375int temac_indirect_busywait(struct temac_local *lp);
376u32 temac_indirect_in32(struct temac_local *lp, int reg);
377void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
378
379
380/* xilinx_temac_mdio.c */
381int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
382void temac_mdio_teardown(struct temac_local *lp);
383
384#endif /* XILINX_LL_TEMAC_H */