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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Intel PRO/1000 Linux driver
3 * Copyright(c) 1999 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 * Contact Information:
18 * Linux NICS <linux.nics@intel.com>
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 */
22
23#ifndef _E1000_HW_H_
24#define _E1000_HW_H_
25
26#include "regs.h"
27#include "defines.h"
28
29struct e1000_hw;
30
31#define E1000_DEV_ID_82571EB_COPPER 0x105E
32#define E1000_DEV_ID_82571EB_FIBER 0x105F
33#define E1000_DEV_ID_82571EB_SERDES 0x1060
34#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
35#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
36#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
37#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
38#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
39#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
40#define E1000_DEV_ID_82572EI_COPPER 0x107D
41#define E1000_DEV_ID_82572EI_FIBER 0x107E
42#define E1000_DEV_ID_82572EI_SERDES 0x107F
43#define E1000_DEV_ID_82572EI 0x10B9
44#define E1000_DEV_ID_82573E 0x108B
45#define E1000_DEV_ID_82573E_IAMT 0x108C
46#define E1000_DEV_ID_82573L 0x109A
47#define E1000_DEV_ID_82574L 0x10D3
48#define E1000_DEV_ID_82574LA 0x10F6
49#define E1000_DEV_ID_82583V 0x150C
50#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
51#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
52#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
53#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
54#define E1000_DEV_ID_ICH8_82567V_3 0x1501
55#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
56#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
57#define E1000_DEV_ID_ICH8_IGP_C 0x104B
58#define E1000_DEV_ID_ICH8_IFE 0x104C
59#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
60#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
61#define E1000_DEV_ID_ICH8_IGP_M 0x104D
62#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
63#define E1000_DEV_ID_ICH9_BM 0x10E5
64#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
65#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
66#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
67#define E1000_DEV_ID_ICH9_IGP_C 0x294C
68#define E1000_DEV_ID_ICH9_IFE 0x10C0
69#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
70#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
71#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
72#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
73#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
74#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
75#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
76#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
77#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
78#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
79#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
80#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
81#define E1000_DEV_ID_PCH2_LV_LM 0x1502
82#define E1000_DEV_ID_PCH2_LV_V 0x1503
83#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
84#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
85#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
86#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
87#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
88#define E1000_DEV_ID_PCH_I218_V2 0x15A1
89#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
90#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
91#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
92#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
93#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
94#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
95#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
96#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
97#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
98#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
99#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
100#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
101#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
102#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
103#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
104#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
105#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
106#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
107#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
108
109#define E1000_REVISION_4 4
110
111#define E1000_FUNC_1 1
112
113#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
114#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
115
116enum e1000_mac_type {
117 e1000_82571,
118 e1000_82572,
119 e1000_82573,
120 e1000_82574,
121 e1000_82583,
122 e1000_80003es2lan,
123 e1000_ich8lan,
124 e1000_ich9lan,
125 e1000_ich10lan,
126 e1000_pchlan,
127 e1000_pch2lan,
128 e1000_pch_lpt,
129 e1000_pch_spt,
130 e1000_pch_cnp,
131};
132
133enum e1000_media_type {
134 e1000_media_type_unknown = 0,
135 e1000_media_type_copper = 1,
136 e1000_media_type_fiber = 2,
137 e1000_media_type_internal_serdes = 3,
138 e1000_num_media_types
139};
140
141enum e1000_nvm_type {
142 e1000_nvm_unknown = 0,
143 e1000_nvm_none,
144 e1000_nvm_eeprom_spi,
145 e1000_nvm_flash_hw,
146 e1000_nvm_flash_sw
147};
148
149enum e1000_nvm_override {
150 e1000_nvm_override_none = 0,
151 e1000_nvm_override_spi_small,
152 e1000_nvm_override_spi_large
153};
154
155enum e1000_phy_type {
156 e1000_phy_unknown = 0,
157 e1000_phy_none,
158 e1000_phy_m88,
159 e1000_phy_igp,
160 e1000_phy_igp_2,
161 e1000_phy_gg82563,
162 e1000_phy_igp_3,
163 e1000_phy_ife,
164 e1000_phy_bm,
165 e1000_phy_82578,
166 e1000_phy_82577,
167 e1000_phy_82579,
168 e1000_phy_i217,
169};
170
171enum e1000_bus_width {
172 e1000_bus_width_unknown = 0,
173 e1000_bus_width_pcie_x1,
174 e1000_bus_width_pcie_x2,
175 e1000_bus_width_pcie_x4 = 4,
176 e1000_bus_width_pcie_x8 = 8,
177 e1000_bus_width_32,
178 e1000_bus_width_64,
179 e1000_bus_width_reserved
180};
181
182enum e1000_1000t_rx_status {
183 e1000_1000t_rx_status_not_ok = 0,
184 e1000_1000t_rx_status_ok,
185 e1000_1000t_rx_status_undefined = 0xFF
186};
187
188enum e1000_rev_polarity {
189 e1000_rev_polarity_normal = 0,
190 e1000_rev_polarity_reversed,
191 e1000_rev_polarity_undefined = 0xFF
192};
193
194enum e1000_fc_mode {
195 e1000_fc_none = 0,
196 e1000_fc_rx_pause,
197 e1000_fc_tx_pause,
198 e1000_fc_full,
199 e1000_fc_default = 0xFF
200};
201
202enum e1000_ms_type {
203 e1000_ms_hw_default = 0,
204 e1000_ms_force_master,
205 e1000_ms_force_slave,
206 e1000_ms_auto
207};
208
209enum e1000_smart_speed {
210 e1000_smart_speed_default = 0,
211 e1000_smart_speed_on,
212 e1000_smart_speed_off
213};
214
215enum e1000_serdes_link_state {
216 e1000_serdes_link_down = 0,
217 e1000_serdes_link_autoneg_progress,
218 e1000_serdes_link_autoneg_complete,
219 e1000_serdes_link_forced_up
220};
221
222/* Receive Descriptor - Extended */
223union e1000_rx_desc_extended {
224 struct {
225 __le64 buffer_addr;
226 __le64 reserved;
227 } read;
228 struct {
229 struct {
230 __le32 mrq; /* Multiple Rx Queues */
231 union {
232 __le32 rss; /* RSS Hash */
233 struct {
234 __le16 ip_id; /* IP id */
235 __le16 csum; /* Packet Checksum */
236 } csum_ip;
237 } hi_dword;
238 } lower;
239 struct {
240 __le32 status_error; /* ext status/error */
241 __le16 length;
242 __le16 vlan; /* VLAN tag */
243 } upper;
244 } wb; /* writeback */
245};
246
247#define MAX_PS_BUFFERS 4
248
249/* Number of packet split data buffers (not including the header buffer) */
250#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
251
252/* Receive Descriptor - Packet Split */
253union e1000_rx_desc_packet_split {
254 struct {
255 /* one buffer for protocol header(s), three data buffers */
256 __le64 buffer_addr[MAX_PS_BUFFERS];
257 } read;
258 struct {
259 struct {
260 __le32 mrq; /* Multiple Rx Queues */
261 union {
262 __le32 rss; /* RSS Hash */
263 struct {
264 __le16 ip_id; /* IP id */
265 __le16 csum; /* Packet Checksum */
266 } csum_ip;
267 } hi_dword;
268 } lower;
269 struct {
270 __le32 status_error; /* ext status/error */
271 __le16 length0; /* length of buffer 0 */
272 __le16 vlan; /* VLAN tag */
273 } middle;
274 struct {
275 __le16 header_status;
276 /* length of buffers 1-3 */
277 __le16 length[PS_PAGE_BUFFERS];
278 } upper;
279 __le64 reserved;
280 } wb; /* writeback */
281};
282
283/* Transmit Descriptor */
284struct e1000_tx_desc {
285 __le64 buffer_addr; /* Address of the descriptor's data buffer */
286 union {
287 __le32 data;
288 struct {
289 __le16 length; /* Data buffer length */
290 u8 cso; /* Checksum offset */
291 u8 cmd; /* Descriptor control */
292 } flags;
293 } lower;
294 union {
295 __le32 data;
296 struct {
297 u8 status; /* Descriptor status */
298 u8 css; /* Checksum start */
299 __le16 special;
300 } fields;
301 } upper;
302};
303
304/* Offload Context Descriptor */
305struct e1000_context_desc {
306 union {
307 __le32 ip_config;
308 struct {
309 u8 ipcss; /* IP checksum start */
310 u8 ipcso; /* IP checksum offset */
311 __le16 ipcse; /* IP checksum end */
312 } ip_fields;
313 } lower_setup;
314 union {
315 __le32 tcp_config;
316 struct {
317 u8 tucss; /* TCP checksum start */
318 u8 tucso; /* TCP checksum offset */
319 __le16 tucse; /* TCP checksum end */
320 } tcp_fields;
321 } upper_setup;
322 __le32 cmd_and_length;
323 union {
324 __le32 data;
325 struct {
326 u8 status; /* Descriptor status */
327 u8 hdr_len; /* Header length */
328 __le16 mss; /* Maximum segment size */
329 } fields;
330 } tcp_seg_setup;
331};
332
333/* Offload data descriptor */
334struct e1000_data_desc {
335 __le64 buffer_addr; /* Address of the descriptor's buffer address */
336 union {
337 __le32 data;
338 struct {
339 __le16 length; /* Data buffer length */
340 u8 typ_len_ext;
341 u8 cmd;
342 } flags;
343 } lower;
344 union {
345 __le32 data;
346 struct {
347 u8 status; /* Descriptor status */
348 u8 popts; /* Packet Options */
349 __le16 special;
350 } fields;
351 } upper;
352};
353
354/* Statistics counters collected by the MAC */
355struct e1000_hw_stats {
356 u64 crcerrs;
357 u64 algnerrc;
358 u64 symerrs;
359 u64 rxerrc;
360 u64 mpc;
361 u64 scc;
362 u64 ecol;
363 u64 mcc;
364 u64 latecol;
365 u64 colc;
366 u64 dc;
367 u64 tncrs;
368 u64 sec;
369 u64 cexterr;
370 u64 rlec;
371 u64 xonrxc;
372 u64 xontxc;
373 u64 xoffrxc;
374 u64 xofftxc;
375 u64 fcruc;
376 u64 prc64;
377 u64 prc127;
378 u64 prc255;
379 u64 prc511;
380 u64 prc1023;
381 u64 prc1522;
382 u64 gprc;
383 u64 bprc;
384 u64 mprc;
385 u64 gptc;
386 u64 gorc;
387 u64 gotc;
388 u64 rnbc;
389 u64 ruc;
390 u64 rfc;
391 u64 roc;
392 u64 rjc;
393 u64 mgprc;
394 u64 mgpdc;
395 u64 mgptc;
396 u64 tor;
397 u64 tot;
398 u64 tpr;
399 u64 tpt;
400 u64 ptc64;
401 u64 ptc127;
402 u64 ptc255;
403 u64 ptc511;
404 u64 ptc1023;
405 u64 ptc1522;
406 u64 mptc;
407 u64 bptc;
408 u64 tsctc;
409 u64 tsctfc;
410 u64 iac;
411 u64 icrxptc;
412 u64 icrxatc;
413 u64 ictxptc;
414 u64 ictxatc;
415 u64 ictxqec;
416 u64 ictxqmtc;
417 u64 icrxdmtc;
418 u64 icrxoc;
419};
420
421struct e1000_phy_stats {
422 u32 idle_errors;
423 u32 receive_errors;
424};
425
426struct e1000_host_mng_dhcp_cookie {
427 u32 signature;
428 u8 status;
429 u8 reserved0;
430 u16 vlan_id;
431 u32 reserved1;
432 u16 reserved2;
433 u8 reserved3;
434 u8 checksum;
435};
436
437/* Host Interface "Rev 1" */
438struct e1000_host_command_header {
439 u8 command_id;
440 u8 command_length;
441 u8 command_options;
442 u8 checksum;
443};
444
445#define E1000_HI_MAX_DATA_LENGTH 252
446struct e1000_host_command_info {
447 struct e1000_host_command_header command_header;
448 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
449};
450
451/* Host Interface "Rev 2" */
452struct e1000_host_mng_command_header {
453 u8 command_id;
454 u8 checksum;
455 u16 reserved1;
456 u16 reserved2;
457 u16 command_length;
458};
459
460#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
461struct e1000_host_mng_command_info {
462 struct e1000_host_mng_command_header command_header;
463 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
464};
465
466#include "mac.h"
467#include "phy.h"
468#include "nvm.h"
469#include "manage.h"
470
471/* Function pointers for the MAC. */
472struct e1000_mac_operations {
473 s32 (*id_led_init)(struct e1000_hw *);
474 s32 (*blink_led)(struct e1000_hw *);
475 bool (*check_mng_mode)(struct e1000_hw *);
476 s32 (*check_for_link)(struct e1000_hw *);
477 s32 (*cleanup_led)(struct e1000_hw *);
478 void (*clear_hw_cntrs)(struct e1000_hw *);
479 void (*clear_vfta)(struct e1000_hw *);
480 s32 (*get_bus_info)(struct e1000_hw *);
481 void (*set_lan_id)(struct e1000_hw *);
482 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
483 s32 (*led_on)(struct e1000_hw *);
484 s32 (*led_off)(struct e1000_hw *);
485 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
486 s32 (*reset_hw)(struct e1000_hw *);
487 s32 (*init_hw)(struct e1000_hw *);
488 s32 (*setup_link)(struct e1000_hw *);
489 s32 (*setup_physical_interface)(struct e1000_hw *);
490 s32 (*setup_led)(struct e1000_hw *);
491 void (*write_vfta)(struct e1000_hw *, u32, u32);
492 void (*config_collision_dist)(struct e1000_hw *);
493 int (*rar_set)(struct e1000_hw *, u8 *, u32);
494 s32 (*read_mac_addr)(struct e1000_hw *);
495 u32 (*rar_get_count)(struct e1000_hw *);
496};
497
498/* When to use various PHY register access functions:
499 *
500 * Func Caller
501 * Function Does Does When to use
502 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
503 * X_reg L,P,A n/a for simple PHY reg accesses
504 * X_reg_locked P,A L for multiple accesses of different regs
505 * on different pages
506 * X_reg_page A L,P for multiple accesses of different regs
507 * on the same page
508 *
509 * Where X=[read|write], L=locking, P=sets page, A=register access
510 *
511 */
512struct e1000_phy_operations {
513 s32 (*acquire)(struct e1000_hw *);
514 s32 (*cfg_on_link_up)(struct e1000_hw *);
515 s32 (*check_polarity)(struct e1000_hw *);
516 s32 (*check_reset_block)(struct e1000_hw *);
517 s32 (*commit)(struct e1000_hw *);
518 s32 (*force_speed_duplex)(struct e1000_hw *);
519 s32 (*get_cfg_done)(struct e1000_hw *hw);
520 s32 (*get_cable_length)(struct e1000_hw *);
521 s32 (*get_info)(struct e1000_hw *);
522 s32 (*set_page)(struct e1000_hw *, u16);
523 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
524 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
525 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
526 void (*release)(struct e1000_hw *);
527 s32 (*reset)(struct e1000_hw *);
528 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
529 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
530 s32 (*write_reg)(struct e1000_hw *, u32, u16);
531 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
532 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
533 void (*power_up)(struct e1000_hw *);
534 void (*power_down)(struct e1000_hw *);
535};
536
537/* Function pointers for the NVM. */
538struct e1000_nvm_operations {
539 s32 (*acquire)(struct e1000_hw *);
540 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
541 void (*release)(struct e1000_hw *);
542 void (*reload)(struct e1000_hw *);
543 s32 (*update)(struct e1000_hw *);
544 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
545 s32 (*validate)(struct e1000_hw *);
546 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
547};
548
549struct e1000_mac_info {
550 struct e1000_mac_operations ops;
551 u8 addr[ETH_ALEN];
552 u8 perm_addr[ETH_ALEN];
553
554 enum e1000_mac_type type;
555
556 u32 collision_delta;
557 u32 ledctl_default;
558 u32 ledctl_mode1;
559 u32 ledctl_mode2;
560 u32 mc_filter_type;
561 u32 tx_packet_delta;
562 u32 txcw;
563
564 u16 current_ifs_val;
565 u16 ifs_max_val;
566 u16 ifs_min_val;
567 u16 ifs_ratio;
568 u16 ifs_step_size;
569 u16 mta_reg_count;
570
571 /* Maximum size of the MTA register table in all supported adapters */
572#define MAX_MTA_REG 128
573 u32 mta_shadow[MAX_MTA_REG];
574 u16 rar_entry_count;
575
576 u8 forced_speed_duplex;
577
578 bool adaptive_ifs;
579 bool has_fwsm;
580 bool arc_subsystem_valid;
581 bool autoneg;
582 bool autoneg_failed;
583 bool get_link_status;
584 bool in_ifs_mode;
585 bool serdes_has_link;
586 bool tx_pkt_filtering;
587 enum e1000_serdes_link_state serdes_link_state;
588};
589
590struct e1000_phy_info {
591 struct e1000_phy_operations ops;
592
593 enum e1000_phy_type type;
594
595 enum e1000_1000t_rx_status local_rx;
596 enum e1000_1000t_rx_status remote_rx;
597 enum e1000_ms_type ms_type;
598 enum e1000_ms_type original_ms_type;
599 enum e1000_rev_polarity cable_polarity;
600 enum e1000_smart_speed smart_speed;
601
602 u32 addr;
603 u32 id;
604 u32 reset_delay_us; /* in usec */
605 u32 revision;
606
607 enum e1000_media_type media_type;
608
609 u16 autoneg_advertised;
610 u16 autoneg_mask;
611 u16 cable_length;
612 u16 max_cable_length;
613 u16 min_cable_length;
614
615 u8 mdix;
616
617 bool disable_polarity_correction;
618 bool is_mdix;
619 bool polarity_correction;
620 bool speed_downgraded;
621 bool autoneg_wait_to_complete;
622};
623
624struct e1000_nvm_info {
625 struct e1000_nvm_operations ops;
626
627 enum e1000_nvm_type type;
628 enum e1000_nvm_override override;
629
630 u32 flash_bank_size;
631 u32 flash_base_addr;
632
633 u16 word_size;
634 u16 delay_usec;
635 u16 address_bits;
636 u16 opcode_bits;
637 u16 page_size;
638};
639
640struct e1000_bus_info {
641 enum e1000_bus_width width;
642
643 u16 func;
644};
645
646struct e1000_fc_info {
647 u32 high_water; /* Flow control high-water mark */
648 u32 low_water; /* Flow control low-water mark */
649 u16 pause_time; /* Flow control pause timer */
650 u16 refresh_time; /* Flow control refresh timer */
651 bool send_xon; /* Flow control send XON */
652 bool strict_ieee; /* Strict IEEE mode */
653 enum e1000_fc_mode current_mode; /* FC mode in effect */
654 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
655};
656
657struct e1000_dev_spec_82571 {
658 bool laa_is_present;
659 u32 smb_counter;
660};
661
662struct e1000_dev_spec_80003es2lan {
663 bool mdic_wa_enable;
664};
665
666struct e1000_shadow_ram {
667 u16 value;
668 bool modified;
669};
670
671#define E1000_ICH8_SHADOW_RAM_WORDS 2048
672
673/* I218 PHY Ultra Low Power (ULP) states */
674enum e1000_ulp_state {
675 e1000_ulp_state_unknown,
676 e1000_ulp_state_off,
677 e1000_ulp_state_on,
678};
679
680struct e1000_dev_spec_ich8lan {
681 bool kmrn_lock_loss_workaround_enabled;
682 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
683 bool nvm_k1_enabled;
684 bool eee_disable;
685 u16 eee_lp_ability;
686 enum e1000_ulp_state ulp_state;
687};
688
689struct e1000_hw {
690 struct e1000_adapter *adapter;
691
692 void __iomem *hw_addr;
693 void __iomem *flash_address;
694
695 struct e1000_mac_info mac;
696 struct e1000_fc_info fc;
697 struct e1000_phy_info phy;
698 struct e1000_nvm_info nvm;
699 struct e1000_bus_info bus;
700 struct e1000_host_mng_dhcp_cookie mng_cookie;
701
702 union {
703 struct e1000_dev_spec_82571 e82571;
704 struct e1000_dev_spec_80003es2lan e80003es2lan;
705 struct e1000_dev_spec_ich8lan ich8lan;
706 } dev_spec;
707};
708
709#include "82571.h"
710#include "80003es2lan.h"
711#include "ich8lan.h"
712
713#endif
1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22#ifndef _E1000_HW_H_
23#define _E1000_HW_H_
24
25#include "regs.h"
26#include "defines.h"
27
28struct e1000_hw;
29
30#define E1000_DEV_ID_82571EB_COPPER 0x105E
31#define E1000_DEV_ID_82571EB_FIBER 0x105F
32#define E1000_DEV_ID_82571EB_SERDES 0x1060
33#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
34#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
35#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
36#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
37#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
38#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
39#define E1000_DEV_ID_82572EI_COPPER 0x107D
40#define E1000_DEV_ID_82572EI_FIBER 0x107E
41#define E1000_DEV_ID_82572EI_SERDES 0x107F
42#define E1000_DEV_ID_82572EI 0x10B9
43#define E1000_DEV_ID_82573E 0x108B
44#define E1000_DEV_ID_82573E_IAMT 0x108C
45#define E1000_DEV_ID_82573L 0x109A
46#define E1000_DEV_ID_82574L 0x10D3
47#define E1000_DEV_ID_82574LA 0x10F6
48#define E1000_DEV_ID_82583V 0x150C
49#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
50#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
51#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
52#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
53#define E1000_DEV_ID_ICH8_82567V_3 0x1501
54#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
55#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
56#define E1000_DEV_ID_ICH8_IGP_C 0x104B
57#define E1000_DEV_ID_ICH8_IFE 0x104C
58#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
59#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
60#define E1000_DEV_ID_ICH8_IGP_M 0x104D
61#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
62#define E1000_DEV_ID_ICH9_BM 0x10E5
63#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
64#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
65#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
66#define E1000_DEV_ID_ICH9_IGP_C 0x294C
67#define E1000_DEV_ID_ICH9_IFE 0x10C0
68#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
69#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
70#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
71#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
72#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
73#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
74#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
75#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
76#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
77#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
78#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
79#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
80#define E1000_DEV_ID_PCH2_LV_LM 0x1502
81#define E1000_DEV_ID_PCH2_LV_V 0x1503
82#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
83#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
84#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
85#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
86#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
87#define E1000_DEV_ID_PCH_I218_V2 0x15A1
88#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
89#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
90#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
91#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
92#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
93#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
94#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
95#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
96#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
97#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
98#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
99
100#define E1000_REVISION_4 4
101
102#define E1000_FUNC_1 1
103
104#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
105#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
106
107enum e1000_mac_type {
108 e1000_82571,
109 e1000_82572,
110 e1000_82573,
111 e1000_82574,
112 e1000_82583,
113 e1000_80003es2lan,
114 e1000_ich8lan,
115 e1000_ich9lan,
116 e1000_ich10lan,
117 e1000_pchlan,
118 e1000_pch2lan,
119 e1000_pch_lpt,
120 e1000_pch_spt,
121};
122
123enum e1000_media_type {
124 e1000_media_type_unknown = 0,
125 e1000_media_type_copper = 1,
126 e1000_media_type_fiber = 2,
127 e1000_media_type_internal_serdes = 3,
128 e1000_num_media_types
129};
130
131enum e1000_nvm_type {
132 e1000_nvm_unknown = 0,
133 e1000_nvm_none,
134 e1000_nvm_eeprom_spi,
135 e1000_nvm_flash_hw,
136 e1000_nvm_flash_sw
137};
138
139enum e1000_nvm_override {
140 e1000_nvm_override_none = 0,
141 e1000_nvm_override_spi_small,
142 e1000_nvm_override_spi_large
143};
144
145enum e1000_phy_type {
146 e1000_phy_unknown = 0,
147 e1000_phy_none,
148 e1000_phy_m88,
149 e1000_phy_igp,
150 e1000_phy_igp_2,
151 e1000_phy_gg82563,
152 e1000_phy_igp_3,
153 e1000_phy_ife,
154 e1000_phy_bm,
155 e1000_phy_82578,
156 e1000_phy_82577,
157 e1000_phy_82579,
158 e1000_phy_i217,
159};
160
161enum e1000_bus_width {
162 e1000_bus_width_unknown = 0,
163 e1000_bus_width_pcie_x1,
164 e1000_bus_width_pcie_x2,
165 e1000_bus_width_pcie_x4 = 4,
166 e1000_bus_width_pcie_x8 = 8,
167 e1000_bus_width_32,
168 e1000_bus_width_64,
169 e1000_bus_width_reserved
170};
171
172enum e1000_1000t_rx_status {
173 e1000_1000t_rx_status_not_ok = 0,
174 e1000_1000t_rx_status_ok,
175 e1000_1000t_rx_status_undefined = 0xFF
176};
177
178enum e1000_rev_polarity {
179 e1000_rev_polarity_normal = 0,
180 e1000_rev_polarity_reversed,
181 e1000_rev_polarity_undefined = 0xFF
182};
183
184enum e1000_fc_mode {
185 e1000_fc_none = 0,
186 e1000_fc_rx_pause,
187 e1000_fc_tx_pause,
188 e1000_fc_full,
189 e1000_fc_default = 0xFF
190};
191
192enum e1000_ms_type {
193 e1000_ms_hw_default = 0,
194 e1000_ms_force_master,
195 e1000_ms_force_slave,
196 e1000_ms_auto
197};
198
199enum e1000_smart_speed {
200 e1000_smart_speed_default = 0,
201 e1000_smart_speed_on,
202 e1000_smart_speed_off
203};
204
205enum e1000_serdes_link_state {
206 e1000_serdes_link_down = 0,
207 e1000_serdes_link_autoneg_progress,
208 e1000_serdes_link_autoneg_complete,
209 e1000_serdes_link_forced_up
210};
211
212/* Receive Descriptor - Extended */
213union e1000_rx_desc_extended {
214 struct {
215 __le64 buffer_addr;
216 __le64 reserved;
217 } read;
218 struct {
219 struct {
220 __le32 mrq; /* Multiple Rx Queues */
221 union {
222 __le32 rss; /* RSS Hash */
223 struct {
224 __le16 ip_id; /* IP id */
225 __le16 csum; /* Packet Checksum */
226 } csum_ip;
227 } hi_dword;
228 } lower;
229 struct {
230 __le32 status_error; /* ext status/error */
231 __le16 length;
232 __le16 vlan; /* VLAN tag */
233 } upper;
234 } wb; /* writeback */
235};
236
237#define MAX_PS_BUFFERS 4
238
239/* Number of packet split data buffers (not including the header buffer) */
240#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
241
242/* Receive Descriptor - Packet Split */
243union e1000_rx_desc_packet_split {
244 struct {
245 /* one buffer for protocol header(s), three data buffers */
246 __le64 buffer_addr[MAX_PS_BUFFERS];
247 } read;
248 struct {
249 struct {
250 __le32 mrq; /* Multiple Rx Queues */
251 union {
252 __le32 rss; /* RSS Hash */
253 struct {
254 __le16 ip_id; /* IP id */
255 __le16 csum; /* Packet Checksum */
256 } csum_ip;
257 } hi_dword;
258 } lower;
259 struct {
260 __le32 status_error; /* ext status/error */
261 __le16 length0; /* length of buffer 0 */
262 __le16 vlan; /* VLAN tag */
263 } middle;
264 struct {
265 __le16 header_status;
266 /* length of buffers 1-3 */
267 __le16 length[PS_PAGE_BUFFERS];
268 } upper;
269 __le64 reserved;
270 } wb; /* writeback */
271};
272
273/* Transmit Descriptor */
274struct e1000_tx_desc {
275 __le64 buffer_addr; /* Address of the descriptor's data buffer */
276 union {
277 __le32 data;
278 struct {
279 __le16 length; /* Data buffer length */
280 u8 cso; /* Checksum offset */
281 u8 cmd; /* Descriptor control */
282 } flags;
283 } lower;
284 union {
285 __le32 data;
286 struct {
287 u8 status; /* Descriptor status */
288 u8 css; /* Checksum start */
289 __le16 special;
290 } fields;
291 } upper;
292};
293
294/* Offload Context Descriptor */
295struct e1000_context_desc {
296 union {
297 __le32 ip_config;
298 struct {
299 u8 ipcss; /* IP checksum start */
300 u8 ipcso; /* IP checksum offset */
301 __le16 ipcse; /* IP checksum end */
302 } ip_fields;
303 } lower_setup;
304 union {
305 __le32 tcp_config;
306 struct {
307 u8 tucss; /* TCP checksum start */
308 u8 tucso; /* TCP checksum offset */
309 __le16 tucse; /* TCP checksum end */
310 } tcp_fields;
311 } upper_setup;
312 __le32 cmd_and_length;
313 union {
314 __le32 data;
315 struct {
316 u8 status; /* Descriptor status */
317 u8 hdr_len; /* Header length */
318 __le16 mss; /* Maximum segment size */
319 } fields;
320 } tcp_seg_setup;
321};
322
323/* Offload data descriptor */
324struct e1000_data_desc {
325 __le64 buffer_addr; /* Address of the descriptor's buffer address */
326 union {
327 __le32 data;
328 struct {
329 __le16 length; /* Data buffer length */
330 u8 typ_len_ext;
331 u8 cmd;
332 } flags;
333 } lower;
334 union {
335 __le32 data;
336 struct {
337 u8 status; /* Descriptor status */
338 u8 popts; /* Packet Options */
339 __le16 special;
340 } fields;
341 } upper;
342};
343
344/* Statistics counters collected by the MAC */
345struct e1000_hw_stats {
346 u64 crcerrs;
347 u64 algnerrc;
348 u64 symerrs;
349 u64 rxerrc;
350 u64 mpc;
351 u64 scc;
352 u64 ecol;
353 u64 mcc;
354 u64 latecol;
355 u64 colc;
356 u64 dc;
357 u64 tncrs;
358 u64 sec;
359 u64 cexterr;
360 u64 rlec;
361 u64 xonrxc;
362 u64 xontxc;
363 u64 xoffrxc;
364 u64 xofftxc;
365 u64 fcruc;
366 u64 prc64;
367 u64 prc127;
368 u64 prc255;
369 u64 prc511;
370 u64 prc1023;
371 u64 prc1522;
372 u64 gprc;
373 u64 bprc;
374 u64 mprc;
375 u64 gptc;
376 u64 gorc;
377 u64 gotc;
378 u64 rnbc;
379 u64 ruc;
380 u64 rfc;
381 u64 roc;
382 u64 rjc;
383 u64 mgprc;
384 u64 mgpdc;
385 u64 mgptc;
386 u64 tor;
387 u64 tot;
388 u64 tpr;
389 u64 tpt;
390 u64 ptc64;
391 u64 ptc127;
392 u64 ptc255;
393 u64 ptc511;
394 u64 ptc1023;
395 u64 ptc1522;
396 u64 mptc;
397 u64 bptc;
398 u64 tsctc;
399 u64 tsctfc;
400 u64 iac;
401 u64 icrxptc;
402 u64 icrxatc;
403 u64 ictxptc;
404 u64 ictxatc;
405 u64 ictxqec;
406 u64 ictxqmtc;
407 u64 icrxdmtc;
408 u64 icrxoc;
409};
410
411struct e1000_phy_stats {
412 u32 idle_errors;
413 u32 receive_errors;
414};
415
416struct e1000_host_mng_dhcp_cookie {
417 u32 signature;
418 u8 status;
419 u8 reserved0;
420 u16 vlan_id;
421 u32 reserved1;
422 u16 reserved2;
423 u8 reserved3;
424 u8 checksum;
425};
426
427/* Host Interface "Rev 1" */
428struct e1000_host_command_header {
429 u8 command_id;
430 u8 command_length;
431 u8 command_options;
432 u8 checksum;
433};
434
435#define E1000_HI_MAX_DATA_LENGTH 252
436struct e1000_host_command_info {
437 struct e1000_host_command_header command_header;
438 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
439};
440
441/* Host Interface "Rev 2" */
442struct e1000_host_mng_command_header {
443 u8 command_id;
444 u8 checksum;
445 u16 reserved1;
446 u16 reserved2;
447 u16 command_length;
448};
449
450#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
451struct e1000_host_mng_command_info {
452 struct e1000_host_mng_command_header command_header;
453 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
454};
455
456#include "mac.h"
457#include "phy.h"
458#include "nvm.h"
459#include "manage.h"
460
461/* Function pointers for the MAC. */
462struct e1000_mac_operations {
463 s32 (*id_led_init)(struct e1000_hw *);
464 s32 (*blink_led)(struct e1000_hw *);
465 bool (*check_mng_mode)(struct e1000_hw *);
466 s32 (*check_for_link)(struct e1000_hw *);
467 s32 (*cleanup_led)(struct e1000_hw *);
468 void (*clear_hw_cntrs)(struct e1000_hw *);
469 void (*clear_vfta)(struct e1000_hw *);
470 s32 (*get_bus_info)(struct e1000_hw *);
471 void (*set_lan_id)(struct e1000_hw *);
472 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
473 s32 (*led_on)(struct e1000_hw *);
474 s32 (*led_off)(struct e1000_hw *);
475 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
476 s32 (*reset_hw)(struct e1000_hw *);
477 s32 (*init_hw)(struct e1000_hw *);
478 s32 (*setup_link)(struct e1000_hw *);
479 s32 (*setup_physical_interface)(struct e1000_hw *);
480 s32 (*setup_led)(struct e1000_hw *);
481 void (*write_vfta)(struct e1000_hw *, u32, u32);
482 void (*config_collision_dist)(struct e1000_hw *);
483 int (*rar_set)(struct e1000_hw *, u8 *, u32);
484 s32 (*read_mac_addr)(struct e1000_hw *);
485 u32 (*rar_get_count)(struct e1000_hw *);
486};
487
488/* When to use various PHY register access functions:
489 *
490 * Func Caller
491 * Function Does Does When to use
492 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
493 * X_reg L,P,A n/a for simple PHY reg accesses
494 * X_reg_locked P,A L for multiple accesses of different regs
495 * on different pages
496 * X_reg_page A L,P for multiple accesses of different regs
497 * on the same page
498 *
499 * Where X=[read|write], L=locking, P=sets page, A=register access
500 *
501 */
502struct e1000_phy_operations {
503 s32 (*acquire)(struct e1000_hw *);
504 s32 (*cfg_on_link_up)(struct e1000_hw *);
505 s32 (*check_polarity)(struct e1000_hw *);
506 s32 (*check_reset_block)(struct e1000_hw *);
507 s32 (*commit)(struct e1000_hw *);
508 s32 (*force_speed_duplex)(struct e1000_hw *);
509 s32 (*get_cfg_done)(struct e1000_hw *hw);
510 s32 (*get_cable_length)(struct e1000_hw *);
511 s32 (*get_info)(struct e1000_hw *);
512 s32 (*set_page)(struct e1000_hw *, u16);
513 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
514 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
515 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
516 void (*release)(struct e1000_hw *);
517 s32 (*reset)(struct e1000_hw *);
518 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
519 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
520 s32 (*write_reg)(struct e1000_hw *, u32, u16);
521 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
522 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
523 void (*power_up)(struct e1000_hw *);
524 void (*power_down)(struct e1000_hw *);
525};
526
527/* Function pointers for the NVM. */
528struct e1000_nvm_operations {
529 s32 (*acquire)(struct e1000_hw *);
530 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
531 void (*release)(struct e1000_hw *);
532 void (*reload)(struct e1000_hw *);
533 s32 (*update)(struct e1000_hw *);
534 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
535 s32 (*validate)(struct e1000_hw *);
536 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
537};
538
539struct e1000_mac_info {
540 struct e1000_mac_operations ops;
541 u8 addr[ETH_ALEN];
542 u8 perm_addr[ETH_ALEN];
543
544 enum e1000_mac_type type;
545
546 u32 collision_delta;
547 u32 ledctl_default;
548 u32 ledctl_mode1;
549 u32 ledctl_mode2;
550 u32 mc_filter_type;
551 u32 tx_packet_delta;
552 u32 txcw;
553
554 u16 current_ifs_val;
555 u16 ifs_max_val;
556 u16 ifs_min_val;
557 u16 ifs_ratio;
558 u16 ifs_step_size;
559 u16 mta_reg_count;
560
561 /* Maximum size of the MTA register table in all supported adapters */
562#define MAX_MTA_REG 128
563 u32 mta_shadow[MAX_MTA_REG];
564 u16 rar_entry_count;
565
566 u8 forced_speed_duplex;
567
568 bool adaptive_ifs;
569 bool has_fwsm;
570 bool arc_subsystem_valid;
571 bool autoneg;
572 bool autoneg_failed;
573 bool get_link_status;
574 bool in_ifs_mode;
575 bool serdes_has_link;
576 bool tx_pkt_filtering;
577 enum e1000_serdes_link_state serdes_link_state;
578};
579
580struct e1000_phy_info {
581 struct e1000_phy_operations ops;
582
583 enum e1000_phy_type type;
584
585 enum e1000_1000t_rx_status local_rx;
586 enum e1000_1000t_rx_status remote_rx;
587 enum e1000_ms_type ms_type;
588 enum e1000_ms_type original_ms_type;
589 enum e1000_rev_polarity cable_polarity;
590 enum e1000_smart_speed smart_speed;
591
592 u32 addr;
593 u32 id;
594 u32 reset_delay_us; /* in usec */
595 u32 revision;
596
597 enum e1000_media_type media_type;
598
599 u16 autoneg_advertised;
600 u16 autoneg_mask;
601 u16 cable_length;
602 u16 max_cable_length;
603 u16 min_cable_length;
604
605 u8 mdix;
606
607 bool disable_polarity_correction;
608 bool is_mdix;
609 bool polarity_correction;
610 bool speed_downgraded;
611 bool autoneg_wait_to_complete;
612};
613
614struct e1000_nvm_info {
615 struct e1000_nvm_operations ops;
616
617 enum e1000_nvm_type type;
618 enum e1000_nvm_override override;
619
620 u32 flash_bank_size;
621 u32 flash_base_addr;
622
623 u16 word_size;
624 u16 delay_usec;
625 u16 address_bits;
626 u16 opcode_bits;
627 u16 page_size;
628};
629
630struct e1000_bus_info {
631 enum e1000_bus_width width;
632
633 u16 func;
634};
635
636struct e1000_fc_info {
637 u32 high_water; /* Flow control high-water mark */
638 u32 low_water; /* Flow control low-water mark */
639 u16 pause_time; /* Flow control pause timer */
640 u16 refresh_time; /* Flow control refresh timer */
641 bool send_xon; /* Flow control send XON */
642 bool strict_ieee; /* Strict IEEE mode */
643 enum e1000_fc_mode current_mode; /* FC mode in effect */
644 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
645};
646
647struct e1000_dev_spec_82571 {
648 bool laa_is_present;
649 u32 smb_counter;
650};
651
652struct e1000_dev_spec_80003es2lan {
653 bool mdic_wa_enable;
654};
655
656struct e1000_shadow_ram {
657 u16 value;
658 bool modified;
659};
660
661#define E1000_ICH8_SHADOW_RAM_WORDS 2048
662
663/* I218 PHY Ultra Low Power (ULP) states */
664enum e1000_ulp_state {
665 e1000_ulp_state_unknown,
666 e1000_ulp_state_off,
667 e1000_ulp_state_on,
668};
669
670struct e1000_dev_spec_ich8lan {
671 bool kmrn_lock_loss_workaround_enabled;
672 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
673 bool nvm_k1_enabled;
674 bool eee_disable;
675 u16 eee_lp_ability;
676 enum e1000_ulp_state ulp_state;
677};
678
679struct e1000_hw {
680 struct e1000_adapter *adapter;
681
682 void __iomem *hw_addr;
683 void __iomem *flash_address;
684
685 struct e1000_mac_info mac;
686 struct e1000_fc_info fc;
687 struct e1000_phy_info phy;
688 struct e1000_nvm_info nvm;
689 struct e1000_bus_info bus;
690 struct e1000_host_mng_dhcp_cookie mng_cookie;
691
692 union {
693 struct e1000_dev_spec_82571 e82571;
694 struct e1000_dev_spec_80003es2lan e80003es2lan;
695 struct e1000_dev_spec_ich8lan ich8lan;
696 } dev_spec;
697};
698
699#include "82571.h"
700#include "80003es2lan.h"
701#include "ich8lan.h"
702
703#endif