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1/*
2 * Copyright (C) 2005 - 2016 Broadcom
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18#include <linux/module.h>
19#include "be.h"
20#include "be_cmds.h"
21
22const char * const be_misconfig_evt_port_state[] = {
23 "Physical Link is functional",
24 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
25 "Optics of two types installed – Remove one optic or install matching pair of optics.",
26 "Incompatible optics – Replace with compatible optics for card to function.",
27 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
28 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
29};
30
31static char *be_port_misconfig_evt_severity[] = {
32 "KERN_WARN",
33 "KERN_INFO",
34 "KERN_ERR",
35 "KERN_WARN"
36};
37
38static char *phy_state_oper_desc[] = {
39 "Link is non-operational",
40 "Link is operational",
41 ""
42};
43
44static struct be_cmd_priv_map cmd_priv_map[] = {
45 {
46 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
47 CMD_SUBSYSTEM_ETH,
48 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_GET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_COMMON_SET_FLOW_CONTROL,
59 CMD_SUBSYSTEM_COMMON,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_ETH_GET_PPORT_STATS,
65 CMD_SUBSYSTEM_ETH,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 },
69 {
70 OPCODE_COMMON_GET_PHY_DETAILS,
71 CMD_SUBSYSTEM_COMMON,
72 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
73 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
74 },
75 {
76 OPCODE_LOWLEVEL_HOST_DDR_DMA,
77 CMD_SUBSYSTEM_LOWLEVEL,
78 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
79 },
80 {
81 OPCODE_LOWLEVEL_LOOPBACK_TEST,
82 CMD_SUBSYSTEM_LOWLEVEL,
83 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
84 },
85 {
86 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
87 CMD_SUBSYSTEM_LOWLEVEL,
88 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
89 },
90 {
91 OPCODE_COMMON_SET_HSW_CONFIG,
92 CMD_SUBSYSTEM_COMMON,
93 BE_PRIV_DEVCFG | BE_PRIV_VHADM |
94 BE_PRIV_DEVSEC
95 },
96 {
97 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
98 CMD_SUBSYSTEM_COMMON,
99 BE_PRIV_DEVCFG
100 }
101};
102
103static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
104{
105 int i;
106 int num_entries = ARRAY_SIZE(cmd_priv_map);
107 u32 cmd_privileges = adapter->cmd_privileges;
108
109 for (i = 0; i < num_entries; i++)
110 if (opcode == cmd_priv_map[i].opcode &&
111 subsystem == cmd_priv_map[i].subsystem)
112 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
113 return false;
114
115 return true;
116}
117
118static inline void *embedded_payload(struct be_mcc_wrb *wrb)
119{
120 return wrb->payload.embedded_payload;
121}
122
123static int be_mcc_notify(struct be_adapter *adapter)
124{
125 struct be_queue_info *mccq = &adapter->mcc_obj.q;
126 u32 val = 0;
127
128 if (be_check_error(adapter, BE_ERROR_ANY))
129 return -EIO;
130
131 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
132 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
133
134 wmb();
135 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
136
137 return 0;
138}
139
140/* To check if valid bit is set, check the entire word as we don't know
141 * the endianness of the data (old entry is host endian while a new entry is
142 * little endian) */
143static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
144{
145 u32 flags;
146
147 if (compl->flags != 0) {
148 flags = le32_to_cpu(compl->flags);
149 if (flags & CQE_FLAGS_VALID_MASK) {
150 compl->flags = flags;
151 return true;
152 }
153 }
154 return false;
155}
156
157/* Need to reset the entire word that houses the valid bit */
158static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
159{
160 compl->flags = 0;
161}
162
163static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
164{
165 unsigned long addr;
166
167 addr = tag1;
168 addr = ((addr << 16) << 16) | tag0;
169 return (void *)addr;
170}
171
172static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
173{
174 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
175 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
176 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
177 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
178 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
179 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
180 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
181 return true;
182 else
183 return false;
184}
185
186/* Place holder for all the async MCC cmds wherein the caller is not in a busy
187 * loop (has not issued be_mcc_notify_wait())
188 */
189static void be_async_cmd_process(struct be_adapter *adapter,
190 struct be_mcc_compl *compl,
191 struct be_cmd_resp_hdr *resp_hdr)
192{
193 enum mcc_base_status base_status = base_status(compl->status);
194 u8 opcode = 0, subsystem = 0;
195
196 if (resp_hdr) {
197 opcode = resp_hdr->opcode;
198 subsystem = resp_hdr->subsystem;
199 }
200
201 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
202 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
203 complete(&adapter->et_cmd_compl);
204 return;
205 }
206
207 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
208 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
209 complete(&adapter->et_cmd_compl);
210 return;
211 }
212
213 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
214 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
215 subsystem == CMD_SUBSYSTEM_COMMON) {
216 adapter->flash_status = compl->status;
217 complete(&adapter->et_cmd_compl);
218 return;
219 }
220
221 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
222 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
223 subsystem == CMD_SUBSYSTEM_ETH &&
224 base_status == MCC_STATUS_SUCCESS) {
225 be_parse_stats(adapter);
226 adapter->stats_cmd_sent = false;
227 return;
228 }
229
230 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
231 subsystem == CMD_SUBSYSTEM_COMMON) {
232 if (base_status == MCC_STATUS_SUCCESS) {
233 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
234 (void *)resp_hdr;
235 adapter->hwmon_info.be_on_die_temp =
236 resp->on_die_temperature;
237 } else {
238 adapter->be_get_temp_freq = 0;
239 adapter->hwmon_info.be_on_die_temp =
240 BE_INVALID_DIE_TEMP;
241 }
242 return;
243 }
244}
245
246static int be_mcc_compl_process(struct be_adapter *adapter,
247 struct be_mcc_compl *compl)
248{
249 enum mcc_base_status base_status;
250 enum mcc_addl_status addl_status;
251 struct be_cmd_resp_hdr *resp_hdr;
252 u8 opcode = 0, subsystem = 0;
253
254 /* Just swap the status to host endian; mcc tag is opaquely copied
255 * from mcc_wrb */
256 be_dws_le_to_cpu(compl, 4);
257
258 base_status = base_status(compl->status);
259 addl_status = addl_status(compl->status);
260
261 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
262 if (resp_hdr) {
263 opcode = resp_hdr->opcode;
264 subsystem = resp_hdr->subsystem;
265 }
266
267 be_async_cmd_process(adapter, compl, resp_hdr);
268
269 if (base_status != MCC_STATUS_SUCCESS &&
270 !be_skip_err_log(opcode, base_status, addl_status)) {
271 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
272 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
273 dev_warn(&adapter->pdev->dev,
274 "VF is not privileged to issue opcode %d-%d\n",
275 opcode, subsystem);
276 } else {
277 dev_err(&adapter->pdev->dev,
278 "opcode %d-%d failed:status %d-%d\n",
279 opcode, subsystem, base_status, addl_status);
280 }
281 }
282 return compl->status;
283}
284
285/* Link state evt is a string of bytes; no need for endian swapping */
286static void be_async_link_state_process(struct be_adapter *adapter,
287 struct be_mcc_compl *compl)
288{
289 struct be_async_event_link_state *evt =
290 (struct be_async_event_link_state *)compl;
291
292 /* When link status changes, link speed must be re-queried from FW */
293 adapter->phy.link_speed = -1;
294
295 /* On BEx the FW does not send a separate link status
296 * notification for physical and logical link.
297 * On other chips just process the logical link
298 * status notification
299 */
300 if (!BEx_chip(adapter) &&
301 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
302 return;
303
304 /* For the initial link status do not rely on the ASYNC event as
305 * it may not be received in some cases.
306 */
307 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
308 be_link_status_update(adapter,
309 evt->port_link_status & LINK_STATUS_MASK);
310}
311
312static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
313 struct be_mcc_compl *compl)
314{
315 struct be_async_event_misconfig_port *evt =
316 (struct be_async_event_misconfig_port *)compl;
317 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
318 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
319 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
320 struct device *dev = &adapter->pdev->dev;
321 u8 msg_severity = DEFAULT_MSG_SEVERITY;
322 u8 phy_state_info;
323 u8 new_phy_state;
324
325 new_phy_state =
326 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
327
328 if (new_phy_state == adapter->phy_state)
329 return;
330
331 adapter->phy_state = new_phy_state;
332
333 /* for older fw that doesn't populate link effect data */
334 if (!sfp_misconfig_evt_word2)
335 goto log_message;
336
337 phy_state_info =
338 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
339
340 if (phy_state_info & PHY_STATE_INFO_VALID) {
341 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
342
343 if (be_phy_unqualified(new_phy_state))
344 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
345 }
346
347log_message:
348 /* Log an error message that would allow a user to determine
349 * whether the SFPs have an issue
350 */
351 if (be_phy_state_unknown(new_phy_state))
352 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
353 "Port %c: Unrecognized Optics state: 0x%x. %s",
354 adapter->port_name,
355 new_phy_state,
356 phy_state_oper_desc[phy_oper_state]);
357 else
358 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
359 "Port %c: %s %s",
360 adapter->port_name,
361 be_misconfig_evt_port_state[new_phy_state],
362 phy_state_oper_desc[phy_oper_state]);
363
364 /* Log Vendor name and part no. if a misconfigured SFP is detected */
365 if (be_phy_misconfigured(new_phy_state))
366 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
367}
368
369/* Grp5 CoS Priority evt */
370static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
371 struct be_mcc_compl *compl)
372{
373 struct be_async_event_grp5_cos_priority *evt =
374 (struct be_async_event_grp5_cos_priority *)compl;
375
376 if (evt->valid) {
377 adapter->vlan_prio_bmap = evt->available_priority_bmap;
378 adapter->recommended_prio_bits =
379 evt->reco_default_priority << VLAN_PRIO_SHIFT;
380 }
381}
382
383/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
384static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
385 struct be_mcc_compl *compl)
386{
387 struct be_async_event_grp5_qos_link_speed *evt =
388 (struct be_async_event_grp5_qos_link_speed *)compl;
389
390 if (adapter->phy.link_speed >= 0 &&
391 evt->physical_port == adapter->port_num)
392 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
393}
394
395/*Grp5 PVID evt*/
396static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
397 struct be_mcc_compl *compl)
398{
399 struct be_async_event_grp5_pvid_state *evt =
400 (struct be_async_event_grp5_pvid_state *)compl;
401
402 if (evt->enabled) {
403 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
404 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
405 } else {
406 adapter->pvid = 0;
407 }
408}
409
410#define MGMT_ENABLE_MASK 0x4
411static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
412 struct be_mcc_compl *compl)
413{
414 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
415 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
416
417 if (evt_dw1 & MGMT_ENABLE_MASK) {
418 adapter->flags |= BE_FLAGS_OS2BMC;
419 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
420 } else {
421 adapter->flags &= ~BE_FLAGS_OS2BMC;
422 }
423}
424
425static void be_async_grp5_evt_process(struct be_adapter *adapter,
426 struct be_mcc_compl *compl)
427{
428 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
429 ASYNC_EVENT_TYPE_MASK;
430
431 switch (event_type) {
432 case ASYNC_EVENT_COS_PRIORITY:
433 be_async_grp5_cos_priority_process(adapter, compl);
434 break;
435 case ASYNC_EVENT_QOS_SPEED:
436 be_async_grp5_qos_speed_process(adapter, compl);
437 break;
438 case ASYNC_EVENT_PVID_STATE:
439 be_async_grp5_pvid_state_process(adapter, compl);
440 break;
441 /* Async event to disable/enable os2bmc and/or mac-learning */
442 case ASYNC_EVENT_FW_CONTROL:
443 be_async_grp5_fw_control_process(adapter, compl);
444 break;
445 default:
446 break;
447 }
448}
449
450static void be_async_dbg_evt_process(struct be_adapter *adapter,
451 struct be_mcc_compl *cmp)
452{
453 u8 event_type = 0;
454 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
455
456 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
457 ASYNC_EVENT_TYPE_MASK;
458
459 switch (event_type) {
460 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
461 if (evt->valid)
462 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
463 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
464 break;
465 default:
466 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
467 event_type);
468 break;
469 }
470}
471
472static void be_async_sliport_evt_process(struct be_adapter *adapter,
473 struct be_mcc_compl *cmp)
474{
475 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
476 ASYNC_EVENT_TYPE_MASK;
477
478 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
479 be_async_port_misconfig_event_process(adapter, cmp);
480}
481
482static inline bool is_link_state_evt(u32 flags)
483{
484 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
485 ASYNC_EVENT_CODE_LINK_STATE;
486}
487
488static inline bool is_grp5_evt(u32 flags)
489{
490 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
491 ASYNC_EVENT_CODE_GRP_5;
492}
493
494static inline bool is_dbg_evt(u32 flags)
495{
496 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
497 ASYNC_EVENT_CODE_QNQ;
498}
499
500static inline bool is_sliport_evt(u32 flags)
501{
502 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
503 ASYNC_EVENT_CODE_SLIPORT;
504}
505
506static void be_mcc_event_process(struct be_adapter *adapter,
507 struct be_mcc_compl *compl)
508{
509 if (is_link_state_evt(compl->flags))
510 be_async_link_state_process(adapter, compl);
511 else if (is_grp5_evt(compl->flags))
512 be_async_grp5_evt_process(adapter, compl);
513 else if (is_dbg_evt(compl->flags))
514 be_async_dbg_evt_process(adapter, compl);
515 else if (is_sliport_evt(compl->flags))
516 be_async_sliport_evt_process(adapter, compl);
517}
518
519static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
520{
521 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
522 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
523
524 if (be_mcc_compl_is_new(compl)) {
525 queue_tail_inc(mcc_cq);
526 return compl;
527 }
528 return NULL;
529}
530
531void be_async_mcc_enable(struct be_adapter *adapter)
532{
533 spin_lock_bh(&adapter->mcc_cq_lock);
534
535 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
536 adapter->mcc_obj.rearm_cq = true;
537
538 spin_unlock_bh(&adapter->mcc_cq_lock);
539}
540
541void be_async_mcc_disable(struct be_adapter *adapter)
542{
543 spin_lock_bh(&adapter->mcc_cq_lock);
544
545 adapter->mcc_obj.rearm_cq = false;
546 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
547
548 spin_unlock_bh(&adapter->mcc_cq_lock);
549}
550
551int be_process_mcc(struct be_adapter *adapter)
552{
553 struct be_mcc_compl *compl;
554 int num = 0, status = 0;
555 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
556
557 spin_lock(&adapter->mcc_cq_lock);
558
559 while ((compl = be_mcc_compl_get(adapter))) {
560 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
561 be_mcc_event_process(adapter, compl);
562 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
563 status = be_mcc_compl_process(adapter, compl);
564 atomic_dec(&mcc_obj->q.used);
565 }
566 be_mcc_compl_use(compl);
567 num++;
568 }
569
570 if (num)
571 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
572
573 spin_unlock(&adapter->mcc_cq_lock);
574 return status;
575}
576
577/* Wait till no more pending mcc requests are present */
578static int be_mcc_wait_compl(struct be_adapter *adapter)
579{
580#define mcc_timeout 12000 /* 12s timeout */
581 int i, status = 0;
582 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
583
584 for (i = 0; i < mcc_timeout; i++) {
585 if (be_check_error(adapter, BE_ERROR_ANY))
586 return -EIO;
587
588 local_bh_disable();
589 status = be_process_mcc(adapter);
590 local_bh_enable();
591
592 if (atomic_read(&mcc_obj->q.used) == 0)
593 break;
594 usleep_range(500, 1000);
595 }
596 if (i == mcc_timeout) {
597 dev_err(&adapter->pdev->dev, "FW not responding\n");
598 be_set_error(adapter, BE_ERROR_FW);
599 return -EIO;
600 }
601 return status;
602}
603
604/* Notify MCC requests and wait for completion */
605static int be_mcc_notify_wait(struct be_adapter *adapter)
606{
607 int status;
608 struct be_mcc_wrb *wrb;
609 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
610 u32 index = mcc_obj->q.head;
611 struct be_cmd_resp_hdr *resp;
612
613 index_dec(&index, mcc_obj->q.len);
614 wrb = queue_index_node(&mcc_obj->q, index);
615
616 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
617
618 status = be_mcc_notify(adapter);
619 if (status)
620 goto out;
621
622 status = be_mcc_wait_compl(adapter);
623 if (status == -EIO)
624 goto out;
625
626 status = (resp->base_status |
627 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
628 CQE_ADDL_STATUS_SHIFT));
629out:
630 return status;
631}
632
633static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
634{
635 int msecs = 0;
636 u32 ready;
637
638 do {
639 if (be_check_error(adapter, BE_ERROR_ANY))
640 return -EIO;
641
642 ready = ioread32(db);
643 if (ready == 0xffffffff)
644 return -1;
645
646 ready &= MPU_MAILBOX_DB_RDY_MASK;
647 if (ready)
648 break;
649
650 if (msecs > 4000) {
651 dev_err(&adapter->pdev->dev, "FW not responding\n");
652 be_set_error(adapter, BE_ERROR_FW);
653 be_detect_error(adapter);
654 return -1;
655 }
656
657 msleep(1);
658 msecs++;
659 } while (true);
660
661 return 0;
662}
663
664/*
665 * Insert the mailbox address into the doorbell in two steps
666 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
667 */
668static int be_mbox_notify_wait(struct be_adapter *adapter)
669{
670 int status;
671 u32 val = 0;
672 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
673 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
674 struct be_mcc_mailbox *mbox = mbox_mem->va;
675 struct be_mcc_compl *compl = &mbox->compl;
676
677 /* wait for ready to be set */
678 status = be_mbox_db_ready_wait(adapter, db);
679 if (status != 0)
680 return status;
681
682 val |= MPU_MAILBOX_DB_HI_MASK;
683 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
684 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
685 iowrite32(val, db);
686
687 /* wait for ready to be set */
688 status = be_mbox_db_ready_wait(adapter, db);
689 if (status != 0)
690 return status;
691
692 val = 0;
693 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
694 val |= (u32)(mbox_mem->dma >> 4) << 2;
695 iowrite32(val, db);
696
697 status = be_mbox_db_ready_wait(adapter, db);
698 if (status != 0)
699 return status;
700
701 /* A cq entry has been made now */
702 if (be_mcc_compl_is_new(compl)) {
703 status = be_mcc_compl_process(adapter, &mbox->compl);
704 be_mcc_compl_use(compl);
705 if (status)
706 return status;
707 } else {
708 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
709 return -1;
710 }
711 return 0;
712}
713
714u16 be_POST_stage_get(struct be_adapter *adapter)
715{
716 u32 sem;
717
718 if (BEx_chip(adapter))
719 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
720 else
721 pci_read_config_dword(adapter->pdev,
722 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
723
724 return sem & POST_STAGE_MASK;
725}
726
727static int lancer_wait_ready(struct be_adapter *adapter)
728{
729#define SLIPORT_READY_TIMEOUT 30
730 u32 sliport_status;
731 int i;
732
733 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
734 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
735 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
736 return 0;
737
738 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
739 !(sliport_status & SLIPORT_STATUS_RN_MASK))
740 return -EIO;
741
742 msleep(1000);
743 }
744
745 return sliport_status ? : -1;
746}
747
748int be_fw_wait_ready(struct be_adapter *adapter)
749{
750 u16 stage;
751 int status, timeout = 0;
752 struct device *dev = &adapter->pdev->dev;
753
754 if (lancer_chip(adapter)) {
755 status = lancer_wait_ready(adapter);
756 if (status) {
757 stage = status;
758 goto err;
759 }
760 return 0;
761 }
762
763 do {
764 /* There's no means to poll POST state on BE2/3 VFs */
765 if (BEx_chip(adapter) && be_virtfn(adapter))
766 return 0;
767
768 stage = be_POST_stage_get(adapter);
769 if (stage == POST_STAGE_ARMFW_RDY)
770 return 0;
771
772 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
773 if (msleep_interruptible(2000)) {
774 dev_err(dev, "Waiting for POST aborted\n");
775 return -EINTR;
776 }
777 timeout += 2;
778 } while (timeout < 60);
779
780err:
781 dev_err(dev, "POST timeout; stage=%#x\n", stage);
782 return -ETIMEDOUT;
783}
784
785static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
786{
787 return &wrb->payload.sgl[0];
788}
789
790static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
791{
792 wrb->tag0 = addr & 0xFFFFFFFF;
793 wrb->tag1 = upper_32_bits(addr);
794}
795
796/* Don't touch the hdr after it's prepared */
797/* mem will be NULL for embedded commands */
798static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
799 u8 subsystem, u8 opcode, int cmd_len,
800 struct be_mcc_wrb *wrb,
801 struct be_dma_mem *mem)
802{
803 struct be_sge *sge;
804
805 req_hdr->opcode = opcode;
806 req_hdr->subsystem = subsystem;
807 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
808 req_hdr->version = 0;
809 fill_wrb_tags(wrb, (ulong) req_hdr);
810 wrb->payload_length = cmd_len;
811 if (mem) {
812 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
813 MCC_WRB_SGE_CNT_SHIFT;
814 sge = nonembedded_sgl(wrb);
815 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
816 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
817 sge->len = cpu_to_le32(mem->size);
818 } else
819 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
820 be_dws_cpu_to_le(wrb, 8);
821}
822
823static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
824 struct be_dma_mem *mem)
825{
826 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
827 u64 dma = (u64)mem->dma;
828
829 for (i = 0; i < buf_pages; i++) {
830 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
831 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
832 dma += PAGE_SIZE_4K;
833 }
834}
835
836static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
837{
838 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
839 struct be_mcc_wrb *wrb
840 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
841 memset(wrb, 0, sizeof(*wrb));
842 return wrb;
843}
844
845static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
846{
847 struct be_queue_info *mccq = &adapter->mcc_obj.q;
848 struct be_mcc_wrb *wrb;
849
850 if (!mccq->created)
851 return NULL;
852
853 if (atomic_read(&mccq->used) >= mccq->len)
854 return NULL;
855
856 wrb = queue_head_node(mccq);
857 queue_head_inc(mccq);
858 atomic_inc(&mccq->used);
859 memset(wrb, 0, sizeof(*wrb));
860 return wrb;
861}
862
863static bool use_mcc(struct be_adapter *adapter)
864{
865 return adapter->mcc_obj.q.created;
866}
867
868/* Must be used only in process context */
869static int be_cmd_lock(struct be_adapter *adapter)
870{
871 if (use_mcc(adapter)) {
872 mutex_lock(&adapter->mcc_lock);
873 return 0;
874 } else {
875 return mutex_lock_interruptible(&adapter->mbox_lock);
876 }
877}
878
879/* Must be used only in process context */
880static void be_cmd_unlock(struct be_adapter *adapter)
881{
882 if (use_mcc(adapter))
883 return mutex_unlock(&adapter->mcc_lock);
884 else
885 return mutex_unlock(&adapter->mbox_lock);
886}
887
888static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
889 struct be_mcc_wrb *wrb)
890{
891 struct be_mcc_wrb *dest_wrb;
892
893 if (use_mcc(adapter)) {
894 dest_wrb = wrb_from_mccq(adapter);
895 if (!dest_wrb)
896 return NULL;
897 } else {
898 dest_wrb = wrb_from_mbox(adapter);
899 }
900
901 memcpy(dest_wrb, wrb, sizeof(*wrb));
902 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
903 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
904
905 return dest_wrb;
906}
907
908/* Must be used only in process context */
909static int be_cmd_notify_wait(struct be_adapter *adapter,
910 struct be_mcc_wrb *wrb)
911{
912 struct be_mcc_wrb *dest_wrb;
913 int status;
914
915 status = be_cmd_lock(adapter);
916 if (status)
917 return status;
918
919 dest_wrb = be_cmd_copy(adapter, wrb);
920 if (!dest_wrb) {
921 status = -EBUSY;
922 goto unlock;
923 }
924
925 if (use_mcc(adapter))
926 status = be_mcc_notify_wait(adapter);
927 else
928 status = be_mbox_notify_wait(adapter);
929
930 if (!status)
931 memcpy(wrb, dest_wrb, sizeof(*wrb));
932
933unlock:
934 be_cmd_unlock(adapter);
935 return status;
936}
937
938/* Tell fw we're about to start firing cmds by writing a
939 * special pattern across the wrb hdr; uses mbox
940 */
941int be_cmd_fw_init(struct be_adapter *adapter)
942{
943 u8 *wrb;
944 int status;
945
946 if (lancer_chip(adapter))
947 return 0;
948
949 if (mutex_lock_interruptible(&adapter->mbox_lock))
950 return -1;
951
952 wrb = (u8 *)wrb_from_mbox(adapter);
953 *wrb++ = 0xFF;
954 *wrb++ = 0x12;
955 *wrb++ = 0x34;
956 *wrb++ = 0xFF;
957 *wrb++ = 0xFF;
958 *wrb++ = 0x56;
959 *wrb++ = 0x78;
960 *wrb = 0xFF;
961
962 status = be_mbox_notify_wait(adapter);
963
964 mutex_unlock(&adapter->mbox_lock);
965 return status;
966}
967
968/* Tell fw we're done with firing cmds by writing a
969 * special pattern across the wrb hdr; uses mbox
970 */
971int be_cmd_fw_clean(struct be_adapter *adapter)
972{
973 u8 *wrb;
974 int status;
975
976 if (lancer_chip(adapter))
977 return 0;
978
979 if (mutex_lock_interruptible(&adapter->mbox_lock))
980 return -1;
981
982 wrb = (u8 *)wrb_from_mbox(adapter);
983 *wrb++ = 0xFF;
984 *wrb++ = 0xAA;
985 *wrb++ = 0xBB;
986 *wrb++ = 0xFF;
987 *wrb++ = 0xFF;
988 *wrb++ = 0xCC;
989 *wrb++ = 0xDD;
990 *wrb = 0xFF;
991
992 status = be_mbox_notify_wait(adapter);
993
994 mutex_unlock(&adapter->mbox_lock);
995 return status;
996}
997
998int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
999{
1000 struct be_mcc_wrb *wrb;
1001 struct be_cmd_req_eq_create *req;
1002 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
1003 int status, ver = 0;
1004
1005 if (mutex_lock_interruptible(&adapter->mbox_lock))
1006 return -1;
1007
1008 wrb = wrb_from_mbox(adapter);
1009 req = embedded_payload(wrb);
1010
1011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1012 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1013 NULL);
1014
1015 /* Support for EQ_CREATEv2 available only SH-R onwards */
1016 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1017 ver = 2;
1018
1019 req->hdr.version = ver;
1020 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1021
1022 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1023 /* 4byte eqe*/
1024 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1025 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1026 __ilog2_u32(eqo->q.len / 256));
1027 be_dws_cpu_to_le(req->context, sizeof(req->context));
1028
1029 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1030
1031 status = be_mbox_notify_wait(adapter);
1032 if (!status) {
1033 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1034
1035 eqo->q.id = le16_to_cpu(resp->eq_id);
1036 eqo->msix_idx =
1037 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1038 eqo->q.created = true;
1039 }
1040
1041 mutex_unlock(&adapter->mbox_lock);
1042 return status;
1043}
1044
1045/* Use MCC */
1046int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1047 bool permanent, u32 if_handle, u32 pmac_id)
1048{
1049 struct be_mcc_wrb *wrb;
1050 struct be_cmd_req_mac_query *req;
1051 int status;
1052
1053 mutex_lock(&adapter->mcc_lock);
1054
1055 wrb = wrb_from_mccq(adapter);
1056 if (!wrb) {
1057 status = -EBUSY;
1058 goto err;
1059 }
1060 req = embedded_payload(wrb);
1061
1062 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1063 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1064 NULL);
1065 req->type = MAC_ADDRESS_TYPE_NETWORK;
1066 if (permanent) {
1067 req->permanent = 1;
1068 } else {
1069 req->if_id = cpu_to_le16((u16)if_handle);
1070 req->pmac_id = cpu_to_le32(pmac_id);
1071 req->permanent = 0;
1072 }
1073
1074 status = be_mcc_notify_wait(adapter);
1075 if (!status) {
1076 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1077
1078 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1079 }
1080
1081err:
1082 mutex_unlock(&adapter->mcc_lock);
1083 return status;
1084}
1085
1086/* Uses synchronous MCCQ */
1087int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1088 u32 if_id, u32 *pmac_id, u32 domain)
1089{
1090 struct be_mcc_wrb *wrb;
1091 struct be_cmd_req_pmac_add *req;
1092 int status;
1093
1094 mutex_lock(&adapter->mcc_lock);
1095
1096 wrb = wrb_from_mccq(adapter);
1097 if (!wrb) {
1098 status = -EBUSY;
1099 goto err;
1100 }
1101 req = embedded_payload(wrb);
1102
1103 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1104 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1105 NULL);
1106
1107 req->hdr.domain = domain;
1108 req->if_id = cpu_to_le32(if_id);
1109 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1110
1111 status = be_mcc_notify_wait(adapter);
1112 if (!status) {
1113 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1114
1115 *pmac_id = le32_to_cpu(resp->pmac_id);
1116 }
1117
1118err:
1119 mutex_unlock(&adapter->mcc_lock);
1120
1121 if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
1122 status = -EPERM;
1123
1124 return status;
1125}
1126
1127/* Uses synchronous MCCQ */
1128int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1129{
1130 struct be_mcc_wrb *wrb;
1131 struct be_cmd_req_pmac_del *req;
1132 int status;
1133
1134 if (pmac_id == -1)
1135 return 0;
1136
1137 mutex_lock(&adapter->mcc_lock);
1138
1139 wrb = wrb_from_mccq(adapter);
1140 if (!wrb) {
1141 status = -EBUSY;
1142 goto err;
1143 }
1144 req = embedded_payload(wrb);
1145
1146 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1147 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1148 wrb, NULL);
1149
1150 req->hdr.domain = dom;
1151 req->if_id = cpu_to_le32(if_id);
1152 req->pmac_id = cpu_to_le32(pmac_id);
1153
1154 status = be_mcc_notify_wait(adapter);
1155
1156err:
1157 mutex_unlock(&adapter->mcc_lock);
1158 return status;
1159}
1160
1161/* Uses Mbox */
1162int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1163 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1164{
1165 struct be_mcc_wrb *wrb;
1166 struct be_cmd_req_cq_create *req;
1167 struct be_dma_mem *q_mem = &cq->dma_mem;
1168 void *ctxt;
1169 int status;
1170
1171 if (mutex_lock_interruptible(&adapter->mbox_lock))
1172 return -1;
1173
1174 wrb = wrb_from_mbox(adapter);
1175 req = embedded_payload(wrb);
1176 ctxt = &req->context;
1177
1178 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1179 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1180 NULL);
1181
1182 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1183
1184 if (BEx_chip(adapter)) {
1185 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1186 coalesce_wm);
1187 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1188 ctxt, no_delay);
1189 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1190 __ilog2_u32(cq->len / 256));
1191 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1192 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1193 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1194 } else {
1195 req->hdr.version = 2;
1196 req->page_size = 1; /* 1 for 4K */
1197
1198 /* coalesce-wm field in this cmd is not relevant to Lancer.
1199 * Lancer uses COMMON_MODIFY_CQ to set this field
1200 */
1201 if (!lancer_chip(adapter))
1202 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1203 ctxt, coalesce_wm);
1204 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1205 no_delay);
1206 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1207 __ilog2_u32(cq->len / 256));
1208 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1209 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1210 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1211 }
1212
1213 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1214
1215 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216
1217 status = be_mbox_notify_wait(adapter);
1218 if (!status) {
1219 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1220
1221 cq->id = le16_to_cpu(resp->cq_id);
1222 cq->created = true;
1223 }
1224
1225 mutex_unlock(&adapter->mbox_lock);
1226
1227 return status;
1228}
1229
1230static u32 be_encoded_q_len(int q_len)
1231{
1232 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1233
1234 if (len_encoded == 16)
1235 len_encoded = 0;
1236 return len_encoded;
1237}
1238
1239static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1240 struct be_queue_info *mccq,
1241 struct be_queue_info *cq)
1242{
1243 struct be_mcc_wrb *wrb;
1244 struct be_cmd_req_mcc_ext_create *req;
1245 struct be_dma_mem *q_mem = &mccq->dma_mem;
1246 void *ctxt;
1247 int status;
1248
1249 if (mutex_lock_interruptible(&adapter->mbox_lock))
1250 return -1;
1251
1252 wrb = wrb_from_mbox(adapter);
1253 req = embedded_payload(wrb);
1254 ctxt = &req->context;
1255
1256 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1257 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1258 NULL);
1259
1260 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1261 if (BEx_chip(adapter)) {
1262 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1263 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1264 be_encoded_q_len(mccq->len));
1265 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1266 } else {
1267 req->hdr.version = 1;
1268 req->cq_id = cpu_to_le16(cq->id);
1269
1270 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1271 be_encoded_q_len(mccq->len));
1272 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1273 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1274 ctxt, cq->id);
1275 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1276 ctxt, 1);
1277 }
1278
1279 /* Subscribe to Link State, Sliport Event and Group 5 Events
1280 * (bits 1, 5 and 17 set)
1281 */
1282 req->async_event_bitmap[0] =
1283 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1284 BIT(ASYNC_EVENT_CODE_GRP_5) |
1285 BIT(ASYNC_EVENT_CODE_QNQ) |
1286 BIT(ASYNC_EVENT_CODE_SLIPORT));
1287
1288 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1289
1290 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1291
1292 status = be_mbox_notify_wait(adapter);
1293 if (!status) {
1294 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1295
1296 mccq->id = le16_to_cpu(resp->id);
1297 mccq->created = true;
1298 }
1299 mutex_unlock(&adapter->mbox_lock);
1300
1301 return status;
1302}
1303
1304static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1305 struct be_queue_info *mccq,
1306 struct be_queue_info *cq)
1307{
1308 struct be_mcc_wrb *wrb;
1309 struct be_cmd_req_mcc_create *req;
1310 struct be_dma_mem *q_mem = &mccq->dma_mem;
1311 void *ctxt;
1312 int status;
1313
1314 if (mutex_lock_interruptible(&adapter->mbox_lock))
1315 return -1;
1316
1317 wrb = wrb_from_mbox(adapter);
1318 req = embedded_payload(wrb);
1319 ctxt = &req->context;
1320
1321 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1322 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1323 NULL);
1324
1325 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1326
1327 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1328 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1329 be_encoded_q_len(mccq->len));
1330 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1331
1332 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1333
1334 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1335
1336 status = be_mbox_notify_wait(adapter);
1337 if (!status) {
1338 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1339
1340 mccq->id = le16_to_cpu(resp->id);
1341 mccq->created = true;
1342 }
1343
1344 mutex_unlock(&adapter->mbox_lock);
1345 return status;
1346}
1347
1348int be_cmd_mccq_create(struct be_adapter *adapter,
1349 struct be_queue_info *mccq, struct be_queue_info *cq)
1350{
1351 int status;
1352
1353 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1354 if (status && BEx_chip(adapter)) {
1355 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1356 "or newer to avoid conflicting priorities between NIC "
1357 "and FCoE traffic");
1358 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1359 }
1360 return status;
1361}
1362
1363int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1364{
1365 struct be_mcc_wrb wrb = {0};
1366 struct be_cmd_req_eth_tx_create *req;
1367 struct be_queue_info *txq = &txo->q;
1368 struct be_queue_info *cq = &txo->cq;
1369 struct be_dma_mem *q_mem = &txq->dma_mem;
1370 int status, ver = 0;
1371
1372 req = embedded_payload(&wrb);
1373 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1374 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1375
1376 if (lancer_chip(adapter)) {
1377 req->hdr.version = 1;
1378 } else if (BEx_chip(adapter)) {
1379 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1380 req->hdr.version = 2;
1381 } else { /* For SH */
1382 req->hdr.version = 2;
1383 }
1384
1385 if (req->hdr.version > 0)
1386 req->if_id = cpu_to_le16(adapter->if_handle);
1387 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1388 req->ulp_num = BE_ULP1_NUM;
1389 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1390 req->cq_id = cpu_to_le16(cq->id);
1391 req->queue_size = be_encoded_q_len(txq->len);
1392 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1393 ver = req->hdr.version;
1394
1395 status = be_cmd_notify_wait(adapter, &wrb);
1396 if (!status) {
1397 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1398
1399 txq->id = le16_to_cpu(resp->cid);
1400 if (ver == 2)
1401 txo->db_offset = le32_to_cpu(resp->db_offset);
1402 else
1403 txo->db_offset = DB_TXULP1_OFFSET;
1404 txq->created = true;
1405 }
1406
1407 return status;
1408}
1409
1410/* Uses MCC */
1411int be_cmd_rxq_create(struct be_adapter *adapter,
1412 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1413 u32 if_id, u32 rss, u8 *rss_id)
1414{
1415 struct be_mcc_wrb *wrb;
1416 struct be_cmd_req_eth_rx_create *req;
1417 struct be_dma_mem *q_mem = &rxq->dma_mem;
1418 int status;
1419
1420 mutex_lock(&adapter->mcc_lock);
1421
1422 wrb = wrb_from_mccq(adapter);
1423 if (!wrb) {
1424 status = -EBUSY;
1425 goto err;
1426 }
1427 req = embedded_payload(wrb);
1428
1429 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1430 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1431
1432 req->cq_id = cpu_to_le16(cq_id);
1433 req->frag_size = fls(frag_size) - 1;
1434 req->num_pages = 2;
1435 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1436 req->interface_id = cpu_to_le32(if_id);
1437 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1438 req->rss_queue = cpu_to_le32(rss);
1439
1440 status = be_mcc_notify_wait(adapter);
1441 if (!status) {
1442 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1443
1444 rxq->id = le16_to_cpu(resp->id);
1445 rxq->created = true;
1446 *rss_id = resp->rss_id;
1447 }
1448
1449err:
1450 mutex_unlock(&adapter->mcc_lock);
1451 return status;
1452}
1453
1454/* Generic destroyer function for all types of queues
1455 * Uses Mbox
1456 */
1457int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1458 int queue_type)
1459{
1460 struct be_mcc_wrb *wrb;
1461 struct be_cmd_req_q_destroy *req;
1462 u8 subsys = 0, opcode = 0;
1463 int status;
1464
1465 if (mutex_lock_interruptible(&adapter->mbox_lock))
1466 return -1;
1467
1468 wrb = wrb_from_mbox(adapter);
1469 req = embedded_payload(wrb);
1470
1471 switch (queue_type) {
1472 case QTYPE_EQ:
1473 subsys = CMD_SUBSYSTEM_COMMON;
1474 opcode = OPCODE_COMMON_EQ_DESTROY;
1475 break;
1476 case QTYPE_CQ:
1477 subsys = CMD_SUBSYSTEM_COMMON;
1478 opcode = OPCODE_COMMON_CQ_DESTROY;
1479 break;
1480 case QTYPE_TXQ:
1481 subsys = CMD_SUBSYSTEM_ETH;
1482 opcode = OPCODE_ETH_TX_DESTROY;
1483 break;
1484 case QTYPE_RXQ:
1485 subsys = CMD_SUBSYSTEM_ETH;
1486 opcode = OPCODE_ETH_RX_DESTROY;
1487 break;
1488 case QTYPE_MCCQ:
1489 subsys = CMD_SUBSYSTEM_COMMON;
1490 opcode = OPCODE_COMMON_MCC_DESTROY;
1491 break;
1492 default:
1493 BUG();
1494 }
1495
1496 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1497 NULL);
1498 req->id = cpu_to_le16(q->id);
1499
1500 status = be_mbox_notify_wait(adapter);
1501 q->created = false;
1502
1503 mutex_unlock(&adapter->mbox_lock);
1504 return status;
1505}
1506
1507/* Uses MCC */
1508int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1509{
1510 struct be_mcc_wrb *wrb;
1511 struct be_cmd_req_q_destroy *req;
1512 int status;
1513
1514 mutex_lock(&adapter->mcc_lock);
1515
1516 wrb = wrb_from_mccq(adapter);
1517 if (!wrb) {
1518 status = -EBUSY;
1519 goto err;
1520 }
1521 req = embedded_payload(wrb);
1522
1523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1524 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1525 req->id = cpu_to_le16(q->id);
1526
1527 status = be_mcc_notify_wait(adapter);
1528 q->created = false;
1529
1530err:
1531 mutex_unlock(&adapter->mcc_lock);
1532 return status;
1533}
1534
1535/* Create an rx filtering policy configuration on an i/f
1536 * Will use MBOX only if MCCQ has not been created.
1537 */
1538int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1539 u32 *if_handle, u32 domain)
1540{
1541 struct be_mcc_wrb wrb = {0};
1542 struct be_cmd_req_if_create *req;
1543 int status;
1544
1545 req = embedded_payload(&wrb);
1546 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1547 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1548 sizeof(*req), &wrb, NULL);
1549 req->hdr.domain = domain;
1550 req->capability_flags = cpu_to_le32(cap_flags);
1551 req->enable_flags = cpu_to_le32(en_flags);
1552 req->pmac_invalid = true;
1553
1554 status = be_cmd_notify_wait(adapter, &wrb);
1555 if (!status) {
1556 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1557
1558 *if_handle = le32_to_cpu(resp->interface_id);
1559
1560 /* Hack to retrieve VF's pmac-id on BE3 */
1561 if (BE3_chip(adapter) && be_virtfn(adapter))
1562 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1563 }
1564 return status;
1565}
1566
1567/* Uses MCCQ if available else MBOX */
1568int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1569{
1570 struct be_mcc_wrb wrb = {0};
1571 struct be_cmd_req_if_destroy *req;
1572 int status;
1573
1574 if (interface_id == -1)
1575 return 0;
1576
1577 req = embedded_payload(&wrb);
1578
1579 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1580 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1581 sizeof(*req), &wrb, NULL);
1582 req->hdr.domain = domain;
1583 req->interface_id = cpu_to_le32(interface_id);
1584
1585 status = be_cmd_notify_wait(adapter, &wrb);
1586 return status;
1587}
1588
1589/* Get stats is a non embedded command: the request is not embedded inside
1590 * WRB but is a separate dma memory block
1591 * Uses asynchronous MCC
1592 */
1593int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1594{
1595 struct be_mcc_wrb *wrb;
1596 struct be_cmd_req_hdr *hdr;
1597 int status = 0;
1598
1599 mutex_lock(&adapter->mcc_lock);
1600
1601 wrb = wrb_from_mccq(adapter);
1602 if (!wrb) {
1603 status = -EBUSY;
1604 goto err;
1605 }
1606 hdr = nonemb_cmd->va;
1607
1608 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1609 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1610 nonemb_cmd);
1611
1612 /* version 1 of the cmd is not supported only by BE2 */
1613 if (BE2_chip(adapter))
1614 hdr->version = 0;
1615 if (BE3_chip(adapter) || lancer_chip(adapter))
1616 hdr->version = 1;
1617 else
1618 hdr->version = 2;
1619
1620 status = be_mcc_notify(adapter);
1621 if (status)
1622 goto err;
1623
1624 adapter->stats_cmd_sent = true;
1625
1626err:
1627 mutex_unlock(&adapter->mcc_lock);
1628 return status;
1629}
1630
1631/* Lancer Stats */
1632int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1633 struct be_dma_mem *nonemb_cmd)
1634{
1635 struct be_mcc_wrb *wrb;
1636 struct lancer_cmd_req_pport_stats *req;
1637 int status = 0;
1638
1639 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1640 CMD_SUBSYSTEM_ETH))
1641 return -EPERM;
1642
1643 mutex_lock(&adapter->mcc_lock);
1644
1645 wrb = wrb_from_mccq(adapter);
1646 if (!wrb) {
1647 status = -EBUSY;
1648 goto err;
1649 }
1650 req = nonemb_cmd->va;
1651
1652 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1653 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1654 wrb, nonemb_cmd);
1655
1656 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1657 req->cmd_params.params.reset_stats = 0;
1658
1659 status = be_mcc_notify(adapter);
1660 if (status)
1661 goto err;
1662
1663 adapter->stats_cmd_sent = true;
1664
1665err:
1666 mutex_unlock(&adapter->mcc_lock);
1667 return status;
1668}
1669
1670static int be_mac_to_link_speed(int mac_speed)
1671{
1672 switch (mac_speed) {
1673 case PHY_LINK_SPEED_ZERO:
1674 return 0;
1675 case PHY_LINK_SPEED_10MBPS:
1676 return 10;
1677 case PHY_LINK_SPEED_100MBPS:
1678 return 100;
1679 case PHY_LINK_SPEED_1GBPS:
1680 return 1000;
1681 case PHY_LINK_SPEED_10GBPS:
1682 return 10000;
1683 case PHY_LINK_SPEED_20GBPS:
1684 return 20000;
1685 case PHY_LINK_SPEED_25GBPS:
1686 return 25000;
1687 case PHY_LINK_SPEED_40GBPS:
1688 return 40000;
1689 }
1690 return 0;
1691}
1692
1693/* Uses synchronous mcc
1694 * Returns link_speed in Mbps
1695 */
1696int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1697 u8 *link_status, u32 dom)
1698{
1699 struct be_mcc_wrb *wrb;
1700 struct be_cmd_req_link_status *req;
1701 int status;
1702
1703 mutex_lock(&adapter->mcc_lock);
1704
1705 if (link_status)
1706 *link_status = LINK_DOWN;
1707
1708 wrb = wrb_from_mccq(adapter);
1709 if (!wrb) {
1710 status = -EBUSY;
1711 goto err;
1712 }
1713 req = embedded_payload(wrb);
1714
1715 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1716 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1717 sizeof(*req), wrb, NULL);
1718
1719 /* version 1 of the cmd is not supported only by BE2 */
1720 if (!BE2_chip(adapter))
1721 req->hdr.version = 1;
1722
1723 req->hdr.domain = dom;
1724
1725 status = be_mcc_notify_wait(adapter);
1726 if (!status) {
1727 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1728
1729 if (link_speed) {
1730 *link_speed = resp->link_speed ?
1731 le16_to_cpu(resp->link_speed) * 10 :
1732 be_mac_to_link_speed(resp->mac_speed);
1733
1734 if (!resp->logical_link_status)
1735 *link_speed = 0;
1736 }
1737 if (link_status)
1738 *link_status = resp->logical_link_status;
1739 }
1740
1741err:
1742 mutex_unlock(&adapter->mcc_lock);
1743 return status;
1744}
1745
1746/* Uses synchronous mcc */
1747int be_cmd_get_die_temperature(struct be_adapter *adapter)
1748{
1749 struct be_mcc_wrb *wrb;
1750 struct be_cmd_req_get_cntl_addnl_attribs *req;
1751 int status = 0;
1752
1753 mutex_lock(&adapter->mcc_lock);
1754
1755 wrb = wrb_from_mccq(adapter);
1756 if (!wrb) {
1757 status = -EBUSY;
1758 goto err;
1759 }
1760 req = embedded_payload(wrb);
1761
1762 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1763 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1764 sizeof(*req), wrb, NULL);
1765
1766 status = be_mcc_notify(adapter);
1767err:
1768 mutex_unlock(&adapter->mcc_lock);
1769 return status;
1770}
1771
1772/* Uses synchronous mcc */
1773int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1774{
1775 struct be_mcc_wrb wrb = {0};
1776 struct be_cmd_req_get_fat *req;
1777 int status;
1778
1779 req = embedded_payload(&wrb);
1780
1781 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1782 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1783 &wrb, NULL);
1784 req->fat_operation = cpu_to_le32(QUERY_FAT);
1785 status = be_cmd_notify_wait(adapter, &wrb);
1786 if (!status) {
1787 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1788
1789 if (dump_size && resp->log_size)
1790 *dump_size = le32_to_cpu(resp->log_size) -
1791 sizeof(u32);
1792 }
1793 return status;
1794}
1795
1796int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1797{
1798 struct be_dma_mem get_fat_cmd;
1799 struct be_mcc_wrb *wrb;
1800 struct be_cmd_req_get_fat *req;
1801 u32 offset = 0, total_size, buf_size,
1802 log_offset = sizeof(u32), payload_len;
1803 int status;
1804
1805 if (buf_len == 0)
1806 return 0;
1807
1808 total_size = buf_len;
1809
1810 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1811 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1812 get_fat_cmd.size,
1813 &get_fat_cmd.dma, GFP_ATOMIC);
1814 if (!get_fat_cmd.va)
1815 return -ENOMEM;
1816
1817 mutex_lock(&adapter->mcc_lock);
1818
1819 while (total_size) {
1820 buf_size = min(total_size, (u32)60*1024);
1821 total_size -= buf_size;
1822
1823 wrb = wrb_from_mccq(adapter);
1824 if (!wrb) {
1825 status = -EBUSY;
1826 goto err;
1827 }
1828 req = get_fat_cmd.va;
1829
1830 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1831 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1832 OPCODE_COMMON_MANAGE_FAT, payload_len,
1833 wrb, &get_fat_cmd);
1834
1835 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1836 req->read_log_offset = cpu_to_le32(log_offset);
1837 req->read_log_length = cpu_to_le32(buf_size);
1838 req->data_buffer_size = cpu_to_le32(buf_size);
1839
1840 status = be_mcc_notify_wait(adapter);
1841 if (!status) {
1842 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1843
1844 memcpy(buf + offset,
1845 resp->data_buffer,
1846 le32_to_cpu(resp->read_log_length));
1847 } else {
1848 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1849 goto err;
1850 }
1851 offset += buf_size;
1852 log_offset += buf_size;
1853 }
1854err:
1855 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1856 get_fat_cmd.va, get_fat_cmd.dma);
1857 mutex_unlock(&adapter->mcc_lock);
1858 return status;
1859}
1860
1861/* Uses synchronous mcc */
1862int be_cmd_get_fw_ver(struct be_adapter *adapter)
1863{
1864 struct be_mcc_wrb *wrb;
1865 struct be_cmd_req_get_fw_version *req;
1866 int status;
1867
1868 mutex_lock(&adapter->mcc_lock);
1869
1870 wrb = wrb_from_mccq(adapter);
1871 if (!wrb) {
1872 status = -EBUSY;
1873 goto err;
1874 }
1875
1876 req = embedded_payload(wrb);
1877
1878 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1879 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1880 NULL);
1881 status = be_mcc_notify_wait(adapter);
1882 if (!status) {
1883 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1884
1885 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1886 sizeof(adapter->fw_ver));
1887 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1888 sizeof(adapter->fw_on_flash));
1889 }
1890err:
1891 mutex_unlock(&adapter->mcc_lock);
1892 return status;
1893}
1894
1895/* set the EQ delay interval of an EQ to specified value
1896 * Uses async mcc
1897 */
1898static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1899 struct be_set_eqd *set_eqd, int num)
1900{
1901 struct be_mcc_wrb *wrb;
1902 struct be_cmd_req_modify_eq_delay *req;
1903 int status = 0, i;
1904
1905 mutex_lock(&adapter->mcc_lock);
1906
1907 wrb = wrb_from_mccq(adapter);
1908 if (!wrb) {
1909 status = -EBUSY;
1910 goto err;
1911 }
1912 req = embedded_payload(wrb);
1913
1914 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1915 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1916 NULL);
1917
1918 req->num_eq = cpu_to_le32(num);
1919 for (i = 0; i < num; i++) {
1920 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1921 req->set_eqd[i].phase = 0;
1922 req->set_eqd[i].delay_multiplier =
1923 cpu_to_le32(set_eqd[i].delay_multiplier);
1924 }
1925
1926 status = be_mcc_notify(adapter);
1927err:
1928 mutex_unlock(&adapter->mcc_lock);
1929 return status;
1930}
1931
1932int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1933 int num)
1934{
1935 int num_eqs, i = 0;
1936
1937 while (num) {
1938 num_eqs = min(num, 8);
1939 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1940 i += num_eqs;
1941 num -= num_eqs;
1942 }
1943
1944 return 0;
1945}
1946
1947/* Uses sycnhronous mcc */
1948int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1949 u32 num, u32 domain)
1950{
1951 struct be_mcc_wrb *wrb;
1952 struct be_cmd_req_vlan_config *req;
1953 int status;
1954
1955 mutex_lock(&adapter->mcc_lock);
1956
1957 wrb = wrb_from_mccq(adapter);
1958 if (!wrb) {
1959 status = -EBUSY;
1960 goto err;
1961 }
1962 req = embedded_payload(wrb);
1963
1964 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1965 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1966 wrb, NULL);
1967 req->hdr.domain = domain;
1968
1969 req->interface_id = if_id;
1970 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1971 req->num_vlan = num;
1972 memcpy(req->normal_vlan, vtag_array,
1973 req->num_vlan * sizeof(vtag_array[0]));
1974
1975 status = be_mcc_notify_wait(adapter);
1976err:
1977 mutex_unlock(&adapter->mcc_lock);
1978 return status;
1979}
1980
1981static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1982{
1983 struct be_mcc_wrb *wrb;
1984 struct be_dma_mem *mem = &adapter->rx_filter;
1985 struct be_cmd_req_rx_filter *req = mem->va;
1986 int status;
1987
1988 mutex_lock(&adapter->mcc_lock);
1989
1990 wrb = wrb_from_mccq(adapter);
1991 if (!wrb) {
1992 status = -EBUSY;
1993 goto err;
1994 }
1995 memset(req, 0, sizeof(*req));
1996 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1997 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1998 wrb, mem);
1999
2000 req->if_id = cpu_to_le32(adapter->if_handle);
2001 req->if_flags_mask = cpu_to_le32(flags);
2002 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
2003
2004 if (flags & BE_IF_FLAGS_MULTICAST) {
2005 int i;
2006
2007 /* Reset mcast promisc mode if already set by setting mask
2008 * and not setting flags field
2009 */
2010 req->if_flags_mask |=
2011 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2012 be_if_cap_flags(adapter));
2013 req->mcast_num = cpu_to_le32(adapter->mc_count);
2014 for (i = 0; i < adapter->mc_count; i++)
2015 ether_addr_copy(req->mcast_mac[i].byte,
2016 adapter->mc_list[i].mac);
2017 }
2018
2019 status = be_mcc_notify_wait(adapter);
2020err:
2021 mutex_unlock(&adapter->mcc_lock);
2022 return status;
2023}
2024
2025int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2026{
2027 struct device *dev = &adapter->pdev->dev;
2028
2029 if ((flags & be_if_cap_flags(adapter)) != flags) {
2030 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2031 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2032 be_if_cap_flags(adapter));
2033 }
2034 flags &= be_if_cap_flags(adapter);
2035 if (!flags)
2036 return -ENOTSUPP;
2037
2038 return __be_cmd_rx_filter(adapter, flags, value);
2039}
2040
2041/* Uses synchrounous mcc */
2042int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2043{
2044 struct be_mcc_wrb *wrb;
2045 struct be_cmd_req_set_flow_control *req;
2046 int status;
2047
2048 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2049 CMD_SUBSYSTEM_COMMON))
2050 return -EPERM;
2051
2052 mutex_lock(&adapter->mcc_lock);
2053
2054 wrb = wrb_from_mccq(adapter);
2055 if (!wrb) {
2056 status = -EBUSY;
2057 goto err;
2058 }
2059 req = embedded_payload(wrb);
2060
2061 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2062 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2063 wrb, NULL);
2064
2065 req->hdr.version = 1;
2066 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2067 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2068
2069 status = be_mcc_notify_wait(adapter);
2070
2071err:
2072 mutex_unlock(&adapter->mcc_lock);
2073
2074 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2075 return -EOPNOTSUPP;
2076
2077 return status;
2078}
2079
2080/* Uses sycn mcc */
2081int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2082{
2083 struct be_mcc_wrb *wrb;
2084 struct be_cmd_req_get_flow_control *req;
2085 int status;
2086
2087 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2088 CMD_SUBSYSTEM_COMMON))
2089 return -EPERM;
2090
2091 mutex_lock(&adapter->mcc_lock);
2092
2093 wrb = wrb_from_mccq(adapter);
2094 if (!wrb) {
2095 status = -EBUSY;
2096 goto err;
2097 }
2098 req = embedded_payload(wrb);
2099
2100 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2101 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2102 wrb, NULL);
2103
2104 status = be_mcc_notify_wait(adapter);
2105 if (!status) {
2106 struct be_cmd_resp_get_flow_control *resp =
2107 embedded_payload(wrb);
2108
2109 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2110 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2111 }
2112
2113err:
2114 mutex_unlock(&adapter->mcc_lock);
2115 return status;
2116}
2117
2118/* Uses mbox */
2119int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2120{
2121 struct be_mcc_wrb *wrb;
2122 struct be_cmd_req_query_fw_cfg *req;
2123 int status;
2124
2125 if (mutex_lock_interruptible(&adapter->mbox_lock))
2126 return -1;
2127
2128 wrb = wrb_from_mbox(adapter);
2129 req = embedded_payload(wrb);
2130
2131 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2132 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2133 sizeof(*req), wrb, NULL);
2134
2135 status = be_mbox_notify_wait(adapter);
2136 if (!status) {
2137 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2138
2139 adapter->port_num = le32_to_cpu(resp->phys_port);
2140 adapter->function_mode = le32_to_cpu(resp->function_mode);
2141 adapter->function_caps = le32_to_cpu(resp->function_caps);
2142 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2143 dev_info(&adapter->pdev->dev,
2144 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2145 adapter->function_mode, adapter->function_caps);
2146 }
2147
2148 mutex_unlock(&adapter->mbox_lock);
2149 return status;
2150}
2151
2152/* Uses mbox */
2153int be_cmd_reset_function(struct be_adapter *adapter)
2154{
2155 struct be_mcc_wrb *wrb;
2156 struct be_cmd_req_hdr *req;
2157 int status;
2158
2159 if (lancer_chip(adapter)) {
2160 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2161 adapter->db + SLIPORT_CONTROL_OFFSET);
2162 status = lancer_wait_ready(adapter);
2163 if (status)
2164 dev_err(&adapter->pdev->dev,
2165 "Adapter in non recoverable error\n");
2166 return status;
2167 }
2168
2169 if (mutex_lock_interruptible(&adapter->mbox_lock))
2170 return -1;
2171
2172 wrb = wrb_from_mbox(adapter);
2173 req = embedded_payload(wrb);
2174
2175 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2176 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2177 NULL);
2178
2179 status = be_mbox_notify_wait(adapter);
2180
2181 mutex_unlock(&adapter->mbox_lock);
2182 return status;
2183}
2184
2185int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2186 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2187{
2188 struct be_mcc_wrb *wrb;
2189 struct be_cmd_req_rss_config *req;
2190 int status;
2191
2192 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2193 return 0;
2194
2195 mutex_lock(&adapter->mcc_lock);
2196
2197 wrb = wrb_from_mccq(adapter);
2198 if (!wrb) {
2199 status = -EBUSY;
2200 goto err;
2201 }
2202 req = embedded_payload(wrb);
2203
2204 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2205 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2206
2207 req->if_id = cpu_to_le32(adapter->if_handle);
2208 req->enable_rss = cpu_to_le16(rss_hash_opts);
2209 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2210
2211 if (!BEx_chip(adapter))
2212 req->hdr.version = 1;
2213
2214 memcpy(req->cpu_table, rsstable, table_size);
2215 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2216 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2217
2218 status = be_mcc_notify_wait(adapter);
2219err:
2220 mutex_unlock(&adapter->mcc_lock);
2221 return status;
2222}
2223
2224/* Uses sync mcc */
2225int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2226 u8 bcn, u8 sts, u8 state)
2227{
2228 struct be_mcc_wrb *wrb;
2229 struct be_cmd_req_enable_disable_beacon *req;
2230 int status;
2231
2232 mutex_lock(&adapter->mcc_lock);
2233
2234 wrb = wrb_from_mccq(adapter);
2235 if (!wrb) {
2236 status = -EBUSY;
2237 goto err;
2238 }
2239 req = embedded_payload(wrb);
2240
2241 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2242 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2243 sizeof(*req), wrb, NULL);
2244
2245 req->port_num = port_num;
2246 req->beacon_state = state;
2247 req->beacon_duration = bcn;
2248 req->status_duration = sts;
2249
2250 status = be_mcc_notify_wait(adapter);
2251
2252err:
2253 mutex_unlock(&adapter->mcc_lock);
2254 return status;
2255}
2256
2257/* Uses sync mcc */
2258int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2259{
2260 struct be_mcc_wrb *wrb;
2261 struct be_cmd_req_get_beacon_state *req;
2262 int status;
2263
2264 mutex_lock(&adapter->mcc_lock);
2265
2266 wrb = wrb_from_mccq(adapter);
2267 if (!wrb) {
2268 status = -EBUSY;
2269 goto err;
2270 }
2271 req = embedded_payload(wrb);
2272
2273 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2274 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2275 wrb, NULL);
2276
2277 req->port_num = port_num;
2278
2279 status = be_mcc_notify_wait(adapter);
2280 if (!status) {
2281 struct be_cmd_resp_get_beacon_state *resp =
2282 embedded_payload(wrb);
2283
2284 *state = resp->beacon_state;
2285 }
2286
2287err:
2288 mutex_unlock(&adapter->mcc_lock);
2289 return status;
2290}
2291
2292/* Uses sync mcc */
2293int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2294 u8 page_num, u8 *data)
2295{
2296 struct be_dma_mem cmd;
2297 struct be_mcc_wrb *wrb;
2298 struct be_cmd_req_port_type *req;
2299 int status;
2300
2301 if (page_num > TR_PAGE_A2)
2302 return -EINVAL;
2303
2304 cmd.size = sizeof(struct be_cmd_resp_port_type);
2305 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2306 GFP_ATOMIC);
2307 if (!cmd.va) {
2308 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2309 return -ENOMEM;
2310 }
2311
2312 mutex_lock(&adapter->mcc_lock);
2313
2314 wrb = wrb_from_mccq(adapter);
2315 if (!wrb) {
2316 status = -EBUSY;
2317 goto err;
2318 }
2319 req = cmd.va;
2320
2321 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2322 OPCODE_COMMON_READ_TRANSRECV_DATA,
2323 cmd.size, wrb, &cmd);
2324
2325 req->port = cpu_to_le32(adapter->hba_port_num);
2326 req->page_num = cpu_to_le32(page_num);
2327 status = be_mcc_notify_wait(adapter);
2328 if (!status) {
2329 struct be_cmd_resp_port_type *resp = cmd.va;
2330
2331 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2332 }
2333err:
2334 mutex_unlock(&adapter->mcc_lock);
2335 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2336 return status;
2337}
2338
2339static int lancer_cmd_write_object(struct be_adapter *adapter,
2340 struct be_dma_mem *cmd, u32 data_size,
2341 u32 data_offset, const char *obj_name,
2342 u32 *data_written, u8 *change_status,
2343 u8 *addn_status)
2344{
2345 struct be_mcc_wrb *wrb;
2346 struct lancer_cmd_req_write_object *req;
2347 struct lancer_cmd_resp_write_object *resp;
2348 void *ctxt = NULL;
2349 int status;
2350
2351 mutex_lock(&adapter->mcc_lock);
2352 adapter->flash_status = 0;
2353
2354 wrb = wrb_from_mccq(adapter);
2355 if (!wrb) {
2356 status = -EBUSY;
2357 goto err_unlock;
2358 }
2359
2360 req = embedded_payload(wrb);
2361
2362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2363 OPCODE_COMMON_WRITE_OBJECT,
2364 sizeof(struct lancer_cmd_req_write_object), wrb,
2365 NULL);
2366
2367 ctxt = &req->context;
2368 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2369 write_length, ctxt, data_size);
2370
2371 if (data_size == 0)
2372 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2373 eof, ctxt, 1);
2374 else
2375 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2376 eof, ctxt, 0);
2377
2378 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2379 req->write_offset = cpu_to_le32(data_offset);
2380 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2381 req->descriptor_count = cpu_to_le32(1);
2382 req->buf_len = cpu_to_le32(data_size);
2383 req->addr_low = cpu_to_le32((cmd->dma +
2384 sizeof(struct lancer_cmd_req_write_object))
2385 & 0xFFFFFFFF);
2386 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2387 sizeof(struct lancer_cmd_req_write_object)));
2388
2389 status = be_mcc_notify(adapter);
2390 if (status)
2391 goto err_unlock;
2392
2393 mutex_unlock(&adapter->mcc_lock);
2394
2395 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2396 msecs_to_jiffies(60000)))
2397 status = -ETIMEDOUT;
2398 else
2399 status = adapter->flash_status;
2400
2401 resp = embedded_payload(wrb);
2402 if (!status) {
2403 *data_written = le32_to_cpu(resp->actual_write_len);
2404 *change_status = resp->change_status;
2405 } else {
2406 *addn_status = resp->additional_status;
2407 }
2408
2409 return status;
2410
2411err_unlock:
2412 mutex_unlock(&adapter->mcc_lock);
2413 return status;
2414}
2415
2416int be_cmd_query_cable_type(struct be_adapter *adapter)
2417{
2418 u8 page_data[PAGE_DATA_LEN];
2419 int status;
2420
2421 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2422 page_data);
2423 if (!status) {
2424 switch (adapter->phy.interface_type) {
2425 case PHY_TYPE_QSFP:
2426 adapter->phy.cable_type =
2427 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2428 break;
2429 case PHY_TYPE_SFP_PLUS_10GB:
2430 adapter->phy.cable_type =
2431 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2432 break;
2433 default:
2434 adapter->phy.cable_type = 0;
2435 break;
2436 }
2437 }
2438 return status;
2439}
2440
2441int be_cmd_query_sfp_info(struct be_adapter *adapter)
2442{
2443 u8 page_data[PAGE_DATA_LEN];
2444 int status;
2445
2446 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2447 page_data);
2448 if (!status) {
2449 strlcpy(adapter->phy.vendor_name, page_data +
2450 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2451 strlcpy(adapter->phy.vendor_pn,
2452 page_data + SFP_VENDOR_PN_OFFSET,
2453 SFP_VENDOR_NAME_LEN - 1);
2454 }
2455
2456 return status;
2457}
2458
2459static int lancer_cmd_delete_object(struct be_adapter *adapter,
2460 const char *obj_name)
2461{
2462 struct lancer_cmd_req_delete_object *req;
2463 struct be_mcc_wrb *wrb;
2464 int status;
2465
2466 mutex_lock(&adapter->mcc_lock);
2467
2468 wrb = wrb_from_mccq(adapter);
2469 if (!wrb) {
2470 status = -EBUSY;
2471 goto err;
2472 }
2473
2474 req = embedded_payload(wrb);
2475
2476 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477 OPCODE_COMMON_DELETE_OBJECT,
2478 sizeof(*req), wrb, NULL);
2479
2480 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2481
2482 status = be_mcc_notify_wait(adapter);
2483err:
2484 mutex_unlock(&adapter->mcc_lock);
2485 return status;
2486}
2487
2488int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2489 u32 data_size, u32 data_offset, const char *obj_name,
2490 u32 *data_read, u32 *eof, u8 *addn_status)
2491{
2492 struct be_mcc_wrb *wrb;
2493 struct lancer_cmd_req_read_object *req;
2494 struct lancer_cmd_resp_read_object *resp;
2495 int status;
2496
2497 mutex_lock(&adapter->mcc_lock);
2498
2499 wrb = wrb_from_mccq(adapter);
2500 if (!wrb) {
2501 status = -EBUSY;
2502 goto err_unlock;
2503 }
2504
2505 req = embedded_payload(wrb);
2506
2507 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2508 OPCODE_COMMON_READ_OBJECT,
2509 sizeof(struct lancer_cmd_req_read_object), wrb,
2510 NULL);
2511
2512 req->desired_read_len = cpu_to_le32(data_size);
2513 req->read_offset = cpu_to_le32(data_offset);
2514 strcpy(req->object_name, obj_name);
2515 req->descriptor_count = cpu_to_le32(1);
2516 req->buf_len = cpu_to_le32(data_size);
2517 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2518 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2519
2520 status = be_mcc_notify_wait(adapter);
2521
2522 resp = embedded_payload(wrb);
2523 if (!status) {
2524 *data_read = le32_to_cpu(resp->actual_read_len);
2525 *eof = le32_to_cpu(resp->eof);
2526 } else {
2527 *addn_status = resp->additional_status;
2528 }
2529
2530err_unlock:
2531 mutex_unlock(&adapter->mcc_lock);
2532 return status;
2533}
2534
2535static int be_cmd_write_flashrom(struct be_adapter *adapter,
2536 struct be_dma_mem *cmd, u32 flash_type,
2537 u32 flash_opcode, u32 img_offset, u32 buf_size)
2538{
2539 struct be_mcc_wrb *wrb;
2540 struct be_cmd_write_flashrom *req;
2541 int status;
2542
2543 mutex_lock(&adapter->mcc_lock);
2544 adapter->flash_status = 0;
2545
2546 wrb = wrb_from_mccq(adapter);
2547 if (!wrb) {
2548 status = -EBUSY;
2549 goto err_unlock;
2550 }
2551 req = cmd->va;
2552
2553 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2554 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2555 cmd);
2556
2557 req->params.op_type = cpu_to_le32(flash_type);
2558 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2559 req->params.offset = cpu_to_le32(img_offset);
2560
2561 req->params.op_code = cpu_to_le32(flash_opcode);
2562 req->params.data_buf_size = cpu_to_le32(buf_size);
2563
2564 status = be_mcc_notify(adapter);
2565 if (status)
2566 goto err_unlock;
2567
2568 mutex_unlock(&adapter->mcc_lock);
2569
2570 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2571 msecs_to_jiffies(40000)))
2572 status = -ETIMEDOUT;
2573 else
2574 status = adapter->flash_status;
2575
2576 return status;
2577
2578err_unlock:
2579 mutex_unlock(&adapter->mcc_lock);
2580 return status;
2581}
2582
2583static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2584 u16 img_optype, u32 img_offset, u32 crc_offset)
2585{
2586 struct be_cmd_read_flash_crc *req;
2587 struct be_mcc_wrb *wrb;
2588 int status;
2589
2590 mutex_lock(&adapter->mcc_lock);
2591
2592 wrb = wrb_from_mccq(adapter);
2593 if (!wrb) {
2594 status = -EBUSY;
2595 goto err;
2596 }
2597 req = embedded_payload(wrb);
2598
2599 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2600 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2601 wrb, NULL);
2602
2603 req->params.op_type = cpu_to_le32(img_optype);
2604 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2605 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2606 else
2607 req->params.offset = cpu_to_le32(crc_offset);
2608
2609 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2610 req->params.data_buf_size = cpu_to_le32(0x4);
2611
2612 status = be_mcc_notify_wait(adapter);
2613 if (!status)
2614 memcpy(flashed_crc, req->crc, 4);
2615
2616err:
2617 mutex_unlock(&adapter->mcc_lock);
2618 return status;
2619}
2620
2621static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2622
2623static bool phy_flashing_required(struct be_adapter *adapter)
2624{
2625 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2626 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2627}
2628
2629static bool is_comp_in_ufi(struct be_adapter *adapter,
2630 struct flash_section_info *fsec, int type)
2631{
2632 int i = 0, img_type = 0;
2633 struct flash_section_info_g2 *fsec_g2 = NULL;
2634
2635 if (BE2_chip(adapter))
2636 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2637
2638 for (i = 0; i < MAX_FLASH_COMP; i++) {
2639 if (fsec_g2)
2640 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2641 else
2642 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2643
2644 if (img_type == type)
2645 return true;
2646 }
2647 return false;
2648}
2649
2650static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2651 int header_size,
2652 const struct firmware *fw)
2653{
2654 struct flash_section_info *fsec = NULL;
2655 const u8 *p = fw->data;
2656
2657 p += header_size;
2658 while (p < (fw->data + fw->size)) {
2659 fsec = (struct flash_section_info *)p;
2660 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2661 return fsec;
2662 p += 32;
2663 }
2664 return NULL;
2665}
2666
2667static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2668 u32 img_offset, u32 img_size, int hdr_size,
2669 u16 img_optype, bool *crc_match)
2670{
2671 u32 crc_offset;
2672 int status;
2673 u8 crc[4];
2674
2675 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2676 img_size - 4);
2677 if (status)
2678 return status;
2679
2680 crc_offset = hdr_size + img_offset + img_size - 4;
2681
2682 /* Skip flashing, if crc of flashed region matches */
2683 if (!memcmp(crc, p + crc_offset, 4))
2684 *crc_match = true;
2685 else
2686 *crc_match = false;
2687
2688 return status;
2689}
2690
2691static int be_flash(struct be_adapter *adapter, const u8 *img,
2692 struct be_dma_mem *flash_cmd, int optype, int img_size,
2693 u32 img_offset)
2694{
2695 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2696 struct be_cmd_write_flashrom *req = flash_cmd->va;
2697 int status;
2698
2699 while (total_bytes) {
2700 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2701
2702 total_bytes -= num_bytes;
2703
2704 if (!total_bytes) {
2705 if (optype == OPTYPE_PHY_FW)
2706 flash_op = FLASHROM_OPER_PHY_FLASH;
2707 else
2708 flash_op = FLASHROM_OPER_FLASH;
2709 } else {
2710 if (optype == OPTYPE_PHY_FW)
2711 flash_op = FLASHROM_OPER_PHY_SAVE;
2712 else
2713 flash_op = FLASHROM_OPER_SAVE;
2714 }
2715
2716 memcpy(req->data_buf, img, num_bytes);
2717 img += num_bytes;
2718 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2719 flash_op, img_offset +
2720 bytes_sent, num_bytes);
2721 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2722 optype == OPTYPE_PHY_FW)
2723 break;
2724 else if (status)
2725 return status;
2726
2727 bytes_sent += num_bytes;
2728 }
2729 return 0;
2730}
2731
2732#define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2733static bool be_fw_ncsi_supported(char *ver)
2734{
2735 int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2736 int v2[4];
2737 int i;
2738
2739 if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2740 return false;
2741
2742 for (i = 0; i < 4; i++) {
2743 if (v1[i] < v2[i])
2744 return true;
2745 else if (v1[i] > v2[i])
2746 return false;
2747 }
2748
2749 return true;
2750}
2751
2752/* For BE2, BE3 and BE3-R */
2753static int be_flash_BEx(struct be_adapter *adapter,
2754 const struct firmware *fw,
2755 struct be_dma_mem *flash_cmd, int num_of_images)
2756{
2757 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2758 struct device *dev = &adapter->pdev->dev;
2759 struct flash_section_info *fsec = NULL;
2760 int status, i, filehdr_size, num_comp;
2761 const struct flash_comp *pflashcomp;
2762 bool crc_match;
2763 const u8 *p;
2764
2765 struct flash_comp gen3_flash_types[] = {
2766 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2767 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2768 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2769 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2770 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2771 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2772 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2773 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2774 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2775 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2776 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2777 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2778 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2779 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2780 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2781 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2782 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2783 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2784 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2785 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2786 };
2787
2788 struct flash_comp gen2_flash_types[] = {
2789 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2790 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2791 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2792 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2793 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2794 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2795 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2796 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2797 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2798 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2799 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2800 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2801 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2802 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2803 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2804 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2805 };
2806
2807 if (BE3_chip(adapter)) {
2808 pflashcomp = gen3_flash_types;
2809 filehdr_size = sizeof(struct flash_file_hdr_g3);
2810 num_comp = ARRAY_SIZE(gen3_flash_types);
2811 } else {
2812 pflashcomp = gen2_flash_types;
2813 filehdr_size = sizeof(struct flash_file_hdr_g2);
2814 num_comp = ARRAY_SIZE(gen2_flash_types);
2815 img_hdrs_size = 0;
2816 }
2817
2818 /* Get flash section info*/
2819 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2820 if (!fsec) {
2821 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2822 return -1;
2823 }
2824 for (i = 0; i < num_comp; i++) {
2825 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2826 continue;
2827
2828 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2829 !be_fw_ncsi_supported(adapter->fw_ver)) {
2830 dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
2831 continue;
2832 }
2833
2834 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2835 !phy_flashing_required(adapter))
2836 continue;
2837
2838 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2839 status = be_check_flash_crc(adapter, fw->data,
2840 pflashcomp[i].offset,
2841 pflashcomp[i].size,
2842 filehdr_size +
2843 img_hdrs_size,
2844 OPTYPE_REDBOOT, &crc_match);
2845 if (status) {
2846 dev_err(dev,
2847 "Could not get CRC for 0x%x region\n",
2848 pflashcomp[i].optype);
2849 continue;
2850 }
2851
2852 if (crc_match)
2853 continue;
2854 }
2855
2856 p = fw->data + filehdr_size + pflashcomp[i].offset +
2857 img_hdrs_size;
2858 if (p + pflashcomp[i].size > fw->data + fw->size)
2859 return -1;
2860
2861 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2862 pflashcomp[i].size, 0);
2863 if (status) {
2864 dev_err(dev, "Flashing section type 0x%x failed\n",
2865 pflashcomp[i].img_type);
2866 return status;
2867 }
2868 }
2869 return 0;
2870}
2871
2872static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2873{
2874 u32 img_type = le32_to_cpu(fsec_entry.type);
2875 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2876
2877 if (img_optype != 0xFFFF)
2878 return img_optype;
2879
2880 switch (img_type) {
2881 case IMAGE_FIRMWARE_ISCSI:
2882 img_optype = OPTYPE_ISCSI_ACTIVE;
2883 break;
2884 case IMAGE_BOOT_CODE:
2885 img_optype = OPTYPE_REDBOOT;
2886 break;
2887 case IMAGE_OPTION_ROM_ISCSI:
2888 img_optype = OPTYPE_BIOS;
2889 break;
2890 case IMAGE_OPTION_ROM_PXE:
2891 img_optype = OPTYPE_PXE_BIOS;
2892 break;
2893 case IMAGE_OPTION_ROM_FCOE:
2894 img_optype = OPTYPE_FCOE_BIOS;
2895 break;
2896 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2897 img_optype = OPTYPE_ISCSI_BACKUP;
2898 break;
2899 case IMAGE_NCSI:
2900 img_optype = OPTYPE_NCSI_FW;
2901 break;
2902 case IMAGE_FLASHISM_JUMPVECTOR:
2903 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2904 break;
2905 case IMAGE_FIRMWARE_PHY:
2906 img_optype = OPTYPE_SH_PHY_FW;
2907 break;
2908 case IMAGE_REDBOOT_DIR:
2909 img_optype = OPTYPE_REDBOOT_DIR;
2910 break;
2911 case IMAGE_REDBOOT_CONFIG:
2912 img_optype = OPTYPE_REDBOOT_CONFIG;
2913 break;
2914 case IMAGE_UFI_DIR:
2915 img_optype = OPTYPE_UFI_DIR;
2916 break;
2917 default:
2918 break;
2919 }
2920
2921 return img_optype;
2922}
2923
2924static int be_flash_skyhawk(struct be_adapter *adapter,
2925 const struct firmware *fw,
2926 struct be_dma_mem *flash_cmd, int num_of_images)
2927{
2928 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2929 bool crc_match, old_fw_img, flash_offset_support = true;
2930 struct device *dev = &adapter->pdev->dev;
2931 struct flash_section_info *fsec = NULL;
2932 u32 img_offset, img_size, img_type;
2933 u16 img_optype, flash_optype;
2934 int status, i, filehdr_size;
2935 const u8 *p;
2936
2937 filehdr_size = sizeof(struct flash_file_hdr_g3);
2938 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2939 if (!fsec) {
2940 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2941 return -EINVAL;
2942 }
2943
2944retry_flash:
2945 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2946 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2947 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2948 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2949 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2950 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2951
2952 if (img_optype == 0xFFFF)
2953 continue;
2954
2955 if (flash_offset_support)
2956 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2957 else
2958 flash_optype = img_optype;
2959
2960 /* Don't bother verifying CRC if an old FW image is being
2961 * flashed
2962 */
2963 if (old_fw_img)
2964 goto flash;
2965
2966 status = be_check_flash_crc(adapter, fw->data, img_offset,
2967 img_size, filehdr_size +
2968 img_hdrs_size, flash_optype,
2969 &crc_match);
2970 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2971 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2972 /* The current FW image on the card does not support
2973 * OFFSET based flashing. Retry using older mechanism
2974 * of OPTYPE based flashing
2975 */
2976 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2977 flash_offset_support = false;
2978 goto retry_flash;
2979 }
2980
2981 /* The current FW image on the card does not recognize
2982 * the new FLASH op_type. The FW download is partially
2983 * complete. Reboot the server now to enable FW image
2984 * to recognize the new FLASH op_type. To complete the
2985 * remaining process, download the same FW again after
2986 * the reboot.
2987 */
2988 dev_err(dev, "Flash incomplete. Reset the server\n");
2989 dev_err(dev, "Download FW image again after reset\n");
2990 return -EAGAIN;
2991 } else if (status) {
2992 dev_err(dev, "Could not get CRC for 0x%x region\n",
2993 img_optype);
2994 return -EFAULT;
2995 }
2996
2997 if (crc_match)
2998 continue;
2999
3000flash:
3001 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
3002 if (p + img_size > fw->data + fw->size)
3003 return -1;
3004
3005 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3006 img_offset);
3007
3008 /* The current FW image on the card does not support OFFSET
3009 * based flashing. Retry using older mechanism of OPTYPE based
3010 * flashing
3011 */
3012 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3013 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3014 flash_offset_support = false;
3015 goto retry_flash;
3016 }
3017
3018 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3019 * UFI_DIR region
3020 */
3021 if (old_fw_img &&
3022 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3023 (img_optype == OPTYPE_UFI_DIR &&
3024 base_status(status) == MCC_STATUS_FAILED))) {
3025 continue;
3026 } else if (status) {
3027 dev_err(dev, "Flashing section type 0x%x failed\n",
3028 img_type);
3029
3030 switch (addl_status(status)) {
3031 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3032 dev_err(dev,
3033 "Digital signature missing in FW\n");
3034 return -EINVAL;
3035 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3036 dev_err(dev,
3037 "Invalid digital signature in FW\n");
3038 return -EINVAL;
3039 default:
3040 return -EFAULT;
3041 }
3042 }
3043 }
3044 return 0;
3045}
3046
3047int lancer_fw_download(struct be_adapter *adapter,
3048 const struct firmware *fw)
3049{
3050 struct device *dev = &adapter->pdev->dev;
3051 struct be_dma_mem flash_cmd;
3052 const u8 *data_ptr = NULL;
3053 u8 *dest_image_ptr = NULL;
3054 size_t image_size = 0;
3055 u32 chunk_size = 0;
3056 u32 data_written = 0;
3057 u32 offset = 0;
3058 int status = 0;
3059 u8 add_status = 0;
3060 u8 change_status;
3061
3062 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3063 dev_err(dev, "FW image size should be multiple of 4\n");
3064 return -EINVAL;
3065 }
3066
3067 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3068 + LANCER_FW_DOWNLOAD_CHUNK;
3069 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3070 &flash_cmd.dma, GFP_KERNEL);
3071 if (!flash_cmd.va)
3072 return -ENOMEM;
3073
3074 dest_image_ptr = flash_cmd.va +
3075 sizeof(struct lancer_cmd_req_write_object);
3076 image_size = fw->size;
3077 data_ptr = fw->data;
3078
3079 while (image_size) {
3080 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3081
3082 /* Copy the image chunk content. */
3083 memcpy(dest_image_ptr, data_ptr, chunk_size);
3084
3085 status = lancer_cmd_write_object(adapter, &flash_cmd,
3086 chunk_size, offset,
3087 LANCER_FW_DOWNLOAD_LOCATION,
3088 &data_written, &change_status,
3089 &add_status);
3090 if (status)
3091 break;
3092
3093 offset += data_written;
3094 data_ptr += data_written;
3095 image_size -= data_written;
3096 }
3097
3098 if (!status) {
3099 /* Commit the FW written */
3100 status = lancer_cmd_write_object(adapter, &flash_cmd,
3101 0, offset,
3102 LANCER_FW_DOWNLOAD_LOCATION,
3103 &data_written, &change_status,
3104 &add_status);
3105 }
3106
3107 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3108 if (status) {
3109 dev_err(dev, "Firmware load error\n");
3110 return be_cmd_status(status);
3111 }
3112
3113 dev_info(dev, "Firmware flashed successfully\n");
3114
3115 if (change_status == LANCER_FW_RESET_NEEDED) {
3116 dev_info(dev, "Resetting adapter to activate new FW\n");
3117 status = lancer_physdev_ctrl(adapter,
3118 PHYSDEV_CONTROL_FW_RESET_MASK);
3119 if (status) {
3120 dev_err(dev, "Adapter busy, could not reset FW\n");
3121 dev_err(dev, "Reboot server to activate new FW\n");
3122 }
3123 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3124 dev_info(dev, "Reboot server to activate new FW\n");
3125 }
3126
3127 return 0;
3128}
3129
3130/* Check if the flash image file is compatible with the adapter that
3131 * is being flashed.
3132 */
3133static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3134 struct flash_file_hdr_g3 *fhdr)
3135{
3136 if (!fhdr) {
3137 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3138 return false;
3139 }
3140
3141 /* First letter of the build version is used to identify
3142 * which chip this image file is meant for.
3143 */
3144 switch (fhdr->build[0]) {
3145 case BLD_STR_UFI_TYPE_SH:
3146 if (!skyhawk_chip(adapter))
3147 return false;
3148 break;
3149 case BLD_STR_UFI_TYPE_BE3:
3150 if (!BE3_chip(adapter))
3151 return false;
3152 break;
3153 case BLD_STR_UFI_TYPE_BE2:
3154 if (!BE2_chip(adapter))
3155 return false;
3156 break;
3157 default:
3158 return false;
3159 }
3160
3161 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3162 * asic_rev of the chips it is compatible with.
3163 * When asic_type_rev is 0 the image is compatible only with
3164 * pre-BE3-R chips (asic_rev < 0x10)
3165 */
3166 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3167 return adapter->asic_rev < 0x10;
3168 else
3169 return (fhdr->asic_type_rev >= adapter->asic_rev);
3170}
3171
3172int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3173{
3174 struct device *dev = &adapter->pdev->dev;
3175 struct flash_file_hdr_g3 *fhdr3;
3176 struct image_hdr *img_hdr_ptr;
3177 int status = 0, i, num_imgs;
3178 struct be_dma_mem flash_cmd;
3179
3180 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3181 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3182 dev_err(dev, "Flash image is not compatible with adapter\n");
3183 return -EINVAL;
3184 }
3185
3186 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3187 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3188 GFP_KERNEL);
3189 if (!flash_cmd.va)
3190 return -ENOMEM;
3191
3192 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3193 for (i = 0; i < num_imgs; i++) {
3194 img_hdr_ptr = (struct image_hdr *)(fw->data +
3195 (sizeof(struct flash_file_hdr_g3) +
3196 i * sizeof(struct image_hdr)));
3197 if (!BE2_chip(adapter) &&
3198 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3199 continue;
3200
3201 if (skyhawk_chip(adapter))
3202 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3203 num_imgs);
3204 else
3205 status = be_flash_BEx(adapter, fw, &flash_cmd,
3206 num_imgs);
3207 }
3208
3209 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3210 if (!status)
3211 dev_info(dev, "Firmware flashed successfully\n");
3212
3213 return status;
3214}
3215
3216int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3217 struct be_dma_mem *nonemb_cmd)
3218{
3219 struct be_mcc_wrb *wrb;
3220 struct be_cmd_req_acpi_wol_magic_config *req;
3221 int status;
3222
3223 mutex_lock(&adapter->mcc_lock);
3224
3225 wrb = wrb_from_mccq(adapter);
3226 if (!wrb) {
3227 status = -EBUSY;
3228 goto err;
3229 }
3230 req = nonemb_cmd->va;
3231
3232 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3233 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3234 wrb, nonemb_cmd);
3235 memcpy(req->magic_mac, mac, ETH_ALEN);
3236
3237 status = be_mcc_notify_wait(adapter);
3238
3239err:
3240 mutex_unlock(&adapter->mcc_lock);
3241 return status;
3242}
3243
3244int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3245 u8 loopback_type, u8 enable)
3246{
3247 struct be_mcc_wrb *wrb;
3248 struct be_cmd_req_set_lmode *req;
3249 int status;
3250
3251 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3252 CMD_SUBSYSTEM_LOWLEVEL))
3253 return -EPERM;
3254
3255 mutex_lock(&adapter->mcc_lock);
3256
3257 wrb = wrb_from_mccq(adapter);
3258 if (!wrb) {
3259 status = -EBUSY;
3260 goto err_unlock;
3261 }
3262
3263 req = embedded_payload(wrb);
3264
3265 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3266 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3267 wrb, NULL);
3268
3269 req->src_port = port_num;
3270 req->dest_port = port_num;
3271 req->loopback_type = loopback_type;
3272 req->loopback_state = enable;
3273
3274 status = be_mcc_notify(adapter);
3275 if (status)
3276 goto err_unlock;
3277
3278 mutex_unlock(&adapter->mcc_lock);
3279
3280 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3281 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3282 status = -ETIMEDOUT;
3283
3284 return status;
3285
3286err_unlock:
3287 mutex_unlock(&adapter->mcc_lock);
3288 return status;
3289}
3290
3291int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3292 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3293 u64 pattern)
3294{
3295 struct be_mcc_wrb *wrb;
3296 struct be_cmd_req_loopback_test *req;
3297 struct be_cmd_resp_loopback_test *resp;
3298 int status;
3299
3300 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3301 CMD_SUBSYSTEM_LOWLEVEL))
3302 return -EPERM;
3303
3304 mutex_lock(&adapter->mcc_lock);
3305
3306 wrb = wrb_from_mccq(adapter);
3307 if (!wrb) {
3308 status = -EBUSY;
3309 goto err;
3310 }
3311
3312 req = embedded_payload(wrb);
3313
3314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3315 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3316 NULL);
3317
3318 req->hdr.timeout = cpu_to_le32(15);
3319 req->pattern = cpu_to_le64(pattern);
3320 req->src_port = cpu_to_le32(port_num);
3321 req->dest_port = cpu_to_le32(port_num);
3322 req->pkt_size = cpu_to_le32(pkt_size);
3323 req->num_pkts = cpu_to_le32(num_pkts);
3324 req->loopback_type = cpu_to_le32(loopback_type);
3325
3326 status = be_mcc_notify(adapter);
3327 if (status)
3328 goto err;
3329
3330 mutex_unlock(&adapter->mcc_lock);
3331
3332 wait_for_completion(&adapter->et_cmd_compl);
3333 resp = embedded_payload(wrb);
3334 status = le32_to_cpu(resp->status);
3335
3336 return status;
3337err:
3338 mutex_unlock(&adapter->mcc_lock);
3339 return status;
3340}
3341
3342int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3343 u32 byte_cnt, struct be_dma_mem *cmd)
3344{
3345 struct be_mcc_wrb *wrb;
3346 struct be_cmd_req_ddrdma_test *req;
3347 int status;
3348 int i, j = 0;
3349
3350 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3351 CMD_SUBSYSTEM_LOWLEVEL))
3352 return -EPERM;
3353
3354 mutex_lock(&adapter->mcc_lock);
3355
3356 wrb = wrb_from_mccq(adapter);
3357 if (!wrb) {
3358 status = -EBUSY;
3359 goto err;
3360 }
3361 req = cmd->va;
3362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3363 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3364 cmd);
3365
3366 req->pattern = cpu_to_le64(pattern);
3367 req->byte_count = cpu_to_le32(byte_cnt);
3368 for (i = 0; i < byte_cnt; i++) {
3369 req->snd_buff[i] = (u8)(pattern >> (j*8));
3370 j++;
3371 if (j > 7)
3372 j = 0;
3373 }
3374
3375 status = be_mcc_notify_wait(adapter);
3376
3377 if (!status) {
3378 struct be_cmd_resp_ddrdma_test *resp;
3379
3380 resp = cmd->va;
3381 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3382 resp->snd_err) {
3383 status = -1;
3384 }
3385 }
3386
3387err:
3388 mutex_unlock(&adapter->mcc_lock);
3389 return status;
3390}
3391
3392int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3393 struct be_dma_mem *nonemb_cmd)
3394{
3395 struct be_mcc_wrb *wrb;
3396 struct be_cmd_req_seeprom_read *req;
3397 int status;
3398
3399 mutex_lock(&adapter->mcc_lock);
3400
3401 wrb = wrb_from_mccq(adapter);
3402 if (!wrb) {
3403 status = -EBUSY;
3404 goto err;
3405 }
3406 req = nonemb_cmd->va;
3407
3408 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3409 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3410 nonemb_cmd);
3411
3412 status = be_mcc_notify_wait(adapter);
3413
3414err:
3415 mutex_unlock(&adapter->mcc_lock);
3416 return status;
3417}
3418
3419int be_cmd_get_phy_info(struct be_adapter *adapter)
3420{
3421 struct be_mcc_wrb *wrb;
3422 struct be_cmd_req_get_phy_info *req;
3423 struct be_dma_mem cmd;
3424 int status;
3425
3426 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3427 CMD_SUBSYSTEM_COMMON))
3428 return -EPERM;
3429
3430 mutex_lock(&adapter->mcc_lock);
3431
3432 wrb = wrb_from_mccq(adapter);
3433 if (!wrb) {
3434 status = -EBUSY;
3435 goto err;
3436 }
3437 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3438 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3439 GFP_ATOMIC);
3440 if (!cmd.va) {
3441 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3442 status = -ENOMEM;
3443 goto err;
3444 }
3445
3446 req = cmd.va;
3447
3448 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3449 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3450 wrb, &cmd);
3451
3452 status = be_mcc_notify_wait(adapter);
3453 if (!status) {
3454 struct be_phy_info *resp_phy_info =
3455 cmd.va + sizeof(struct be_cmd_req_hdr);
3456
3457 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3458 adapter->phy.interface_type =
3459 le16_to_cpu(resp_phy_info->interface_type);
3460 adapter->phy.auto_speeds_supported =
3461 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3462 adapter->phy.fixed_speeds_supported =
3463 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3464 adapter->phy.misc_params =
3465 le32_to_cpu(resp_phy_info->misc_params);
3466
3467 if (BE2_chip(adapter)) {
3468 adapter->phy.fixed_speeds_supported =
3469 BE_SUPPORTED_SPEED_10GBPS |
3470 BE_SUPPORTED_SPEED_1GBPS;
3471 }
3472 }
3473 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3474err:
3475 mutex_unlock(&adapter->mcc_lock);
3476 return status;
3477}
3478
3479static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3480{
3481 struct be_mcc_wrb *wrb;
3482 struct be_cmd_req_set_qos *req;
3483 int status;
3484
3485 mutex_lock(&adapter->mcc_lock);
3486
3487 wrb = wrb_from_mccq(adapter);
3488 if (!wrb) {
3489 status = -EBUSY;
3490 goto err;
3491 }
3492
3493 req = embedded_payload(wrb);
3494
3495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3496 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3497
3498 req->hdr.domain = domain;
3499 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3500 req->max_bps_nic = cpu_to_le32(bps);
3501
3502 status = be_mcc_notify_wait(adapter);
3503
3504err:
3505 mutex_unlock(&adapter->mcc_lock);
3506 return status;
3507}
3508
3509int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3510{
3511 struct be_mcc_wrb *wrb;
3512 struct be_cmd_req_cntl_attribs *req;
3513 struct be_cmd_resp_cntl_attribs *resp;
3514 int status, i;
3515 int payload_len = max(sizeof(*req), sizeof(*resp));
3516 struct mgmt_controller_attrib *attribs;
3517 struct be_dma_mem attribs_cmd;
3518 u32 *serial_num;
3519
3520 if (mutex_lock_interruptible(&adapter->mbox_lock))
3521 return -1;
3522
3523 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3524 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3525 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3526 attribs_cmd.size,
3527 &attribs_cmd.dma, GFP_ATOMIC);
3528 if (!attribs_cmd.va) {
3529 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3530 status = -ENOMEM;
3531 goto err;
3532 }
3533
3534 wrb = wrb_from_mbox(adapter);
3535 if (!wrb) {
3536 status = -EBUSY;
3537 goto err;
3538 }
3539 req = attribs_cmd.va;
3540
3541 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3542 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3543 wrb, &attribs_cmd);
3544
3545 status = be_mbox_notify_wait(adapter);
3546 if (!status) {
3547 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3548 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3549 serial_num = attribs->hba_attribs.controller_serial_number;
3550 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3551 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3552 (BIT_MASK(16) - 1);
3553 /* For BEx, since GET_FUNC_CONFIG command is not
3554 * supported, we read funcnum here as a workaround.
3555 */
3556 if (BEx_chip(adapter))
3557 adapter->pf_num = attribs->hba_attribs.pci_funcnum;
3558 }
3559
3560err:
3561 mutex_unlock(&adapter->mbox_lock);
3562 if (attribs_cmd.va)
3563 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3564 attribs_cmd.va, attribs_cmd.dma);
3565 return status;
3566}
3567
3568/* Uses mbox */
3569int be_cmd_req_native_mode(struct be_adapter *adapter)
3570{
3571 struct be_mcc_wrb *wrb;
3572 struct be_cmd_req_set_func_cap *req;
3573 int status;
3574
3575 if (mutex_lock_interruptible(&adapter->mbox_lock))
3576 return -1;
3577
3578 wrb = wrb_from_mbox(adapter);
3579 if (!wrb) {
3580 status = -EBUSY;
3581 goto err;
3582 }
3583
3584 req = embedded_payload(wrb);
3585
3586 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3587 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3588 sizeof(*req), wrb, NULL);
3589
3590 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3591 CAPABILITY_BE3_NATIVE_ERX_API);
3592 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3593
3594 status = be_mbox_notify_wait(adapter);
3595 if (!status) {
3596 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3597
3598 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3599 CAPABILITY_BE3_NATIVE_ERX_API;
3600 if (!adapter->be3_native)
3601 dev_warn(&adapter->pdev->dev,
3602 "adapter not in advanced mode\n");
3603 }
3604err:
3605 mutex_unlock(&adapter->mbox_lock);
3606 return status;
3607}
3608
3609/* Get privilege(s) for a function */
3610int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3611 u32 domain)
3612{
3613 struct be_mcc_wrb *wrb;
3614 struct be_cmd_req_get_fn_privileges *req;
3615 int status;
3616
3617 mutex_lock(&adapter->mcc_lock);
3618
3619 wrb = wrb_from_mccq(adapter);
3620 if (!wrb) {
3621 status = -EBUSY;
3622 goto err;
3623 }
3624
3625 req = embedded_payload(wrb);
3626
3627 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3628 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3629 wrb, NULL);
3630
3631 req->hdr.domain = domain;
3632
3633 status = be_mcc_notify_wait(adapter);
3634 if (!status) {
3635 struct be_cmd_resp_get_fn_privileges *resp =
3636 embedded_payload(wrb);
3637
3638 *privilege = le32_to_cpu(resp->privilege_mask);
3639
3640 /* In UMC mode FW does not return right privileges.
3641 * Override with correct privilege equivalent to PF.
3642 */
3643 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3644 be_physfn(adapter))
3645 *privilege = MAX_PRIVILEGES;
3646 }
3647
3648err:
3649 mutex_unlock(&adapter->mcc_lock);
3650 return status;
3651}
3652
3653/* Set privilege(s) for a function */
3654int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3655 u32 domain)
3656{
3657 struct be_mcc_wrb *wrb;
3658 struct be_cmd_req_set_fn_privileges *req;
3659 int status;
3660
3661 mutex_lock(&adapter->mcc_lock);
3662
3663 wrb = wrb_from_mccq(adapter);
3664 if (!wrb) {
3665 status = -EBUSY;
3666 goto err;
3667 }
3668
3669 req = embedded_payload(wrb);
3670 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3671 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3672 wrb, NULL);
3673 req->hdr.domain = domain;
3674 if (lancer_chip(adapter))
3675 req->privileges_lancer = cpu_to_le32(privileges);
3676 else
3677 req->privileges = cpu_to_le32(privileges);
3678
3679 status = be_mcc_notify_wait(adapter);
3680err:
3681 mutex_unlock(&adapter->mcc_lock);
3682 return status;
3683}
3684
3685/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3686 * pmac_id_valid: false => pmac_id or MAC address is requested.
3687 * If pmac_id is returned, pmac_id_valid is returned as true
3688 */
3689int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3690 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3691 u8 domain)
3692{
3693 struct be_mcc_wrb *wrb;
3694 struct be_cmd_req_get_mac_list *req;
3695 int status;
3696 int mac_count;
3697 struct be_dma_mem get_mac_list_cmd;
3698 int i;
3699
3700 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3701 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3702 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3703 get_mac_list_cmd.size,
3704 &get_mac_list_cmd.dma,
3705 GFP_ATOMIC);
3706
3707 if (!get_mac_list_cmd.va) {
3708 dev_err(&adapter->pdev->dev,
3709 "Memory allocation failure during GET_MAC_LIST\n");
3710 return -ENOMEM;
3711 }
3712
3713 mutex_lock(&adapter->mcc_lock);
3714
3715 wrb = wrb_from_mccq(adapter);
3716 if (!wrb) {
3717 status = -EBUSY;
3718 goto out;
3719 }
3720
3721 req = get_mac_list_cmd.va;
3722
3723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3724 OPCODE_COMMON_GET_MAC_LIST,
3725 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3726 req->hdr.domain = domain;
3727 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3728 if (*pmac_id_valid) {
3729 req->mac_id = cpu_to_le32(*pmac_id);
3730 req->iface_id = cpu_to_le16(if_handle);
3731 req->perm_override = 0;
3732 } else {
3733 req->perm_override = 1;
3734 }
3735
3736 status = be_mcc_notify_wait(adapter);
3737 if (!status) {
3738 struct be_cmd_resp_get_mac_list *resp =
3739 get_mac_list_cmd.va;
3740
3741 if (*pmac_id_valid) {
3742 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3743 ETH_ALEN);
3744 goto out;
3745 }
3746
3747 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3748 /* Mac list returned could contain one or more active mac_ids
3749 * or one or more true or pseudo permanent mac addresses.
3750 * If an active mac_id is present, return first active mac_id
3751 * found.
3752 */
3753 for (i = 0; i < mac_count; i++) {
3754 struct get_list_macaddr *mac_entry;
3755 u16 mac_addr_size;
3756 u32 mac_id;
3757
3758 mac_entry = &resp->macaddr_list[i];
3759 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3760 /* mac_id is a 32 bit value and mac_addr size
3761 * is 6 bytes
3762 */
3763 if (mac_addr_size == sizeof(u32)) {
3764 *pmac_id_valid = true;
3765 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3766 *pmac_id = le32_to_cpu(mac_id);
3767 goto out;
3768 }
3769 }
3770 /* If no active mac_id found, return first mac addr */
3771 *pmac_id_valid = false;
3772 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3773 ETH_ALEN);
3774 }
3775
3776out:
3777 mutex_unlock(&adapter->mcc_lock);
3778 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3779 get_mac_list_cmd.va, get_mac_list_cmd.dma);
3780 return status;
3781}
3782
3783int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3784 u8 *mac, u32 if_handle, bool active, u32 domain)
3785{
3786 if (!active)
3787 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3788 if_handle, domain);
3789 if (BEx_chip(adapter))
3790 return be_cmd_mac_addr_query(adapter, mac, false,
3791 if_handle, curr_pmac_id);
3792 else
3793 /* Fetch the MAC address using pmac_id */
3794 return be_cmd_get_mac_from_list(adapter, mac, &active,
3795 &curr_pmac_id,
3796 if_handle, domain);
3797}
3798
3799int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3800{
3801 int status;
3802 bool pmac_valid = false;
3803
3804 eth_zero_addr(mac);
3805
3806 if (BEx_chip(adapter)) {
3807 if (be_physfn(adapter))
3808 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3809 0);
3810 else
3811 status = be_cmd_mac_addr_query(adapter, mac, false,
3812 adapter->if_handle, 0);
3813 } else {
3814 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3815 NULL, adapter->if_handle, 0);
3816 }
3817
3818 return status;
3819}
3820
3821/* Uses synchronous MCCQ */
3822int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3823 u8 mac_count, u32 domain)
3824{
3825 struct be_mcc_wrb *wrb;
3826 struct be_cmd_req_set_mac_list *req;
3827 int status;
3828 struct be_dma_mem cmd;
3829
3830 memset(&cmd, 0, sizeof(struct be_dma_mem));
3831 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3832 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3833 GFP_KERNEL);
3834 if (!cmd.va)
3835 return -ENOMEM;
3836
3837 mutex_lock(&adapter->mcc_lock);
3838
3839 wrb = wrb_from_mccq(adapter);
3840 if (!wrb) {
3841 status = -EBUSY;
3842 goto err;
3843 }
3844
3845 req = cmd.va;
3846 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3847 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3848 wrb, &cmd);
3849
3850 req->hdr.domain = domain;
3851 req->mac_count = mac_count;
3852 if (mac_count)
3853 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3854
3855 status = be_mcc_notify_wait(adapter);
3856
3857err:
3858 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3859 mutex_unlock(&adapter->mcc_lock);
3860 return status;
3861}
3862
3863/* Wrapper to delete any active MACs and provision the new mac.
3864 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3865 * current list are active.
3866 */
3867int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3868{
3869 bool active_mac = false;
3870 u8 old_mac[ETH_ALEN];
3871 u32 pmac_id;
3872 int status;
3873
3874 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3875 &pmac_id, if_id, dom);
3876
3877 if (!status && active_mac)
3878 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3879
3880 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3881}
3882
3883int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3884 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3885{
3886 struct be_mcc_wrb *wrb;
3887 struct be_cmd_req_set_hsw_config *req;
3888 void *ctxt;
3889 int status;
3890
3891 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3892 CMD_SUBSYSTEM_COMMON))
3893 return -EPERM;
3894
3895 mutex_lock(&adapter->mcc_lock);
3896
3897 wrb = wrb_from_mccq(adapter);
3898 if (!wrb) {
3899 status = -EBUSY;
3900 goto err;
3901 }
3902
3903 req = embedded_payload(wrb);
3904 ctxt = &req->context;
3905
3906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3907 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3908 NULL);
3909
3910 req->hdr.domain = domain;
3911 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3912 if (pvid) {
3913 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3914 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3915 }
3916 if (hsw_mode) {
3917 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3918 ctxt, adapter->hba_port_num);
3919 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3920 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3921 ctxt, hsw_mode);
3922 }
3923
3924 /* Enable/disable both mac and vlan spoof checking */
3925 if (!BEx_chip(adapter) && spoofchk) {
3926 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3927 ctxt, spoofchk);
3928 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3929 ctxt, spoofchk);
3930 }
3931
3932 be_dws_cpu_to_le(req->context, sizeof(req->context));
3933 status = be_mcc_notify_wait(adapter);
3934
3935err:
3936 mutex_unlock(&adapter->mcc_lock);
3937 return status;
3938}
3939
3940/* Get Hyper switch config */
3941int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3942 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3943{
3944 struct be_mcc_wrb *wrb;
3945 struct be_cmd_req_get_hsw_config *req;
3946 void *ctxt;
3947 int status;
3948 u16 vid;
3949
3950 mutex_lock(&adapter->mcc_lock);
3951
3952 wrb = wrb_from_mccq(adapter);
3953 if (!wrb) {
3954 status = -EBUSY;
3955 goto err;
3956 }
3957
3958 req = embedded_payload(wrb);
3959 ctxt = &req->context;
3960
3961 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3962 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3963 NULL);
3964
3965 req->hdr.domain = domain;
3966 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3967 ctxt, intf_id);
3968 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3969
3970 if (!BEx_chip(adapter) && mode) {
3971 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3972 ctxt, adapter->hba_port_num);
3973 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3974 }
3975 be_dws_cpu_to_le(req->context, sizeof(req->context));
3976
3977 status = be_mcc_notify_wait(adapter);
3978 if (!status) {
3979 struct be_cmd_resp_get_hsw_config *resp =
3980 embedded_payload(wrb);
3981
3982 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3983 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3984 pvid, &resp->context);
3985 if (pvid)
3986 *pvid = le16_to_cpu(vid);
3987 if (mode)
3988 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3989 port_fwd_type, &resp->context);
3990 if (spoofchk)
3991 *spoofchk =
3992 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3993 spoofchk, &resp->context);
3994 }
3995
3996err:
3997 mutex_unlock(&adapter->mcc_lock);
3998 return status;
3999}
4000
4001static bool be_is_wol_excluded(struct be_adapter *adapter)
4002{
4003 struct pci_dev *pdev = adapter->pdev;
4004
4005 if (be_virtfn(adapter))
4006 return true;
4007
4008 switch (pdev->subsystem_device) {
4009 case OC_SUBSYS_DEVICE_ID1:
4010 case OC_SUBSYS_DEVICE_ID2:
4011 case OC_SUBSYS_DEVICE_ID3:
4012 case OC_SUBSYS_DEVICE_ID4:
4013 return true;
4014 default:
4015 return false;
4016 }
4017}
4018
4019int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4020{
4021 struct be_mcc_wrb *wrb;
4022 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
4023 int status = 0;
4024 struct be_dma_mem cmd;
4025
4026 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4027 CMD_SUBSYSTEM_ETH))
4028 return -EPERM;
4029
4030 if (be_is_wol_excluded(adapter))
4031 return status;
4032
4033 if (mutex_lock_interruptible(&adapter->mbox_lock))
4034 return -1;
4035
4036 memset(&cmd, 0, sizeof(struct be_dma_mem));
4037 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4038 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4039 GFP_ATOMIC);
4040 if (!cmd.va) {
4041 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4042 status = -ENOMEM;
4043 goto err;
4044 }
4045
4046 wrb = wrb_from_mbox(adapter);
4047 if (!wrb) {
4048 status = -EBUSY;
4049 goto err;
4050 }
4051
4052 req = cmd.va;
4053
4054 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4055 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4056 sizeof(*req), wrb, &cmd);
4057
4058 req->hdr.version = 1;
4059 req->query_options = BE_GET_WOL_CAP;
4060
4061 status = be_mbox_notify_wait(adapter);
4062 if (!status) {
4063 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4064
4065 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4066
4067 adapter->wol_cap = resp->wol_settings;
4068
4069 /* Non-zero macaddr indicates WOL is enabled */
4070 if (adapter->wol_cap & BE_WOL_CAP &&
4071 !is_zero_ether_addr(resp->magic_mac))
4072 adapter->wol_en = true;
4073 }
4074err:
4075 mutex_unlock(&adapter->mbox_lock);
4076 if (cmd.va)
4077 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4078 cmd.dma);
4079 return status;
4080
4081}
4082
4083int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4084{
4085 struct be_dma_mem extfat_cmd;
4086 struct be_fat_conf_params *cfgs;
4087 int status;
4088 int i, j;
4089
4090 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4091 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4092 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4093 extfat_cmd.size, &extfat_cmd.dma,
4094 GFP_ATOMIC);
4095 if (!extfat_cmd.va)
4096 return -ENOMEM;
4097
4098 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4099 if (status)
4100 goto err;
4101
4102 cfgs = (struct be_fat_conf_params *)
4103 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4104 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4105 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4106
4107 for (j = 0; j < num_modes; j++) {
4108 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4109 cfgs->module[i].trace_lvl[j].dbg_lvl =
4110 cpu_to_le32(level);
4111 }
4112 }
4113
4114 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4115err:
4116 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4117 extfat_cmd.dma);
4118 return status;
4119}
4120
4121int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4122{
4123 struct be_dma_mem extfat_cmd;
4124 struct be_fat_conf_params *cfgs;
4125 int status, j;
4126 int level = 0;
4127
4128 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4129 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4130 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4131 extfat_cmd.size, &extfat_cmd.dma,
4132 GFP_ATOMIC);
4133
4134 if (!extfat_cmd.va) {
4135 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4136 __func__);
4137 goto err;
4138 }
4139
4140 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4141 if (!status) {
4142 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4143 sizeof(struct be_cmd_resp_hdr));
4144
4145 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4146 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4147 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4148 }
4149 }
4150 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4151 extfat_cmd.dma);
4152err:
4153 return level;
4154}
4155
4156int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4157 struct be_dma_mem *cmd)
4158{
4159 struct be_mcc_wrb *wrb;
4160 struct be_cmd_req_get_ext_fat_caps *req;
4161 int status;
4162
4163 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4164 CMD_SUBSYSTEM_COMMON))
4165 return -EPERM;
4166
4167 if (mutex_lock_interruptible(&adapter->mbox_lock))
4168 return -1;
4169
4170 wrb = wrb_from_mbox(adapter);
4171 if (!wrb) {
4172 status = -EBUSY;
4173 goto err;
4174 }
4175
4176 req = cmd->va;
4177 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4178 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4179 cmd->size, wrb, cmd);
4180 req->parameter_type = cpu_to_le32(1);
4181
4182 status = be_mbox_notify_wait(adapter);
4183err:
4184 mutex_unlock(&adapter->mbox_lock);
4185 return status;
4186}
4187
4188int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4189 struct be_dma_mem *cmd,
4190 struct be_fat_conf_params *configs)
4191{
4192 struct be_mcc_wrb *wrb;
4193 struct be_cmd_req_set_ext_fat_caps *req;
4194 int status;
4195
4196 mutex_lock(&adapter->mcc_lock);
4197
4198 wrb = wrb_from_mccq(adapter);
4199 if (!wrb) {
4200 status = -EBUSY;
4201 goto err;
4202 }
4203
4204 req = cmd->va;
4205 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4206 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4207 OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
4208 cmd->size, wrb, cmd);
4209
4210 status = be_mcc_notify_wait(adapter);
4211err:
4212 mutex_unlock(&adapter->mcc_lock);
4213 return status;
4214}
4215
4216int be_cmd_query_port_name(struct be_adapter *adapter)
4217{
4218 struct be_cmd_req_get_port_name *req;
4219 struct be_mcc_wrb *wrb;
4220 int status;
4221
4222 if (mutex_lock_interruptible(&adapter->mbox_lock))
4223 return -1;
4224
4225 wrb = wrb_from_mbox(adapter);
4226 req = embedded_payload(wrb);
4227
4228 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4229 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4230 NULL);
4231 if (!BEx_chip(adapter))
4232 req->hdr.version = 1;
4233
4234 status = be_mbox_notify_wait(adapter);
4235 if (!status) {
4236 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4237
4238 adapter->port_name = resp->port_name[adapter->hba_port_num];
4239 } else {
4240 adapter->port_name = adapter->hba_port_num + '0';
4241 }
4242
4243 mutex_unlock(&adapter->mbox_lock);
4244 return status;
4245}
4246
4247/* When more than 1 NIC descriptor is present in the descriptor list,
4248 * the caller must specify the pf_num to obtain the NIC descriptor
4249 * corresponding to its pci function.
4250 * get_vft must be true when the caller wants the VF-template desc of the
4251 * PF-pool.
4252 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4253 * that only it's NIC descriptor is present in the descriptor list.
4254 */
4255static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4256 bool get_vft, u8 pf_num)
4257{
4258 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4259 struct be_nic_res_desc *nic;
4260 int i;
4261
4262 for (i = 0; i < desc_count; i++) {
4263 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4264 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4265 nic = (struct be_nic_res_desc *)hdr;
4266
4267 if ((pf_num == PF_NUM_IGNORE ||
4268 nic->pf_num == pf_num) &&
4269 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4270 return nic;
4271 }
4272 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4273 hdr = (void *)hdr + hdr->desc_len;
4274 }
4275 return NULL;
4276}
4277
4278static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4279 u8 pf_num)
4280{
4281 return be_get_nic_desc(buf, desc_count, true, pf_num);
4282}
4283
4284static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4285 u8 pf_num)
4286{
4287 return be_get_nic_desc(buf, desc_count, false, pf_num);
4288}
4289
4290static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4291 u8 pf_num)
4292{
4293 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4294 struct be_pcie_res_desc *pcie;
4295 int i;
4296
4297 for (i = 0; i < desc_count; i++) {
4298 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4299 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4300 pcie = (struct be_pcie_res_desc *)hdr;
4301 if (pcie->pf_num == pf_num)
4302 return pcie;
4303 }
4304
4305 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4306 hdr = (void *)hdr + hdr->desc_len;
4307 }
4308 return NULL;
4309}
4310
4311static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4312{
4313 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4314 int i;
4315
4316 for (i = 0; i < desc_count; i++) {
4317 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4318 return (struct be_port_res_desc *)hdr;
4319
4320 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4321 hdr = (void *)hdr + hdr->desc_len;
4322 }
4323 return NULL;
4324}
4325
4326static void be_copy_nic_desc(struct be_resources *res,
4327 struct be_nic_res_desc *desc)
4328{
4329 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4330 res->max_vlans = le16_to_cpu(desc->vlan_count);
4331 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4332 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4333 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4334 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4335 res->max_evt_qs = le16_to_cpu(desc->eq_count);
4336 res->max_cq_count = le16_to_cpu(desc->cq_count);
4337 res->max_iface_count = le16_to_cpu(desc->iface_count);
4338 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4339 /* Clear flags that driver is not interested in */
4340 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4341 BE_IF_CAP_FLAGS_WANT;
4342}
4343
4344/* Uses Mbox */
4345int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4346{
4347 struct be_mcc_wrb *wrb;
4348 struct be_cmd_req_get_func_config *req;
4349 int status;
4350 struct be_dma_mem cmd;
4351
4352 if (mutex_lock_interruptible(&adapter->mbox_lock))
4353 return -1;
4354
4355 memset(&cmd, 0, sizeof(struct be_dma_mem));
4356 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4357 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4358 GFP_ATOMIC);
4359 if (!cmd.va) {
4360 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4361 status = -ENOMEM;
4362 goto err;
4363 }
4364
4365 wrb = wrb_from_mbox(adapter);
4366 if (!wrb) {
4367 status = -EBUSY;
4368 goto err;
4369 }
4370
4371 req = cmd.va;
4372
4373 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4374 OPCODE_COMMON_GET_FUNC_CONFIG,
4375 cmd.size, wrb, &cmd);
4376
4377 if (skyhawk_chip(adapter))
4378 req->hdr.version = 1;
4379
4380 status = be_mbox_notify_wait(adapter);
4381 if (!status) {
4382 struct be_cmd_resp_get_func_config *resp = cmd.va;
4383 u32 desc_count = le32_to_cpu(resp->desc_count);
4384 struct be_nic_res_desc *desc;
4385
4386 /* GET_FUNC_CONFIG returns resource descriptors of the
4387 * current function only. So, pf_num should be set to
4388 * PF_NUM_IGNORE.
4389 */
4390 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4391 PF_NUM_IGNORE);
4392 if (!desc) {
4393 status = -EINVAL;
4394 goto err;
4395 }
4396
4397 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4398 adapter->pf_num = desc->pf_num;
4399 adapter->vf_num = desc->vf_num;
4400
4401 if (res)
4402 be_copy_nic_desc(res, desc);
4403 }
4404err:
4405 mutex_unlock(&adapter->mbox_lock);
4406 if (cmd.va)
4407 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4408 cmd.dma);
4409 return status;
4410}
4411
4412/* This routine returns a list of all the NIC PF_nums in the adapter */
4413static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4414{
4415 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4416 struct be_pcie_res_desc *pcie = NULL;
4417 int i;
4418 u16 nic_pf_count = 0;
4419
4420 for (i = 0; i < desc_count; i++) {
4421 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4422 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4423 pcie = (struct be_pcie_res_desc *)hdr;
4424 if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4425 pcie->pf_type == MISSION_RDMA)) {
4426 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4427 }
4428 }
4429
4430 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4431 hdr = (void *)hdr + hdr->desc_len;
4432 }
4433 return nic_pf_count;
4434}
4435
4436/* Will use MBOX only if MCCQ has not been created */
4437int be_cmd_get_profile_config(struct be_adapter *adapter,
4438 struct be_resources *res,
4439 struct be_port_resources *port_res,
4440 u8 profile_type, u8 query, u8 domain)
4441{
4442 struct be_cmd_resp_get_profile_config *resp;
4443 struct be_cmd_req_get_profile_config *req;
4444 struct be_nic_res_desc *vf_res;
4445 struct be_pcie_res_desc *pcie;
4446 struct be_port_res_desc *port;
4447 struct be_nic_res_desc *nic;
4448 struct be_mcc_wrb wrb = {0};
4449 struct be_dma_mem cmd;
4450 u16 desc_count;
4451 int status;
4452
4453 memset(&cmd, 0, sizeof(struct be_dma_mem));
4454 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4455 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4456 GFP_ATOMIC);
4457 if (!cmd.va)
4458 return -ENOMEM;
4459
4460 req = cmd.va;
4461 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4462 OPCODE_COMMON_GET_PROFILE_CONFIG,
4463 cmd.size, &wrb, &cmd);
4464
4465 if (!lancer_chip(adapter))
4466 req->hdr.version = 1;
4467 req->type = profile_type;
4468 req->hdr.domain = domain;
4469
4470 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4471 * descriptors with all bits set to "1" for the fields which can be
4472 * modified using SET_PROFILE_CONFIG cmd.
4473 */
4474 if (query == RESOURCE_MODIFIABLE)
4475 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4476
4477 status = be_cmd_notify_wait(adapter, &wrb);
4478 if (status)
4479 goto err;
4480
4481 resp = cmd.va;
4482 desc_count = le16_to_cpu(resp->desc_count);
4483
4484 if (port_res) {
4485 u16 nic_pf_cnt = 0, i;
4486 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4487
4488 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4489 desc_count,
4490 nic_pf_num_list);
4491
4492 for (i = 0; i < nic_pf_cnt; i++) {
4493 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4494 nic_pf_num_list[i]);
4495 if (nic->link_param == adapter->port_num) {
4496 port_res->nic_pfs++;
4497 pcie = be_get_pcie_desc(resp->func_param,
4498 desc_count,
4499 nic_pf_num_list[i]);
4500 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4501 }
4502 }
4503 return status;
4504 }
4505
4506 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4507 adapter->pf_num);
4508 if (pcie)
4509 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4510
4511 port = be_get_port_desc(resp->func_param, desc_count);
4512 if (port)
4513 adapter->mc_type = port->mc_type;
4514
4515 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4516 adapter->pf_num);
4517 if (nic)
4518 be_copy_nic_desc(res, nic);
4519
4520 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4521 adapter->pf_num);
4522 if (vf_res)
4523 res->vf_if_cap_flags = vf_res->cap_flags;
4524err:
4525 if (cmd.va)
4526 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4527 cmd.dma);
4528 return status;
4529}
4530
4531/* Will use MBOX only if MCCQ has not been created */
4532static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4533 int size, int count, u8 version, u8 domain)
4534{
4535 struct be_cmd_req_set_profile_config *req;
4536 struct be_mcc_wrb wrb = {0};
4537 struct be_dma_mem cmd;
4538 int status;
4539
4540 memset(&cmd, 0, sizeof(struct be_dma_mem));
4541 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4542 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4543 GFP_ATOMIC);
4544 if (!cmd.va)
4545 return -ENOMEM;
4546
4547 req = cmd.va;
4548 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4549 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4550 &wrb, &cmd);
4551 req->hdr.version = version;
4552 req->hdr.domain = domain;
4553 req->desc_count = cpu_to_le32(count);
4554 memcpy(req->desc, desc, size);
4555
4556 status = be_cmd_notify_wait(adapter, &wrb);
4557
4558 if (cmd.va)
4559 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4560 cmd.dma);
4561 return status;
4562}
4563
4564/* Mark all fields invalid */
4565static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4566{
4567 memset(nic, 0, sizeof(*nic));
4568 nic->unicast_mac_count = 0xFFFF;
4569 nic->mcc_count = 0xFFFF;
4570 nic->vlan_count = 0xFFFF;
4571 nic->mcast_mac_count = 0xFFFF;
4572 nic->txq_count = 0xFFFF;
4573 nic->rq_count = 0xFFFF;
4574 nic->rssq_count = 0xFFFF;
4575 nic->lro_count = 0xFFFF;
4576 nic->cq_count = 0xFFFF;
4577 nic->toe_conn_count = 0xFFFF;
4578 nic->eq_count = 0xFFFF;
4579 nic->iface_count = 0xFFFF;
4580 nic->link_param = 0xFF;
4581 nic->channel_id_param = cpu_to_le16(0xF000);
4582 nic->acpi_params = 0xFF;
4583 nic->wol_param = 0x0F;
4584 nic->tunnel_iface_count = 0xFFFF;
4585 nic->direct_tenant_iface_count = 0xFFFF;
4586 nic->bw_min = 0xFFFFFFFF;
4587 nic->bw_max = 0xFFFFFFFF;
4588}
4589
4590/* Mark all fields invalid */
4591static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4592{
4593 memset(pcie, 0, sizeof(*pcie));
4594 pcie->sriov_state = 0xFF;
4595 pcie->pf_state = 0xFF;
4596 pcie->pf_type = 0xFF;
4597 pcie->num_vfs = 0xFFFF;
4598}
4599
4600int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4601 u8 domain)
4602{
4603 struct be_nic_res_desc nic_desc;
4604 u32 bw_percent;
4605 u16 version = 0;
4606
4607 if (BE3_chip(adapter))
4608 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4609
4610 be_reset_nic_desc(&nic_desc);
4611 nic_desc.pf_num = adapter->pf_num;
4612 nic_desc.vf_num = domain;
4613 nic_desc.bw_min = 0;
4614 if (lancer_chip(adapter)) {
4615 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4616 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4617 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4618 (1 << NOSV_SHIFT);
4619 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4620 } else {
4621 version = 1;
4622 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4623 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4624 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4625 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4626 nic_desc.bw_max = cpu_to_le32(bw_percent);
4627 }
4628
4629 return be_cmd_set_profile_config(adapter, &nic_desc,
4630 nic_desc.hdr.desc_len,
4631 1, version, domain);
4632}
4633
4634int be_cmd_set_sriov_config(struct be_adapter *adapter,
4635 struct be_resources pool_res, u16 num_vfs,
4636 struct be_resources *vft_res)
4637{
4638 struct {
4639 struct be_pcie_res_desc pcie;
4640 struct be_nic_res_desc nic_vft;
4641 } __packed desc;
4642
4643 /* PF PCIE descriptor */
4644 be_reset_pcie_desc(&desc.pcie);
4645 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4646 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4647 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4648 desc.pcie.pf_num = adapter->pdev->devfn;
4649 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4650 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4651
4652 /* VF NIC Template descriptor */
4653 be_reset_nic_desc(&desc.nic_vft);
4654 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4655 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4656 desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4657 BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4658 desc.nic_vft.pf_num = adapter->pdev->devfn;
4659 desc.nic_vft.vf_num = 0;
4660 desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4661 desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4662 desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4663 desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4664 desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4665
4666 if (vft_res->max_uc_mac)
4667 desc.nic_vft.unicast_mac_count =
4668 cpu_to_le16(vft_res->max_uc_mac);
4669 if (vft_res->max_vlans)
4670 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4671 if (vft_res->max_iface_count)
4672 desc.nic_vft.iface_count =
4673 cpu_to_le16(vft_res->max_iface_count);
4674 if (vft_res->max_mcc_count)
4675 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4676
4677 return be_cmd_set_profile_config(adapter, &desc,
4678 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4679}
4680
4681int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4682{
4683 struct be_mcc_wrb *wrb;
4684 struct be_cmd_req_manage_iface_filters *req;
4685 int status;
4686
4687 if (iface == 0xFFFFFFFF)
4688 return -1;
4689
4690 mutex_lock(&adapter->mcc_lock);
4691
4692 wrb = wrb_from_mccq(adapter);
4693 if (!wrb) {
4694 status = -EBUSY;
4695 goto err;
4696 }
4697 req = embedded_payload(wrb);
4698
4699 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4700 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4701 wrb, NULL);
4702 req->op = op;
4703 req->target_iface_id = cpu_to_le32(iface);
4704
4705 status = be_mcc_notify_wait(adapter);
4706err:
4707 mutex_unlock(&adapter->mcc_lock);
4708 return status;
4709}
4710
4711int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4712{
4713 struct be_port_res_desc port_desc;
4714
4715 memset(&port_desc, 0, sizeof(port_desc));
4716 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4717 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4718 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4719 port_desc.link_num = adapter->hba_port_num;
4720 if (port) {
4721 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4722 (1 << RCVID_SHIFT);
4723 port_desc.nv_port = swab16(port);
4724 } else {
4725 port_desc.nv_flags = NV_TYPE_DISABLED;
4726 port_desc.nv_port = 0;
4727 }
4728
4729 return be_cmd_set_profile_config(adapter, &port_desc,
4730 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4731}
4732
4733int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4734 int vf_num)
4735{
4736 struct be_mcc_wrb *wrb;
4737 struct be_cmd_req_get_iface_list *req;
4738 struct be_cmd_resp_get_iface_list *resp;
4739 int status;
4740
4741 mutex_lock(&adapter->mcc_lock);
4742
4743 wrb = wrb_from_mccq(adapter);
4744 if (!wrb) {
4745 status = -EBUSY;
4746 goto err;
4747 }
4748 req = embedded_payload(wrb);
4749
4750 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4751 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4752 wrb, NULL);
4753 req->hdr.domain = vf_num + 1;
4754
4755 status = be_mcc_notify_wait(adapter);
4756 if (!status) {
4757 resp = (struct be_cmd_resp_get_iface_list *)req;
4758 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4759 }
4760
4761err:
4762 mutex_unlock(&adapter->mcc_lock);
4763 return status;
4764}
4765
4766static int lancer_wait_idle(struct be_adapter *adapter)
4767{
4768#define SLIPORT_IDLE_TIMEOUT 30
4769 u32 reg_val;
4770 int status = 0, i;
4771
4772 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4773 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4774 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4775 break;
4776
4777 ssleep(1);
4778 }
4779
4780 if (i == SLIPORT_IDLE_TIMEOUT)
4781 status = -1;
4782
4783 return status;
4784}
4785
4786int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4787{
4788 int status = 0;
4789
4790 status = lancer_wait_idle(adapter);
4791 if (status)
4792 return status;
4793
4794 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4795
4796 return status;
4797}
4798
4799/* Routine to check whether dump image is present or not */
4800bool dump_present(struct be_adapter *adapter)
4801{
4802 u32 sliport_status = 0;
4803
4804 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4805 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4806}
4807
4808int lancer_initiate_dump(struct be_adapter *adapter)
4809{
4810 struct device *dev = &adapter->pdev->dev;
4811 int status;
4812
4813 if (dump_present(adapter)) {
4814 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4815 return -EEXIST;
4816 }
4817
4818 /* give firmware reset and diagnostic dump */
4819 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4820 PHYSDEV_CONTROL_DD_MASK);
4821 if (status < 0) {
4822 dev_err(dev, "FW reset failed\n");
4823 return status;
4824 }
4825
4826 status = lancer_wait_idle(adapter);
4827 if (status)
4828 return status;
4829
4830 if (!dump_present(adapter)) {
4831 dev_err(dev, "FW dump not generated\n");
4832 return -EIO;
4833 }
4834
4835 return 0;
4836}
4837
4838int lancer_delete_dump(struct be_adapter *adapter)
4839{
4840 int status;
4841
4842 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4843 return be_cmd_status(status);
4844}
4845
4846/* Uses sync mcc */
4847int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4848{
4849 struct be_mcc_wrb *wrb;
4850 struct be_cmd_enable_disable_vf *req;
4851 int status;
4852
4853 if (BEx_chip(adapter))
4854 return 0;
4855
4856 mutex_lock(&adapter->mcc_lock);
4857
4858 wrb = wrb_from_mccq(adapter);
4859 if (!wrb) {
4860 status = -EBUSY;
4861 goto err;
4862 }
4863
4864 req = embedded_payload(wrb);
4865
4866 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4867 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4868 wrb, NULL);
4869
4870 req->hdr.domain = domain;
4871 req->enable = 1;
4872 status = be_mcc_notify_wait(adapter);
4873err:
4874 mutex_unlock(&adapter->mcc_lock);
4875 return status;
4876}
4877
4878int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4879{
4880 struct be_mcc_wrb *wrb;
4881 struct be_cmd_req_intr_set *req;
4882 int status;
4883
4884 if (mutex_lock_interruptible(&adapter->mbox_lock))
4885 return -1;
4886
4887 wrb = wrb_from_mbox(adapter);
4888
4889 req = embedded_payload(wrb);
4890
4891 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4892 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4893 wrb, NULL);
4894
4895 req->intr_enabled = intr_enable;
4896
4897 status = be_mbox_notify_wait(adapter);
4898
4899 mutex_unlock(&adapter->mbox_lock);
4900 return status;
4901}
4902
4903/* Uses MBOX */
4904int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4905{
4906 struct be_cmd_req_get_active_profile *req;
4907 struct be_mcc_wrb *wrb;
4908 int status;
4909
4910 if (mutex_lock_interruptible(&adapter->mbox_lock))
4911 return -1;
4912
4913 wrb = wrb_from_mbox(adapter);
4914 if (!wrb) {
4915 status = -EBUSY;
4916 goto err;
4917 }
4918
4919 req = embedded_payload(wrb);
4920
4921 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4922 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4923 wrb, NULL);
4924
4925 status = be_mbox_notify_wait(adapter);
4926 if (!status) {
4927 struct be_cmd_resp_get_active_profile *resp =
4928 embedded_payload(wrb);
4929
4930 *profile_id = le16_to_cpu(resp->active_profile_id);
4931 }
4932
4933err:
4934 mutex_unlock(&adapter->mbox_lock);
4935 return status;
4936}
4937
4938static int
4939__be_cmd_set_logical_link_config(struct be_adapter *adapter,
4940 int link_state, int version, u8 domain)
4941{
4942 struct be_cmd_req_set_ll_link *req;
4943 struct be_mcc_wrb *wrb;
4944 u32 link_config = 0;
4945 int status;
4946
4947 mutex_lock(&adapter->mcc_lock);
4948
4949 wrb = wrb_from_mccq(adapter);
4950 if (!wrb) {
4951 status = -EBUSY;
4952 goto err;
4953 }
4954
4955 req = embedded_payload(wrb);
4956
4957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4958 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4959 sizeof(*req), wrb, NULL);
4960
4961 req->hdr.version = version;
4962 req->hdr.domain = domain;
4963
4964 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4965 link_state == IFLA_VF_LINK_STATE_AUTO)
4966 link_config |= PLINK_ENABLE;
4967
4968 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4969 link_config |= PLINK_TRACK;
4970
4971 req->link_config = cpu_to_le32(link_config);
4972
4973 status = be_mcc_notify_wait(adapter);
4974err:
4975 mutex_unlock(&adapter->mcc_lock);
4976 return status;
4977}
4978
4979int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4980 int link_state, u8 domain)
4981{
4982 int status;
4983
4984 if (BE2_chip(adapter))
4985 return -EOPNOTSUPP;
4986
4987 status = __be_cmd_set_logical_link_config(adapter, link_state,
4988 2, domain);
4989
4990 /* Version 2 of the command will not be recognized by older FW.
4991 * On such a failure issue version 1 of the command.
4992 */
4993 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4994 status = __be_cmd_set_logical_link_config(adapter, link_state,
4995 1, domain);
4996 return status;
4997}
4998
4999int be_cmd_set_features(struct be_adapter *adapter)
5000{
5001 struct be_cmd_resp_set_features *resp;
5002 struct be_cmd_req_set_features *req;
5003 struct be_mcc_wrb *wrb;
5004 int status;
5005
5006 if (mutex_lock_interruptible(&adapter->mcc_lock))
5007 return -1;
5008
5009 wrb = wrb_from_mccq(adapter);
5010 if (!wrb) {
5011 status = -EBUSY;
5012 goto err;
5013 }
5014
5015 req = embedded_payload(wrb);
5016
5017 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5018 OPCODE_COMMON_SET_FEATURES,
5019 sizeof(*req), wrb, NULL);
5020
5021 req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5022 req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5023 req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5024
5025 status = be_mcc_notify_wait(adapter);
5026 if (status)
5027 goto err;
5028
5029 resp = embedded_payload(wrb);
5030
5031 adapter->error_recovery.ue_to_poll_time =
5032 le16_to_cpu(resp->parameter.resp.ue2rp);
5033 adapter->error_recovery.ue_to_reset_time =
5034 le16_to_cpu(resp->parameter.resp.ue2sr);
5035 adapter->error_recovery.recovery_supported = true;
5036err:
5037 /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5038 * returns this error in older firmware versions
5039 */
5040 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5041 base_status(status) == MCC_STATUS_INVALID_LENGTH)
5042 dev_info(&adapter->pdev->dev,
5043 "Adapter does not support HW error recovery\n");
5044
5045 mutex_unlock(&adapter->mcc_lock);
5046 return status;
5047}
5048
5049int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
5050 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
5051{
5052 struct be_adapter *adapter = netdev_priv(netdev_handle);
5053 struct be_mcc_wrb *wrb;
5054 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
5055 struct be_cmd_req_hdr *req;
5056 struct be_cmd_resp_hdr *resp;
5057 int status;
5058
5059 mutex_lock(&adapter->mcc_lock);
5060
5061 wrb = wrb_from_mccq(adapter);
5062 if (!wrb) {
5063 status = -EBUSY;
5064 goto err;
5065 }
5066 req = embedded_payload(wrb);
5067 resp = embedded_payload(wrb);
5068
5069 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5070 hdr->opcode, wrb_payload_size, wrb, NULL);
5071 memcpy(req, wrb_payload, wrb_payload_size);
5072 be_dws_cpu_to_le(req, wrb_payload_size);
5073
5074 status = be_mcc_notify_wait(adapter);
5075 if (cmd_status)
5076 *cmd_status = (status & 0xffff);
5077 if (ext_status)
5078 *ext_status = 0;
5079 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5080 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5081err:
5082 mutex_unlock(&adapter->mcc_lock);
5083 return status;
5084}
5085EXPORT_SYMBOL(be_roce_mcc_cmd);
1/*
2 * Copyright (C) 2005 - 2015 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18#include <linux/module.h>
19#include "be.h"
20#include "be_cmds.h"
21
22char *be_misconfig_evt_port_state[] = {
23 "Physical Link is functional",
24 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
25 "Optics of two types installed – Remove one optic or install matching pair of optics.",
26 "Incompatible optics – Replace with compatible optics for card to function.",
27 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
28 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
29};
30
31static char *be_port_misconfig_evt_severity[] = {
32 "KERN_WARN",
33 "KERN_INFO",
34 "KERN_ERR",
35 "KERN_WARN"
36};
37
38static char *phy_state_oper_desc[] = {
39 "Link is non-operational",
40 "Link is operational",
41 ""
42};
43
44static struct be_cmd_priv_map cmd_priv_map[] = {
45 {
46 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
47 CMD_SUBSYSTEM_ETH,
48 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_GET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_COMMON_SET_FLOW_CONTROL,
59 CMD_SUBSYSTEM_COMMON,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_ETH_GET_PPORT_STATS,
65 CMD_SUBSYSTEM_ETH,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 },
69 {
70 OPCODE_COMMON_GET_PHY_DETAILS,
71 CMD_SUBSYSTEM_COMMON,
72 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
73 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
74 },
75 {
76 OPCODE_LOWLEVEL_HOST_DDR_DMA,
77 CMD_SUBSYSTEM_LOWLEVEL,
78 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
79 },
80 {
81 OPCODE_LOWLEVEL_LOOPBACK_TEST,
82 CMD_SUBSYSTEM_LOWLEVEL,
83 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
84 },
85 {
86 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
87 CMD_SUBSYSTEM_LOWLEVEL,
88 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
89 },
90};
91
92static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
93{
94 int i;
95 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
96 u32 cmd_privileges = adapter->cmd_privileges;
97
98 for (i = 0; i < num_entries; i++)
99 if (opcode == cmd_priv_map[i].opcode &&
100 subsystem == cmd_priv_map[i].subsystem)
101 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
102 return false;
103
104 return true;
105}
106
107static inline void *embedded_payload(struct be_mcc_wrb *wrb)
108{
109 return wrb->payload.embedded_payload;
110}
111
112static int be_mcc_notify(struct be_adapter *adapter)
113{
114 struct be_queue_info *mccq = &adapter->mcc_obj.q;
115 u32 val = 0;
116
117 if (be_check_error(adapter, BE_ERROR_ANY))
118 return -EIO;
119
120 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
121 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
122
123 wmb();
124 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
125
126 return 0;
127}
128
129/* To check if valid bit is set, check the entire word as we don't know
130 * the endianness of the data (old entry is host endian while a new entry is
131 * little endian) */
132static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
133{
134 u32 flags;
135
136 if (compl->flags != 0) {
137 flags = le32_to_cpu(compl->flags);
138 if (flags & CQE_FLAGS_VALID_MASK) {
139 compl->flags = flags;
140 return true;
141 }
142 }
143 return false;
144}
145
146/* Need to reset the entire word that houses the valid bit */
147static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
148{
149 compl->flags = 0;
150}
151
152static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
153{
154 unsigned long addr;
155
156 addr = tag1;
157 addr = ((addr << 16) << 16) | tag0;
158 return (void *)addr;
159}
160
161static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
162{
163 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
164 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
165 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
166 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
167 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
168 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
169 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
170 return true;
171 else
172 return false;
173}
174
175/* Place holder for all the async MCC cmds wherein the caller is not in a busy
176 * loop (has not issued be_mcc_notify_wait())
177 */
178static void be_async_cmd_process(struct be_adapter *adapter,
179 struct be_mcc_compl *compl,
180 struct be_cmd_resp_hdr *resp_hdr)
181{
182 enum mcc_base_status base_status = base_status(compl->status);
183 u8 opcode = 0, subsystem = 0;
184
185 if (resp_hdr) {
186 opcode = resp_hdr->opcode;
187 subsystem = resp_hdr->subsystem;
188 }
189
190 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
191 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
192 complete(&adapter->et_cmd_compl);
193 return;
194 }
195
196 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
197 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
198 complete(&adapter->et_cmd_compl);
199 return;
200 }
201
202 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
203 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
204 subsystem == CMD_SUBSYSTEM_COMMON) {
205 adapter->flash_status = compl->status;
206 complete(&adapter->et_cmd_compl);
207 return;
208 }
209
210 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
211 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
212 subsystem == CMD_SUBSYSTEM_ETH &&
213 base_status == MCC_STATUS_SUCCESS) {
214 be_parse_stats(adapter);
215 adapter->stats_cmd_sent = false;
216 return;
217 }
218
219 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
220 subsystem == CMD_SUBSYSTEM_COMMON) {
221 if (base_status == MCC_STATUS_SUCCESS) {
222 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
223 (void *)resp_hdr;
224 adapter->hwmon_info.be_on_die_temp =
225 resp->on_die_temperature;
226 } else {
227 adapter->be_get_temp_freq = 0;
228 adapter->hwmon_info.be_on_die_temp =
229 BE_INVALID_DIE_TEMP;
230 }
231 return;
232 }
233}
234
235static int be_mcc_compl_process(struct be_adapter *adapter,
236 struct be_mcc_compl *compl)
237{
238 enum mcc_base_status base_status;
239 enum mcc_addl_status addl_status;
240 struct be_cmd_resp_hdr *resp_hdr;
241 u8 opcode = 0, subsystem = 0;
242
243 /* Just swap the status to host endian; mcc tag is opaquely copied
244 * from mcc_wrb */
245 be_dws_le_to_cpu(compl, 4);
246
247 base_status = base_status(compl->status);
248 addl_status = addl_status(compl->status);
249
250 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
251 if (resp_hdr) {
252 opcode = resp_hdr->opcode;
253 subsystem = resp_hdr->subsystem;
254 }
255
256 be_async_cmd_process(adapter, compl, resp_hdr);
257
258 if (base_status != MCC_STATUS_SUCCESS &&
259 !be_skip_err_log(opcode, base_status, addl_status)) {
260 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
261 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
262 dev_warn(&adapter->pdev->dev,
263 "VF is not privileged to issue opcode %d-%d\n",
264 opcode, subsystem);
265 } else {
266 dev_err(&adapter->pdev->dev,
267 "opcode %d-%d failed:status %d-%d\n",
268 opcode, subsystem, base_status, addl_status);
269 }
270 }
271 return compl->status;
272}
273
274/* Link state evt is a string of bytes; no need for endian swapping */
275static void be_async_link_state_process(struct be_adapter *adapter,
276 struct be_mcc_compl *compl)
277{
278 struct be_async_event_link_state *evt =
279 (struct be_async_event_link_state *)compl;
280
281 /* When link status changes, link speed must be re-queried from FW */
282 adapter->phy.link_speed = -1;
283
284 /* On BEx the FW does not send a separate link status
285 * notification for physical and logical link.
286 * On other chips just process the logical link
287 * status notification
288 */
289 if (!BEx_chip(adapter) &&
290 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
291 return;
292
293 /* For the initial link status do not rely on the ASYNC event as
294 * it may not be received in some cases.
295 */
296 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
297 be_link_status_update(adapter,
298 evt->port_link_status & LINK_STATUS_MASK);
299}
300
301static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
302 struct be_mcc_compl *compl)
303{
304 struct be_async_event_misconfig_port *evt =
305 (struct be_async_event_misconfig_port *)compl;
306 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
307 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
308 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
309 struct device *dev = &adapter->pdev->dev;
310 u8 msg_severity = DEFAULT_MSG_SEVERITY;
311 u8 phy_state_info;
312 u8 new_phy_state;
313
314 new_phy_state =
315 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
316
317 if (new_phy_state == adapter->phy_state)
318 return;
319
320 adapter->phy_state = new_phy_state;
321
322 /* for older fw that doesn't populate link effect data */
323 if (!sfp_misconfig_evt_word2)
324 goto log_message;
325
326 phy_state_info =
327 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
328
329 if (phy_state_info & PHY_STATE_INFO_VALID) {
330 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
331
332 if (be_phy_unqualified(new_phy_state))
333 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
334 }
335
336log_message:
337 /* Log an error message that would allow a user to determine
338 * whether the SFPs have an issue
339 */
340 if (be_phy_state_unknown(new_phy_state))
341 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
342 "Port %c: Unrecognized Optics state: 0x%x. %s",
343 adapter->port_name,
344 new_phy_state,
345 phy_state_oper_desc[phy_oper_state]);
346 else
347 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
348 "Port %c: %s %s",
349 adapter->port_name,
350 be_misconfig_evt_port_state[new_phy_state],
351 phy_state_oper_desc[phy_oper_state]);
352
353 /* Log Vendor name and part no. if a misconfigured SFP is detected */
354 if (be_phy_misconfigured(new_phy_state))
355 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
356}
357
358/* Grp5 CoS Priority evt */
359static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
360 struct be_mcc_compl *compl)
361{
362 struct be_async_event_grp5_cos_priority *evt =
363 (struct be_async_event_grp5_cos_priority *)compl;
364
365 if (evt->valid) {
366 adapter->vlan_prio_bmap = evt->available_priority_bmap;
367 adapter->recommended_prio_bits =
368 evt->reco_default_priority << VLAN_PRIO_SHIFT;
369 }
370}
371
372/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
373static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
374 struct be_mcc_compl *compl)
375{
376 struct be_async_event_grp5_qos_link_speed *evt =
377 (struct be_async_event_grp5_qos_link_speed *)compl;
378
379 if (adapter->phy.link_speed >= 0 &&
380 evt->physical_port == adapter->port_num)
381 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
382}
383
384/*Grp5 PVID evt*/
385static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
386 struct be_mcc_compl *compl)
387{
388 struct be_async_event_grp5_pvid_state *evt =
389 (struct be_async_event_grp5_pvid_state *)compl;
390
391 if (evt->enabled) {
392 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
393 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
394 } else {
395 adapter->pvid = 0;
396 }
397}
398
399#define MGMT_ENABLE_MASK 0x4
400static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
401 struct be_mcc_compl *compl)
402{
403 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
404 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
405
406 if (evt_dw1 & MGMT_ENABLE_MASK) {
407 adapter->flags |= BE_FLAGS_OS2BMC;
408 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
409 } else {
410 adapter->flags &= ~BE_FLAGS_OS2BMC;
411 }
412}
413
414static void be_async_grp5_evt_process(struct be_adapter *adapter,
415 struct be_mcc_compl *compl)
416{
417 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
418 ASYNC_EVENT_TYPE_MASK;
419
420 switch (event_type) {
421 case ASYNC_EVENT_COS_PRIORITY:
422 be_async_grp5_cos_priority_process(adapter, compl);
423 break;
424 case ASYNC_EVENT_QOS_SPEED:
425 be_async_grp5_qos_speed_process(adapter, compl);
426 break;
427 case ASYNC_EVENT_PVID_STATE:
428 be_async_grp5_pvid_state_process(adapter, compl);
429 break;
430 /* Async event to disable/enable os2bmc and/or mac-learning */
431 case ASYNC_EVENT_FW_CONTROL:
432 be_async_grp5_fw_control_process(adapter, compl);
433 break;
434 default:
435 break;
436 }
437}
438
439static void be_async_dbg_evt_process(struct be_adapter *adapter,
440 struct be_mcc_compl *cmp)
441{
442 u8 event_type = 0;
443 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
444
445 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
446 ASYNC_EVENT_TYPE_MASK;
447
448 switch (event_type) {
449 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
450 if (evt->valid)
451 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
452 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
453 break;
454 default:
455 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
456 event_type);
457 break;
458 }
459}
460
461static void be_async_sliport_evt_process(struct be_adapter *adapter,
462 struct be_mcc_compl *cmp)
463{
464 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
465 ASYNC_EVENT_TYPE_MASK;
466
467 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
468 be_async_port_misconfig_event_process(adapter, cmp);
469}
470
471static inline bool is_link_state_evt(u32 flags)
472{
473 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
474 ASYNC_EVENT_CODE_LINK_STATE;
475}
476
477static inline bool is_grp5_evt(u32 flags)
478{
479 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
480 ASYNC_EVENT_CODE_GRP_5;
481}
482
483static inline bool is_dbg_evt(u32 flags)
484{
485 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
486 ASYNC_EVENT_CODE_QNQ;
487}
488
489static inline bool is_sliport_evt(u32 flags)
490{
491 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
492 ASYNC_EVENT_CODE_SLIPORT;
493}
494
495static void be_mcc_event_process(struct be_adapter *adapter,
496 struct be_mcc_compl *compl)
497{
498 if (is_link_state_evt(compl->flags))
499 be_async_link_state_process(adapter, compl);
500 else if (is_grp5_evt(compl->flags))
501 be_async_grp5_evt_process(adapter, compl);
502 else if (is_dbg_evt(compl->flags))
503 be_async_dbg_evt_process(adapter, compl);
504 else if (is_sliport_evt(compl->flags))
505 be_async_sliport_evt_process(adapter, compl);
506}
507
508static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
509{
510 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
511 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
512
513 if (be_mcc_compl_is_new(compl)) {
514 queue_tail_inc(mcc_cq);
515 return compl;
516 }
517 return NULL;
518}
519
520void be_async_mcc_enable(struct be_adapter *adapter)
521{
522 spin_lock_bh(&adapter->mcc_cq_lock);
523
524 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
525 adapter->mcc_obj.rearm_cq = true;
526
527 spin_unlock_bh(&adapter->mcc_cq_lock);
528}
529
530void be_async_mcc_disable(struct be_adapter *adapter)
531{
532 spin_lock_bh(&adapter->mcc_cq_lock);
533
534 adapter->mcc_obj.rearm_cq = false;
535 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
536
537 spin_unlock_bh(&adapter->mcc_cq_lock);
538}
539
540int be_process_mcc(struct be_adapter *adapter)
541{
542 struct be_mcc_compl *compl;
543 int num = 0, status = 0;
544 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
545
546 spin_lock(&adapter->mcc_cq_lock);
547
548 while ((compl = be_mcc_compl_get(adapter))) {
549 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
550 be_mcc_event_process(adapter, compl);
551 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
552 status = be_mcc_compl_process(adapter, compl);
553 atomic_dec(&mcc_obj->q.used);
554 }
555 be_mcc_compl_use(compl);
556 num++;
557 }
558
559 if (num)
560 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
561
562 spin_unlock(&adapter->mcc_cq_lock);
563 return status;
564}
565
566/* Wait till no more pending mcc requests are present */
567static int be_mcc_wait_compl(struct be_adapter *adapter)
568{
569#define mcc_timeout 120000 /* 12s timeout */
570 int i, status = 0;
571 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
572
573 for (i = 0; i < mcc_timeout; i++) {
574 if (be_check_error(adapter, BE_ERROR_ANY))
575 return -EIO;
576
577 local_bh_disable();
578 status = be_process_mcc(adapter);
579 local_bh_enable();
580
581 if (atomic_read(&mcc_obj->q.used) == 0)
582 break;
583 udelay(100);
584 }
585 if (i == mcc_timeout) {
586 dev_err(&adapter->pdev->dev, "FW not responding\n");
587 be_set_error(adapter, BE_ERROR_FW);
588 return -EIO;
589 }
590 return status;
591}
592
593/* Notify MCC requests and wait for completion */
594static int be_mcc_notify_wait(struct be_adapter *adapter)
595{
596 int status;
597 struct be_mcc_wrb *wrb;
598 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
599 u32 index = mcc_obj->q.head;
600 struct be_cmd_resp_hdr *resp;
601
602 index_dec(&index, mcc_obj->q.len);
603 wrb = queue_index_node(&mcc_obj->q, index);
604
605 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
606
607 status = be_mcc_notify(adapter);
608 if (status)
609 goto out;
610
611 status = be_mcc_wait_compl(adapter);
612 if (status == -EIO)
613 goto out;
614
615 status = (resp->base_status |
616 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
617 CQE_ADDL_STATUS_SHIFT));
618out:
619 return status;
620}
621
622static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
623{
624 int msecs = 0;
625 u32 ready;
626
627 do {
628 if (be_check_error(adapter, BE_ERROR_ANY))
629 return -EIO;
630
631 ready = ioread32(db);
632 if (ready == 0xffffffff)
633 return -1;
634
635 ready &= MPU_MAILBOX_DB_RDY_MASK;
636 if (ready)
637 break;
638
639 if (msecs > 4000) {
640 dev_err(&adapter->pdev->dev, "FW not responding\n");
641 be_set_error(adapter, BE_ERROR_FW);
642 be_detect_error(adapter);
643 return -1;
644 }
645
646 msleep(1);
647 msecs++;
648 } while (true);
649
650 return 0;
651}
652
653/*
654 * Insert the mailbox address into the doorbell in two steps
655 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
656 */
657static int be_mbox_notify_wait(struct be_adapter *adapter)
658{
659 int status;
660 u32 val = 0;
661 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
662 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
663 struct be_mcc_mailbox *mbox = mbox_mem->va;
664 struct be_mcc_compl *compl = &mbox->compl;
665
666 /* wait for ready to be set */
667 status = be_mbox_db_ready_wait(adapter, db);
668 if (status != 0)
669 return status;
670
671 val |= MPU_MAILBOX_DB_HI_MASK;
672 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
673 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
674 iowrite32(val, db);
675
676 /* wait for ready to be set */
677 status = be_mbox_db_ready_wait(adapter, db);
678 if (status != 0)
679 return status;
680
681 val = 0;
682 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
683 val |= (u32)(mbox_mem->dma >> 4) << 2;
684 iowrite32(val, db);
685
686 status = be_mbox_db_ready_wait(adapter, db);
687 if (status != 0)
688 return status;
689
690 /* A cq entry has been made now */
691 if (be_mcc_compl_is_new(compl)) {
692 status = be_mcc_compl_process(adapter, &mbox->compl);
693 be_mcc_compl_use(compl);
694 if (status)
695 return status;
696 } else {
697 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
698 return -1;
699 }
700 return 0;
701}
702
703static u16 be_POST_stage_get(struct be_adapter *adapter)
704{
705 u32 sem;
706
707 if (BEx_chip(adapter))
708 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
709 else
710 pci_read_config_dword(adapter->pdev,
711 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
712
713 return sem & POST_STAGE_MASK;
714}
715
716static int lancer_wait_ready(struct be_adapter *adapter)
717{
718#define SLIPORT_READY_TIMEOUT 30
719 u32 sliport_status;
720 int i;
721
722 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
723 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
724 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
725 return 0;
726
727 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
728 !(sliport_status & SLIPORT_STATUS_RN_MASK))
729 return -EIO;
730
731 msleep(1000);
732 }
733
734 return sliport_status ? : -1;
735}
736
737int be_fw_wait_ready(struct be_adapter *adapter)
738{
739 u16 stage;
740 int status, timeout = 0;
741 struct device *dev = &adapter->pdev->dev;
742
743 if (lancer_chip(adapter)) {
744 status = lancer_wait_ready(adapter);
745 if (status) {
746 stage = status;
747 goto err;
748 }
749 return 0;
750 }
751
752 do {
753 /* There's no means to poll POST state on BE2/3 VFs */
754 if (BEx_chip(adapter) && be_virtfn(adapter))
755 return 0;
756
757 stage = be_POST_stage_get(adapter);
758 if (stage == POST_STAGE_ARMFW_RDY)
759 return 0;
760
761 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
762 if (msleep_interruptible(2000)) {
763 dev_err(dev, "Waiting for POST aborted\n");
764 return -EINTR;
765 }
766 timeout += 2;
767 } while (timeout < 60);
768
769err:
770 dev_err(dev, "POST timeout; stage=%#x\n", stage);
771 return -ETIMEDOUT;
772}
773
774static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
775{
776 return &wrb->payload.sgl[0];
777}
778
779static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
780{
781 wrb->tag0 = addr & 0xFFFFFFFF;
782 wrb->tag1 = upper_32_bits(addr);
783}
784
785/* Don't touch the hdr after it's prepared */
786/* mem will be NULL for embedded commands */
787static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
788 u8 subsystem, u8 opcode, int cmd_len,
789 struct be_mcc_wrb *wrb,
790 struct be_dma_mem *mem)
791{
792 struct be_sge *sge;
793
794 req_hdr->opcode = opcode;
795 req_hdr->subsystem = subsystem;
796 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
797 req_hdr->version = 0;
798 fill_wrb_tags(wrb, (ulong) req_hdr);
799 wrb->payload_length = cmd_len;
800 if (mem) {
801 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
802 MCC_WRB_SGE_CNT_SHIFT;
803 sge = nonembedded_sgl(wrb);
804 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
805 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
806 sge->len = cpu_to_le32(mem->size);
807 } else
808 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
809 be_dws_cpu_to_le(wrb, 8);
810}
811
812static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
813 struct be_dma_mem *mem)
814{
815 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
816 u64 dma = (u64)mem->dma;
817
818 for (i = 0; i < buf_pages; i++) {
819 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
820 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
821 dma += PAGE_SIZE_4K;
822 }
823}
824
825static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
826{
827 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
828 struct be_mcc_wrb *wrb
829 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
830 memset(wrb, 0, sizeof(*wrb));
831 return wrb;
832}
833
834static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
835{
836 struct be_queue_info *mccq = &adapter->mcc_obj.q;
837 struct be_mcc_wrb *wrb;
838
839 if (!mccq->created)
840 return NULL;
841
842 if (atomic_read(&mccq->used) >= mccq->len)
843 return NULL;
844
845 wrb = queue_head_node(mccq);
846 queue_head_inc(mccq);
847 atomic_inc(&mccq->used);
848 memset(wrb, 0, sizeof(*wrb));
849 return wrb;
850}
851
852static bool use_mcc(struct be_adapter *adapter)
853{
854 return adapter->mcc_obj.q.created;
855}
856
857/* Must be used only in process context */
858static int be_cmd_lock(struct be_adapter *adapter)
859{
860 if (use_mcc(adapter)) {
861 spin_lock_bh(&adapter->mcc_lock);
862 return 0;
863 } else {
864 return mutex_lock_interruptible(&adapter->mbox_lock);
865 }
866}
867
868/* Must be used only in process context */
869static void be_cmd_unlock(struct be_adapter *adapter)
870{
871 if (use_mcc(adapter))
872 spin_unlock_bh(&adapter->mcc_lock);
873 else
874 return mutex_unlock(&adapter->mbox_lock);
875}
876
877static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
878 struct be_mcc_wrb *wrb)
879{
880 struct be_mcc_wrb *dest_wrb;
881
882 if (use_mcc(adapter)) {
883 dest_wrb = wrb_from_mccq(adapter);
884 if (!dest_wrb)
885 return NULL;
886 } else {
887 dest_wrb = wrb_from_mbox(adapter);
888 }
889
890 memcpy(dest_wrb, wrb, sizeof(*wrb));
891 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
892 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
893
894 return dest_wrb;
895}
896
897/* Must be used only in process context */
898static int be_cmd_notify_wait(struct be_adapter *adapter,
899 struct be_mcc_wrb *wrb)
900{
901 struct be_mcc_wrb *dest_wrb;
902 int status;
903
904 status = be_cmd_lock(adapter);
905 if (status)
906 return status;
907
908 dest_wrb = be_cmd_copy(adapter, wrb);
909 if (!dest_wrb) {
910 status = -EBUSY;
911 goto unlock;
912 }
913
914 if (use_mcc(adapter))
915 status = be_mcc_notify_wait(adapter);
916 else
917 status = be_mbox_notify_wait(adapter);
918
919 if (!status)
920 memcpy(wrb, dest_wrb, sizeof(*wrb));
921
922unlock:
923 be_cmd_unlock(adapter);
924 return status;
925}
926
927/* Tell fw we're about to start firing cmds by writing a
928 * special pattern across the wrb hdr; uses mbox
929 */
930int be_cmd_fw_init(struct be_adapter *adapter)
931{
932 u8 *wrb;
933 int status;
934
935 if (lancer_chip(adapter))
936 return 0;
937
938 if (mutex_lock_interruptible(&adapter->mbox_lock))
939 return -1;
940
941 wrb = (u8 *)wrb_from_mbox(adapter);
942 *wrb++ = 0xFF;
943 *wrb++ = 0x12;
944 *wrb++ = 0x34;
945 *wrb++ = 0xFF;
946 *wrb++ = 0xFF;
947 *wrb++ = 0x56;
948 *wrb++ = 0x78;
949 *wrb = 0xFF;
950
951 status = be_mbox_notify_wait(adapter);
952
953 mutex_unlock(&adapter->mbox_lock);
954 return status;
955}
956
957/* Tell fw we're done with firing cmds by writing a
958 * special pattern across the wrb hdr; uses mbox
959 */
960int be_cmd_fw_clean(struct be_adapter *adapter)
961{
962 u8 *wrb;
963 int status;
964
965 if (lancer_chip(adapter))
966 return 0;
967
968 if (mutex_lock_interruptible(&adapter->mbox_lock))
969 return -1;
970
971 wrb = (u8 *)wrb_from_mbox(adapter);
972 *wrb++ = 0xFF;
973 *wrb++ = 0xAA;
974 *wrb++ = 0xBB;
975 *wrb++ = 0xFF;
976 *wrb++ = 0xFF;
977 *wrb++ = 0xCC;
978 *wrb++ = 0xDD;
979 *wrb = 0xFF;
980
981 status = be_mbox_notify_wait(adapter);
982
983 mutex_unlock(&adapter->mbox_lock);
984 return status;
985}
986
987int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
988{
989 struct be_mcc_wrb *wrb;
990 struct be_cmd_req_eq_create *req;
991 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
992 int status, ver = 0;
993
994 if (mutex_lock_interruptible(&adapter->mbox_lock))
995 return -1;
996
997 wrb = wrb_from_mbox(adapter);
998 req = embedded_payload(wrb);
999
1000 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1001 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1002 NULL);
1003
1004 /* Support for EQ_CREATEv2 available only SH-R onwards */
1005 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1006 ver = 2;
1007
1008 req->hdr.version = ver;
1009 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1010
1011 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1012 /* 4byte eqe*/
1013 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1014 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1015 __ilog2_u32(eqo->q.len / 256));
1016 be_dws_cpu_to_le(req->context, sizeof(req->context));
1017
1018 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1019
1020 status = be_mbox_notify_wait(adapter);
1021 if (!status) {
1022 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1023
1024 eqo->q.id = le16_to_cpu(resp->eq_id);
1025 eqo->msix_idx =
1026 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1027 eqo->q.created = true;
1028 }
1029
1030 mutex_unlock(&adapter->mbox_lock);
1031 return status;
1032}
1033
1034/* Use MCC */
1035int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1036 bool permanent, u32 if_handle, u32 pmac_id)
1037{
1038 struct be_mcc_wrb *wrb;
1039 struct be_cmd_req_mac_query *req;
1040 int status;
1041
1042 spin_lock_bh(&adapter->mcc_lock);
1043
1044 wrb = wrb_from_mccq(adapter);
1045 if (!wrb) {
1046 status = -EBUSY;
1047 goto err;
1048 }
1049 req = embedded_payload(wrb);
1050
1051 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1052 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1053 NULL);
1054 req->type = MAC_ADDRESS_TYPE_NETWORK;
1055 if (permanent) {
1056 req->permanent = 1;
1057 } else {
1058 req->if_id = cpu_to_le16((u16)if_handle);
1059 req->pmac_id = cpu_to_le32(pmac_id);
1060 req->permanent = 0;
1061 }
1062
1063 status = be_mcc_notify_wait(adapter);
1064 if (!status) {
1065 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1066
1067 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1068 }
1069
1070err:
1071 spin_unlock_bh(&adapter->mcc_lock);
1072 return status;
1073}
1074
1075/* Uses synchronous MCCQ */
1076int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1077 u32 if_id, u32 *pmac_id, u32 domain)
1078{
1079 struct be_mcc_wrb *wrb;
1080 struct be_cmd_req_pmac_add *req;
1081 int status;
1082
1083 spin_lock_bh(&adapter->mcc_lock);
1084
1085 wrb = wrb_from_mccq(adapter);
1086 if (!wrb) {
1087 status = -EBUSY;
1088 goto err;
1089 }
1090 req = embedded_payload(wrb);
1091
1092 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1093 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1094 NULL);
1095
1096 req->hdr.domain = domain;
1097 req->if_id = cpu_to_le32(if_id);
1098 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1099
1100 status = be_mcc_notify_wait(adapter);
1101 if (!status) {
1102 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1103
1104 *pmac_id = le32_to_cpu(resp->pmac_id);
1105 }
1106
1107err:
1108 spin_unlock_bh(&adapter->mcc_lock);
1109
1110 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1111 status = -EPERM;
1112
1113 return status;
1114}
1115
1116/* Uses synchronous MCCQ */
1117int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1118{
1119 struct be_mcc_wrb *wrb;
1120 struct be_cmd_req_pmac_del *req;
1121 int status;
1122
1123 if (pmac_id == -1)
1124 return 0;
1125
1126 spin_lock_bh(&adapter->mcc_lock);
1127
1128 wrb = wrb_from_mccq(adapter);
1129 if (!wrb) {
1130 status = -EBUSY;
1131 goto err;
1132 }
1133 req = embedded_payload(wrb);
1134
1135 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1136 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1137 wrb, NULL);
1138
1139 req->hdr.domain = dom;
1140 req->if_id = cpu_to_le32(if_id);
1141 req->pmac_id = cpu_to_le32(pmac_id);
1142
1143 status = be_mcc_notify_wait(adapter);
1144
1145err:
1146 spin_unlock_bh(&adapter->mcc_lock);
1147 return status;
1148}
1149
1150/* Uses Mbox */
1151int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1152 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1153{
1154 struct be_mcc_wrb *wrb;
1155 struct be_cmd_req_cq_create *req;
1156 struct be_dma_mem *q_mem = &cq->dma_mem;
1157 void *ctxt;
1158 int status;
1159
1160 if (mutex_lock_interruptible(&adapter->mbox_lock))
1161 return -1;
1162
1163 wrb = wrb_from_mbox(adapter);
1164 req = embedded_payload(wrb);
1165 ctxt = &req->context;
1166
1167 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1168 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1169 NULL);
1170
1171 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1172
1173 if (BEx_chip(adapter)) {
1174 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1175 coalesce_wm);
1176 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1177 ctxt, no_delay);
1178 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1179 __ilog2_u32(cq->len / 256));
1180 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1181 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1182 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1183 } else {
1184 req->hdr.version = 2;
1185 req->page_size = 1; /* 1 for 4K */
1186
1187 /* coalesce-wm field in this cmd is not relevant to Lancer.
1188 * Lancer uses COMMON_MODIFY_CQ to set this field
1189 */
1190 if (!lancer_chip(adapter))
1191 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1192 ctxt, coalesce_wm);
1193 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1194 no_delay);
1195 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1196 __ilog2_u32(cq->len / 256));
1197 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1198 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1199 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1200 }
1201
1202 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1203
1204 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1205
1206 status = be_mbox_notify_wait(adapter);
1207 if (!status) {
1208 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1209
1210 cq->id = le16_to_cpu(resp->cq_id);
1211 cq->created = true;
1212 }
1213
1214 mutex_unlock(&adapter->mbox_lock);
1215
1216 return status;
1217}
1218
1219static u32 be_encoded_q_len(int q_len)
1220{
1221 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1222
1223 if (len_encoded == 16)
1224 len_encoded = 0;
1225 return len_encoded;
1226}
1227
1228static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1229 struct be_queue_info *mccq,
1230 struct be_queue_info *cq)
1231{
1232 struct be_mcc_wrb *wrb;
1233 struct be_cmd_req_mcc_ext_create *req;
1234 struct be_dma_mem *q_mem = &mccq->dma_mem;
1235 void *ctxt;
1236 int status;
1237
1238 if (mutex_lock_interruptible(&adapter->mbox_lock))
1239 return -1;
1240
1241 wrb = wrb_from_mbox(adapter);
1242 req = embedded_payload(wrb);
1243 ctxt = &req->context;
1244
1245 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1246 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1247 NULL);
1248
1249 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1250 if (BEx_chip(adapter)) {
1251 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1252 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1253 be_encoded_q_len(mccq->len));
1254 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1255 } else {
1256 req->hdr.version = 1;
1257 req->cq_id = cpu_to_le16(cq->id);
1258
1259 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1260 be_encoded_q_len(mccq->len));
1261 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1262 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1263 ctxt, cq->id);
1264 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1265 ctxt, 1);
1266 }
1267
1268 /* Subscribe to Link State, Sliport Event and Group 5 Events
1269 * (bits 1, 5 and 17 set)
1270 */
1271 req->async_event_bitmap[0] =
1272 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1273 BIT(ASYNC_EVENT_CODE_GRP_5) |
1274 BIT(ASYNC_EVENT_CODE_QNQ) |
1275 BIT(ASYNC_EVENT_CODE_SLIPORT));
1276
1277 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1278
1279 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1280
1281 status = be_mbox_notify_wait(adapter);
1282 if (!status) {
1283 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1284
1285 mccq->id = le16_to_cpu(resp->id);
1286 mccq->created = true;
1287 }
1288 mutex_unlock(&adapter->mbox_lock);
1289
1290 return status;
1291}
1292
1293static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1294 struct be_queue_info *mccq,
1295 struct be_queue_info *cq)
1296{
1297 struct be_mcc_wrb *wrb;
1298 struct be_cmd_req_mcc_create *req;
1299 struct be_dma_mem *q_mem = &mccq->dma_mem;
1300 void *ctxt;
1301 int status;
1302
1303 if (mutex_lock_interruptible(&adapter->mbox_lock))
1304 return -1;
1305
1306 wrb = wrb_from_mbox(adapter);
1307 req = embedded_payload(wrb);
1308 ctxt = &req->context;
1309
1310 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1311 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1312 NULL);
1313
1314 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1315
1316 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1317 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1318 be_encoded_q_len(mccq->len));
1319 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1320
1321 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1322
1323 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1324
1325 status = be_mbox_notify_wait(adapter);
1326 if (!status) {
1327 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1328
1329 mccq->id = le16_to_cpu(resp->id);
1330 mccq->created = true;
1331 }
1332
1333 mutex_unlock(&adapter->mbox_lock);
1334 return status;
1335}
1336
1337int be_cmd_mccq_create(struct be_adapter *adapter,
1338 struct be_queue_info *mccq, struct be_queue_info *cq)
1339{
1340 int status;
1341
1342 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1343 if (status && BEx_chip(adapter)) {
1344 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1345 "or newer to avoid conflicting priorities between NIC "
1346 "and FCoE traffic");
1347 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1348 }
1349 return status;
1350}
1351
1352int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1353{
1354 struct be_mcc_wrb wrb = {0};
1355 struct be_cmd_req_eth_tx_create *req;
1356 struct be_queue_info *txq = &txo->q;
1357 struct be_queue_info *cq = &txo->cq;
1358 struct be_dma_mem *q_mem = &txq->dma_mem;
1359 int status, ver = 0;
1360
1361 req = embedded_payload(&wrb);
1362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1363 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1364
1365 if (lancer_chip(adapter)) {
1366 req->hdr.version = 1;
1367 } else if (BEx_chip(adapter)) {
1368 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1369 req->hdr.version = 2;
1370 } else { /* For SH */
1371 req->hdr.version = 2;
1372 }
1373
1374 if (req->hdr.version > 0)
1375 req->if_id = cpu_to_le16(adapter->if_handle);
1376 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1377 req->ulp_num = BE_ULP1_NUM;
1378 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1379 req->cq_id = cpu_to_le16(cq->id);
1380 req->queue_size = be_encoded_q_len(txq->len);
1381 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1382 ver = req->hdr.version;
1383
1384 status = be_cmd_notify_wait(adapter, &wrb);
1385 if (!status) {
1386 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1387
1388 txq->id = le16_to_cpu(resp->cid);
1389 if (ver == 2)
1390 txo->db_offset = le32_to_cpu(resp->db_offset);
1391 else
1392 txo->db_offset = DB_TXULP1_OFFSET;
1393 txq->created = true;
1394 }
1395
1396 return status;
1397}
1398
1399/* Uses MCC */
1400int be_cmd_rxq_create(struct be_adapter *adapter,
1401 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1402 u32 if_id, u32 rss, u8 *rss_id)
1403{
1404 struct be_mcc_wrb *wrb;
1405 struct be_cmd_req_eth_rx_create *req;
1406 struct be_dma_mem *q_mem = &rxq->dma_mem;
1407 int status;
1408
1409 spin_lock_bh(&adapter->mcc_lock);
1410
1411 wrb = wrb_from_mccq(adapter);
1412 if (!wrb) {
1413 status = -EBUSY;
1414 goto err;
1415 }
1416 req = embedded_payload(wrb);
1417
1418 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1419 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1420
1421 req->cq_id = cpu_to_le16(cq_id);
1422 req->frag_size = fls(frag_size) - 1;
1423 req->num_pages = 2;
1424 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1425 req->interface_id = cpu_to_le32(if_id);
1426 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1427 req->rss_queue = cpu_to_le32(rss);
1428
1429 status = be_mcc_notify_wait(adapter);
1430 if (!status) {
1431 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1432
1433 rxq->id = le16_to_cpu(resp->id);
1434 rxq->created = true;
1435 *rss_id = resp->rss_id;
1436 }
1437
1438err:
1439 spin_unlock_bh(&adapter->mcc_lock);
1440 return status;
1441}
1442
1443/* Generic destroyer function for all types of queues
1444 * Uses Mbox
1445 */
1446int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1447 int queue_type)
1448{
1449 struct be_mcc_wrb *wrb;
1450 struct be_cmd_req_q_destroy *req;
1451 u8 subsys = 0, opcode = 0;
1452 int status;
1453
1454 if (mutex_lock_interruptible(&adapter->mbox_lock))
1455 return -1;
1456
1457 wrb = wrb_from_mbox(adapter);
1458 req = embedded_payload(wrb);
1459
1460 switch (queue_type) {
1461 case QTYPE_EQ:
1462 subsys = CMD_SUBSYSTEM_COMMON;
1463 opcode = OPCODE_COMMON_EQ_DESTROY;
1464 break;
1465 case QTYPE_CQ:
1466 subsys = CMD_SUBSYSTEM_COMMON;
1467 opcode = OPCODE_COMMON_CQ_DESTROY;
1468 break;
1469 case QTYPE_TXQ:
1470 subsys = CMD_SUBSYSTEM_ETH;
1471 opcode = OPCODE_ETH_TX_DESTROY;
1472 break;
1473 case QTYPE_RXQ:
1474 subsys = CMD_SUBSYSTEM_ETH;
1475 opcode = OPCODE_ETH_RX_DESTROY;
1476 break;
1477 case QTYPE_MCCQ:
1478 subsys = CMD_SUBSYSTEM_COMMON;
1479 opcode = OPCODE_COMMON_MCC_DESTROY;
1480 break;
1481 default:
1482 BUG();
1483 }
1484
1485 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1486 NULL);
1487 req->id = cpu_to_le16(q->id);
1488
1489 status = be_mbox_notify_wait(adapter);
1490 q->created = false;
1491
1492 mutex_unlock(&adapter->mbox_lock);
1493 return status;
1494}
1495
1496/* Uses MCC */
1497int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1498{
1499 struct be_mcc_wrb *wrb;
1500 struct be_cmd_req_q_destroy *req;
1501 int status;
1502
1503 spin_lock_bh(&adapter->mcc_lock);
1504
1505 wrb = wrb_from_mccq(adapter);
1506 if (!wrb) {
1507 status = -EBUSY;
1508 goto err;
1509 }
1510 req = embedded_payload(wrb);
1511
1512 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1513 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1514 req->id = cpu_to_le16(q->id);
1515
1516 status = be_mcc_notify_wait(adapter);
1517 q->created = false;
1518
1519err:
1520 spin_unlock_bh(&adapter->mcc_lock);
1521 return status;
1522}
1523
1524/* Create an rx filtering policy configuration on an i/f
1525 * Will use MBOX only if MCCQ has not been created.
1526 */
1527int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1528 u32 *if_handle, u32 domain)
1529{
1530 struct be_mcc_wrb wrb = {0};
1531 struct be_cmd_req_if_create *req;
1532 int status;
1533
1534 req = embedded_payload(&wrb);
1535 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1536 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1537 sizeof(*req), &wrb, NULL);
1538 req->hdr.domain = domain;
1539 req->capability_flags = cpu_to_le32(cap_flags);
1540 req->enable_flags = cpu_to_le32(en_flags);
1541 req->pmac_invalid = true;
1542
1543 status = be_cmd_notify_wait(adapter, &wrb);
1544 if (!status) {
1545 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1546
1547 *if_handle = le32_to_cpu(resp->interface_id);
1548
1549 /* Hack to retrieve VF's pmac-id on BE3 */
1550 if (BE3_chip(adapter) && be_virtfn(adapter))
1551 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1552 }
1553 return status;
1554}
1555
1556/* Uses MCCQ if available else MBOX */
1557int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1558{
1559 struct be_mcc_wrb wrb = {0};
1560 struct be_cmd_req_if_destroy *req;
1561 int status;
1562
1563 if (interface_id == -1)
1564 return 0;
1565
1566 req = embedded_payload(&wrb);
1567
1568 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1569 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1570 sizeof(*req), &wrb, NULL);
1571 req->hdr.domain = domain;
1572 req->interface_id = cpu_to_le32(interface_id);
1573
1574 status = be_cmd_notify_wait(adapter, &wrb);
1575 return status;
1576}
1577
1578/* Get stats is a non embedded command: the request is not embedded inside
1579 * WRB but is a separate dma memory block
1580 * Uses asynchronous MCC
1581 */
1582int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1583{
1584 struct be_mcc_wrb *wrb;
1585 struct be_cmd_req_hdr *hdr;
1586 int status = 0;
1587
1588 spin_lock_bh(&adapter->mcc_lock);
1589
1590 wrb = wrb_from_mccq(adapter);
1591 if (!wrb) {
1592 status = -EBUSY;
1593 goto err;
1594 }
1595 hdr = nonemb_cmd->va;
1596
1597 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1598 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1599 nonemb_cmd);
1600
1601 /* version 1 of the cmd is not supported only by BE2 */
1602 if (BE2_chip(adapter))
1603 hdr->version = 0;
1604 if (BE3_chip(adapter) || lancer_chip(adapter))
1605 hdr->version = 1;
1606 else
1607 hdr->version = 2;
1608
1609 status = be_mcc_notify(adapter);
1610 if (status)
1611 goto err;
1612
1613 adapter->stats_cmd_sent = true;
1614
1615err:
1616 spin_unlock_bh(&adapter->mcc_lock);
1617 return status;
1618}
1619
1620/* Lancer Stats */
1621int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1622 struct be_dma_mem *nonemb_cmd)
1623{
1624 struct be_mcc_wrb *wrb;
1625 struct lancer_cmd_req_pport_stats *req;
1626 int status = 0;
1627
1628 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1629 CMD_SUBSYSTEM_ETH))
1630 return -EPERM;
1631
1632 spin_lock_bh(&adapter->mcc_lock);
1633
1634 wrb = wrb_from_mccq(adapter);
1635 if (!wrb) {
1636 status = -EBUSY;
1637 goto err;
1638 }
1639 req = nonemb_cmd->va;
1640
1641 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1642 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1643 wrb, nonemb_cmd);
1644
1645 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1646 req->cmd_params.params.reset_stats = 0;
1647
1648 status = be_mcc_notify(adapter);
1649 if (status)
1650 goto err;
1651
1652 adapter->stats_cmd_sent = true;
1653
1654err:
1655 spin_unlock_bh(&adapter->mcc_lock);
1656 return status;
1657}
1658
1659static int be_mac_to_link_speed(int mac_speed)
1660{
1661 switch (mac_speed) {
1662 case PHY_LINK_SPEED_ZERO:
1663 return 0;
1664 case PHY_LINK_SPEED_10MBPS:
1665 return 10;
1666 case PHY_LINK_SPEED_100MBPS:
1667 return 100;
1668 case PHY_LINK_SPEED_1GBPS:
1669 return 1000;
1670 case PHY_LINK_SPEED_10GBPS:
1671 return 10000;
1672 case PHY_LINK_SPEED_20GBPS:
1673 return 20000;
1674 case PHY_LINK_SPEED_25GBPS:
1675 return 25000;
1676 case PHY_LINK_SPEED_40GBPS:
1677 return 40000;
1678 }
1679 return 0;
1680}
1681
1682/* Uses synchronous mcc
1683 * Returns link_speed in Mbps
1684 */
1685int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1686 u8 *link_status, u32 dom)
1687{
1688 struct be_mcc_wrb *wrb;
1689 struct be_cmd_req_link_status *req;
1690 int status;
1691
1692 spin_lock_bh(&adapter->mcc_lock);
1693
1694 if (link_status)
1695 *link_status = LINK_DOWN;
1696
1697 wrb = wrb_from_mccq(adapter);
1698 if (!wrb) {
1699 status = -EBUSY;
1700 goto err;
1701 }
1702 req = embedded_payload(wrb);
1703
1704 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1705 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1706 sizeof(*req), wrb, NULL);
1707
1708 /* version 1 of the cmd is not supported only by BE2 */
1709 if (!BE2_chip(adapter))
1710 req->hdr.version = 1;
1711
1712 req->hdr.domain = dom;
1713
1714 status = be_mcc_notify_wait(adapter);
1715 if (!status) {
1716 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1717
1718 if (link_speed) {
1719 *link_speed = resp->link_speed ?
1720 le16_to_cpu(resp->link_speed) * 10 :
1721 be_mac_to_link_speed(resp->mac_speed);
1722
1723 if (!resp->logical_link_status)
1724 *link_speed = 0;
1725 }
1726 if (link_status)
1727 *link_status = resp->logical_link_status;
1728 }
1729
1730err:
1731 spin_unlock_bh(&adapter->mcc_lock);
1732 return status;
1733}
1734
1735/* Uses synchronous mcc */
1736int be_cmd_get_die_temperature(struct be_adapter *adapter)
1737{
1738 struct be_mcc_wrb *wrb;
1739 struct be_cmd_req_get_cntl_addnl_attribs *req;
1740 int status = 0;
1741
1742 spin_lock_bh(&adapter->mcc_lock);
1743
1744 wrb = wrb_from_mccq(adapter);
1745 if (!wrb) {
1746 status = -EBUSY;
1747 goto err;
1748 }
1749 req = embedded_payload(wrb);
1750
1751 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1752 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1753 sizeof(*req), wrb, NULL);
1754
1755 status = be_mcc_notify(adapter);
1756err:
1757 spin_unlock_bh(&adapter->mcc_lock);
1758 return status;
1759}
1760
1761/* Uses synchronous mcc */
1762int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1763{
1764 struct be_mcc_wrb wrb = {0};
1765 struct be_cmd_req_get_fat *req;
1766 int status;
1767
1768 req = embedded_payload(&wrb);
1769
1770 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1771 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1772 &wrb, NULL);
1773 req->fat_operation = cpu_to_le32(QUERY_FAT);
1774 status = be_cmd_notify_wait(adapter, &wrb);
1775 if (!status) {
1776 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1777
1778 if (dump_size && resp->log_size)
1779 *dump_size = le32_to_cpu(resp->log_size) -
1780 sizeof(u32);
1781 }
1782 return status;
1783}
1784
1785int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1786{
1787 struct be_dma_mem get_fat_cmd;
1788 struct be_mcc_wrb *wrb;
1789 struct be_cmd_req_get_fat *req;
1790 u32 offset = 0, total_size, buf_size,
1791 log_offset = sizeof(u32), payload_len;
1792 int status;
1793
1794 if (buf_len == 0)
1795 return 0;
1796
1797 total_size = buf_len;
1798
1799 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1800 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1801 get_fat_cmd.size,
1802 &get_fat_cmd.dma, GFP_ATOMIC);
1803 if (!get_fat_cmd.va)
1804 return -ENOMEM;
1805
1806 spin_lock_bh(&adapter->mcc_lock);
1807
1808 while (total_size) {
1809 buf_size = min(total_size, (u32)60*1024);
1810 total_size -= buf_size;
1811
1812 wrb = wrb_from_mccq(adapter);
1813 if (!wrb) {
1814 status = -EBUSY;
1815 goto err;
1816 }
1817 req = get_fat_cmd.va;
1818
1819 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1820 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1821 OPCODE_COMMON_MANAGE_FAT, payload_len,
1822 wrb, &get_fat_cmd);
1823
1824 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1825 req->read_log_offset = cpu_to_le32(log_offset);
1826 req->read_log_length = cpu_to_le32(buf_size);
1827 req->data_buffer_size = cpu_to_le32(buf_size);
1828
1829 status = be_mcc_notify_wait(adapter);
1830 if (!status) {
1831 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1832
1833 memcpy(buf + offset,
1834 resp->data_buffer,
1835 le32_to_cpu(resp->read_log_length));
1836 } else {
1837 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1838 goto err;
1839 }
1840 offset += buf_size;
1841 log_offset += buf_size;
1842 }
1843err:
1844 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1845 get_fat_cmd.va, get_fat_cmd.dma);
1846 spin_unlock_bh(&adapter->mcc_lock);
1847 return status;
1848}
1849
1850/* Uses synchronous mcc */
1851int be_cmd_get_fw_ver(struct be_adapter *adapter)
1852{
1853 struct be_mcc_wrb *wrb;
1854 struct be_cmd_req_get_fw_version *req;
1855 int status;
1856
1857 spin_lock_bh(&adapter->mcc_lock);
1858
1859 wrb = wrb_from_mccq(adapter);
1860 if (!wrb) {
1861 status = -EBUSY;
1862 goto err;
1863 }
1864
1865 req = embedded_payload(wrb);
1866
1867 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1868 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1869 NULL);
1870 status = be_mcc_notify_wait(adapter);
1871 if (!status) {
1872 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1873
1874 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1875 sizeof(adapter->fw_ver));
1876 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1877 sizeof(adapter->fw_on_flash));
1878 }
1879err:
1880 spin_unlock_bh(&adapter->mcc_lock);
1881 return status;
1882}
1883
1884/* set the EQ delay interval of an EQ to specified value
1885 * Uses async mcc
1886 */
1887static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1888 struct be_set_eqd *set_eqd, int num)
1889{
1890 struct be_mcc_wrb *wrb;
1891 struct be_cmd_req_modify_eq_delay *req;
1892 int status = 0, i;
1893
1894 spin_lock_bh(&adapter->mcc_lock);
1895
1896 wrb = wrb_from_mccq(adapter);
1897 if (!wrb) {
1898 status = -EBUSY;
1899 goto err;
1900 }
1901 req = embedded_payload(wrb);
1902
1903 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1904 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1905 NULL);
1906
1907 req->num_eq = cpu_to_le32(num);
1908 for (i = 0; i < num; i++) {
1909 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1910 req->set_eqd[i].phase = 0;
1911 req->set_eqd[i].delay_multiplier =
1912 cpu_to_le32(set_eqd[i].delay_multiplier);
1913 }
1914
1915 status = be_mcc_notify(adapter);
1916err:
1917 spin_unlock_bh(&adapter->mcc_lock);
1918 return status;
1919}
1920
1921int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1922 int num)
1923{
1924 int num_eqs, i = 0;
1925
1926 while (num) {
1927 num_eqs = min(num, 8);
1928 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1929 i += num_eqs;
1930 num -= num_eqs;
1931 }
1932
1933 return 0;
1934}
1935
1936/* Uses sycnhronous mcc */
1937int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1938 u32 num, u32 domain)
1939{
1940 struct be_mcc_wrb *wrb;
1941 struct be_cmd_req_vlan_config *req;
1942 int status;
1943
1944 spin_lock_bh(&adapter->mcc_lock);
1945
1946 wrb = wrb_from_mccq(adapter);
1947 if (!wrb) {
1948 status = -EBUSY;
1949 goto err;
1950 }
1951 req = embedded_payload(wrb);
1952
1953 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1954 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1955 wrb, NULL);
1956 req->hdr.domain = domain;
1957
1958 req->interface_id = if_id;
1959 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1960 req->num_vlan = num;
1961 memcpy(req->normal_vlan, vtag_array,
1962 req->num_vlan * sizeof(vtag_array[0]));
1963
1964 status = be_mcc_notify_wait(adapter);
1965err:
1966 spin_unlock_bh(&adapter->mcc_lock);
1967 return status;
1968}
1969
1970static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1971{
1972 struct be_mcc_wrb *wrb;
1973 struct be_dma_mem *mem = &adapter->rx_filter;
1974 struct be_cmd_req_rx_filter *req = mem->va;
1975 int status;
1976
1977 spin_lock_bh(&adapter->mcc_lock);
1978
1979 wrb = wrb_from_mccq(adapter);
1980 if (!wrb) {
1981 status = -EBUSY;
1982 goto err;
1983 }
1984 memset(req, 0, sizeof(*req));
1985 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1986 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1987 wrb, mem);
1988
1989 req->if_id = cpu_to_le32(adapter->if_handle);
1990 req->if_flags_mask = cpu_to_le32(flags);
1991 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1992
1993 if (flags & BE_IF_FLAGS_MULTICAST) {
1994 struct netdev_hw_addr *ha;
1995 int i = 0;
1996
1997 /* Reset mcast promisc mode if already set by setting mask
1998 * and not setting flags field
1999 */
2000 req->if_flags_mask |=
2001 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2002 be_if_cap_flags(adapter));
2003 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
2004 netdev_for_each_mc_addr(ha, adapter->netdev)
2005 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
2006 }
2007
2008 status = be_mcc_notify_wait(adapter);
2009err:
2010 spin_unlock_bh(&adapter->mcc_lock);
2011 return status;
2012}
2013
2014int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2015{
2016 struct device *dev = &adapter->pdev->dev;
2017
2018 if ((flags & be_if_cap_flags(adapter)) != flags) {
2019 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2020 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2021 be_if_cap_flags(adapter));
2022 }
2023 flags &= be_if_cap_flags(adapter);
2024 if (!flags)
2025 return -ENOTSUPP;
2026
2027 return __be_cmd_rx_filter(adapter, flags, value);
2028}
2029
2030/* Uses synchrounous mcc */
2031int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2032{
2033 struct be_mcc_wrb *wrb;
2034 struct be_cmd_req_set_flow_control *req;
2035 int status;
2036
2037 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2038 CMD_SUBSYSTEM_COMMON))
2039 return -EPERM;
2040
2041 spin_lock_bh(&adapter->mcc_lock);
2042
2043 wrb = wrb_from_mccq(adapter);
2044 if (!wrb) {
2045 status = -EBUSY;
2046 goto err;
2047 }
2048 req = embedded_payload(wrb);
2049
2050 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2051 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2052 wrb, NULL);
2053
2054 req->hdr.version = 1;
2055 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2056 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2057
2058 status = be_mcc_notify_wait(adapter);
2059
2060err:
2061 spin_unlock_bh(&adapter->mcc_lock);
2062
2063 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2064 return -EOPNOTSUPP;
2065
2066 return status;
2067}
2068
2069/* Uses sycn mcc */
2070int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2071{
2072 struct be_mcc_wrb *wrb;
2073 struct be_cmd_req_get_flow_control *req;
2074 int status;
2075
2076 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2077 CMD_SUBSYSTEM_COMMON))
2078 return -EPERM;
2079
2080 spin_lock_bh(&adapter->mcc_lock);
2081
2082 wrb = wrb_from_mccq(adapter);
2083 if (!wrb) {
2084 status = -EBUSY;
2085 goto err;
2086 }
2087 req = embedded_payload(wrb);
2088
2089 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2090 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2091 wrb, NULL);
2092
2093 status = be_mcc_notify_wait(adapter);
2094 if (!status) {
2095 struct be_cmd_resp_get_flow_control *resp =
2096 embedded_payload(wrb);
2097
2098 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2099 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2100 }
2101
2102err:
2103 spin_unlock_bh(&adapter->mcc_lock);
2104 return status;
2105}
2106
2107/* Uses mbox */
2108int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2109{
2110 struct be_mcc_wrb *wrb;
2111 struct be_cmd_req_query_fw_cfg *req;
2112 int status;
2113
2114 if (mutex_lock_interruptible(&adapter->mbox_lock))
2115 return -1;
2116
2117 wrb = wrb_from_mbox(adapter);
2118 req = embedded_payload(wrb);
2119
2120 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2121 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2122 sizeof(*req), wrb, NULL);
2123
2124 status = be_mbox_notify_wait(adapter);
2125 if (!status) {
2126 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2127
2128 adapter->port_num = le32_to_cpu(resp->phys_port);
2129 adapter->function_mode = le32_to_cpu(resp->function_mode);
2130 adapter->function_caps = le32_to_cpu(resp->function_caps);
2131 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2132 dev_info(&adapter->pdev->dev,
2133 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2134 adapter->function_mode, adapter->function_caps);
2135 }
2136
2137 mutex_unlock(&adapter->mbox_lock);
2138 return status;
2139}
2140
2141/* Uses mbox */
2142int be_cmd_reset_function(struct be_adapter *adapter)
2143{
2144 struct be_mcc_wrb *wrb;
2145 struct be_cmd_req_hdr *req;
2146 int status;
2147
2148 if (lancer_chip(adapter)) {
2149 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2150 adapter->db + SLIPORT_CONTROL_OFFSET);
2151 status = lancer_wait_ready(adapter);
2152 if (status)
2153 dev_err(&adapter->pdev->dev,
2154 "Adapter in non recoverable error\n");
2155 return status;
2156 }
2157
2158 if (mutex_lock_interruptible(&adapter->mbox_lock))
2159 return -1;
2160
2161 wrb = wrb_from_mbox(adapter);
2162 req = embedded_payload(wrb);
2163
2164 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2165 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2166 NULL);
2167
2168 status = be_mbox_notify_wait(adapter);
2169
2170 mutex_unlock(&adapter->mbox_lock);
2171 return status;
2172}
2173
2174int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2175 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2176{
2177 struct be_mcc_wrb *wrb;
2178 struct be_cmd_req_rss_config *req;
2179 int status;
2180
2181 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2182 return 0;
2183
2184 spin_lock_bh(&adapter->mcc_lock);
2185
2186 wrb = wrb_from_mccq(adapter);
2187 if (!wrb) {
2188 status = -EBUSY;
2189 goto err;
2190 }
2191 req = embedded_payload(wrb);
2192
2193 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2194 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2195
2196 req->if_id = cpu_to_le32(adapter->if_handle);
2197 req->enable_rss = cpu_to_le16(rss_hash_opts);
2198 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2199
2200 if (!BEx_chip(adapter))
2201 req->hdr.version = 1;
2202
2203 memcpy(req->cpu_table, rsstable, table_size);
2204 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2205 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2206
2207 status = be_mcc_notify_wait(adapter);
2208err:
2209 spin_unlock_bh(&adapter->mcc_lock);
2210 return status;
2211}
2212
2213/* Uses sync mcc */
2214int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2215 u8 bcn, u8 sts, u8 state)
2216{
2217 struct be_mcc_wrb *wrb;
2218 struct be_cmd_req_enable_disable_beacon *req;
2219 int status;
2220
2221 spin_lock_bh(&adapter->mcc_lock);
2222
2223 wrb = wrb_from_mccq(adapter);
2224 if (!wrb) {
2225 status = -EBUSY;
2226 goto err;
2227 }
2228 req = embedded_payload(wrb);
2229
2230 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2231 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2232 sizeof(*req), wrb, NULL);
2233
2234 req->port_num = port_num;
2235 req->beacon_state = state;
2236 req->beacon_duration = bcn;
2237 req->status_duration = sts;
2238
2239 status = be_mcc_notify_wait(adapter);
2240
2241err:
2242 spin_unlock_bh(&adapter->mcc_lock);
2243 return status;
2244}
2245
2246/* Uses sync mcc */
2247int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2248{
2249 struct be_mcc_wrb *wrb;
2250 struct be_cmd_req_get_beacon_state *req;
2251 int status;
2252
2253 spin_lock_bh(&adapter->mcc_lock);
2254
2255 wrb = wrb_from_mccq(adapter);
2256 if (!wrb) {
2257 status = -EBUSY;
2258 goto err;
2259 }
2260 req = embedded_payload(wrb);
2261
2262 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2263 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2264 wrb, NULL);
2265
2266 req->port_num = port_num;
2267
2268 status = be_mcc_notify_wait(adapter);
2269 if (!status) {
2270 struct be_cmd_resp_get_beacon_state *resp =
2271 embedded_payload(wrb);
2272
2273 *state = resp->beacon_state;
2274 }
2275
2276err:
2277 spin_unlock_bh(&adapter->mcc_lock);
2278 return status;
2279}
2280
2281/* Uses sync mcc */
2282int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2283 u8 page_num, u8 *data)
2284{
2285 struct be_dma_mem cmd;
2286 struct be_mcc_wrb *wrb;
2287 struct be_cmd_req_port_type *req;
2288 int status;
2289
2290 if (page_num > TR_PAGE_A2)
2291 return -EINVAL;
2292
2293 cmd.size = sizeof(struct be_cmd_resp_port_type);
2294 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2295 GFP_ATOMIC);
2296 if (!cmd.va) {
2297 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2298 return -ENOMEM;
2299 }
2300
2301 spin_lock_bh(&adapter->mcc_lock);
2302
2303 wrb = wrb_from_mccq(adapter);
2304 if (!wrb) {
2305 status = -EBUSY;
2306 goto err;
2307 }
2308 req = cmd.va;
2309
2310 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2311 OPCODE_COMMON_READ_TRANSRECV_DATA,
2312 cmd.size, wrb, &cmd);
2313
2314 req->port = cpu_to_le32(adapter->hba_port_num);
2315 req->page_num = cpu_to_le32(page_num);
2316 status = be_mcc_notify_wait(adapter);
2317 if (!status) {
2318 struct be_cmd_resp_port_type *resp = cmd.va;
2319
2320 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2321 }
2322err:
2323 spin_unlock_bh(&adapter->mcc_lock);
2324 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2325 return status;
2326}
2327
2328static int lancer_cmd_write_object(struct be_adapter *adapter,
2329 struct be_dma_mem *cmd, u32 data_size,
2330 u32 data_offset, const char *obj_name,
2331 u32 *data_written, u8 *change_status,
2332 u8 *addn_status)
2333{
2334 struct be_mcc_wrb *wrb;
2335 struct lancer_cmd_req_write_object *req;
2336 struct lancer_cmd_resp_write_object *resp;
2337 void *ctxt = NULL;
2338 int status;
2339
2340 spin_lock_bh(&adapter->mcc_lock);
2341 adapter->flash_status = 0;
2342
2343 wrb = wrb_from_mccq(adapter);
2344 if (!wrb) {
2345 status = -EBUSY;
2346 goto err_unlock;
2347 }
2348
2349 req = embedded_payload(wrb);
2350
2351 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2352 OPCODE_COMMON_WRITE_OBJECT,
2353 sizeof(struct lancer_cmd_req_write_object), wrb,
2354 NULL);
2355
2356 ctxt = &req->context;
2357 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2358 write_length, ctxt, data_size);
2359
2360 if (data_size == 0)
2361 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2362 eof, ctxt, 1);
2363 else
2364 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2365 eof, ctxt, 0);
2366
2367 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2368 req->write_offset = cpu_to_le32(data_offset);
2369 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2370 req->descriptor_count = cpu_to_le32(1);
2371 req->buf_len = cpu_to_le32(data_size);
2372 req->addr_low = cpu_to_le32((cmd->dma +
2373 sizeof(struct lancer_cmd_req_write_object))
2374 & 0xFFFFFFFF);
2375 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2376 sizeof(struct lancer_cmd_req_write_object)));
2377
2378 status = be_mcc_notify(adapter);
2379 if (status)
2380 goto err_unlock;
2381
2382 spin_unlock_bh(&adapter->mcc_lock);
2383
2384 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2385 msecs_to_jiffies(60000)))
2386 status = -ETIMEDOUT;
2387 else
2388 status = adapter->flash_status;
2389
2390 resp = embedded_payload(wrb);
2391 if (!status) {
2392 *data_written = le32_to_cpu(resp->actual_write_len);
2393 *change_status = resp->change_status;
2394 } else {
2395 *addn_status = resp->additional_status;
2396 }
2397
2398 return status;
2399
2400err_unlock:
2401 spin_unlock_bh(&adapter->mcc_lock);
2402 return status;
2403}
2404
2405int be_cmd_query_cable_type(struct be_adapter *adapter)
2406{
2407 u8 page_data[PAGE_DATA_LEN];
2408 int status;
2409
2410 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2411 page_data);
2412 if (!status) {
2413 switch (adapter->phy.interface_type) {
2414 case PHY_TYPE_QSFP:
2415 adapter->phy.cable_type =
2416 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2417 break;
2418 case PHY_TYPE_SFP_PLUS_10GB:
2419 adapter->phy.cable_type =
2420 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2421 break;
2422 default:
2423 adapter->phy.cable_type = 0;
2424 break;
2425 }
2426 }
2427 return status;
2428}
2429
2430int be_cmd_query_sfp_info(struct be_adapter *adapter)
2431{
2432 u8 page_data[PAGE_DATA_LEN];
2433 int status;
2434
2435 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2436 page_data);
2437 if (!status) {
2438 strlcpy(adapter->phy.vendor_name, page_data +
2439 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2440 strlcpy(adapter->phy.vendor_pn,
2441 page_data + SFP_VENDOR_PN_OFFSET,
2442 SFP_VENDOR_NAME_LEN - 1);
2443 }
2444
2445 return status;
2446}
2447
2448static int lancer_cmd_delete_object(struct be_adapter *adapter,
2449 const char *obj_name)
2450{
2451 struct lancer_cmd_req_delete_object *req;
2452 struct be_mcc_wrb *wrb;
2453 int status;
2454
2455 spin_lock_bh(&adapter->mcc_lock);
2456
2457 wrb = wrb_from_mccq(adapter);
2458 if (!wrb) {
2459 status = -EBUSY;
2460 goto err;
2461 }
2462
2463 req = embedded_payload(wrb);
2464
2465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2466 OPCODE_COMMON_DELETE_OBJECT,
2467 sizeof(*req), wrb, NULL);
2468
2469 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2470
2471 status = be_mcc_notify_wait(adapter);
2472err:
2473 spin_unlock_bh(&adapter->mcc_lock);
2474 return status;
2475}
2476
2477int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2478 u32 data_size, u32 data_offset, const char *obj_name,
2479 u32 *data_read, u32 *eof, u8 *addn_status)
2480{
2481 struct be_mcc_wrb *wrb;
2482 struct lancer_cmd_req_read_object *req;
2483 struct lancer_cmd_resp_read_object *resp;
2484 int status;
2485
2486 spin_lock_bh(&adapter->mcc_lock);
2487
2488 wrb = wrb_from_mccq(adapter);
2489 if (!wrb) {
2490 status = -EBUSY;
2491 goto err_unlock;
2492 }
2493
2494 req = embedded_payload(wrb);
2495
2496 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2497 OPCODE_COMMON_READ_OBJECT,
2498 sizeof(struct lancer_cmd_req_read_object), wrb,
2499 NULL);
2500
2501 req->desired_read_len = cpu_to_le32(data_size);
2502 req->read_offset = cpu_to_le32(data_offset);
2503 strcpy(req->object_name, obj_name);
2504 req->descriptor_count = cpu_to_le32(1);
2505 req->buf_len = cpu_to_le32(data_size);
2506 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2507 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2508
2509 status = be_mcc_notify_wait(adapter);
2510
2511 resp = embedded_payload(wrb);
2512 if (!status) {
2513 *data_read = le32_to_cpu(resp->actual_read_len);
2514 *eof = le32_to_cpu(resp->eof);
2515 } else {
2516 *addn_status = resp->additional_status;
2517 }
2518
2519err_unlock:
2520 spin_unlock_bh(&adapter->mcc_lock);
2521 return status;
2522}
2523
2524static int be_cmd_write_flashrom(struct be_adapter *adapter,
2525 struct be_dma_mem *cmd, u32 flash_type,
2526 u32 flash_opcode, u32 img_offset, u32 buf_size)
2527{
2528 struct be_mcc_wrb *wrb;
2529 struct be_cmd_write_flashrom *req;
2530 int status;
2531
2532 spin_lock_bh(&adapter->mcc_lock);
2533 adapter->flash_status = 0;
2534
2535 wrb = wrb_from_mccq(adapter);
2536 if (!wrb) {
2537 status = -EBUSY;
2538 goto err_unlock;
2539 }
2540 req = cmd->va;
2541
2542 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2543 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2544 cmd);
2545
2546 req->params.op_type = cpu_to_le32(flash_type);
2547 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2548 req->params.offset = cpu_to_le32(img_offset);
2549
2550 req->params.op_code = cpu_to_le32(flash_opcode);
2551 req->params.data_buf_size = cpu_to_le32(buf_size);
2552
2553 status = be_mcc_notify(adapter);
2554 if (status)
2555 goto err_unlock;
2556
2557 spin_unlock_bh(&adapter->mcc_lock);
2558
2559 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2560 msecs_to_jiffies(40000)))
2561 status = -ETIMEDOUT;
2562 else
2563 status = adapter->flash_status;
2564
2565 return status;
2566
2567err_unlock:
2568 spin_unlock_bh(&adapter->mcc_lock);
2569 return status;
2570}
2571
2572static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2573 u16 img_optype, u32 img_offset, u32 crc_offset)
2574{
2575 struct be_cmd_read_flash_crc *req;
2576 struct be_mcc_wrb *wrb;
2577 int status;
2578
2579 spin_lock_bh(&adapter->mcc_lock);
2580
2581 wrb = wrb_from_mccq(adapter);
2582 if (!wrb) {
2583 status = -EBUSY;
2584 goto err;
2585 }
2586 req = embedded_payload(wrb);
2587
2588 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2589 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2590 wrb, NULL);
2591
2592 req->params.op_type = cpu_to_le32(img_optype);
2593 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2594 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2595 else
2596 req->params.offset = cpu_to_le32(crc_offset);
2597
2598 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2599 req->params.data_buf_size = cpu_to_le32(0x4);
2600
2601 status = be_mcc_notify_wait(adapter);
2602 if (!status)
2603 memcpy(flashed_crc, req->crc, 4);
2604
2605err:
2606 spin_unlock_bh(&adapter->mcc_lock);
2607 return status;
2608}
2609
2610static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2611
2612static bool phy_flashing_required(struct be_adapter *adapter)
2613{
2614 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2615 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2616}
2617
2618static bool is_comp_in_ufi(struct be_adapter *adapter,
2619 struct flash_section_info *fsec, int type)
2620{
2621 int i = 0, img_type = 0;
2622 struct flash_section_info_g2 *fsec_g2 = NULL;
2623
2624 if (BE2_chip(adapter))
2625 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2626
2627 for (i = 0; i < MAX_FLASH_COMP; i++) {
2628 if (fsec_g2)
2629 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2630 else
2631 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2632
2633 if (img_type == type)
2634 return true;
2635 }
2636 return false;
2637}
2638
2639static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2640 int header_size,
2641 const struct firmware *fw)
2642{
2643 struct flash_section_info *fsec = NULL;
2644 const u8 *p = fw->data;
2645
2646 p += header_size;
2647 while (p < (fw->data + fw->size)) {
2648 fsec = (struct flash_section_info *)p;
2649 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2650 return fsec;
2651 p += 32;
2652 }
2653 return NULL;
2654}
2655
2656static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2657 u32 img_offset, u32 img_size, int hdr_size,
2658 u16 img_optype, bool *crc_match)
2659{
2660 u32 crc_offset;
2661 int status;
2662 u8 crc[4];
2663
2664 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2665 img_size - 4);
2666 if (status)
2667 return status;
2668
2669 crc_offset = hdr_size + img_offset + img_size - 4;
2670
2671 /* Skip flashing, if crc of flashed region matches */
2672 if (!memcmp(crc, p + crc_offset, 4))
2673 *crc_match = true;
2674 else
2675 *crc_match = false;
2676
2677 return status;
2678}
2679
2680static int be_flash(struct be_adapter *adapter, const u8 *img,
2681 struct be_dma_mem *flash_cmd, int optype, int img_size,
2682 u32 img_offset)
2683{
2684 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2685 struct be_cmd_write_flashrom *req = flash_cmd->va;
2686 int status;
2687
2688 while (total_bytes) {
2689 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2690
2691 total_bytes -= num_bytes;
2692
2693 if (!total_bytes) {
2694 if (optype == OPTYPE_PHY_FW)
2695 flash_op = FLASHROM_OPER_PHY_FLASH;
2696 else
2697 flash_op = FLASHROM_OPER_FLASH;
2698 } else {
2699 if (optype == OPTYPE_PHY_FW)
2700 flash_op = FLASHROM_OPER_PHY_SAVE;
2701 else
2702 flash_op = FLASHROM_OPER_SAVE;
2703 }
2704
2705 memcpy(req->data_buf, img, num_bytes);
2706 img += num_bytes;
2707 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2708 flash_op, img_offset +
2709 bytes_sent, num_bytes);
2710 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2711 optype == OPTYPE_PHY_FW)
2712 break;
2713 else if (status)
2714 return status;
2715
2716 bytes_sent += num_bytes;
2717 }
2718 return 0;
2719}
2720
2721/* For BE2, BE3 and BE3-R */
2722static int be_flash_BEx(struct be_adapter *adapter,
2723 const struct firmware *fw,
2724 struct be_dma_mem *flash_cmd, int num_of_images)
2725{
2726 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2727 struct device *dev = &adapter->pdev->dev;
2728 struct flash_section_info *fsec = NULL;
2729 int status, i, filehdr_size, num_comp;
2730 const struct flash_comp *pflashcomp;
2731 bool crc_match;
2732 const u8 *p;
2733
2734 struct flash_comp gen3_flash_types[] = {
2735 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2736 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2737 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2738 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2739 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2740 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2741 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2742 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2743 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2744 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2745 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2746 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2747 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2748 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2749 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2750 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2751 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2752 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2753 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2754 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2755 };
2756
2757 struct flash_comp gen2_flash_types[] = {
2758 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2759 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2760 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2761 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2762 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2763 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2764 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2765 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2766 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2767 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2768 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2769 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2770 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2771 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2772 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2773 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2774 };
2775
2776 if (BE3_chip(adapter)) {
2777 pflashcomp = gen3_flash_types;
2778 filehdr_size = sizeof(struct flash_file_hdr_g3);
2779 num_comp = ARRAY_SIZE(gen3_flash_types);
2780 } else {
2781 pflashcomp = gen2_flash_types;
2782 filehdr_size = sizeof(struct flash_file_hdr_g2);
2783 num_comp = ARRAY_SIZE(gen2_flash_types);
2784 img_hdrs_size = 0;
2785 }
2786
2787 /* Get flash section info*/
2788 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2789 if (!fsec) {
2790 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2791 return -1;
2792 }
2793 for (i = 0; i < num_comp; i++) {
2794 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2795 continue;
2796
2797 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2798 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2799 continue;
2800
2801 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2802 !phy_flashing_required(adapter))
2803 continue;
2804
2805 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2806 status = be_check_flash_crc(adapter, fw->data,
2807 pflashcomp[i].offset,
2808 pflashcomp[i].size,
2809 filehdr_size +
2810 img_hdrs_size,
2811 OPTYPE_REDBOOT, &crc_match);
2812 if (status) {
2813 dev_err(dev,
2814 "Could not get CRC for 0x%x region\n",
2815 pflashcomp[i].optype);
2816 continue;
2817 }
2818
2819 if (crc_match)
2820 continue;
2821 }
2822
2823 p = fw->data + filehdr_size + pflashcomp[i].offset +
2824 img_hdrs_size;
2825 if (p + pflashcomp[i].size > fw->data + fw->size)
2826 return -1;
2827
2828 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2829 pflashcomp[i].size, 0);
2830 if (status) {
2831 dev_err(dev, "Flashing section type 0x%x failed\n",
2832 pflashcomp[i].img_type);
2833 return status;
2834 }
2835 }
2836 return 0;
2837}
2838
2839static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2840{
2841 u32 img_type = le32_to_cpu(fsec_entry.type);
2842 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2843
2844 if (img_optype != 0xFFFF)
2845 return img_optype;
2846
2847 switch (img_type) {
2848 case IMAGE_FIRMWARE_ISCSI:
2849 img_optype = OPTYPE_ISCSI_ACTIVE;
2850 break;
2851 case IMAGE_BOOT_CODE:
2852 img_optype = OPTYPE_REDBOOT;
2853 break;
2854 case IMAGE_OPTION_ROM_ISCSI:
2855 img_optype = OPTYPE_BIOS;
2856 break;
2857 case IMAGE_OPTION_ROM_PXE:
2858 img_optype = OPTYPE_PXE_BIOS;
2859 break;
2860 case IMAGE_OPTION_ROM_FCOE:
2861 img_optype = OPTYPE_FCOE_BIOS;
2862 break;
2863 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2864 img_optype = OPTYPE_ISCSI_BACKUP;
2865 break;
2866 case IMAGE_NCSI:
2867 img_optype = OPTYPE_NCSI_FW;
2868 break;
2869 case IMAGE_FLASHISM_JUMPVECTOR:
2870 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2871 break;
2872 case IMAGE_FIRMWARE_PHY:
2873 img_optype = OPTYPE_SH_PHY_FW;
2874 break;
2875 case IMAGE_REDBOOT_DIR:
2876 img_optype = OPTYPE_REDBOOT_DIR;
2877 break;
2878 case IMAGE_REDBOOT_CONFIG:
2879 img_optype = OPTYPE_REDBOOT_CONFIG;
2880 break;
2881 case IMAGE_UFI_DIR:
2882 img_optype = OPTYPE_UFI_DIR;
2883 break;
2884 default:
2885 break;
2886 }
2887
2888 return img_optype;
2889}
2890
2891static int be_flash_skyhawk(struct be_adapter *adapter,
2892 const struct firmware *fw,
2893 struct be_dma_mem *flash_cmd, int num_of_images)
2894{
2895 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2896 bool crc_match, old_fw_img, flash_offset_support = true;
2897 struct device *dev = &adapter->pdev->dev;
2898 struct flash_section_info *fsec = NULL;
2899 u32 img_offset, img_size, img_type;
2900 u16 img_optype, flash_optype;
2901 int status, i, filehdr_size;
2902 const u8 *p;
2903
2904 filehdr_size = sizeof(struct flash_file_hdr_g3);
2905 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2906 if (!fsec) {
2907 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2908 return -EINVAL;
2909 }
2910
2911retry_flash:
2912 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2913 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2914 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2915 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2916 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2917 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2918
2919 if (img_optype == 0xFFFF)
2920 continue;
2921
2922 if (flash_offset_support)
2923 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2924 else
2925 flash_optype = img_optype;
2926
2927 /* Don't bother verifying CRC if an old FW image is being
2928 * flashed
2929 */
2930 if (old_fw_img)
2931 goto flash;
2932
2933 status = be_check_flash_crc(adapter, fw->data, img_offset,
2934 img_size, filehdr_size +
2935 img_hdrs_size, flash_optype,
2936 &crc_match);
2937 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2938 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2939 /* The current FW image on the card does not support
2940 * OFFSET based flashing. Retry using older mechanism
2941 * of OPTYPE based flashing
2942 */
2943 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2944 flash_offset_support = false;
2945 goto retry_flash;
2946 }
2947
2948 /* The current FW image on the card does not recognize
2949 * the new FLASH op_type. The FW download is partially
2950 * complete. Reboot the server now to enable FW image
2951 * to recognize the new FLASH op_type. To complete the
2952 * remaining process, download the same FW again after
2953 * the reboot.
2954 */
2955 dev_err(dev, "Flash incomplete. Reset the server\n");
2956 dev_err(dev, "Download FW image again after reset\n");
2957 return -EAGAIN;
2958 } else if (status) {
2959 dev_err(dev, "Could not get CRC for 0x%x region\n",
2960 img_optype);
2961 return -EFAULT;
2962 }
2963
2964 if (crc_match)
2965 continue;
2966
2967flash:
2968 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2969 if (p + img_size > fw->data + fw->size)
2970 return -1;
2971
2972 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2973 img_offset);
2974
2975 /* The current FW image on the card does not support OFFSET
2976 * based flashing. Retry using older mechanism of OPTYPE based
2977 * flashing
2978 */
2979 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2980 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2981 flash_offset_support = false;
2982 goto retry_flash;
2983 }
2984
2985 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2986 * UFI_DIR region
2987 */
2988 if (old_fw_img &&
2989 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2990 (img_optype == OPTYPE_UFI_DIR &&
2991 base_status(status) == MCC_STATUS_FAILED))) {
2992 continue;
2993 } else if (status) {
2994 dev_err(dev, "Flashing section type 0x%x failed\n",
2995 img_type);
2996
2997 switch (addl_status(status)) {
2998 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
2999 dev_err(dev,
3000 "Digital signature missing in FW\n");
3001 return -EINVAL;
3002 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3003 dev_err(dev,
3004 "Invalid digital signature in FW\n");
3005 return -EINVAL;
3006 default:
3007 return -EFAULT;
3008 }
3009 }
3010 }
3011 return 0;
3012}
3013
3014int lancer_fw_download(struct be_adapter *adapter,
3015 const struct firmware *fw)
3016{
3017 struct device *dev = &adapter->pdev->dev;
3018 struct be_dma_mem flash_cmd;
3019 const u8 *data_ptr = NULL;
3020 u8 *dest_image_ptr = NULL;
3021 size_t image_size = 0;
3022 u32 chunk_size = 0;
3023 u32 data_written = 0;
3024 u32 offset = 0;
3025 int status = 0;
3026 u8 add_status = 0;
3027 u8 change_status;
3028
3029 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3030 dev_err(dev, "FW image size should be multiple of 4\n");
3031 return -EINVAL;
3032 }
3033
3034 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3035 + LANCER_FW_DOWNLOAD_CHUNK;
3036 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3037 &flash_cmd.dma, GFP_KERNEL);
3038 if (!flash_cmd.va)
3039 return -ENOMEM;
3040
3041 dest_image_ptr = flash_cmd.va +
3042 sizeof(struct lancer_cmd_req_write_object);
3043 image_size = fw->size;
3044 data_ptr = fw->data;
3045
3046 while (image_size) {
3047 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3048
3049 /* Copy the image chunk content. */
3050 memcpy(dest_image_ptr, data_ptr, chunk_size);
3051
3052 status = lancer_cmd_write_object(adapter, &flash_cmd,
3053 chunk_size, offset,
3054 LANCER_FW_DOWNLOAD_LOCATION,
3055 &data_written, &change_status,
3056 &add_status);
3057 if (status)
3058 break;
3059
3060 offset += data_written;
3061 data_ptr += data_written;
3062 image_size -= data_written;
3063 }
3064
3065 if (!status) {
3066 /* Commit the FW written */
3067 status = lancer_cmd_write_object(adapter, &flash_cmd,
3068 0, offset,
3069 LANCER_FW_DOWNLOAD_LOCATION,
3070 &data_written, &change_status,
3071 &add_status);
3072 }
3073
3074 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3075 if (status) {
3076 dev_err(dev, "Firmware load error\n");
3077 return be_cmd_status(status);
3078 }
3079
3080 dev_info(dev, "Firmware flashed successfully\n");
3081
3082 if (change_status == LANCER_FW_RESET_NEEDED) {
3083 dev_info(dev, "Resetting adapter to activate new FW\n");
3084 status = lancer_physdev_ctrl(adapter,
3085 PHYSDEV_CONTROL_FW_RESET_MASK);
3086 if (status) {
3087 dev_err(dev, "Adapter busy, could not reset FW\n");
3088 dev_err(dev, "Reboot server to activate new FW\n");
3089 }
3090 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3091 dev_info(dev, "Reboot server to activate new FW\n");
3092 }
3093
3094 return 0;
3095}
3096
3097/* Check if the flash image file is compatible with the adapter that
3098 * is being flashed.
3099 */
3100static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3101 struct flash_file_hdr_g3 *fhdr)
3102{
3103 if (!fhdr) {
3104 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3105 return false;
3106 }
3107
3108 /* First letter of the build version is used to identify
3109 * which chip this image file is meant for.
3110 */
3111 switch (fhdr->build[0]) {
3112 case BLD_STR_UFI_TYPE_SH:
3113 if (!skyhawk_chip(adapter))
3114 return false;
3115 break;
3116 case BLD_STR_UFI_TYPE_BE3:
3117 if (!BE3_chip(adapter))
3118 return false;
3119 break;
3120 case BLD_STR_UFI_TYPE_BE2:
3121 if (!BE2_chip(adapter))
3122 return false;
3123 break;
3124 default:
3125 return false;
3126 }
3127
3128 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3129 * asic_rev of the chips it is compatible with.
3130 * When asic_type_rev is 0 the image is compatible only with
3131 * pre-BE3-R chips (asic_rev < 0x10)
3132 */
3133 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3134 return adapter->asic_rev < 0x10;
3135 else
3136 return (fhdr->asic_type_rev >= adapter->asic_rev);
3137}
3138
3139int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3140{
3141 struct device *dev = &adapter->pdev->dev;
3142 struct flash_file_hdr_g3 *fhdr3;
3143 struct image_hdr *img_hdr_ptr;
3144 int status = 0, i, num_imgs;
3145 struct be_dma_mem flash_cmd;
3146
3147 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3148 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3149 dev_err(dev, "Flash image is not compatible with adapter\n");
3150 return -EINVAL;
3151 }
3152
3153 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3154 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3155 GFP_KERNEL);
3156 if (!flash_cmd.va)
3157 return -ENOMEM;
3158
3159 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3160 for (i = 0; i < num_imgs; i++) {
3161 img_hdr_ptr = (struct image_hdr *)(fw->data +
3162 (sizeof(struct flash_file_hdr_g3) +
3163 i * sizeof(struct image_hdr)));
3164 if (!BE2_chip(adapter) &&
3165 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3166 continue;
3167
3168 if (skyhawk_chip(adapter))
3169 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3170 num_imgs);
3171 else
3172 status = be_flash_BEx(adapter, fw, &flash_cmd,
3173 num_imgs);
3174 }
3175
3176 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3177 if (!status)
3178 dev_info(dev, "Firmware flashed successfully\n");
3179
3180 return status;
3181}
3182
3183int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3184 struct be_dma_mem *nonemb_cmd)
3185{
3186 struct be_mcc_wrb *wrb;
3187 struct be_cmd_req_acpi_wol_magic_config *req;
3188 int status;
3189
3190 spin_lock_bh(&adapter->mcc_lock);
3191
3192 wrb = wrb_from_mccq(adapter);
3193 if (!wrb) {
3194 status = -EBUSY;
3195 goto err;
3196 }
3197 req = nonemb_cmd->va;
3198
3199 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3200 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3201 wrb, nonemb_cmd);
3202 memcpy(req->magic_mac, mac, ETH_ALEN);
3203
3204 status = be_mcc_notify_wait(adapter);
3205
3206err:
3207 spin_unlock_bh(&adapter->mcc_lock);
3208 return status;
3209}
3210
3211int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3212 u8 loopback_type, u8 enable)
3213{
3214 struct be_mcc_wrb *wrb;
3215 struct be_cmd_req_set_lmode *req;
3216 int status;
3217
3218 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3219 CMD_SUBSYSTEM_LOWLEVEL))
3220 return -EPERM;
3221
3222 spin_lock_bh(&adapter->mcc_lock);
3223
3224 wrb = wrb_from_mccq(adapter);
3225 if (!wrb) {
3226 status = -EBUSY;
3227 goto err_unlock;
3228 }
3229
3230 req = embedded_payload(wrb);
3231
3232 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3233 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3234 wrb, NULL);
3235
3236 req->src_port = port_num;
3237 req->dest_port = port_num;
3238 req->loopback_type = loopback_type;
3239 req->loopback_state = enable;
3240
3241 status = be_mcc_notify(adapter);
3242 if (status)
3243 goto err_unlock;
3244
3245 spin_unlock_bh(&adapter->mcc_lock);
3246
3247 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3248 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3249 status = -ETIMEDOUT;
3250
3251 return status;
3252
3253err_unlock:
3254 spin_unlock_bh(&adapter->mcc_lock);
3255 return status;
3256}
3257
3258int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3259 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3260 u64 pattern)
3261{
3262 struct be_mcc_wrb *wrb;
3263 struct be_cmd_req_loopback_test *req;
3264 struct be_cmd_resp_loopback_test *resp;
3265 int status;
3266
3267 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3268 CMD_SUBSYSTEM_LOWLEVEL))
3269 return -EPERM;
3270
3271 spin_lock_bh(&adapter->mcc_lock);
3272
3273 wrb = wrb_from_mccq(adapter);
3274 if (!wrb) {
3275 status = -EBUSY;
3276 goto err;
3277 }
3278
3279 req = embedded_payload(wrb);
3280
3281 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3282 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3283 NULL);
3284
3285 req->hdr.timeout = cpu_to_le32(15);
3286 req->pattern = cpu_to_le64(pattern);
3287 req->src_port = cpu_to_le32(port_num);
3288 req->dest_port = cpu_to_le32(port_num);
3289 req->pkt_size = cpu_to_le32(pkt_size);
3290 req->num_pkts = cpu_to_le32(num_pkts);
3291 req->loopback_type = cpu_to_le32(loopback_type);
3292
3293 status = be_mcc_notify(adapter);
3294 if (status)
3295 goto err;
3296
3297 spin_unlock_bh(&adapter->mcc_lock);
3298
3299 wait_for_completion(&adapter->et_cmd_compl);
3300 resp = embedded_payload(wrb);
3301 status = le32_to_cpu(resp->status);
3302
3303 return status;
3304err:
3305 spin_unlock_bh(&adapter->mcc_lock);
3306 return status;
3307}
3308
3309int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3310 u32 byte_cnt, struct be_dma_mem *cmd)
3311{
3312 struct be_mcc_wrb *wrb;
3313 struct be_cmd_req_ddrdma_test *req;
3314 int status;
3315 int i, j = 0;
3316
3317 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3318 CMD_SUBSYSTEM_LOWLEVEL))
3319 return -EPERM;
3320
3321 spin_lock_bh(&adapter->mcc_lock);
3322
3323 wrb = wrb_from_mccq(adapter);
3324 if (!wrb) {
3325 status = -EBUSY;
3326 goto err;
3327 }
3328 req = cmd->va;
3329 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3330 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3331 cmd);
3332
3333 req->pattern = cpu_to_le64(pattern);
3334 req->byte_count = cpu_to_le32(byte_cnt);
3335 for (i = 0; i < byte_cnt; i++) {
3336 req->snd_buff[i] = (u8)(pattern >> (j*8));
3337 j++;
3338 if (j > 7)
3339 j = 0;
3340 }
3341
3342 status = be_mcc_notify_wait(adapter);
3343
3344 if (!status) {
3345 struct be_cmd_resp_ddrdma_test *resp;
3346
3347 resp = cmd->va;
3348 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3349 resp->snd_err) {
3350 status = -1;
3351 }
3352 }
3353
3354err:
3355 spin_unlock_bh(&adapter->mcc_lock);
3356 return status;
3357}
3358
3359int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3360 struct be_dma_mem *nonemb_cmd)
3361{
3362 struct be_mcc_wrb *wrb;
3363 struct be_cmd_req_seeprom_read *req;
3364 int status;
3365
3366 spin_lock_bh(&adapter->mcc_lock);
3367
3368 wrb = wrb_from_mccq(adapter);
3369 if (!wrb) {
3370 status = -EBUSY;
3371 goto err;
3372 }
3373 req = nonemb_cmd->va;
3374
3375 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3376 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3377 nonemb_cmd);
3378
3379 status = be_mcc_notify_wait(adapter);
3380
3381err:
3382 spin_unlock_bh(&adapter->mcc_lock);
3383 return status;
3384}
3385
3386int be_cmd_get_phy_info(struct be_adapter *adapter)
3387{
3388 struct be_mcc_wrb *wrb;
3389 struct be_cmd_req_get_phy_info *req;
3390 struct be_dma_mem cmd;
3391 int status;
3392
3393 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3394 CMD_SUBSYSTEM_COMMON))
3395 return -EPERM;
3396
3397 spin_lock_bh(&adapter->mcc_lock);
3398
3399 wrb = wrb_from_mccq(adapter);
3400 if (!wrb) {
3401 status = -EBUSY;
3402 goto err;
3403 }
3404 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3405 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3406 GFP_ATOMIC);
3407 if (!cmd.va) {
3408 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3409 status = -ENOMEM;
3410 goto err;
3411 }
3412
3413 req = cmd.va;
3414
3415 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3416 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3417 wrb, &cmd);
3418
3419 status = be_mcc_notify_wait(adapter);
3420 if (!status) {
3421 struct be_phy_info *resp_phy_info =
3422 cmd.va + sizeof(struct be_cmd_req_hdr);
3423
3424 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3425 adapter->phy.interface_type =
3426 le16_to_cpu(resp_phy_info->interface_type);
3427 adapter->phy.auto_speeds_supported =
3428 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3429 adapter->phy.fixed_speeds_supported =
3430 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3431 adapter->phy.misc_params =
3432 le32_to_cpu(resp_phy_info->misc_params);
3433
3434 if (BE2_chip(adapter)) {
3435 adapter->phy.fixed_speeds_supported =
3436 BE_SUPPORTED_SPEED_10GBPS |
3437 BE_SUPPORTED_SPEED_1GBPS;
3438 }
3439 }
3440 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3441err:
3442 spin_unlock_bh(&adapter->mcc_lock);
3443 return status;
3444}
3445
3446static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3447{
3448 struct be_mcc_wrb *wrb;
3449 struct be_cmd_req_set_qos *req;
3450 int status;
3451
3452 spin_lock_bh(&adapter->mcc_lock);
3453
3454 wrb = wrb_from_mccq(adapter);
3455 if (!wrb) {
3456 status = -EBUSY;
3457 goto err;
3458 }
3459
3460 req = embedded_payload(wrb);
3461
3462 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3463 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3464
3465 req->hdr.domain = domain;
3466 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3467 req->max_bps_nic = cpu_to_le32(bps);
3468
3469 status = be_mcc_notify_wait(adapter);
3470
3471err:
3472 spin_unlock_bh(&adapter->mcc_lock);
3473 return status;
3474}
3475
3476int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3477{
3478 struct be_mcc_wrb *wrb;
3479 struct be_cmd_req_cntl_attribs *req;
3480 struct be_cmd_resp_cntl_attribs *resp;
3481 int status, i;
3482 int payload_len = max(sizeof(*req), sizeof(*resp));
3483 struct mgmt_controller_attrib *attribs;
3484 struct be_dma_mem attribs_cmd;
3485 u32 *serial_num;
3486
3487 if (mutex_lock_interruptible(&adapter->mbox_lock))
3488 return -1;
3489
3490 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3491 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3492 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3493 attribs_cmd.size,
3494 &attribs_cmd.dma, GFP_ATOMIC);
3495 if (!attribs_cmd.va) {
3496 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3497 status = -ENOMEM;
3498 goto err;
3499 }
3500
3501 wrb = wrb_from_mbox(adapter);
3502 if (!wrb) {
3503 status = -EBUSY;
3504 goto err;
3505 }
3506 req = attribs_cmd.va;
3507
3508 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3509 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3510 wrb, &attribs_cmd);
3511
3512 status = be_mbox_notify_wait(adapter);
3513 if (!status) {
3514 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3515 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3516 serial_num = attribs->hba_attribs.controller_serial_number;
3517 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3518 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3519 (BIT_MASK(16) - 1);
3520 }
3521
3522err:
3523 mutex_unlock(&adapter->mbox_lock);
3524 if (attribs_cmd.va)
3525 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3526 attribs_cmd.va, attribs_cmd.dma);
3527 return status;
3528}
3529
3530/* Uses mbox */
3531int be_cmd_req_native_mode(struct be_adapter *adapter)
3532{
3533 struct be_mcc_wrb *wrb;
3534 struct be_cmd_req_set_func_cap *req;
3535 int status;
3536
3537 if (mutex_lock_interruptible(&adapter->mbox_lock))
3538 return -1;
3539
3540 wrb = wrb_from_mbox(adapter);
3541 if (!wrb) {
3542 status = -EBUSY;
3543 goto err;
3544 }
3545
3546 req = embedded_payload(wrb);
3547
3548 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3549 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3550 sizeof(*req), wrb, NULL);
3551
3552 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3553 CAPABILITY_BE3_NATIVE_ERX_API);
3554 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3555
3556 status = be_mbox_notify_wait(adapter);
3557 if (!status) {
3558 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3559
3560 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3561 CAPABILITY_BE3_NATIVE_ERX_API;
3562 if (!adapter->be3_native)
3563 dev_warn(&adapter->pdev->dev,
3564 "adapter not in advanced mode\n");
3565 }
3566err:
3567 mutex_unlock(&adapter->mbox_lock);
3568 return status;
3569}
3570
3571/* Get privilege(s) for a function */
3572int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3573 u32 domain)
3574{
3575 struct be_mcc_wrb *wrb;
3576 struct be_cmd_req_get_fn_privileges *req;
3577 int status;
3578
3579 spin_lock_bh(&adapter->mcc_lock);
3580
3581 wrb = wrb_from_mccq(adapter);
3582 if (!wrb) {
3583 status = -EBUSY;
3584 goto err;
3585 }
3586
3587 req = embedded_payload(wrb);
3588
3589 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3590 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3591 wrb, NULL);
3592
3593 req->hdr.domain = domain;
3594
3595 status = be_mcc_notify_wait(adapter);
3596 if (!status) {
3597 struct be_cmd_resp_get_fn_privileges *resp =
3598 embedded_payload(wrb);
3599
3600 *privilege = le32_to_cpu(resp->privilege_mask);
3601
3602 /* In UMC mode FW does not return right privileges.
3603 * Override with correct privilege equivalent to PF.
3604 */
3605 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3606 be_physfn(adapter))
3607 *privilege = MAX_PRIVILEGES;
3608 }
3609
3610err:
3611 spin_unlock_bh(&adapter->mcc_lock);
3612 return status;
3613}
3614
3615/* Set privilege(s) for a function */
3616int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3617 u32 domain)
3618{
3619 struct be_mcc_wrb *wrb;
3620 struct be_cmd_req_set_fn_privileges *req;
3621 int status;
3622
3623 spin_lock_bh(&adapter->mcc_lock);
3624
3625 wrb = wrb_from_mccq(adapter);
3626 if (!wrb) {
3627 status = -EBUSY;
3628 goto err;
3629 }
3630
3631 req = embedded_payload(wrb);
3632 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3633 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3634 wrb, NULL);
3635 req->hdr.domain = domain;
3636 if (lancer_chip(adapter))
3637 req->privileges_lancer = cpu_to_le32(privileges);
3638 else
3639 req->privileges = cpu_to_le32(privileges);
3640
3641 status = be_mcc_notify_wait(adapter);
3642err:
3643 spin_unlock_bh(&adapter->mcc_lock);
3644 return status;
3645}
3646
3647/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3648 * pmac_id_valid: false => pmac_id or MAC address is requested.
3649 * If pmac_id is returned, pmac_id_valid is returned as true
3650 */
3651int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3652 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3653 u8 domain)
3654{
3655 struct be_mcc_wrb *wrb;
3656 struct be_cmd_req_get_mac_list *req;
3657 int status;
3658 int mac_count;
3659 struct be_dma_mem get_mac_list_cmd;
3660 int i;
3661
3662 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3663 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3664 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3665 get_mac_list_cmd.size,
3666 &get_mac_list_cmd.dma,
3667 GFP_ATOMIC);
3668
3669 if (!get_mac_list_cmd.va) {
3670 dev_err(&adapter->pdev->dev,
3671 "Memory allocation failure during GET_MAC_LIST\n");
3672 return -ENOMEM;
3673 }
3674
3675 spin_lock_bh(&adapter->mcc_lock);
3676
3677 wrb = wrb_from_mccq(adapter);
3678 if (!wrb) {
3679 status = -EBUSY;
3680 goto out;
3681 }
3682
3683 req = get_mac_list_cmd.va;
3684
3685 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3686 OPCODE_COMMON_GET_MAC_LIST,
3687 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3688 req->hdr.domain = domain;
3689 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3690 if (*pmac_id_valid) {
3691 req->mac_id = cpu_to_le32(*pmac_id);
3692 req->iface_id = cpu_to_le16(if_handle);
3693 req->perm_override = 0;
3694 } else {
3695 req->perm_override = 1;
3696 }
3697
3698 status = be_mcc_notify_wait(adapter);
3699 if (!status) {
3700 struct be_cmd_resp_get_mac_list *resp =
3701 get_mac_list_cmd.va;
3702
3703 if (*pmac_id_valid) {
3704 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3705 ETH_ALEN);
3706 goto out;
3707 }
3708
3709 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3710 /* Mac list returned could contain one or more active mac_ids
3711 * or one or more true or pseudo permanent mac addresses.
3712 * If an active mac_id is present, return first active mac_id
3713 * found.
3714 */
3715 for (i = 0; i < mac_count; i++) {
3716 struct get_list_macaddr *mac_entry;
3717 u16 mac_addr_size;
3718 u32 mac_id;
3719
3720 mac_entry = &resp->macaddr_list[i];
3721 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3722 /* mac_id is a 32 bit value and mac_addr size
3723 * is 6 bytes
3724 */
3725 if (mac_addr_size == sizeof(u32)) {
3726 *pmac_id_valid = true;
3727 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3728 *pmac_id = le32_to_cpu(mac_id);
3729 goto out;
3730 }
3731 }
3732 /* If no active mac_id found, return first mac addr */
3733 *pmac_id_valid = false;
3734 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3735 ETH_ALEN);
3736 }
3737
3738out:
3739 spin_unlock_bh(&adapter->mcc_lock);
3740 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3741 get_mac_list_cmd.va, get_mac_list_cmd.dma);
3742 return status;
3743}
3744
3745int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3746 u8 *mac, u32 if_handle, bool active, u32 domain)
3747{
3748 if (!active)
3749 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3750 if_handle, domain);
3751 if (BEx_chip(adapter))
3752 return be_cmd_mac_addr_query(adapter, mac, false,
3753 if_handle, curr_pmac_id);
3754 else
3755 /* Fetch the MAC address using pmac_id */
3756 return be_cmd_get_mac_from_list(adapter, mac, &active,
3757 &curr_pmac_id,
3758 if_handle, domain);
3759}
3760
3761int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3762{
3763 int status;
3764 bool pmac_valid = false;
3765
3766 eth_zero_addr(mac);
3767
3768 if (BEx_chip(adapter)) {
3769 if (be_physfn(adapter))
3770 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3771 0);
3772 else
3773 status = be_cmd_mac_addr_query(adapter, mac, false,
3774 adapter->if_handle, 0);
3775 } else {
3776 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3777 NULL, adapter->if_handle, 0);
3778 }
3779
3780 return status;
3781}
3782
3783/* Uses synchronous MCCQ */
3784int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3785 u8 mac_count, u32 domain)
3786{
3787 struct be_mcc_wrb *wrb;
3788 struct be_cmd_req_set_mac_list *req;
3789 int status;
3790 struct be_dma_mem cmd;
3791
3792 memset(&cmd, 0, sizeof(struct be_dma_mem));
3793 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3794 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3795 GFP_KERNEL);
3796 if (!cmd.va)
3797 return -ENOMEM;
3798
3799 spin_lock_bh(&adapter->mcc_lock);
3800
3801 wrb = wrb_from_mccq(adapter);
3802 if (!wrb) {
3803 status = -EBUSY;
3804 goto err;
3805 }
3806
3807 req = cmd.va;
3808 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3809 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3810 wrb, &cmd);
3811
3812 req->hdr.domain = domain;
3813 req->mac_count = mac_count;
3814 if (mac_count)
3815 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3816
3817 status = be_mcc_notify_wait(adapter);
3818
3819err:
3820 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3821 spin_unlock_bh(&adapter->mcc_lock);
3822 return status;
3823}
3824
3825/* Wrapper to delete any active MACs and provision the new mac.
3826 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3827 * current list are active.
3828 */
3829int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3830{
3831 bool active_mac = false;
3832 u8 old_mac[ETH_ALEN];
3833 u32 pmac_id;
3834 int status;
3835
3836 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3837 &pmac_id, if_id, dom);
3838
3839 if (!status && active_mac)
3840 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3841
3842 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3843}
3844
3845int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3846 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3847{
3848 struct be_mcc_wrb *wrb;
3849 struct be_cmd_req_set_hsw_config *req;
3850 void *ctxt;
3851 int status;
3852
3853 spin_lock_bh(&adapter->mcc_lock);
3854
3855 wrb = wrb_from_mccq(adapter);
3856 if (!wrb) {
3857 status = -EBUSY;
3858 goto err;
3859 }
3860
3861 req = embedded_payload(wrb);
3862 ctxt = &req->context;
3863
3864 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3865 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3866 NULL);
3867
3868 req->hdr.domain = domain;
3869 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3870 if (pvid) {
3871 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3872 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3873 }
3874 if (!BEx_chip(adapter) && hsw_mode) {
3875 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3876 ctxt, adapter->hba_port_num);
3877 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3878 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3879 ctxt, hsw_mode);
3880 }
3881
3882 /* Enable/disable both mac and vlan spoof checking */
3883 if (!BEx_chip(adapter) && spoofchk) {
3884 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3885 ctxt, spoofchk);
3886 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3887 ctxt, spoofchk);
3888 }
3889
3890 be_dws_cpu_to_le(req->context, sizeof(req->context));
3891 status = be_mcc_notify_wait(adapter);
3892
3893err:
3894 spin_unlock_bh(&adapter->mcc_lock);
3895 return status;
3896}
3897
3898/* Get Hyper switch config */
3899int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3900 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3901{
3902 struct be_mcc_wrb *wrb;
3903 struct be_cmd_req_get_hsw_config *req;
3904 void *ctxt;
3905 int status;
3906 u16 vid;
3907
3908 spin_lock_bh(&adapter->mcc_lock);
3909
3910 wrb = wrb_from_mccq(adapter);
3911 if (!wrb) {
3912 status = -EBUSY;
3913 goto err;
3914 }
3915
3916 req = embedded_payload(wrb);
3917 ctxt = &req->context;
3918
3919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3920 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3921 NULL);
3922
3923 req->hdr.domain = domain;
3924 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3925 ctxt, intf_id);
3926 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3927
3928 if (!BEx_chip(adapter) && mode) {
3929 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3930 ctxt, adapter->hba_port_num);
3931 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3932 }
3933 be_dws_cpu_to_le(req->context, sizeof(req->context));
3934
3935 status = be_mcc_notify_wait(adapter);
3936 if (!status) {
3937 struct be_cmd_resp_get_hsw_config *resp =
3938 embedded_payload(wrb);
3939
3940 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3941 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3942 pvid, &resp->context);
3943 if (pvid)
3944 *pvid = le16_to_cpu(vid);
3945 if (mode)
3946 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3947 port_fwd_type, &resp->context);
3948 if (spoofchk)
3949 *spoofchk =
3950 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3951 spoofchk, &resp->context);
3952 }
3953
3954err:
3955 spin_unlock_bh(&adapter->mcc_lock);
3956 return status;
3957}
3958
3959static bool be_is_wol_excluded(struct be_adapter *adapter)
3960{
3961 struct pci_dev *pdev = adapter->pdev;
3962
3963 if (be_virtfn(adapter))
3964 return true;
3965
3966 switch (pdev->subsystem_device) {
3967 case OC_SUBSYS_DEVICE_ID1:
3968 case OC_SUBSYS_DEVICE_ID2:
3969 case OC_SUBSYS_DEVICE_ID3:
3970 case OC_SUBSYS_DEVICE_ID4:
3971 return true;
3972 default:
3973 return false;
3974 }
3975}
3976
3977int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3978{
3979 struct be_mcc_wrb *wrb;
3980 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3981 int status = 0;
3982 struct be_dma_mem cmd;
3983
3984 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3985 CMD_SUBSYSTEM_ETH))
3986 return -EPERM;
3987
3988 if (be_is_wol_excluded(adapter))
3989 return status;
3990
3991 if (mutex_lock_interruptible(&adapter->mbox_lock))
3992 return -1;
3993
3994 memset(&cmd, 0, sizeof(struct be_dma_mem));
3995 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3996 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3997 GFP_ATOMIC);
3998 if (!cmd.va) {
3999 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4000 status = -ENOMEM;
4001 goto err;
4002 }
4003
4004 wrb = wrb_from_mbox(adapter);
4005 if (!wrb) {
4006 status = -EBUSY;
4007 goto err;
4008 }
4009
4010 req = cmd.va;
4011
4012 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4013 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4014 sizeof(*req), wrb, &cmd);
4015
4016 req->hdr.version = 1;
4017 req->query_options = BE_GET_WOL_CAP;
4018
4019 status = be_mbox_notify_wait(adapter);
4020 if (!status) {
4021 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4022
4023 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4024
4025 adapter->wol_cap = resp->wol_settings;
4026 if (adapter->wol_cap & BE_WOL_CAP)
4027 adapter->wol_en = true;
4028 }
4029err:
4030 mutex_unlock(&adapter->mbox_lock);
4031 if (cmd.va)
4032 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4033 cmd.dma);
4034 return status;
4035
4036}
4037
4038int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4039{
4040 struct be_dma_mem extfat_cmd;
4041 struct be_fat_conf_params *cfgs;
4042 int status;
4043 int i, j;
4044
4045 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4046 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4047 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4048 extfat_cmd.size, &extfat_cmd.dma,
4049 GFP_ATOMIC);
4050 if (!extfat_cmd.va)
4051 return -ENOMEM;
4052
4053 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4054 if (status)
4055 goto err;
4056
4057 cfgs = (struct be_fat_conf_params *)
4058 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4059 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4060 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4061
4062 for (j = 0; j < num_modes; j++) {
4063 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4064 cfgs->module[i].trace_lvl[j].dbg_lvl =
4065 cpu_to_le32(level);
4066 }
4067 }
4068
4069 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4070err:
4071 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4072 extfat_cmd.dma);
4073 return status;
4074}
4075
4076int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4077{
4078 struct be_dma_mem extfat_cmd;
4079 struct be_fat_conf_params *cfgs;
4080 int status, j;
4081 int level = 0;
4082
4083 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4084 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4085 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4086 extfat_cmd.size, &extfat_cmd.dma,
4087 GFP_ATOMIC);
4088
4089 if (!extfat_cmd.va) {
4090 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4091 __func__);
4092 goto err;
4093 }
4094
4095 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4096 if (!status) {
4097 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4098 sizeof(struct be_cmd_resp_hdr));
4099
4100 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4101 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4102 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4103 }
4104 }
4105 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4106 extfat_cmd.dma);
4107err:
4108 return level;
4109}
4110
4111int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4112 struct be_dma_mem *cmd)
4113{
4114 struct be_mcc_wrb *wrb;
4115 struct be_cmd_req_get_ext_fat_caps *req;
4116 int status;
4117
4118 if (mutex_lock_interruptible(&adapter->mbox_lock))
4119 return -1;
4120
4121 wrb = wrb_from_mbox(adapter);
4122 if (!wrb) {
4123 status = -EBUSY;
4124 goto err;
4125 }
4126
4127 req = cmd->va;
4128 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4129 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4130 cmd->size, wrb, cmd);
4131 req->parameter_type = cpu_to_le32(1);
4132
4133 status = be_mbox_notify_wait(adapter);
4134err:
4135 mutex_unlock(&adapter->mbox_lock);
4136 return status;
4137}
4138
4139int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4140 struct be_dma_mem *cmd,
4141 struct be_fat_conf_params *configs)
4142{
4143 struct be_mcc_wrb *wrb;
4144 struct be_cmd_req_set_ext_fat_caps *req;
4145 int status;
4146
4147 spin_lock_bh(&adapter->mcc_lock);
4148
4149 wrb = wrb_from_mccq(adapter);
4150 if (!wrb) {
4151 status = -EBUSY;
4152 goto err;
4153 }
4154
4155 req = cmd->va;
4156 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4157 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4158 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4159 cmd->size, wrb, cmd);
4160
4161 status = be_mcc_notify_wait(adapter);
4162err:
4163 spin_unlock_bh(&adapter->mcc_lock);
4164 return status;
4165}
4166
4167int be_cmd_query_port_name(struct be_adapter *adapter)
4168{
4169 struct be_cmd_req_get_port_name *req;
4170 struct be_mcc_wrb *wrb;
4171 int status;
4172
4173 if (mutex_lock_interruptible(&adapter->mbox_lock))
4174 return -1;
4175
4176 wrb = wrb_from_mbox(adapter);
4177 req = embedded_payload(wrb);
4178
4179 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4180 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4181 NULL);
4182 if (!BEx_chip(adapter))
4183 req->hdr.version = 1;
4184
4185 status = be_mbox_notify_wait(adapter);
4186 if (!status) {
4187 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4188
4189 adapter->port_name = resp->port_name[adapter->hba_port_num];
4190 } else {
4191 adapter->port_name = adapter->hba_port_num + '0';
4192 }
4193
4194 mutex_unlock(&adapter->mbox_lock);
4195 return status;
4196}
4197
4198/* When more than 1 NIC descriptor is present in the descriptor list,
4199 * the caller must specify the pf_num to obtain the NIC descriptor
4200 * corresponding to its pci function.
4201 * get_vft must be true when the caller wants the VF-template desc of the
4202 * PF-pool.
4203 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4204 * that only it's NIC descriptor is present in the descriptor list.
4205 */
4206static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4207 bool get_vft, u8 pf_num)
4208{
4209 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4210 struct be_nic_res_desc *nic;
4211 int i;
4212
4213 for (i = 0; i < desc_count; i++) {
4214 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4215 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4216 nic = (struct be_nic_res_desc *)hdr;
4217
4218 if ((pf_num == PF_NUM_IGNORE ||
4219 nic->pf_num == pf_num) &&
4220 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4221 return nic;
4222 }
4223 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4224 hdr = (void *)hdr + hdr->desc_len;
4225 }
4226 return NULL;
4227}
4228
4229static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4230 u8 pf_num)
4231{
4232 return be_get_nic_desc(buf, desc_count, true, pf_num);
4233}
4234
4235static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4236 u8 pf_num)
4237{
4238 return be_get_nic_desc(buf, desc_count, false, pf_num);
4239}
4240
4241static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4242 u8 pf_num)
4243{
4244 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4245 struct be_pcie_res_desc *pcie;
4246 int i;
4247
4248 for (i = 0; i < desc_count; i++) {
4249 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4250 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4251 pcie = (struct be_pcie_res_desc *)hdr;
4252 if (pcie->pf_num == pf_num)
4253 return pcie;
4254 }
4255
4256 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4257 hdr = (void *)hdr + hdr->desc_len;
4258 }
4259 return NULL;
4260}
4261
4262static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4263{
4264 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4265 int i;
4266
4267 for (i = 0; i < desc_count; i++) {
4268 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4269 return (struct be_port_res_desc *)hdr;
4270
4271 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4272 hdr = (void *)hdr + hdr->desc_len;
4273 }
4274 return NULL;
4275}
4276
4277static void be_copy_nic_desc(struct be_resources *res,
4278 struct be_nic_res_desc *desc)
4279{
4280 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4281 res->max_vlans = le16_to_cpu(desc->vlan_count);
4282 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4283 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4284 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4285 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4286 res->max_evt_qs = le16_to_cpu(desc->eq_count);
4287 res->max_cq_count = le16_to_cpu(desc->cq_count);
4288 res->max_iface_count = le16_to_cpu(desc->iface_count);
4289 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4290 /* Clear flags that driver is not interested in */
4291 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4292 BE_IF_CAP_FLAGS_WANT;
4293}
4294
4295/* Uses Mbox */
4296int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4297{
4298 struct be_mcc_wrb *wrb;
4299 struct be_cmd_req_get_func_config *req;
4300 int status;
4301 struct be_dma_mem cmd;
4302
4303 if (mutex_lock_interruptible(&adapter->mbox_lock))
4304 return -1;
4305
4306 memset(&cmd, 0, sizeof(struct be_dma_mem));
4307 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4308 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4309 GFP_ATOMIC);
4310 if (!cmd.va) {
4311 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4312 status = -ENOMEM;
4313 goto err;
4314 }
4315
4316 wrb = wrb_from_mbox(adapter);
4317 if (!wrb) {
4318 status = -EBUSY;
4319 goto err;
4320 }
4321
4322 req = cmd.va;
4323
4324 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4325 OPCODE_COMMON_GET_FUNC_CONFIG,
4326 cmd.size, wrb, &cmd);
4327
4328 if (skyhawk_chip(adapter))
4329 req->hdr.version = 1;
4330
4331 status = be_mbox_notify_wait(adapter);
4332 if (!status) {
4333 struct be_cmd_resp_get_func_config *resp = cmd.va;
4334 u32 desc_count = le32_to_cpu(resp->desc_count);
4335 struct be_nic_res_desc *desc;
4336
4337 /* GET_FUNC_CONFIG returns resource descriptors of the
4338 * current function only. So, pf_num should be set to
4339 * PF_NUM_IGNORE.
4340 */
4341 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4342 PF_NUM_IGNORE);
4343 if (!desc) {
4344 status = -EINVAL;
4345 goto err;
4346 }
4347
4348 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4349 adapter->pf_num = desc->pf_num;
4350 adapter->vf_num = desc->vf_num;
4351
4352 if (res)
4353 be_copy_nic_desc(res, desc);
4354 }
4355err:
4356 mutex_unlock(&adapter->mbox_lock);
4357 if (cmd.va)
4358 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4359 cmd.dma);
4360 return status;
4361}
4362
4363/* Will use MBOX only if MCCQ has not been created */
4364int be_cmd_get_profile_config(struct be_adapter *adapter,
4365 struct be_resources *res, u8 query, u8 domain)
4366{
4367 struct be_cmd_resp_get_profile_config *resp;
4368 struct be_cmd_req_get_profile_config *req;
4369 struct be_nic_res_desc *vf_res;
4370 struct be_pcie_res_desc *pcie;
4371 struct be_port_res_desc *port;
4372 struct be_nic_res_desc *nic;
4373 struct be_mcc_wrb wrb = {0};
4374 struct be_dma_mem cmd;
4375 u16 desc_count;
4376 int status;
4377
4378 memset(&cmd, 0, sizeof(struct be_dma_mem));
4379 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4380 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4381 GFP_ATOMIC);
4382 if (!cmd.va)
4383 return -ENOMEM;
4384
4385 req = cmd.va;
4386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4387 OPCODE_COMMON_GET_PROFILE_CONFIG,
4388 cmd.size, &wrb, &cmd);
4389
4390 if (!lancer_chip(adapter))
4391 req->hdr.version = 1;
4392 req->type = ACTIVE_PROFILE_TYPE;
4393 req->hdr.domain = domain;
4394
4395 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4396 * descriptors with all bits set to "1" for the fields which can be
4397 * modified using SET_PROFILE_CONFIG cmd.
4398 */
4399 if (query == RESOURCE_MODIFIABLE)
4400 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4401
4402 status = be_cmd_notify_wait(adapter, &wrb);
4403 if (status)
4404 goto err;
4405
4406 resp = cmd.va;
4407 desc_count = le16_to_cpu(resp->desc_count);
4408
4409 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4410 adapter->pf_num);
4411 if (pcie)
4412 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4413
4414 port = be_get_port_desc(resp->func_param, desc_count);
4415 if (port)
4416 adapter->mc_type = port->mc_type;
4417
4418 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4419 adapter->pf_num);
4420 if (nic)
4421 be_copy_nic_desc(res, nic);
4422
4423 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4424 adapter->pf_num);
4425 if (vf_res)
4426 res->vf_if_cap_flags = vf_res->cap_flags;
4427err:
4428 if (cmd.va)
4429 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4430 cmd.dma);
4431 return status;
4432}
4433
4434/* Will use MBOX only if MCCQ has not been created */
4435static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4436 int size, int count, u8 version, u8 domain)
4437{
4438 struct be_cmd_req_set_profile_config *req;
4439 struct be_mcc_wrb wrb = {0};
4440 struct be_dma_mem cmd;
4441 int status;
4442
4443 memset(&cmd, 0, sizeof(struct be_dma_mem));
4444 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4445 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4446 GFP_ATOMIC);
4447 if (!cmd.va)
4448 return -ENOMEM;
4449
4450 req = cmd.va;
4451 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4452 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4453 &wrb, &cmd);
4454 req->hdr.version = version;
4455 req->hdr.domain = domain;
4456 req->desc_count = cpu_to_le32(count);
4457 memcpy(req->desc, desc, size);
4458
4459 status = be_cmd_notify_wait(adapter, &wrb);
4460
4461 if (cmd.va)
4462 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4463 cmd.dma);
4464 return status;
4465}
4466
4467/* Mark all fields invalid */
4468static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4469{
4470 memset(nic, 0, sizeof(*nic));
4471 nic->unicast_mac_count = 0xFFFF;
4472 nic->mcc_count = 0xFFFF;
4473 nic->vlan_count = 0xFFFF;
4474 nic->mcast_mac_count = 0xFFFF;
4475 nic->txq_count = 0xFFFF;
4476 nic->rq_count = 0xFFFF;
4477 nic->rssq_count = 0xFFFF;
4478 nic->lro_count = 0xFFFF;
4479 nic->cq_count = 0xFFFF;
4480 nic->toe_conn_count = 0xFFFF;
4481 nic->eq_count = 0xFFFF;
4482 nic->iface_count = 0xFFFF;
4483 nic->link_param = 0xFF;
4484 nic->channel_id_param = cpu_to_le16(0xF000);
4485 nic->acpi_params = 0xFF;
4486 nic->wol_param = 0x0F;
4487 nic->tunnel_iface_count = 0xFFFF;
4488 nic->direct_tenant_iface_count = 0xFFFF;
4489 nic->bw_min = 0xFFFFFFFF;
4490 nic->bw_max = 0xFFFFFFFF;
4491}
4492
4493/* Mark all fields invalid */
4494static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4495{
4496 memset(pcie, 0, sizeof(*pcie));
4497 pcie->sriov_state = 0xFF;
4498 pcie->pf_state = 0xFF;
4499 pcie->pf_type = 0xFF;
4500 pcie->num_vfs = 0xFFFF;
4501}
4502
4503int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4504 u8 domain)
4505{
4506 struct be_nic_res_desc nic_desc;
4507 u32 bw_percent;
4508 u16 version = 0;
4509
4510 if (BE3_chip(adapter))
4511 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4512
4513 be_reset_nic_desc(&nic_desc);
4514 nic_desc.pf_num = adapter->pf_num;
4515 nic_desc.vf_num = domain;
4516 nic_desc.bw_min = 0;
4517 if (lancer_chip(adapter)) {
4518 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4519 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4520 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4521 (1 << NOSV_SHIFT);
4522 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4523 } else {
4524 version = 1;
4525 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4526 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4527 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4528 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4529 nic_desc.bw_max = cpu_to_le32(bw_percent);
4530 }
4531
4532 return be_cmd_set_profile_config(adapter, &nic_desc,
4533 nic_desc.hdr.desc_len,
4534 1, version, domain);
4535}
4536
4537static void be_fill_vf_res_template(struct be_adapter *adapter,
4538 struct be_resources pool_res,
4539 u16 num_vfs, u16 num_vf_qs,
4540 struct be_nic_res_desc *nic_vft)
4541{
4542 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
4543 struct be_resources res_mod = {0};
4544
4545 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
4546 * which are modifiable using SET_PROFILE_CONFIG cmd.
4547 */
4548 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
4549
4550 /* If RSS IFACE capability flags are modifiable for a VF, set the
4551 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
4552 * more than 1 RSSQ is available for a VF.
4553 * Otherwise, provision only 1 queue pair for VF.
4554 */
4555 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
4556 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4557 if (num_vf_qs > 1) {
4558 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
4559 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
4560 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
4561 } else {
4562 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
4563 BE_IF_FLAGS_DEFQ_RSS);
4564 }
4565 } else {
4566 num_vf_qs = 1;
4567 }
4568
4569 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
4570 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4571 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
4572 }
4573
4574 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
4575 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
4576 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
4577 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
4578 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
4579 (num_vfs + 1));
4580
4581 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
4582 * among the PF and it's VFs, if the fields are changeable
4583 */
4584 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
4585 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
4586 (num_vfs + 1));
4587
4588 if (res_mod.max_vlans == FIELD_MODIFIABLE)
4589 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
4590 (num_vfs + 1));
4591
4592 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
4593 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
4594 (num_vfs + 1));
4595
4596 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
4597 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
4598 (num_vfs + 1));
4599}
4600
4601int be_cmd_set_sriov_config(struct be_adapter *adapter,
4602 struct be_resources pool_res, u16 num_vfs,
4603 u16 num_vf_qs)
4604{
4605 struct {
4606 struct be_pcie_res_desc pcie;
4607 struct be_nic_res_desc nic_vft;
4608 } __packed desc;
4609
4610 /* PF PCIE descriptor */
4611 be_reset_pcie_desc(&desc.pcie);
4612 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4613 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4614 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4615 desc.pcie.pf_num = adapter->pdev->devfn;
4616 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4617 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4618
4619 /* VF NIC Template descriptor */
4620 be_reset_nic_desc(&desc.nic_vft);
4621 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4622 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4623 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4624 desc.nic_vft.pf_num = adapter->pdev->devfn;
4625 desc.nic_vft.vf_num = 0;
4626
4627 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4628 &desc.nic_vft);
4629
4630 return be_cmd_set_profile_config(adapter, &desc,
4631 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4632}
4633
4634int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4635{
4636 struct be_mcc_wrb *wrb;
4637 struct be_cmd_req_manage_iface_filters *req;
4638 int status;
4639
4640 if (iface == 0xFFFFFFFF)
4641 return -1;
4642
4643 spin_lock_bh(&adapter->mcc_lock);
4644
4645 wrb = wrb_from_mccq(adapter);
4646 if (!wrb) {
4647 status = -EBUSY;
4648 goto err;
4649 }
4650 req = embedded_payload(wrb);
4651
4652 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4653 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4654 wrb, NULL);
4655 req->op = op;
4656 req->target_iface_id = cpu_to_le32(iface);
4657
4658 status = be_mcc_notify_wait(adapter);
4659err:
4660 spin_unlock_bh(&adapter->mcc_lock);
4661 return status;
4662}
4663
4664int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4665{
4666 struct be_port_res_desc port_desc;
4667
4668 memset(&port_desc, 0, sizeof(port_desc));
4669 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4670 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4671 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4672 port_desc.link_num = adapter->hba_port_num;
4673 if (port) {
4674 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4675 (1 << RCVID_SHIFT);
4676 port_desc.nv_port = swab16(port);
4677 } else {
4678 port_desc.nv_flags = NV_TYPE_DISABLED;
4679 port_desc.nv_port = 0;
4680 }
4681
4682 return be_cmd_set_profile_config(adapter, &port_desc,
4683 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4684}
4685
4686int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4687 int vf_num)
4688{
4689 struct be_mcc_wrb *wrb;
4690 struct be_cmd_req_get_iface_list *req;
4691 struct be_cmd_resp_get_iface_list *resp;
4692 int status;
4693
4694 spin_lock_bh(&adapter->mcc_lock);
4695
4696 wrb = wrb_from_mccq(adapter);
4697 if (!wrb) {
4698 status = -EBUSY;
4699 goto err;
4700 }
4701 req = embedded_payload(wrb);
4702
4703 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4704 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4705 wrb, NULL);
4706 req->hdr.domain = vf_num + 1;
4707
4708 status = be_mcc_notify_wait(adapter);
4709 if (!status) {
4710 resp = (struct be_cmd_resp_get_iface_list *)req;
4711 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4712 }
4713
4714err:
4715 spin_unlock_bh(&adapter->mcc_lock);
4716 return status;
4717}
4718
4719static int lancer_wait_idle(struct be_adapter *adapter)
4720{
4721#define SLIPORT_IDLE_TIMEOUT 30
4722 u32 reg_val;
4723 int status = 0, i;
4724
4725 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4726 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4727 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4728 break;
4729
4730 ssleep(1);
4731 }
4732
4733 if (i == SLIPORT_IDLE_TIMEOUT)
4734 status = -1;
4735
4736 return status;
4737}
4738
4739int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4740{
4741 int status = 0;
4742
4743 status = lancer_wait_idle(adapter);
4744 if (status)
4745 return status;
4746
4747 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4748
4749 return status;
4750}
4751
4752/* Routine to check whether dump image is present or not */
4753bool dump_present(struct be_adapter *adapter)
4754{
4755 u32 sliport_status = 0;
4756
4757 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4758 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4759}
4760
4761int lancer_initiate_dump(struct be_adapter *adapter)
4762{
4763 struct device *dev = &adapter->pdev->dev;
4764 int status;
4765
4766 if (dump_present(adapter)) {
4767 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4768 return -EEXIST;
4769 }
4770
4771 /* give firmware reset and diagnostic dump */
4772 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4773 PHYSDEV_CONTROL_DD_MASK);
4774 if (status < 0) {
4775 dev_err(dev, "FW reset failed\n");
4776 return status;
4777 }
4778
4779 status = lancer_wait_idle(adapter);
4780 if (status)
4781 return status;
4782
4783 if (!dump_present(adapter)) {
4784 dev_err(dev, "FW dump not generated\n");
4785 return -EIO;
4786 }
4787
4788 return 0;
4789}
4790
4791int lancer_delete_dump(struct be_adapter *adapter)
4792{
4793 int status;
4794
4795 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4796 return be_cmd_status(status);
4797}
4798
4799/* Uses sync mcc */
4800int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4801{
4802 struct be_mcc_wrb *wrb;
4803 struct be_cmd_enable_disable_vf *req;
4804 int status;
4805
4806 if (BEx_chip(adapter))
4807 return 0;
4808
4809 spin_lock_bh(&adapter->mcc_lock);
4810
4811 wrb = wrb_from_mccq(adapter);
4812 if (!wrb) {
4813 status = -EBUSY;
4814 goto err;
4815 }
4816
4817 req = embedded_payload(wrb);
4818
4819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4820 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4821 wrb, NULL);
4822
4823 req->hdr.domain = domain;
4824 req->enable = 1;
4825 status = be_mcc_notify_wait(adapter);
4826err:
4827 spin_unlock_bh(&adapter->mcc_lock);
4828 return status;
4829}
4830
4831int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4832{
4833 struct be_mcc_wrb *wrb;
4834 struct be_cmd_req_intr_set *req;
4835 int status;
4836
4837 if (mutex_lock_interruptible(&adapter->mbox_lock))
4838 return -1;
4839
4840 wrb = wrb_from_mbox(adapter);
4841
4842 req = embedded_payload(wrb);
4843
4844 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4845 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4846 wrb, NULL);
4847
4848 req->intr_enabled = intr_enable;
4849
4850 status = be_mbox_notify_wait(adapter);
4851
4852 mutex_unlock(&adapter->mbox_lock);
4853 return status;
4854}
4855
4856/* Uses MBOX */
4857int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4858{
4859 struct be_cmd_req_get_active_profile *req;
4860 struct be_mcc_wrb *wrb;
4861 int status;
4862
4863 if (mutex_lock_interruptible(&adapter->mbox_lock))
4864 return -1;
4865
4866 wrb = wrb_from_mbox(adapter);
4867 if (!wrb) {
4868 status = -EBUSY;
4869 goto err;
4870 }
4871
4872 req = embedded_payload(wrb);
4873
4874 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4875 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4876 wrb, NULL);
4877
4878 status = be_mbox_notify_wait(adapter);
4879 if (!status) {
4880 struct be_cmd_resp_get_active_profile *resp =
4881 embedded_payload(wrb);
4882
4883 *profile_id = le16_to_cpu(resp->active_profile_id);
4884 }
4885
4886err:
4887 mutex_unlock(&adapter->mbox_lock);
4888 return status;
4889}
4890
4891int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4892 int link_state, int version, u8 domain)
4893{
4894 struct be_mcc_wrb *wrb;
4895 struct be_cmd_req_set_ll_link *req;
4896 int status;
4897
4898 spin_lock_bh(&adapter->mcc_lock);
4899
4900 wrb = wrb_from_mccq(adapter);
4901 if (!wrb) {
4902 status = -EBUSY;
4903 goto err;
4904 }
4905
4906 req = embedded_payload(wrb);
4907
4908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4909 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4910 sizeof(*req), wrb, NULL);
4911
4912 req->hdr.version = version;
4913 req->hdr.domain = domain;
4914
4915 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4916 link_state == IFLA_VF_LINK_STATE_AUTO)
4917 req->link_config |= PLINK_ENABLE;
4918
4919 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4920 req->link_config |= PLINK_TRACK;
4921
4922 status = be_mcc_notify_wait(adapter);
4923err:
4924 spin_unlock_bh(&adapter->mcc_lock);
4925 return status;
4926}
4927
4928int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4929 int link_state, u8 domain)
4930{
4931 int status;
4932
4933 if (BEx_chip(adapter))
4934 return -EOPNOTSUPP;
4935
4936 status = __be_cmd_set_logical_link_config(adapter, link_state,
4937 2, domain);
4938
4939 /* Version 2 of the command will not be recognized by older FW.
4940 * On such a failure issue version 1 of the command.
4941 */
4942 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4943 status = __be_cmd_set_logical_link_config(adapter, link_state,
4944 1, domain);
4945 return status;
4946}
4947int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4948 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4949{
4950 struct be_adapter *adapter = netdev_priv(netdev_handle);
4951 struct be_mcc_wrb *wrb;
4952 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4953 struct be_cmd_req_hdr *req;
4954 struct be_cmd_resp_hdr *resp;
4955 int status;
4956
4957 spin_lock_bh(&adapter->mcc_lock);
4958
4959 wrb = wrb_from_mccq(adapter);
4960 if (!wrb) {
4961 status = -EBUSY;
4962 goto err;
4963 }
4964 req = embedded_payload(wrb);
4965 resp = embedded_payload(wrb);
4966
4967 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4968 hdr->opcode, wrb_payload_size, wrb, NULL);
4969 memcpy(req, wrb_payload, wrb_payload_size);
4970 be_dws_cpu_to_le(req, wrb_payload_size);
4971
4972 status = be_mcc_notify_wait(adapter);
4973 if (cmd_status)
4974 *cmd_status = (status & 0xffff);
4975 if (ext_status)
4976 *ext_status = 0;
4977 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4978 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4979err:
4980 spin_unlock_bh(&adapter->mcc_lock);
4981 return status;
4982}
4983EXPORT_SYMBOL(be_roce_mcc_cmd);