Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
3 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 *
5 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
6 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
7 * Copyright (C) 2004 Sun Microsystems Inc.
8 * Copyright (C) 2007-2016 Broadcom Corporation.
9 * Copyright (C) 2016-2017 Broadcom Limited.
10 */
11
12#ifndef _T3_H
13#define _T3_H
14
15#define TG3_64BIT_REG_HIGH 0x00UL
16#define TG3_64BIT_REG_LOW 0x04UL
17
18/* Descriptor block info. */
19#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
20#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
21#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
22#define BDINFO_FLAGS_DISABLED 0x00000002
23#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
24#define BDINFO_FLAGS_MAXLEN_SHIFT 16
25#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
26#define TG3_BDINFO_SIZE 0x10UL
27
28#define TG3_RX_STD_MAX_SIZE_5700 512
29#define TG3_RX_STD_MAX_SIZE_5717 2048
30#define TG3_RX_JMB_MAX_SIZE_5700 256
31#define TG3_RX_JMB_MAX_SIZE_5717 1024
32#define TG3_RX_RET_MAX_SIZE_5700 1024
33#define TG3_RX_RET_MAX_SIZE_5705 512
34#define TG3_RX_RET_MAX_SIZE_5717 4096
35
36#define TG3_RSS_INDIR_TBL_SIZE 128
37
38/* First 256 bytes are a mirror of PCI config space. */
39#define TG3PCI_VENDOR 0x00000000
40#define TG3PCI_VENDOR_BROADCOM 0x14e4
41#define TG3PCI_DEVICE 0x00000002
42#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
43#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
44#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
45#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
46#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
47#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
48#define TG3PCI_DEVICE_TIGON3_57780 0x1692
49#define TG3PCI_DEVICE_TIGON3_5787M 0x1693
50#define TG3PCI_DEVICE_TIGON3_57760 0x1690
51#define TG3PCI_DEVICE_TIGON3_57790 0x1694
52#define TG3PCI_DEVICE_TIGON3_57788 0x1691
53#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
54#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
55#define TG3PCI_DEVICE_TIGON3_5717 0x1655
56#define TG3PCI_DEVICE_TIGON3_5717_C 0x1665
57#define TG3PCI_DEVICE_TIGON3_5718 0x1656
58#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
59#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
60#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
61#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
62#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
63#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
64#define TG3PCI_DEVICE_TIGON3_5719 0x1657
65#define TG3PCI_DEVICE_TIGON3_5720 0x165f
66#define TG3PCI_DEVICE_TIGON3_57762 0x1682
67#define TG3PCI_DEVICE_TIGON3_57766 0x1686
68#define TG3PCI_DEVICE_TIGON3_57786 0x16b3
69#define TG3PCI_DEVICE_TIGON3_57782 0x16b7
70#define TG3PCI_DEVICE_TIGON3_5762 0x1687
71#define TG3PCI_DEVICE_TIGON3_5725 0x1643
72#define TG3PCI_DEVICE_TIGON3_5727 0x16f3
73#define TG3PCI_DEVICE_TIGON3_57764 0x1642
74#define TG3PCI_DEVICE_TIGON3_57767 0x1683
75#define TG3PCI_DEVICE_TIGON3_57787 0x1641
76/* 0x04 --> 0x2c unused */
77#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
78#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
79#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
80#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
81#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
82#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
83#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
84#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
85#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
86#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
87#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
88#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
89#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
90#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
91#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
92#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
93#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
94#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
95#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
96#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
97#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
98#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
99#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
100#define TG3PCI_SUBDEVICE_ID_DELL_5762 0x07f0
101#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
102#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
103#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
104#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
105#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
106#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
107#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
108#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
109#define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601
110#define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612
111#define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056
112
113/* 0x30 --> 0x64 unused */
114#define TG3PCI_MSI_DATA 0x00000064
115/* 0x66 --> 0x68 unused */
116#define TG3PCI_MISC_HOST_CTRL 0x00000068
117#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
118#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
119#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
120#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
121#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
122#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
123#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
124#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
125#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
126#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
127#define MISC_HOST_CTRL_CHIPREV 0xffff0000
128#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
129
130#define CHIPREV_ID_5700_A0 0x7000
131#define CHIPREV_ID_5700_A1 0x7001
132#define CHIPREV_ID_5700_B0 0x7100
133#define CHIPREV_ID_5700_B1 0x7101
134#define CHIPREV_ID_5700_B3 0x7102
135#define CHIPREV_ID_5700_ALTIMA 0x7104
136#define CHIPREV_ID_5700_C0 0x7200
137#define CHIPREV_ID_5701_A0 0x0000
138#define CHIPREV_ID_5701_B0 0x0100
139#define CHIPREV_ID_5701_B2 0x0102
140#define CHIPREV_ID_5701_B5 0x0105
141#define CHIPREV_ID_5703_A0 0x1000
142#define CHIPREV_ID_5703_A1 0x1001
143#define CHIPREV_ID_5703_A2 0x1002
144#define CHIPREV_ID_5703_A3 0x1003
145#define CHIPREV_ID_5704_A0 0x2000
146#define CHIPREV_ID_5704_A1 0x2001
147#define CHIPREV_ID_5704_A2 0x2002
148#define CHIPREV_ID_5704_A3 0x2003
149#define CHIPREV_ID_5705_A0 0x3000
150#define CHIPREV_ID_5705_A1 0x3001
151#define CHIPREV_ID_5705_A2 0x3002
152#define CHIPREV_ID_5705_A3 0x3003
153#define CHIPREV_ID_5750_A0 0x4000
154#define CHIPREV_ID_5750_A1 0x4001
155#define CHIPREV_ID_5750_A3 0x4003
156#define CHIPREV_ID_5750_C2 0x4202
157#define CHIPREV_ID_5752_A0_HW 0x5000
158#define CHIPREV_ID_5752_A0 0x6000
159#define CHIPREV_ID_5752_A1 0x6001
160#define CHIPREV_ID_5714_A2 0x9002
161#define CHIPREV_ID_5906_A1 0xc001
162#define CHIPREV_ID_57780_A0 0x57780000
163#define CHIPREV_ID_57780_A1 0x57780001
164#define CHIPREV_ID_5717_A0 0x05717000
165#define CHIPREV_ID_5717_C0 0x05717200
166#define CHIPREV_ID_57765_A0 0x57785000
167#define CHIPREV_ID_5719_A0 0x05719000
168#define CHIPREV_ID_5720_A0 0x05720000
169#define CHIPREV_ID_5762_A0 0x05762000
170
171#define ASIC_REV_5700 0x07
172#define ASIC_REV_5701 0x00
173#define ASIC_REV_5703 0x01
174#define ASIC_REV_5704 0x02
175#define ASIC_REV_5705 0x03
176#define ASIC_REV_5750 0x04
177#define ASIC_REV_5752 0x06
178#define ASIC_REV_5780 0x08
179#define ASIC_REV_5714 0x09
180#define ASIC_REV_5755 0x0a
181#define ASIC_REV_5787 0x0b
182#define ASIC_REV_5906 0x0c
183#define ASIC_REV_USE_PROD_ID_REG 0x0f
184#define ASIC_REV_5784 0x5784
185#define ASIC_REV_5761 0x5761
186#define ASIC_REV_5785 0x5785
187#define ASIC_REV_57780 0x57780
188#define ASIC_REV_5717 0x5717
189#define ASIC_REV_57765 0x57785
190#define ASIC_REV_5719 0x5719
191#define ASIC_REV_5720 0x5720
192#define ASIC_REV_57766 0x57766
193#define ASIC_REV_5762 0x5762
194#define CHIPREV_5700_AX 0x70
195#define CHIPREV_5700_BX 0x71
196#define CHIPREV_5700_CX 0x72
197#define CHIPREV_5701_AX 0x00
198#define CHIPREV_5703_AX 0x10
199#define CHIPREV_5704_AX 0x20
200#define CHIPREV_5704_BX 0x21
201#define CHIPREV_5750_AX 0x40
202#define CHIPREV_5750_BX 0x41
203#define CHIPREV_5784_AX 0x57840
204#define CHIPREV_5761_AX 0x57610
205#define CHIPREV_57765_AX 0x577650
206#define METAL_REV_A0 0x00
207#define METAL_REV_A1 0x01
208#define METAL_REV_B0 0x00
209#define METAL_REV_B1 0x01
210#define METAL_REV_B2 0x02
211#define TG3PCI_DMA_RW_CTRL 0x0000006c
212#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
213#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
214#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
215#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
216#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
217#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
218#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
219#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
220#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
221#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
222#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
223#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
224#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
225#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
226#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
227#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
228#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
229#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
230#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
231#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
232#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
233#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
234#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
235#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
236#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
237#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
238#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
239#define DMA_RWCTRL_ONE_DMA 0x00004000
240#define DMA_RWCTRL_READ_WATER 0x00070000
241#define DMA_RWCTRL_READ_WATER_SHIFT 16
242#define DMA_RWCTRL_WRITE_WATER 0x00380000
243#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
244#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
245#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
246#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
247#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
248#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
249#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
250#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
251#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
252#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
253#define TG3PCI_PCISTATE 0x00000070
254#define PCISTATE_FORCE_RESET 0x00000001
255#define PCISTATE_INT_NOT_ACTIVE 0x00000002
256#define PCISTATE_CONV_PCI_MODE 0x00000004
257#define PCISTATE_BUS_SPEED_HIGH 0x00000008
258#define PCISTATE_BUS_32BIT 0x00000010
259#define PCISTATE_ROM_ENABLE 0x00000020
260#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
261#define PCISTATE_FLAT_VIEW 0x00000100
262#define PCISTATE_RETRY_SAME_DMA 0x00002000
263#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
264#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
265#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
266#define TG3PCI_CLOCK_CTRL 0x00000074
267#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
268#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
269#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
270#define CLOCK_CTRL_ALTCLK 0x00001000
271#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
272#define CLOCK_CTRL_44MHZ_CORE 0x00040000
273#define CLOCK_CTRL_625_CORE 0x00100000
274#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
275#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
276#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
277#define TG3PCI_REG_BASE_ADDR 0x00000078
278#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
279#define TG3PCI_REG_DATA 0x00000080
280#define TG3PCI_MEM_WIN_DATA 0x00000084
281#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
282/* 0x94 --> 0x98 unused */
283#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
284#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
285/* 0xa8 --> 0xb8 unused */
286#define TG3PCI_DEV_STATUS_CTRL 0x000000b4
287#define MAX_READ_REQ_SIZE_2048 0x00004000
288#define MAX_READ_REQ_MASK 0x00007000
289#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
290#define DUAL_MAC_CTRL_CH_MASK 0x00000003
291#define DUAL_MAC_CTRL_ID 0x00000004
292#define TG3PCI_PRODID_ASICREV 0x000000bc
293#define PROD_ID_ASIC_REV_MASK 0x0fffffff
294/* 0xc0 --> 0xf4 unused */
295
296#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
297#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
298/* 0xf8 --> 0x200 unused */
299
300#define TG3_CORR_ERR_STAT 0x00000110
301#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
302/* 0x114 --> 0x200 unused */
303
304/* Mailbox registers */
305#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
306#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
307#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
308#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
309#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
310#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
311#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
312#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
313#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
314#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
315#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
316#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
317#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
318#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
319#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
320 TG3_64BIT_REG_LOW)
321#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
322#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
323 TG3_64BIT_REG_LOW)
324#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
325#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
326#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
327#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
328#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
329#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
330#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
331#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
332#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
333#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
334#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
335#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
336#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
337#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
338#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
339#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
340#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
341#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
342#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
343#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
344#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
345#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
346#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
347#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
348#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
349#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
350#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
351#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
352#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
353#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
354#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
355#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
356#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
357#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
358#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
359#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
360#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
361#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
362#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
363#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
364#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
365#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
366#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
367#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
368#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
369#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
370#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
371#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
372#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
373
374/* MAC control registers */
375#define MAC_MODE 0x00000400
376#define MAC_MODE_RESET 0x00000001
377#define MAC_MODE_HALF_DUPLEX 0x00000002
378#define MAC_MODE_PORT_MODE_MASK 0x0000000c
379#define MAC_MODE_PORT_MODE_TBI 0x0000000c
380#define MAC_MODE_PORT_MODE_GMII 0x00000008
381#define MAC_MODE_PORT_MODE_MII 0x00000004
382#define MAC_MODE_PORT_MODE_NONE 0x00000000
383#define MAC_MODE_PORT_INT_LPBACK 0x00000010
384#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
385#define MAC_MODE_TX_BURSTING 0x00000100
386#define MAC_MODE_MAX_DEFER 0x00000200
387#define MAC_MODE_LINK_POLARITY 0x00000400
388#define MAC_MODE_RXSTAT_ENABLE 0x00000800
389#define MAC_MODE_RXSTAT_CLEAR 0x00001000
390#define MAC_MODE_RXSTAT_FLUSH 0x00002000
391#define MAC_MODE_TXSTAT_ENABLE 0x00004000
392#define MAC_MODE_TXSTAT_CLEAR 0x00008000
393#define MAC_MODE_TXSTAT_FLUSH 0x00010000
394#define MAC_MODE_SEND_CONFIGS 0x00020000
395#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
396#define MAC_MODE_ACPI_ENABLE 0x00080000
397#define MAC_MODE_MIP_ENABLE 0x00100000
398#define MAC_MODE_TDE_ENABLE 0x00200000
399#define MAC_MODE_RDE_ENABLE 0x00400000
400#define MAC_MODE_FHDE_ENABLE 0x00800000
401#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
402#define MAC_MODE_APE_RX_EN 0x08000000
403#define MAC_MODE_APE_TX_EN 0x10000000
404#define MAC_STATUS 0x00000404
405#define MAC_STATUS_PCS_SYNCED 0x00000001
406#define MAC_STATUS_SIGNAL_DET 0x00000002
407#define MAC_STATUS_RCVD_CFG 0x00000004
408#define MAC_STATUS_CFG_CHANGED 0x00000008
409#define MAC_STATUS_SYNC_CHANGED 0x00000010
410#define MAC_STATUS_PORT_DEC_ERR 0x00000400
411#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
412#define MAC_STATUS_MI_COMPLETION 0x00400000
413#define MAC_STATUS_MI_INTERRUPT 0x00800000
414#define MAC_STATUS_AP_ERROR 0x01000000
415#define MAC_STATUS_ODI_ERROR 0x02000000
416#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
417#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
418#define MAC_EVENT 0x00000408
419#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
420#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
421#define MAC_EVENT_MI_COMPLETION 0x00400000
422#define MAC_EVENT_MI_INTERRUPT 0x00800000
423#define MAC_EVENT_AP_ERROR 0x01000000
424#define MAC_EVENT_ODI_ERROR 0x02000000
425#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
426#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
427#define MAC_LED_CTRL 0x0000040c
428#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
429#define LED_CTRL_1000MBPS_ON 0x00000002
430#define LED_CTRL_100MBPS_ON 0x00000004
431#define LED_CTRL_10MBPS_ON 0x00000008
432#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
433#define LED_CTRL_TRAFFIC_BLINK 0x00000020
434#define LED_CTRL_TRAFFIC_LED 0x00000040
435#define LED_CTRL_1000MBPS_STATUS 0x00000080
436#define LED_CTRL_100MBPS_STATUS 0x00000100
437#define LED_CTRL_10MBPS_STATUS 0x00000200
438#define LED_CTRL_TRAFFIC_STATUS 0x00000400
439#define LED_CTRL_MODE_MAC 0x00000000
440#define LED_CTRL_MODE_PHY_1 0x00000800
441#define LED_CTRL_MODE_PHY_2 0x00001000
442#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
443#define LED_CTRL_MODE_SHARED 0x00004000
444#define LED_CTRL_MODE_COMBO 0x00008000
445#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
446#define LED_CTRL_BLINK_RATE_SHIFT 19
447#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
448#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
449#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
450#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
451#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
452#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
453#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
454#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
455#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
456#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
457#define MAC_ACPI_MBUF_PTR 0x00000430
458#define MAC_ACPI_LEN_OFFSET 0x00000434
459#define ACPI_LENOFF_LEN_MASK 0x0000ffff
460#define ACPI_LENOFF_LEN_SHIFT 0
461#define ACPI_LENOFF_OFF_MASK 0x0fff0000
462#define ACPI_LENOFF_OFF_SHIFT 16
463#define MAC_TX_BACKOFF_SEED 0x00000438
464#define TX_BACKOFF_SEED_MASK 0x000003ff
465#define MAC_RX_MTU_SIZE 0x0000043c
466#define RX_MTU_SIZE_MASK 0x0000ffff
467#define MAC_PCS_TEST 0x00000440
468#define PCS_TEST_PATTERN_MASK 0x000fffff
469#define PCS_TEST_PATTERN_SHIFT 0
470#define PCS_TEST_ENABLE 0x00100000
471#define MAC_TX_AUTO_NEG 0x00000444
472#define TX_AUTO_NEG_MASK 0x0000ffff
473#define TX_AUTO_NEG_SHIFT 0
474#define MAC_RX_AUTO_NEG 0x00000448
475#define RX_AUTO_NEG_MASK 0x0000ffff
476#define RX_AUTO_NEG_SHIFT 0
477#define MAC_MI_COM 0x0000044c
478#define MI_COM_CMD_MASK 0x0c000000
479#define MI_COM_CMD_WRITE 0x04000000
480#define MI_COM_CMD_READ 0x08000000
481#define MI_COM_READ_FAILED 0x10000000
482#define MI_COM_START 0x20000000
483#define MI_COM_BUSY 0x20000000
484#define MI_COM_PHY_ADDR_MASK 0x03e00000
485#define MI_COM_PHY_ADDR_SHIFT 21
486#define MI_COM_REG_ADDR_MASK 0x001f0000
487#define MI_COM_REG_ADDR_SHIFT 16
488#define MI_COM_DATA_MASK 0x0000ffff
489#define MAC_MI_STAT 0x00000450
490#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
491#define MAC_MI_STAT_10MBPS_MODE 0x00000002
492#define MAC_MI_MODE 0x00000454
493#define MAC_MI_MODE_CLK_10MHZ 0x00000001
494#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
495#define MAC_MI_MODE_AUTO_POLL 0x00000010
496#define MAC_MI_MODE_500KHZ_CONST 0x00008000
497#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
498#define MAC_AUTO_POLL_STATUS 0x00000458
499#define MAC_AUTO_POLL_ERROR 0x00000001
500#define MAC_TX_MODE 0x0000045c
501#define TX_MODE_RESET 0x00000001
502#define TX_MODE_ENABLE 0x00000002
503#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
504#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
505#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
506#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
507#define TX_MODE_JMB_FRM_LEN 0x00400000
508#define TX_MODE_CNT_DN_MODE 0x00800000
509#define MAC_TX_STATUS 0x00000460
510#define TX_STATUS_XOFFED 0x00000001
511#define TX_STATUS_SENT_XOFF 0x00000002
512#define TX_STATUS_SENT_XON 0x00000004
513#define TX_STATUS_LINK_UP 0x00000008
514#define TX_STATUS_ODI_UNDERRUN 0x00000010
515#define TX_STATUS_ODI_OVERRUN 0x00000020
516#define MAC_TX_LENGTHS 0x00000464
517#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
518#define TX_LENGTHS_SLOT_TIME_SHIFT 0
519#define TX_LENGTHS_IPG_MASK 0x00000f00
520#define TX_LENGTHS_IPG_SHIFT 8
521#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
522#define TX_LENGTHS_IPG_CRS_SHIFT 12
523#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
524#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
525#define MAC_RX_MODE 0x00000468
526#define RX_MODE_RESET 0x00000001
527#define RX_MODE_ENABLE 0x00000002
528#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
529#define RX_MODE_KEEP_MAC_CTRL 0x00000008
530#define RX_MODE_KEEP_PAUSE 0x00000010
531#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
532#define RX_MODE_ACCEPT_RUNTS 0x00000040
533#define RX_MODE_LEN_CHECK 0x00000080
534#define RX_MODE_PROMISC 0x00000100
535#define RX_MODE_NO_CRC_CHECK 0x00000200
536#define RX_MODE_KEEP_VLAN_TAG 0x00000400
537#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
538#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
539#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
540#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
541#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
542#define RX_MODE_RSS_ENABLE 0x00800000
543#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
544#define RX_MODE_IPV4_FRAG_FIX 0x02000000
545#define MAC_RX_STATUS 0x0000046c
546#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
547#define RX_STATUS_XOFF_RCVD 0x00000002
548#define RX_STATUS_XON_RCVD 0x00000004
549#define MAC_HASH_REG_0 0x00000470
550#define MAC_HASH_REG_1 0x00000474
551#define MAC_HASH_REG_2 0x00000478
552#define MAC_HASH_REG_3 0x0000047c
553#define MAC_RCV_RULE_0 0x00000480
554#define MAC_RCV_VALUE_0 0x00000484
555#define MAC_RCV_RULE_1 0x00000488
556#define MAC_RCV_VALUE_1 0x0000048c
557#define MAC_RCV_RULE_2 0x00000490
558#define MAC_RCV_VALUE_2 0x00000494
559#define MAC_RCV_RULE_3 0x00000498
560#define MAC_RCV_VALUE_3 0x0000049c
561#define MAC_RCV_RULE_4 0x000004a0
562#define MAC_RCV_VALUE_4 0x000004a4
563#define MAC_RCV_RULE_5 0x000004a8
564#define MAC_RCV_VALUE_5 0x000004ac
565#define MAC_RCV_RULE_6 0x000004b0
566#define MAC_RCV_VALUE_6 0x000004b4
567#define MAC_RCV_RULE_7 0x000004b8
568#define MAC_RCV_VALUE_7 0x000004bc
569#define MAC_RCV_RULE_8 0x000004c0
570#define MAC_RCV_VALUE_8 0x000004c4
571#define MAC_RCV_RULE_9 0x000004c8
572#define MAC_RCV_VALUE_9 0x000004cc
573#define MAC_RCV_RULE_10 0x000004d0
574#define MAC_RCV_VALUE_10 0x000004d4
575#define MAC_RCV_RULE_11 0x000004d8
576#define MAC_RCV_VALUE_11 0x000004dc
577#define MAC_RCV_RULE_12 0x000004e0
578#define MAC_RCV_VALUE_12 0x000004e4
579#define MAC_RCV_RULE_13 0x000004e8
580#define MAC_RCV_VALUE_13 0x000004ec
581#define MAC_RCV_RULE_14 0x000004f0
582#define MAC_RCV_VALUE_14 0x000004f4
583#define MAC_RCV_RULE_15 0x000004f8
584#define MAC_RCV_VALUE_15 0x000004fc
585#define RCV_RULE_DISABLE_MASK 0x7fffffff
586#define MAC_RCV_RULE_CFG 0x00000500
587#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
588#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
589/* 0x508 --> 0x520 unused */
590#define MAC_HASHREGU_0 0x00000520
591#define MAC_HASHREGU_1 0x00000524
592#define MAC_HASHREGU_2 0x00000528
593#define MAC_HASHREGU_3 0x0000052c
594#define MAC_EXTADDR_0_HIGH 0x00000530
595#define MAC_EXTADDR_0_LOW 0x00000534
596#define MAC_EXTADDR_1_HIGH 0x00000538
597#define MAC_EXTADDR_1_LOW 0x0000053c
598#define MAC_EXTADDR_2_HIGH 0x00000540
599#define MAC_EXTADDR_2_LOW 0x00000544
600#define MAC_EXTADDR_3_HIGH 0x00000548
601#define MAC_EXTADDR_3_LOW 0x0000054c
602#define MAC_EXTADDR_4_HIGH 0x00000550
603#define MAC_EXTADDR_4_LOW 0x00000554
604#define MAC_EXTADDR_5_HIGH 0x00000558
605#define MAC_EXTADDR_5_LOW 0x0000055c
606#define MAC_EXTADDR_6_HIGH 0x00000560
607#define MAC_EXTADDR_6_LOW 0x00000564
608#define MAC_EXTADDR_7_HIGH 0x00000568
609#define MAC_EXTADDR_7_LOW 0x0000056c
610#define MAC_EXTADDR_8_HIGH 0x00000570
611#define MAC_EXTADDR_8_LOW 0x00000574
612#define MAC_EXTADDR_9_HIGH 0x00000578
613#define MAC_EXTADDR_9_LOW 0x0000057c
614#define MAC_EXTADDR_10_HIGH 0x00000580
615#define MAC_EXTADDR_10_LOW 0x00000584
616#define MAC_EXTADDR_11_HIGH 0x00000588
617#define MAC_EXTADDR_11_LOW 0x0000058c
618#define MAC_SERDES_CFG 0x00000590
619#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
620#define MAC_SERDES_STAT 0x00000594
621/* 0x598 --> 0x5a0 unused */
622#define MAC_PHYCFG1 0x000005a0
623#define MAC_PHYCFG1_RGMII_INT 0x00000001
624#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
625#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
626#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
627#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
628#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
629#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
630#define MAC_PHYCFG1_TXC_DRV 0x20000000
631#define MAC_PHYCFG2 0x000005a4
632#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
633#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
634#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
635#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
636#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
637#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
638#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
639#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
640#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
641#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
642#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
643#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
644#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
645#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
646#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
647#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
648#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
649#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
650#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
651#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
652#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
653#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
654#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
655#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
656#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
657#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
658#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
659#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
660#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
661#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
662#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
663#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
664#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
665#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
666#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
667#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
668#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
669#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
670#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
671#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
672#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
673#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
674#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
675#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
676#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
677#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
678#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
679#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
680#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
681#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
682#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
683#define MAC_PHYCFG2_50610_LED_MODES \
684 (MAC_PHYCFG2_EMODE_MASK_50610 | \
685 MAC_PHYCFG2_EMODE_COMP_50610 | \
686 MAC_PHYCFG2_FMODE_MASK_50610 | \
687 MAC_PHYCFG2_FMODE_COMP_50610 | \
688 MAC_PHYCFG2_GMODE_MASK_50610 | \
689 MAC_PHYCFG2_GMODE_COMP_50610 | \
690 MAC_PHYCFG2_ACT_MASK_50610 | \
691 MAC_PHYCFG2_ACT_COMP_50610 | \
692 MAC_PHYCFG2_QUAL_MASK_50610 | \
693 MAC_PHYCFG2_QUAL_COMP_50610)
694#define MAC_PHYCFG2_AC131_LED_MODES \
695 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
696 MAC_PHYCFG2_EMODE_COMP_AC131 | \
697 MAC_PHYCFG2_FMODE_MASK_AC131 | \
698 MAC_PHYCFG2_FMODE_COMP_AC131 | \
699 MAC_PHYCFG2_GMODE_MASK_AC131 | \
700 MAC_PHYCFG2_GMODE_COMP_AC131 | \
701 MAC_PHYCFG2_ACT_MASK_AC131 | \
702 MAC_PHYCFG2_ACT_COMP_AC131 | \
703 MAC_PHYCFG2_QUAL_MASK_AC131 | \
704 MAC_PHYCFG2_QUAL_COMP_AC131)
705#define MAC_PHYCFG2_RTL8211C_LED_MODES \
706 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
707 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
708 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
709 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
710 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
711 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
712 MAC_PHYCFG2_ACT_MASK_RT8211 | \
713 MAC_PHYCFG2_ACT_COMP_RT8211 | \
714 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
715 MAC_PHYCFG2_QUAL_COMP_RT8211)
716#define MAC_PHYCFG2_RTL8201E_LED_MODES \
717 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
718 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
719 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
720 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
721 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
722 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
723 MAC_PHYCFG2_ACT_MASK_RT8201 | \
724 MAC_PHYCFG2_ACT_COMP_RT8201 | \
725 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
726 MAC_PHYCFG2_QUAL_COMP_RT8201)
727#define MAC_EXT_RGMII_MODE 0x000005a8
728#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
729#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
730#define MAC_RGMII_MODE_TX_RESET 0x00000004
731#define MAC_RGMII_MODE_RX_INT_B 0x00000100
732#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
733#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
734#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
735/* 0x5ac --> 0x5b0 unused */
736#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
737#define SERDES_RX_SIG_DETECT 0x00000400
738#define SG_DIG_CTRL 0x000005b0
739#define SG_DIG_USING_HW_AUTONEG 0x80000000
740#define SG_DIG_SOFT_RESET 0x40000000
741#define SG_DIG_DISABLE_LINKRDY 0x20000000
742#define SG_DIG_CRC16_CLEAR_N 0x01000000
743#define SG_DIG_EN10B 0x00800000
744#define SG_DIG_CLEAR_STATUS 0x00400000
745#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
746#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
747#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
748#define SG_DIG_SPEED_STATUS_SHIFT 18
749#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
750#define SG_DIG_RESTART_AUTONEG 0x00010000
751#define SG_DIG_FIBER_MODE 0x00008000
752#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
753#define SG_DIG_PAUSE_MASK 0x00001800
754#define SG_DIG_PAUSE_CAP 0x00000800
755#define SG_DIG_ASYM_PAUSE 0x00001000
756#define SG_DIG_GBIC_ENABLE 0x00000400
757#define SG_DIG_CHECK_END_ENABLE 0x00000200
758#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
759#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
760#define SG_DIG_GMII_INPUT_SELECT 0x00000040
761#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
762#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
763#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
764#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
765#define SG_DIG_REMOTE_LOOPBACK 0x00000002
766#define SG_DIG_LOOPBACK 0x00000001
767#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
768 SG_DIG_LOCAL_DUPLEX_STATUS | \
769 SG_DIG_LOCAL_LINK_STATUS | \
770 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
771 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
772#define SG_DIG_STATUS 0x000005b4
773#define SG_DIG_CRC16_BUS_MASK 0xffff0000
774#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
775#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
776#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
777#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
778#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
779#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
780#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
781#define SG_DIG_IS_SERDES 0x00000100
782#define SG_DIG_COMMA_DETECTOR 0x00000008
783#define SG_DIG_MAC_ACK_STATUS 0x00000004
784#define SG_DIG_AUTONEG_COMPLETE 0x00000002
785#define SG_DIG_AUTONEG_ERROR 0x00000001
786#define TG3_TX_TSTAMP_LSB 0x000005c0
787#define TG3_TX_TSTAMP_MSB 0x000005c4
788#define TG3_TSTAMP_MASK 0x7fffffffffffffffLL
789/* 0x5c8 --> 0x600 unused */
790#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
791#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
792/* 0x624 --> 0x670 unused */
793
794#define MAC_RSS_INDIR_TBL_0 0x00000630
795
796#define MAC_RSS_HASH_KEY_0 0x00000670
797#define MAC_RSS_HASH_KEY_1 0x00000674
798#define MAC_RSS_HASH_KEY_2 0x00000678
799#define MAC_RSS_HASH_KEY_3 0x0000067c
800#define MAC_RSS_HASH_KEY_4 0x00000680
801#define MAC_RSS_HASH_KEY_5 0x00000684
802#define MAC_RSS_HASH_KEY_6 0x00000688
803#define MAC_RSS_HASH_KEY_7 0x0000068c
804#define MAC_RSS_HASH_KEY_8 0x00000690
805#define MAC_RSS_HASH_KEY_9 0x00000694
806/* 0x698 --> 0x6b0 unused */
807
808#define TG3_RX_TSTAMP_LSB 0x000006b0
809#define TG3_RX_TSTAMP_MSB 0x000006b4
810/* 0x6b8 --> 0x6c8 unused */
811
812#define TG3_RX_PTP_CTL 0x000006c8
813#define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001
814#define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002
815#define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004
816#define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008
817#define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
818 TG3_RX_PTP_CTL_DELAY_REQ)
819#define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
820 TG3_RX_PTP_CTL_DELAY_REQ | \
821 TG3_RX_PTP_CTL_PDLAY_REQ | \
822 TG3_RX_PTP_CTL_PDLAY_RES)
823#define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100
824#define TG3_RX_PTP_CTL_DELAY_RES 0x00000200
825#define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400
826#define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800
827#define TG3_RX_PTP_CTL_SIGNALING 0x00001000
828#define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000
829#define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000
830#define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000
831#define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \
832 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN)
833#define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000
834#define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000
835/* 0x6cc --> 0x800 unused */
836
837#define MAC_TX_STATS_OCTETS 0x00000800
838#define MAC_TX_STATS_RESV1 0x00000804
839#define MAC_TX_STATS_COLLISIONS 0x00000808
840#define MAC_TX_STATS_XON_SENT 0x0000080c
841#define MAC_TX_STATS_XOFF_SENT 0x00000810
842#define MAC_TX_STATS_RESV2 0x00000814
843#define MAC_TX_STATS_MAC_ERRORS 0x00000818
844#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
845#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
846#define MAC_TX_STATS_DEFERRED 0x00000824
847#define MAC_TX_STATS_RESV3 0x00000828
848#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
849#define MAC_TX_STATS_LATE_COL 0x00000830
850#define MAC_TX_STATS_RESV4_1 0x00000834
851#define MAC_TX_STATS_RESV4_2 0x00000838
852#define MAC_TX_STATS_RESV4_3 0x0000083c
853#define MAC_TX_STATS_RESV4_4 0x00000840
854#define MAC_TX_STATS_RESV4_5 0x00000844
855#define MAC_TX_STATS_RESV4_6 0x00000848
856#define MAC_TX_STATS_RESV4_7 0x0000084c
857#define MAC_TX_STATS_RESV4_8 0x00000850
858#define MAC_TX_STATS_RESV4_9 0x00000854
859#define MAC_TX_STATS_RESV4_10 0x00000858
860#define MAC_TX_STATS_RESV4_11 0x0000085c
861#define MAC_TX_STATS_RESV4_12 0x00000860
862#define MAC_TX_STATS_RESV4_13 0x00000864
863#define MAC_TX_STATS_RESV4_14 0x00000868
864#define MAC_TX_STATS_UCAST 0x0000086c
865#define MAC_TX_STATS_MCAST 0x00000870
866#define MAC_TX_STATS_BCAST 0x00000874
867#define MAC_TX_STATS_RESV5_1 0x00000878
868#define MAC_TX_STATS_RESV5_2 0x0000087c
869#define MAC_RX_STATS_OCTETS 0x00000880
870#define MAC_RX_STATS_RESV1 0x00000884
871#define MAC_RX_STATS_FRAGMENTS 0x00000888
872#define MAC_RX_STATS_UCAST 0x0000088c
873#define MAC_RX_STATS_MCAST 0x00000890
874#define MAC_RX_STATS_BCAST 0x00000894
875#define MAC_RX_STATS_FCS_ERRORS 0x00000898
876#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
877#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
878#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
879#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
880#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
881#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
882#define MAC_RX_STATS_JABBERS 0x000008b4
883#define MAC_RX_STATS_UNDERSIZE 0x000008b8
884/* 0x8bc --> 0xc00 unused */
885
886/* Send data initiator control registers */
887#define SNDDATAI_MODE 0x00000c00
888#define SNDDATAI_MODE_RESET 0x00000001
889#define SNDDATAI_MODE_ENABLE 0x00000002
890#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
891#define SNDDATAI_STATUS 0x00000c04
892#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
893#define SNDDATAI_STATSCTRL 0x00000c08
894#define SNDDATAI_SCTRL_ENABLE 0x00000001
895#define SNDDATAI_SCTRL_FASTUPD 0x00000002
896#define SNDDATAI_SCTRL_CLEAR 0x00000004
897#define SNDDATAI_SCTRL_FLUSH 0x00000008
898#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
899#define SNDDATAI_STATSENAB 0x00000c0c
900#define SNDDATAI_STATSINCMASK 0x00000c10
901#define ISO_PKT_TX 0x00000c20
902/* 0xc24 --> 0xc80 unused */
903#define SNDDATAI_COS_CNT_0 0x00000c80
904#define SNDDATAI_COS_CNT_1 0x00000c84
905#define SNDDATAI_COS_CNT_2 0x00000c88
906#define SNDDATAI_COS_CNT_3 0x00000c8c
907#define SNDDATAI_COS_CNT_4 0x00000c90
908#define SNDDATAI_COS_CNT_5 0x00000c94
909#define SNDDATAI_COS_CNT_6 0x00000c98
910#define SNDDATAI_COS_CNT_7 0x00000c9c
911#define SNDDATAI_COS_CNT_8 0x00000ca0
912#define SNDDATAI_COS_CNT_9 0x00000ca4
913#define SNDDATAI_COS_CNT_10 0x00000ca8
914#define SNDDATAI_COS_CNT_11 0x00000cac
915#define SNDDATAI_COS_CNT_12 0x00000cb0
916#define SNDDATAI_COS_CNT_13 0x00000cb4
917#define SNDDATAI_COS_CNT_14 0x00000cb8
918#define SNDDATAI_COS_CNT_15 0x00000cbc
919#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
920#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
921#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
922#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
923#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
924#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
925#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
926#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
927/* 0xce0 --> 0x1000 unused */
928
929/* Send data completion control registers */
930#define SNDDATAC_MODE 0x00001000
931#define SNDDATAC_MODE_RESET 0x00000001
932#define SNDDATAC_MODE_ENABLE 0x00000002
933#define SNDDATAC_MODE_CDELAY 0x00000010
934/* 0x1004 --> 0x1400 unused */
935
936/* Send BD ring selector */
937#define SNDBDS_MODE 0x00001400
938#define SNDBDS_MODE_RESET 0x00000001
939#define SNDBDS_MODE_ENABLE 0x00000002
940#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
941#define SNDBDS_STATUS 0x00001404
942#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
943#define SNDBDS_HWDIAG 0x00001408
944/* 0x140c --> 0x1440 */
945#define SNDBDS_SEL_CON_IDX_0 0x00001440
946#define SNDBDS_SEL_CON_IDX_1 0x00001444
947#define SNDBDS_SEL_CON_IDX_2 0x00001448
948#define SNDBDS_SEL_CON_IDX_3 0x0000144c
949#define SNDBDS_SEL_CON_IDX_4 0x00001450
950#define SNDBDS_SEL_CON_IDX_5 0x00001454
951#define SNDBDS_SEL_CON_IDX_6 0x00001458
952#define SNDBDS_SEL_CON_IDX_7 0x0000145c
953#define SNDBDS_SEL_CON_IDX_8 0x00001460
954#define SNDBDS_SEL_CON_IDX_9 0x00001464
955#define SNDBDS_SEL_CON_IDX_10 0x00001468
956#define SNDBDS_SEL_CON_IDX_11 0x0000146c
957#define SNDBDS_SEL_CON_IDX_12 0x00001470
958#define SNDBDS_SEL_CON_IDX_13 0x00001474
959#define SNDBDS_SEL_CON_IDX_14 0x00001478
960#define SNDBDS_SEL_CON_IDX_15 0x0000147c
961/* 0x1480 --> 0x1800 unused */
962
963/* Send BD initiator control registers */
964#define SNDBDI_MODE 0x00001800
965#define SNDBDI_MODE_RESET 0x00000001
966#define SNDBDI_MODE_ENABLE 0x00000002
967#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
968#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
969#define SNDBDI_STATUS 0x00001804
970#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
971#define SNDBDI_IN_PROD_IDX_0 0x00001808
972#define SNDBDI_IN_PROD_IDX_1 0x0000180c
973#define SNDBDI_IN_PROD_IDX_2 0x00001810
974#define SNDBDI_IN_PROD_IDX_3 0x00001814
975#define SNDBDI_IN_PROD_IDX_4 0x00001818
976#define SNDBDI_IN_PROD_IDX_5 0x0000181c
977#define SNDBDI_IN_PROD_IDX_6 0x00001820
978#define SNDBDI_IN_PROD_IDX_7 0x00001824
979#define SNDBDI_IN_PROD_IDX_8 0x00001828
980#define SNDBDI_IN_PROD_IDX_9 0x0000182c
981#define SNDBDI_IN_PROD_IDX_10 0x00001830
982#define SNDBDI_IN_PROD_IDX_11 0x00001834
983#define SNDBDI_IN_PROD_IDX_12 0x00001838
984#define SNDBDI_IN_PROD_IDX_13 0x0000183c
985#define SNDBDI_IN_PROD_IDX_14 0x00001840
986#define SNDBDI_IN_PROD_IDX_15 0x00001844
987/* 0x1848 --> 0x1c00 unused */
988
989/* Send BD completion control registers */
990#define SNDBDC_MODE 0x00001c00
991#define SNDBDC_MODE_RESET 0x00000001
992#define SNDBDC_MODE_ENABLE 0x00000002
993#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
994/* 0x1c04 --> 0x2000 unused */
995
996/* Receive list placement control registers */
997#define RCVLPC_MODE 0x00002000
998#define RCVLPC_MODE_RESET 0x00000001
999#define RCVLPC_MODE_ENABLE 0x00000002
1000#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
1001#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
1002#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
1003#define RCVLPC_STATUS 0x00002004
1004#define RCVLPC_STATUS_CLASS0 0x00000004
1005#define RCVLPC_STATUS_MAPOOR 0x00000008
1006#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1007#define RCVLPC_LOCK 0x00002008
1008#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1009#define RCVLPC_LOCK_REQ_SHIFT 0
1010#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1011#define RCVLPC_LOCK_GRANT_SHIFT 16
1012#define RCVLPC_NON_EMPTY_BITS 0x0000200c
1013#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1014#define RCVLPC_CONFIG 0x00002010
1015#define RCVLPC_STATSCTRL 0x00002014
1016#define RCVLPC_STATSCTRL_ENABLE 0x00000001
1017#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1018#define RCVLPC_STATS_ENABLE 0x00002018
1019#define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1020#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1021#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1022#define RCVLPC_STATS_INCMASK 0x0000201c
1023/* 0x2020 --> 0x2100 unused */
1024#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1025#define SELLST_TAIL 0x00000004
1026#define SELLST_CONT 0x00000008
1027#define SELLST_UNUSED 0x0000000c
1028#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1029#define RCVLPC_DROP_FILTER_CNT 0x00002240
1030#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1031#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1032#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1033#define RCVLPC_IN_DISCARDS_CNT 0x00002250
1034#define RCVLPC_IN_ERRORS_CNT 0x00002254
1035#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1036/* 0x225c --> 0x2400 unused */
1037
1038/* Receive Data and Receive BD Initiator Control */
1039#define RCVDBDI_MODE 0x00002400
1040#define RCVDBDI_MODE_RESET 0x00000001
1041#define RCVDBDI_MODE_ENABLE 0x00000002
1042#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1043#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1044#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1045#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1046#define RCVDBDI_STATUS 0x00002404
1047#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1048#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1049#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1050#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1051/* 0x240c --> 0x2440 unused */
1052#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1053#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1054#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1055#define RCVDBDI_JUMBO_CON_IDX 0x00002470
1056#define RCVDBDI_STD_CON_IDX 0x00002474
1057#define RCVDBDI_MINI_CON_IDX 0x00002478
1058/* 0x247c --> 0x2480 unused */
1059#define RCVDBDI_BD_PROD_IDX_0 0x00002480
1060#define RCVDBDI_BD_PROD_IDX_1 0x00002484
1061#define RCVDBDI_BD_PROD_IDX_2 0x00002488
1062#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1063#define RCVDBDI_BD_PROD_IDX_4 0x00002490
1064#define RCVDBDI_BD_PROD_IDX_5 0x00002494
1065#define RCVDBDI_BD_PROD_IDX_6 0x00002498
1066#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1067#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1068#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1069#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1070#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1071#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1072#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1073#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1074#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1075#define RCVDBDI_HWDIAG 0x000024c0
1076/* 0x24c4 --> 0x2800 unused */
1077
1078/* Receive Data Completion Control */
1079#define RCVDCC_MODE 0x00002800
1080#define RCVDCC_MODE_RESET 0x00000001
1081#define RCVDCC_MODE_ENABLE 0x00000002
1082#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1083/* 0x2804 --> 0x2c00 unused */
1084
1085/* Receive BD Initiator Control Registers */
1086#define RCVBDI_MODE 0x00002c00
1087#define RCVBDI_MODE_RESET 0x00000001
1088#define RCVBDI_MODE_ENABLE 0x00000002
1089#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1090#define RCVBDI_STATUS 0x00002c04
1091#define RCVBDI_STATUS_RCB_ATTN 0x00000004
1092#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1093#define RCVBDI_STD_PROD_IDX 0x00002c0c
1094#define RCVBDI_MINI_PROD_IDX 0x00002c10
1095#define RCVBDI_MINI_THRESH 0x00002c14
1096#define RCVBDI_STD_THRESH 0x00002c18
1097#define RCVBDI_JUMBO_THRESH 0x00002c1c
1098/* 0x2c20 --> 0x2d00 unused */
1099
1100#define STD_REPLENISH_LWM 0x00002d00
1101#define JMB_REPLENISH_LWM 0x00002d04
1102/* 0x2d08 --> 0x3000 unused */
1103
1104/* Receive BD Completion Control Registers */
1105#define RCVCC_MODE 0x00003000
1106#define RCVCC_MODE_RESET 0x00000001
1107#define RCVCC_MODE_ENABLE 0x00000002
1108#define RCVCC_MODE_ATTN_ENABLE 0x00000004
1109#define RCVCC_STATUS 0x00003004
1110#define RCVCC_STATUS_ERROR_ATTN 0x00000004
1111#define RCVCC_JUMP_PROD_IDX 0x00003008
1112#define RCVCC_STD_PROD_IDX 0x0000300c
1113#define RCVCC_MINI_PROD_IDX 0x00003010
1114/* 0x3014 --> 0x3400 unused */
1115
1116/* Receive list selector control registers */
1117#define RCVLSC_MODE 0x00003400
1118#define RCVLSC_MODE_RESET 0x00000001
1119#define RCVLSC_MODE_ENABLE 0x00000002
1120#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1121#define RCVLSC_STATUS 0x00003404
1122#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1123/* 0x3408 --> 0x3600 unused */
1124
1125#define TG3_CPMU_DRV_STATUS 0x0000344c
1126
1127/* CPMU registers */
1128#define TG3_CPMU_CTRL 0x00003600
1129#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1130#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1131#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1132#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1133#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1134#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1135#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1136/* 0x3608 --> 0x360c unused */
1137
1138#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1139#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1140#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1141#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1142#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1143#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1144#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1145/* 0x3614 --> 0x361c unused */
1146
1147#define TG3_CPMU_HST_ACC 0x0000361c
1148#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1149#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1150/* 0x3620 --> 0x3630 unused */
1151
1152#define TG3_CPMU_CLCK_ORIDE 0x00003624
1153#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1154
1155#define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628
1156#define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13)
1157
1158#define TG3_CPMU_STATUS 0x0000362c
1159#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1160#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1161#define TG3_CPMU_STATUS_FSHFT_5719 30
1162#define TG3_CPMU_STATUS_LINK_MASK 0x180000
1163
1164#define TG3_CPMU_CLCK_STAT 0x00003630
1165#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1166#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1167#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1168#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1169/* 0x3634 --> 0x365c unused */
1170
1171#define TG3_CPMU_MUTEX_REQ 0x0000365c
1172#define CPMU_MUTEX_REQ_DRIVER 0x00001000
1173#define TG3_CPMU_MUTEX_GNT 0x00003660
1174#define CPMU_MUTEX_GNT_DRIVER 0x00001000
1175#define TG3_CPMU_PHY_STRAP 0x00003664
1176#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1177#define TG3_CPMU_PADRNG_CTL 0x00003668
1178#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000
1179/* 0x3664 --> 0x36b0 unused */
1180
1181#define TG3_CPMU_EEE_MODE 0x000036b0
1182#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1183#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1184#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1185#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1186#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1187#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1188#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1189#define TG3_CPMU_EEE_DBTMR1 0x000036b4
1190#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1191#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
1192#define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff
1193#define TG3_CPMU_EEE_DBTMR2 0x000036b8
1194#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1195#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
1196#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1197#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1198#define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1199#define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002
1200/* 0x36c0 --> 0x36d0 unused */
1201
1202#define TG3_CPMU_EEE_CTRL 0x000036d0
1203#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1204#define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1205#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1206/* 0x36d4 --> 0x3800 unused */
1207
1208/* Mbuf cluster free registers */
1209#define MBFREE_MODE 0x00003800
1210#define MBFREE_MODE_RESET 0x00000001
1211#define MBFREE_MODE_ENABLE 0x00000002
1212#define MBFREE_STATUS 0x00003804
1213/* 0x3808 --> 0x3c00 unused */
1214
1215/* Host coalescing control registers */
1216#define HOSTCC_MODE 0x00003c00
1217#define HOSTCC_MODE_RESET 0x00000001
1218#define HOSTCC_MODE_ENABLE 0x00000002
1219#define HOSTCC_MODE_ATTN 0x00000004
1220#define HOSTCC_MODE_NOW 0x00000008
1221#define HOSTCC_MODE_FULL_STATUS 0x00000000
1222#define HOSTCC_MODE_64BYTE 0x00000080
1223#define HOSTCC_MODE_32BYTE 0x00000100
1224#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1225#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1226#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1227#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1228#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1229#define HOSTCC_STATUS 0x00003c04
1230#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1231#define HOSTCC_RXCOL_TICKS 0x00003c08
1232#define LOW_RXCOL_TICKS 0x00000032
1233#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1234#define DEFAULT_RXCOL_TICKS 0x00000048
1235#define HIGH_RXCOL_TICKS 0x00000096
1236#define MAX_RXCOL_TICKS 0x000003ff
1237#define HOSTCC_TXCOL_TICKS 0x00003c0c
1238#define LOW_TXCOL_TICKS 0x00000096
1239#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1240#define DEFAULT_TXCOL_TICKS 0x0000012c
1241#define HIGH_TXCOL_TICKS 0x00000145
1242#define MAX_TXCOL_TICKS 0x000003ff
1243#define HOSTCC_RXMAX_FRAMES 0x00003c10
1244#define LOW_RXMAX_FRAMES 0x00000005
1245#define DEFAULT_RXMAX_FRAMES 0x00000008
1246#define HIGH_RXMAX_FRAMES 0x00000012
1247#define MAX_RXMAX_FRAMES 0x000000ff
1248#define HOSTCC_TXMAX_FRAMES 0x00003c14
1249#define LOW_TXMAX_FRAMES 0x00000035
1250#define DEFAULT_TXMAX_FRAMES 0x0000004b
1251#define HIGH_TXMAX_FRAMES 0x00000052
1252#define MAX_TXMAX_FRAMES 0x000000ff
1253#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1254#define DEFAULT_RXCOAL_TICK_INT 0x00000019
1255#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1256#define MAX_RXCOAL_TICK_INT 0x000003ff
1257#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1258#define DEFAULT_TXCOAL_TICK_INT 0x00000019
1259#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1260#define MAX_TXCOAL_TICK_INT 0x000003ff
1261#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1262#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1263#define MAX_RXCOAL_MAXF_INT 0x000000ff
1264#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1265#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1266#define MAX_TXCOAL_MAXF_INT 0x000000ff
1267#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1268#define DEFAULT_STAT_COAL_TICKS 0x000f4240
1269#define MAX_STAT_COAL_TICKS 0xd693d400
1270#define MIN_STAT_COAL_TICKS 0x00000064
1271/* 0x3c2c --> 0x3c30 unused */
1272#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1273#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1274#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1275#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1276#define HOSTCC_FLOW_ATTN 0x00003c48
1277#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1278/* 0x3c4c --> 0x3c50 unused */
1279#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1280#define HOSTCC_STD_CON_IDX 0x00003c54
1281#define HOSTCC_MINI_CON_IDX 0x00003c58
1282/* 0x3c5c --> 0x3c80 unused */
1283#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1284#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1285#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1286#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1287#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1288#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1289#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1290#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1291#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1292#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1293#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1294#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1295#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1296#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1297#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1298#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1299#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1300#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1301#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1302#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1303#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1304#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1305#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1306#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1307#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1308#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1309#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1310#define HOSTCC_SND_CON_IDX_11 0x00003cec
1311#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1312#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1313#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1314#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1315#define HOSTCC_STATBLCK_RING1 0x00003d00
1316/* 0x3d00 --> 0x3d80 unused */
1317
1318#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1319#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1320#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1321#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1322#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1323#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1324/* 0x3d98 --> 0x4000 unused */
1325
1326/* Memory arbiter control registers */
1327#define MEMARB_MODE 0x00004000
1328#define MEMARB_MODE_RESET 0x00000001
1329#define MEMARB_MODE_ENABLE 0x00000002
1330#define MEMARB_STATUS 0x00004004
1331#define MEMARB_TRAP_ADDR_LOW 0x00004008
1332#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1333/* 0x4010 --> 0x4400 unused */
1334
1335/* Buffer manager control registers */
1336#define BUFMGR_MODE 0x00004400
1337#define BUFMGR_MODE_RESET 0x00000001
1338#define BUFMGR_MODE_ENABLE 0x00000002
1339#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1340#define BUFMGR_MODE_BM_TEST 0x00000008
1341#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1342#define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1343#define BUFMGR_STATUS 0x00004404
1344#define BUFMGR_STATUS_ERROR 0x00000004
1345#define BUFMGR_STATUS_MBLOW 0x00000010
1346#define BUFMGR_MB_POOL_ADDR 0x00004408
1347#define BUFMGR_MB_POOL_SIZE 0x0000440c
1348#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1349#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1350#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1351#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1352#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1353#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1354#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1355#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1356#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1357#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1358#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1359#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1360#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1361#define BUFMGR_MB_HIGH_WATER 0x00004418
1362#define DEFAULT_MB_HIGH_WATER 0x00000060
1363#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1364#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1365#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1366#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1367#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1368#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1369#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1370#define BUFMGR_MB_ALLOC_BIT 0x10000000
1371#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1372#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1373#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1374#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1375#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1376#define BUFMGR_DMA_LOW_WATER 0x00004434
1377#define DEFAULT_DMA_LOW_WATER 0x00000005
1378#define BUFMGR_DMA_HIGH_WATER 0x00004438
1379#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1380#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1381#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1382#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1383#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1384#define BUFMGR_HWDIAG_0 0x0000444c
1385#define BUFMGR_HWDIAG_1 0x00004450
1386#define BUFMGR_HWDIAG_2 0x00004454
1387/* 0x4458 --> 0x4800 unused */
1388
1389/* Read DMA control registers */
1390#define RDMAC_MODE 0x00004800
1391#define RDMAC_MODE_RESET 0x00000001
1392#define RDMAC_MODE_ENABLE 0x00000002
1393#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1394#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1395#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1396#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1397#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1398#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1399#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1400#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1401#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1402#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1403#define RDMAC_MODE_SPLIT_RESET 0x00001000
1404#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1405#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1406#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1407#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1408#define RDMAC_MODE_JMB_2K_MMRR 0x00800000
1409#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1410#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1411#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1412#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1413#define RDMAC_STATUS 0x00004804
1414#define RDMAC_STATUS_TGTABORT 0x00000004
1415#define RDMAC_STATUS_MSTABORT 0x00000008
1416#define RDMAC_STATUS_PARITYERR 0x00000010
1417#define RDMAC_STATUS_ADDROFLOW 0x00000020
1418#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1419#define RDMAC_STATUS_FIFOURUN 0x00000080
1420#define RDMAC_STATUS_FIFOOREAD 0x00000100
1421#define RDMAC_STATUS_LNGREAD 0x00000200
1422/* 0x4808 --> 0x4890 unused */
1423
1424#define TG3_RDMA_RSRVCTRL_REG2 0x00004890
1425#define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0
1426
1427#define TG3_RDMA_RSRVCTRL_REG 0x00004900
1428#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1429#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1430#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1431#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1432#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1433#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1434#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1435/* 0x4904 --> 0x4910 unused */
1436
1437#define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1438#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1439#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1440#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000
1441#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000
1442/* 0x4914 --> 0x4be0 unused */
1443
1444#define TG3_NUM_RDMA_CHANNELS 4
1445#define TG3_RDMA_LENGTH 0x00004be0
1446
1447/* Write DMA control registers */
1448#define WDMAC_MODE 0x00004c00
1449#define WDMAC_MODE_RESET 0x00000001
1450#define WDMAC_MODE_ENABLE 0x00000002
1451#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1452#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1453#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1454#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1455#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1456#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1457#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1458#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1459#define WDMAC_MODE_RX_ACCEL 0x00000400
1460#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1461#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1462#define WDMAC_STATUS 0x00004c04
1463#define WDMAC_STATUS_TGTABORT 0x00000004
1464#define WDMAC_STATUS_MSTABORT 0x00000008
1465#define WDMAC_STATUS_PARITYERR 0x00000010
1466#define WDMAC_STATUS_ADDROFLOW 0x00000020
1467#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1468#define WDMAC_STATUS_FIFOURUN 0x00000080
1469#define WDMAC_STATUS_FIFOOREAD 0x00000100
1470#define WDMAC_STATUS_LNGREAD 0x00000200
1471/* 0x4c08 --> 0x5000 unused */
1472
1473/* Per-cpu register offsets (arm9) */
1474#define CPU_MODE 0x00000000
1475#define CPU_MODE_RESET 0x00000001
1476#define CPU_MODE_HALT 0x00000400
1477#define CPU_STATE 0x00000004
1478#define CPU_EVTMASK 0x00000008
1479/* 0xc --> 0x1c reserved */
1480#define CPU_PC 0x0000001c
1481#define CPU_INSN 0x00000020
1482#define CPU_SPAD_UFLOW 0x00000024
1483#define CPU_WDOG_CLEAR 0x00000028
1484#define CPU_WDOG_VECTOR 0x0000002c
1485#define CPU_WDOG_PC 0x00000030
1486#define CPU_HW_BP 0x00000034
1487/* 0x38 --> 0x44 unused */
1488#define CPU_WDOG_SAVED_STATE 0x00000044
1489#define CPU_LAST_BRANCH_ADDR 0x00000048
1490#define CPU_SPAD_UFLOW_SET 0x0000004c
1491/* 0x50 --> 0x200 unused */
1492#define CPU_R0 0x00000200
1493#define CPU_R1 0x00000204
1494#define CPU_R2 0x00000208
1495#define CPU_R3 0x0000020c
1496#define CPU_R4 0x00000210
1497#define CPU_R5 0x00000214
1498#define CPU_R6 0x00000218
1499#define CPU_R7 0x0000021c
1500#define CPU_R8 0x00000220
1501#define CPU_R9 0x00000224
1502#define CPU_R10 0x00000228
1503#define CPU_R11 0x0000022c
1504#define CPU_R12 0x00000230
1505#define CPU_R13 0x00000234
1506#define CPU_R14 0x00000238
1507#define CPU_R15 0x0000023c
1508#define CPU_R16 0x00000240
1509#define CPU_R17 0x00000244
1510#define CPU_R18 0x00000248
1511#define CPU_R19 0x0000024c
1512#define CPU_R20 0x00000250
1513#define CPU_R21 0x00000254
1514#define CPU_R22 0x00000258
1515#define CPU_R23 0x0000025c
1516#define CPU_R24 0x00000260
1517#define CPU_R25 0x00000264
1518#define CPU_R26 0x00000268
1519#define CPU_R27 0x0000026c
1520#define CPU_R28 0x00000270
1521#define CPU_R29 0x00000274
1522#define CPU_R30 0x00000278
1523#define CPU_R31 0x0000027c
1524/* 0x280 --> 0x400 unused */
1525
1526#define RX_CPU_BASE 0x00005000
1527#define RX_CPU_MODE 0x00005000
1528#define RX_CPU_STATE 0x00005004
1529#define RX_CPU_PGMCTR 0x0000501c
1530#define RX_CPU_HWBKPT 0x00005034
1531#define TX_CPU_BASE 0x00005400
1532#define TX_CPU_MODE 0x00005400
1533#define TX_CPU_STATE 0x00005404
1534#define TX_CPU_PGMCTR 0x0000541c
1535
1536#define VCPU_STATUS 0x00005100
1537#define VCPU_STATUS_INIT_DONE 0x04000000
1538#define VCPU_STATUS_DRV_RESET 0x08000000
1539
1540#define VCPU_CFGSHDW 0x00005104
1541#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1542#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1543#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1544
1545/* Mailboxes */
1546#define GRCMBOX_BASE 0x00005600
1547#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1548#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1549#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1550#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1551#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1552#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1553#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1554#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1555#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1556#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1557#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1558#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1559#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1560#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1561#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1562#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1563#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1564#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1565#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1566#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1567#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1568#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1569#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1570#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1571#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1572#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1573#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1574#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1575#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1576#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1577#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1578#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1579#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1580#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1581#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1582#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1583#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1584#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1585#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1586#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1587#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1588#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1589#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1590#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1591#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1592#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1593#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1594#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1595#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1596#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1597#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1598#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1599#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1600#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1601#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1602#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1603#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1604#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1605#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1606#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1607#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1608#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1609#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1610#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1611#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1612#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1613#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1614#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1615/* 0x5a10 --> 0x5c00 */
1616
1617/* Flow Through queues */
1618#define FTQ_RESET 0x00005c00
1619/* 0x5c04 --> 0x5c10 unused */
1620#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1621#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1622#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1623#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1624#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1625#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1626#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1627#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1628#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1629#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1630#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1631#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1632#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1633#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1634#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1635#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1636#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1637#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1638#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1639#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1640#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1641#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1642#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1643#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1644#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1645#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1646#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1647#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1648#define FTQ_SWTYPE1_CTL 0x00005c80
1649#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1650#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1651#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1652#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1653#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1654#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1655#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1656#define FTQ_HOST_COAL_CTL 0x00005ca0
1657#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1658#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1659#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1660#define FTQ_MAC_TX_CTL 0x00005cb0
1661#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1662#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1663#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1664#define FTQ_MB_FREE_CTL 0x00005cc0
1665#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1666#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1667#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1668#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1669#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1670#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1671#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1672#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1673#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1674#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1675#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1676#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1677#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1678#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1679#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1680#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1681#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1682#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1683#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1684#define FTQ_SWTYPE2_CTL 0x00005d10
1685#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1686#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1687#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1688/* 0x5d20 --> 0x6000 unused */
1689
1690/* Message signaled interrupt registers */
1691#define MSGINT_MODE 0x00006000
1692#define MSGINT_MODE_RESET 0x00000001
1693#define MSGINT_MODE_ENABLE 0x00000002
1694#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1695#define MSGINT_MODE_MULTIVEC_EN 0x00000080
1696#define MSGINT_STATUS 0x00006004
1697#define MSGINT_STATUS_MSI_REQ 0x00000001
1698#define MSGINT_FIFO 0x00006008
1699/* 0x600c --> 0x6400 unused */
1700
1701/* DMA completion registers */
1702#define DMAC_MODE 0x00006400
1703#define DMAC_MODE_RESET 0x00000001
1704#define DMAC_MODE_ENABLE 0x00000002
1705/* 0x6404 --> 0x6800 unused */
1706
1707/* GRC registers */
1708#define GRC_MODE 0x00006800
1709#define GRC_MODE_UPD_ON_COAL 0x00000001
1710#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1711#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1712#define GRC_MODE_BSWAP_DATA 0x00000010
1713#define GRC_MODE_WSWAP_DATA 0x00000020
1714#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1715#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1716#define GRC_MODE_SPLITHDR 0x00000100
1717#define GRC_MODE_NOFRM_CRACKING 0x00000200
1718#define GRC_MODE_INCL_CRC 0x00000400
1719#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1720#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1721#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1722#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1723#define GRC_MODE_B2HRX_ENABLE 0x00008000
1724#define GRC_MODE_HOST_STACKUP 0x00010000
1725#define GRC_MODE_HOST_SENDBDS 0x00020000
1726#define GRC_MODE_HTX2B_ENABLE 0x00040000
1727#define GRC_MODE_TIME_SYNC_ENABLE 0x00080000
1728#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1729#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1730#define GRC_MODE_PCIE_TL_SEL 0x00000000
1731#define GRC_MODE_PCIE_PL_SEL 0x00400000
1732#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1733#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1734#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1735#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1736#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1737#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1738#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1739#define GRC_MODE_PCIE_DL_SEL 0x20000000
1740#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1741#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1742#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1743 GRC_MODE_PCIE_PL_SEL | \
1744 GRC_MODE_PCIE_DL_SEL | \
1745 GRC_MODE_PCIE_HI_1K_EN)
1746#define GRC_MISC_CFG 0x00006804
1747#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1748#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1749#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1750#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1751#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1752#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1753#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1754#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1755#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1756#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1757#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1758#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1759#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1760#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1761#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1762#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1763#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1764#define GRC_LOCAL_CTRL 0x00006808
1765#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1766#define GRC_LCLCTRL_CLEARINT 0x00000002
1767#define GRC_LCLCTRL_SETINT 0x00000004
1768#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1769#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1770#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1771#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1772#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1773#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1774#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1775#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1776#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1777#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1778#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1779#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1780#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1781#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1782#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1783#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1784#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1785#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1786#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1787#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1788#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1789#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1790#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1791#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1792#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1793#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1794#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1795#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1796#define GRC_TIMER 0x0000680c
1797#define GRC_RX_CPU_EVENT 0x00006810
1798#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1799#define GRC_RX_TIMER_REF 0x00006814
1800#define GRC_RX_CPU_SEM 0x00006818
1801#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1802#define GRC_TX_CPU_EVENT 0x00006820
1803#define GRC_TX_TIMER_REF 0x00006824
1804#define GRC_TX_CPU_SEM 0x00006828
1805#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1806#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1807#define GRC_EEPROM_ADDR 0x00006838
1808#define EEPROM_ADDR_WRITE 0x00000000
1809#define EEPROM_ADDR_READ 0x80000000
1810#define EEPROM_ADDR_COMPLETE 0x40000000
1811#define EEPROM_ADDR_FSM_RESET 0x20000000
1812#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1813#define EEPROM_ADDR_DEVID_SHIFT 26
1814#define EEPROM_ADDR_START 0x02000000
1815#define EEPROM_ADDR_CLKPERD_SHIFT 16
1816#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1817#define EEPROM_ADDR_ADDR_SHIFT 0
1818#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1819#define EEPROM_CHIP_SIZE (64 * 1024)
1820#define GRC_EEPROM_DATA 0x0000683c
1821#define GRC_EEPROM_CTRL 0x00006840
1822#define GRC_MDI_CTRL 0x00006844
1823#define GRC_SEEPROM_DELAY 0x00006848
1824/* 0x684c --> 0x6890 unused */
1825#define GRC_VCPU_EXT_CTRL 0x00006890
1826#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1827#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1828#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1829
1830#define TG3_EAV_REF_CLCK_LSB 0x00006900
1831#define TG3_EAV_REF_CLCK_MSB 0x00006904
1832#define TG3_EAV_REF_CLCK_CTL 0x00006908
1833#define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002
1834#define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004
1835#define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16)
1836#define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17)
1837
1838#define TG3_EAV_WATCHDOG0_LSB 0x00006918
1839#define TG3_EAV_WATCHDOG0_MSB 0x0000691c
1840#define TG3_EAV_WATCHDOG0_EN (1 << 31)
1841#define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff
1842
1843#define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928
1844#define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31)
1845#define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30)
1846
1847#define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff
1848
1849/* 0x692c --> 0x7000 unused */
1850
1851/* NVRAM Control registers */
1852#define NVRAM_CMD 0x00007000
1853#define NVRAM_CMD_RESET 0x00000001
1854#define NVRAM_CMD_DONE 0x00000008
1855#define NVRAM_CMD_GO 0x00000010
1856#define NVRAM_CMD_WR 0x00000020
1857#define NVRAM_CMD_RD 0x00000000
1858#define NVRAM_CMD_ERASE 0x00000040
1859#define NVRAM_CMD_FIRST 0x00000080
1860#define NVRAM_CMD_LAST 0x00000100
1861#define NVRAM_CMD_WREN 0x00010000
1862#define NVRAM_CMD_WRDI 0x00020000
1863#define NVRAM_STAT 0x00007004
1864#define NVRAM_WRDATA 0x00007008
1865#define NVRAM_ADDR 0x0000700c
1866#define NVRAM_ADDR_MSK 0x07ffffff
1867#define NVRAM_RDDATA 0x00007010
1868#define NVRAM_CFG1 0x00007014
1869#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1870#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1871#define NVRAM_CFG1_PASS_THRU 0x00000004
1872#define NVRAM_CFG1_STATUS_BITS 0x00000070
1873#define NVRAM_CFG1_BIT_BANG 0x00000008
1874#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1875#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1876#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1877#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1878#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1879#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1880#define FLASH_VENDOR_ST 0x03000001
1881#define FLASH_VENDOR_SAIFUN 0x01000003
1882#define FLASH_VENDOR_SST_SMALL 0x00000001
1883#define FLASH_VENDOR_SST_LARGE 0x02000001
1884#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1885#define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003
1886#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1887#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1888#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1889#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1890#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1891#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1892#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1893#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1894#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1895#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1896#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1897#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1898#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1899#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1900#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1901#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1902#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1903#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1904#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1905#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1906#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1907#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1908#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1909#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1910#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1911#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1912#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1913#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1914#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1915#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1916#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1917#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1918#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1919#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1920#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1921#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1922#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1923#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1924#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1925#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1926#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1927#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1928#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1929#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1930#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1931#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1932#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1933#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1934#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1935#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1936#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1937#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1938#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1939#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1940#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1941#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1942#define FLASH_5717VENDOR_ST_25USPT 0x03400002
1943#define FLASH_5717VENDOR_ST_45USPT 0x03400001
1944#define FLASH_5720_EEPROM_HD 0x00000001
1945#define FLASH_5720_EEPROM_LD 0x00000003
1946#define FLASH_5762_EEPROM_HD 0x02000001
1947#define FLASH_5762_EEPROM_LD 0x02000003
1948#define FLASH_5762_MX25L_100 0x00800000
1949#define FLASH_5762_MX25L_200 0x00800002
1950#define FLASH_5762_MX25L_400 0x00800001
1951#define FLASH_5762_MX25L_800 0x00800003
1952#define FLASH_5762_MX25L_160_320 0x03800002
1953#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1954#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1955#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1956#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1957#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1958#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1959#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1960#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1961#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1962#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1963#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1964#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1965#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1966#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1967#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1968#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1969#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1970#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1971#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1972#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
1973#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
1974#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
1975#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
1976#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
1977#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
1978#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
1979#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
1980#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
1981#define FLASH_5720VENDOR_ST_25USPT 0x03c00002
1982#define FLASH_5720VENDOR_ST_45USPT 0x03c00001
1983#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1984#define FLASH_5752PAGE_SIZE_256 0x00000000
1985#define FLASH_5752PAGE_SIZE_512 0x10000000
1986#define FLASH_5752PAGE_SIZE_1K 0x20000000
1987#define FLASH_5752PAGE_SIZE_2K 0x30000000
1988#define FLASH_5752PAGE_SIZE_4K 0x40000000
1989#define FLASH_5752PAGE_SIZE_264 0x50000000
1990#define FLASH_5752PAGE_SIZE_528 0x60000000
1991#define NVRAM_CFG2 0x00007018
1992#define NVRAM_CFG3 0x0000701c
1993#define NVRAM_SWARB 0x00007020
1994#define SWARB_REQ_SET0 0x00000001
1995#define SWARB_REQ_SET1 0x00000002
1996#define SWARB_REQ_SET2 0x00000004
1997#define SWARB_REQ_SET3 0x00000008
1998#define SWARB_REQ_CLR0 0x00000010
1999#define SWARB_REQ_CLR1 0x00000020
2000#define SWARB_REQ_CLR2 0x00000040
2001#define SWARB_REQ_CLR3 0x00000080
2002#define SWARB_GNT0 0x00000100
2003#define SWARB_GNT1 0x00000200
2004#define SWARB_GNT2 0x00000400
2005#define SWARB_GNT3 0x00000800
2006#define SWARB_REQ0 0x00001000
2007#define SWARB_REQ1 0x00002000
2008#define SWARB_REQ2 0x00004000
2009#define SWARB_REQ3 0x00008000
2010#define NVRAM_ACCESS 0x00007024
2011#define ACCESS_ENABLE 0x00000001
2012#define ACCESS_WR_ENABLE 0x00000002
2013#define NVRAM_WRITE1 0x00007028
2014/* 0x702c unused */
2015
2016#define NVRAM_ADDR_LOCKOUT 0x00007030
2017#define NVRAM_AUTOSENSE_STATUS 0x00007038
2018#define AUTOSENSE_DEVID 0x00000010
2019#define AUTOSENSE_DEVID_MASK 0x00000007
2020#define AUTOSENSE_SIZE_IN_MB 17
2021/* 0x703c --> 0x7500 unused */
2022
2023#define OTP_MODE 0x00007500
2024#define OTP_MODE_OTP_THRU_GRC 0x00000001
2025#define OTP_CTRL 0x00007504
2026#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
2027#define OTP_CTRL_OTP_CMD_READ 0x00000000
2028#define OTP_CTRL_OTP_CMD_INIT 0x00000008
2029#define OTP_CTRL_OTP_CMD_START 0x00000001
2030#define OTP_STATUS 0x00007508
2031#define OTP_STATUS_CMD_DONE 0x00000001
2032#define OTP_ADDRESS 0x0000750c
2033#define OTP_ADDRESS_MAGIC1 0x000000a0
2034#define OTP_ADDRESS_MAGIC2 0x00000080
2035/* 0x7510 unused */
2036
2037#define OTP_READ_DATA 0x00007514
2038/* 0x7518 --> 0x7c04 unused */
2039
2040#define PCIE_TRANSACTION_CFG 0x00007c04
2041#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
2042#define PCIE_TRANS_CFG_LOM 0x00000020
2043/* 0x7c08 --> 0x7d28 unused */
2044
2045#define PCIE_PWR_MGMT_THRESH 0x00007d28
2046#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2047#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2048#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2049/* 0x7d2c --> 0x7d54 unused */
2050
2051#define TG3_PCIE_LNKCTL 0x00007d54
2052#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2053#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2054/* 0x7d58 --> 0x7e70 unused */
2055
2056#define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2057#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2058#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2059
2060#define TG3_PCIE_EIDLE_DELAY 0x00007e70
2061#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2062#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2063/* 0x7e74 --> 0x8000 unused */
2064
2065
2066/* Alternate PCIE definitions */
2067#define TG3_PCIE_TLDLPL_PORT 0x00007c00
2068#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2069#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2070#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2071#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2072#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2073#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2074#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2075
2076#define TG3_REG_BLK_SIZE 0x00008000
2077
2078/* OTP bit definitions */
2079#define TG3_OTP_AGCTGT_MASK 0x000000e0
2080#define TG3_OTP_AGCTGT_SHIFT 1
2081#define TG3_OTP_HPFFLTR_MASK 0x00000300
2082#define TG3_OTP_HPFFLTR_SHIFT 1
2083#define TG3_OTP_HPFOVER_MASK 0x00000400
2084#define TG3_OTP_HPFOVER_SHIFT 1
2085#define TG3_OTP_LPFDIS_MASK 0x00000800
2086#define TG3_OTP_LPFDIS_SHIFT 11
2087#define TG3_OTP_VDAC_MASK 0xff000000
2088#define TG3_OTP_VDAC_SHIFT 24
2089#define TG3_OTP_10BTAMP_MASK 0x0000f000
2090#define TG3_OTP_10BTAMP_SHIFT 8
2091#define TG3_OTP_ROFF_MASK 0x00e00000
2092#define TG3_OTP_ROFF_SHIFT 11
2093#define TG3_OTP_RCOFF_MASK 0x001c0000
2094#define TG3_OTP_RCOFF_SHIFT 16
2095
2096#define TG3_OTP_DEFAULT 0x286c1640
2097
2098
2099/* Hardware Legacy NVRAM layout */
2100#define TG3_NVM_VPD_OFF 0x100
2101#define TG3_NVM_VPD_LEN 256
2102
2103/* Hardware Selfboot NVRAM layout */
2104#define TG3_NVM_HWSB_CFG1 0x00000004
2105#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2106#define TG3_NVM_HWSB_CFG1_MAJSFT 27
2107#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2108#define TG3_NVM_HWSB_CFG1_MINSFT 22
2109
2110#define TG3_EEPROM_MAGIC 0x669955aa
2111#define TG3_EEPROM_MAGIC_FW 0xa5000000
2112#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2113#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2114#define TG3_EEPROM_SB_FORMAT_1 0x00200000
2115#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2116#define TG3_EEPROM_SB_REVISION_0 0x00000000
2117#define TG3_EEPROM_SB_REVISION_2 0x00020000
2118#define TG3_EEPROM_SB_REVISION_3 0x00030000
2119#define TG3_EEPROM_SB_REVISION_4 0x00040000
2120#define TG3_EEPROM_SB_REVISION_5 0x00050000
2121#define TG3_EEPROM_SB_REVISION_6 0x00060000
2122#define TG3_EEPROM_MAGIC_HW 0xabcd
2123#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2124
2125#define TG3_NVM_DIR_START 0x18
2126#define TG3_NVM_DIR_END 0x78
2127#define TG3_NVM_DIRENT_SIZE 0xc
2128#define TG3_NVM_DIRTYPE_SHIFT 24
2129#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2130#define TG3_NVM_DIRTYPE_ASFINI 1
2131#define TG3_NVM_DIRTYPE_EXTVPD 20
2132#define TG3_NVM_PTREV_BCVER 0x94
2133#define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2134#define TG3_NVM_BCVER_MAJSFT 8
2135#define TG3_NVM_BCVER_MINMSK 0x000000ff
2136
2137#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2138#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2139#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2140#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2141#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2142#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2143#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2144#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2145#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2146#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2147#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2148#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2149
2150
2151/* 32K Window into NIC internal memory */
2152#define NIC_SRAM_WIN_BASE 0x00008000
2153
2154/* Offsets into first 32k of NIC internal memory. */
2155#define NIC_SRAM_PAGE_ZERO 0x00000000
2156#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
2157#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
2158#define NIC_SRAM_STATS_BLK 0x00000300
2159#define NIC_SRAM_STATUS_BLK 0x00000b00
2160
2161#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2162#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2163#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
2164
2165#define NIC_SRAM_DATA_SIG 0x00000b54
2166#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
2167
2168#define NIC_SRAM_DATA_CFG 0x00000b58
2169#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2170#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2171#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2172#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2173#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2174#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2175#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2176#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2177#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2178#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2179#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2180#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2181#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2182#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2183#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2184
2185#define NIC_SRAM_DATA_VER 0x00000b5c
2186#define NIC_SRAM_DATA_VER_SHIFT 16
2187
2188#define NIC_SRAM_DATA_PHY_ID 0x00000b74
2189#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2190#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2191
2192#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2193#define FWCMD_NICDRV_ALIVE 0x00000001
2194#define FWCMD_NICDRV_PAUSE_FW 0x00000002
2195#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2196#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2197#define FWCMD_NICDRV_FIX_DMAR 0x00000005
2198#define FWCMD_NICDRV_FIX_DMAW 0x00000006
2199#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2200#define FWCMD_NICDRV_ALIVE2 0x0000000d
2201#define FWCMD_NICDRV_ALIVE3 0x0000000e
2202#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2203#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2204#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2205#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2206#define DRV_STATE_START 0x00000001
2207#define DRV_STATE_START_DONE 0x80000001
2208#define DRV_STATE_UNLOAD 0x00000002
2209#define DRV_STATE_UNLOAD_DONE 0x80000002
2210#define DRV_STATE_WOL 0x00000003
2211#define DRV_STATE_SUSPEND 0x00000004
2212
2213#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2214
2215#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2216#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2217
2218#define NIC_SRAM_WOL_MBOX 0x00000d30
2219#define WOL_SIGNATURE 0x474c0000
2220#define WOL_DRV_STATE_SHUTDOWN 0x00000001
2221#define WOL_DRV_WOL 0x00000002
2222#define WOL_SET_MAGIC_PKT 0x00000004
2223
2224#define NIC_SRAM_DATA_CFG_2 0x00000d38
2225
2226#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000
2227#define SHASTA_EXT_LED_MODE_MASK 0x00018000
2228#define SHASTA_EXT_LED_LEGACY 0x00000000
2229#define SHASTA_EXT_LED_SHARED 0x00008000
2230#define SHASTA_EXT_LED_MAC 0x00010000
2231#define SHASTA_EXT_LED_COMBO 0x00018000
2232
2233#define NIC_SRAM_DATA_CFG_3 0x00000d3c
2234#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2235#define NIC_SRAM_LNK_FLAP_AVOID 0x00400000
2236#define NIC_SRAM_1G_ON_VAUX_OK 0x00800000
2237
2238#define NIC_SRAM_DATA_CFG_4 0x00000d60
2239#define NIC_SRAM_GMII_MODE 0x00000002
2240#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2241#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2242#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2243
2244#define NIC_SRAM_CPMU_STATUS 0x00000e00
2245#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2246#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2247
2248#define NIC_SRAM_DATA_CFG_5 0x00000e0c
2249#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002
2250
2251#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2252
2253#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2254#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2255#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2256#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2257#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2258#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2259#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2260#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2261#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2262#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2263
2264#define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000
2265#define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000
2266#define TG3_57766_FW_BASE_ADDR 0x00030000
2267#define TG3_57766_FW_HANDSHAKE 0x0003fccc
2268#define TG3_SBROM_IN_SERVICE_LOOP 0x51
2269
2270#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2271#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2272#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2273
2274#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2275#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2276
2277
2278/* Currently this is fixed. */
2279#define TG3_PHY_MII_ADDR 0x01
2280
2281
2282/*** Tigon3 specific PHY MII registers. ***/
2283#define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2284#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2285#define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2286
2287#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2288#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2289#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2290#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2291#define MII_TG3_EXT_CTRL_TBI 0x8000
2292
2293#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2294#define MII_TG3_EXT_STAT_MDIX 0x2000
2295#define MII_TG3_EXT_STAT_LPASS 0x0100
2296
2297#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2298#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2299#define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2300#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2301
2302#define MII_TG3_DSP_TAP1 0x0001
2303#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2304#define MII_TG3_DSP_TAP26 0x001a
2305#define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2306#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2307#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2308#define MII_TG3_DSP_AADJ1CH0 0x001f
2309#define MII_TG3_DSP_CH34TP2 0x4022
2310#define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff
2311#define MII_TG3_DSP_AADJ1CH3 0x601f
2312#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2313#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2314#define MII_TG3_DSP_EXP8 0x0f08
2315#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2316#define MII_TG3_DSP_EXP8_AEDW 0x0200
2317#define MII_TG3_DSP_EXP75 0x0f75
2318#define MII_TG3_DSP_EXP96 0x0f96
2319#define MII_TG3_DSP_EXP97 0x0f97
2320
2321#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
2322
2323#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2324#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2325#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2326#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2327#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
2328
2329#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2330#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2331#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2332#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2333#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2334#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2335
2336#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2337
2338#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2339#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2340#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2341#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2342#define MII_TG3_AUXCTL_MISC_WREN 0x8000
2343
2344
2345#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
2346#define MII_TG3_AUX_STAT_LPASS 0x0004
2347#define MII_TG3_AUX_STAT_SPDMASK 0x0700
2348#define MII_TG3_AUX_STAT_10HALF 0x0100
2349#define MII_TG3_AUX_STAT_10FULL 0x0200
2350#define MII_TG3_AUX_STAT_100HALF 0x0300
2351#define MII_TG3_AUX_STAT_100_4 0x0400
2352#define MII_TG3_AUX_STAT_100FULL 0x0500
2353#define MII_TG3_AUX_STAT_1000HALF 0x0600
2354#define MII_TG3_AUX_STAT_1000FULL 0x0700
2355#define MII_TG3_AUX_STAT_100 0x0008
2356#define MII_TG3_AUX_STAT_FULL 0x0001
2357
2358#define MII_TG3_ISTAT 0x1a /* IRQ status register */
2359#define MII_TG3_IMASK 0x1b /* IRQ mask register */
2360
2361/* ISTAT/IMASK event bits */
2362#define MII_TG3_INT_LINKCHG 0x0002
2363#define MII_TG3_INT_SPEEDCHG 0x0004
2364#define MII_TG3_INT_DUPLEXCHG 0x0008
2365#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2366
2367#define MII_TG3_MISC_SHDW 0x1c
2368#define MII_TG3_MISC_SHDW_WREN 0x8000
2369
2370#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2371#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2372#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2373
2374#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2375#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2376#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2377#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2378#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2379#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2380
2381#define MII_TG3_TEST1 0x1e
2382#define MII_TG3_TEST1_TRIM_EN 0x0010
2383#define MII_TG3_TEST1_CRC_EN 0x8000
2384
2385/* Clause 45 expansion registers */
2386#define TG3_CL45_D7_EEERES_STAT 0x803e
2387#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2388#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2389
2390
2391/* Fast Ethernet Tranceiver definitions */
2392#define MII_TG3_FET_PTEST 0x17
2393#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
2394#define MII_TG3_FET_PTEST_TRIM_2 0x0002
2395#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2396#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2397
2398#define MII_TG3_FET_GEN_STAT 0x1c
2399#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2400
2401#define MII_TG3_FET_TEST 0x1f
2402#define MII_TG3_FET_SHADOW_EN 0x0080
2403
2404#define MII_TG3_FET_SHDW_MISCCTRL 0x10
2405#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2406
2407#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2408#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2409
2410#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2411#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2412
2413/* Serdes PHY Register Definitions */
2414#define SERDES_TG3_1000X_STATUS 0x14
2415#define SERDES_TG3_SGMII_MODE 0x0001
2416#define SERDES_TG3_LINK_UP 0x0002
2417#define SERDES_TG3_FULL_DUPLEX 0x0004
2418#define SERDES_TG3_SPEED_100 0x0008
2419#define SERDES_TG3_SPEED_1000 0x0010
2420
2421/* APE registers. Accessible through BAR1 */
2422#define TG3_APE_GPIO_MSG 0x0008
2423#define TG3_APE_GPIO_MSG_SHIFT 4
2424#define TG3_APE_EVENT 0x000c
2425#define APE_EVENT_1 0x00000001
2426#define TG3_APE_LOCK_REQ 0x002c
2427#define APE_LOCK_REQ_DRIVER 0x00001000
2428#define TG3_APE_LOCK_GRANT 0x004c
2429#define APE_LOCK_GRANT_DRIVER 0x00001000
2430#define TG3_APE_OTP_CTRL 0x00e8
2431#define APE_OTP_CTRL_PROG_EN 0x200000
2432#define APE_OTP_CTRL_CMD_RD 0x000000
2433#define APE_OTP_CTRL_START 0x000001
2434#define TG3_APE_OTP_STATUS 0x00ec
2435#define APE_OTP_STATUS_CMD_DONE 0x000001
2436#define TG3_APE_OTP_ADDR 0x00f0
2437#define APE_OTP_ADDR_CPU_ENABLE 0x80000000
2438#define TG3_APE_OTP_RD_DATA 0x00f8
2439
2440#define OTP_ADDRESS_MAGIC0 0x00000050
2441#define TG3_OTP_MAGIC0_VALID(val) \
2442 ((((val) & 0xf0000000) == 0xa0000000) ||\
2443 (((val) & 0x0f000000) == 0x0a000000))
2444
2445/* APE shared memory. Accessible through BAR1 */
2446#define TG3_APE_SHMEM_BASE 0x4000
2447#define TG3_APE_SEG_SIG 0x4000
2448#define APE_SEG_SIG_MAGIC 0x41504521
2449#define TG3_APE_FW_STATUS 0x400c
2450#define APE_FW_STATUS_READY 0x00000100
2451#define TG3_APE_FW_FEATURES 0x4010
2452#define TG3_APE_FW_FEATURE_NCSI 0x00000002
2453#define TG3_APE_FW_VERSION 0x4018
2454#define APE_FW_VERSION_MAJMSK 0xff000000
2455#define APE_FW_VERSION_MAJSFT 24
2456#define APE_FW_VERSION_MINMSK 0x00ff0000
2457#define APE_FW_VERSION_MINSFT 16
2458#define APE_FW_VERSION_REVMSK 0x0000ff00
2459#define APE_FW_VERSION_REVSFT 8
2460#define APE_FW_VERSION_BLDMSK 0x000000ff
2461#define TG3_APE_SEG_MSG_BUF_OFF 0x401c
2462#define TG3_APE_SEG_MSG_BUF_LEN 0x4020
2463#define TG3_APE_HOST_SEG_SIG 0x4200
2464#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2465#define TG3_APE_HOST_SEG_LEN 0x4204
2466#define APE_HOST_SEG_LEN_MAGIC 0x00000020
2467#define TG3_APE_HOST_INIT_COUNT 0x4208
2468#define TG3_APE_HOST_DRIVER_ID 0x420c
2469#define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2470#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2471 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2472#define TG3_APE_HOST_BEHAVIOR 0x4210
2473#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2474#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2475#define APE_HOST_HEARTBEAT_INT_DISABLE 0
2476#define APE_HOST_HEARTBEAT_INT_5SEC 5000
2477#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2478#define TG3_APE_HOST_DRVR_STATE 0x421c
2479#define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2480#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2481#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2482#define TG3_APE_HOST_WOL_SPEED 0x4224
2483#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2484
2485#define TG3_APE_EVENT_STATUS 0x4300
2486
2487#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2488#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2489#define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600
2490#define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2491#define APE_EVENT_STATUS_STATE_START 0x00010000
2492#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2493#define APE_EVENT_STATUS_STATE_WOL 0x00030000
2494#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2495#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2496
2497#define TG3_APE_PER_LOCK_REQ 0x8400
2498#define APE_LOCK_PER_REQ_DRIVER 0x00001000
2499#define TG3_APE_PER_LOCK_GRANT 0x8420
2500#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2501
2502/* APE convenience enumerations. */
2503#define TG3_APE_LOCK_PHY0 0
2504#define TG3_APE_LOCK_GRC 1
2505#define TG3_APE_LOCK_PHY1 2
2506#define TG3_APE_LOCK_PHY2 3
2507#define TG3_APE_LOCK_MEM 4
2508#define TG3_APE_LOCK_PHY3 5
2509#define TG3_APE_LOCK_GPIO 7
2510
2511#define TG3_APE_HB_INTERVAL (tp->ape_hb_interval)
2512#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2513
2514
2515/* There are two ways to manage the TX descriptors on the tigon3.
2516 * Either the descriptors are in host DMA'able memory, or they
2517 * exist only in the cards on-chip SRAM. All 16 send bds are under
2518 * the same mode, they may not be configured individually.
2519 *
2520 * This driver always uses host memory TX descriptors.
2521 *
2522 * To use host memory TX descriptors:
2523 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2524 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2525 * 2) Allocate DMA'able memory.
2526 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2527 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2528 * obtained in step 2
2529 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2530 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2531 * of TX descriptors. Leave flags field clear.
2532 * 4) Access TX descriptors via host memory. The chip
2533 * will refetch into local SRAM as needed when producer
2534 * index mailboxes are updated.
2535 *
2536 * To use on-chip TX descriptors:
2537 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2538 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2539 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2540 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2541 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2542 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2543 * 3) Access TX descriptors directly in on-chip SRAM
2544 * using normal {read,write}l(). (and not using
2545 * pointer dereferencing of ioremap()'d memory like
2546 * the broken Broadcom driver does)
2547 *
2548 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2549 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2550 */
2551struct tg3_tx_buffer_desc {
2552 u32 addr_hi;
2553 u32 addr_lo;
2554
2555 u32 len_flags;
2556#define TXD_FLAG_TCPUDP_CSUM 0x0001
2557#define TXD_FLAG_IP_CSUM 0x0002
2558#define TXD_FLAG_END 0x0004
2559#define TXD_FLAG_IP_FRAG 0x0008
2560#define TXD_FLAG_JMB_PKT 0x0008
2561#define TXD_FLAG_IP_FRAG_END 0x0010
2562#define TXD_FLAG_HWTSTAMP 0x0020
2563#define TXD_FLAG_VLAN 0x0040
2564#define TXD_FLAG_COAL_NOW 0x0080
2565#define TXD_FLAG_CPU_PRE_DMA 0x0100
2566#define TXD_FLAG_CPU_POST_DMA 0x0200
2567#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2568#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2569#define TXD_FLAG_NO_CRC 0x8000
2570#define TXD_LEN_SHIFT 16
2571
2572 u32 vlan_tag;
2573#define TXD_VLAN_TAG_SHIFT 0
2574#define TXD_MSS_SHIFT 16
2575};
2576
2577#define TXD_ADDR 0x00UL /* 64-bit */
2578#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2579#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2580#define TXD_SIZE 0x10UL
2581
2582struct tg3_rx_buffer_desc {
2583 u32 addr_hi;
2584 u32 addr_lo;
2585
2586 u32 idx_len;
2587#define RXD_IDX_MASK 0xffff0000
2588#define RXD_IDX_SHIFT 16
2589#define RXD_LEN_MASK 0x0000ffff
2590#define RXD_LEN_SHIFT 0
2591
2592 u32 type_flags;
2593#define RXD_TYPE_SHIFT 16
2594#define RXD_FLAGS_SHIFT 0
2595
2596#define RXD_FLAG_END 0x0004
2597#define RXD_FLAG_MINI 0x0800
2598#define RXD_FLAG_JUMBO 0x0020
2599#define RXD_FLAG_VLAN 0x0040
2600#define RXD_FLAG_ERROR 0x0400
2601#define RXD_FLAG_IP_CSUM 0x1000
2602#define RXD_FLAG_TCPUDP_CSUM 0x2000
2603#define RXD_FLAG_IS_TCP 0x4000
2604#define RXD_FLAG_PTPSTAT_MASK 0x0210
2605#define RXD_FLAG_PTPSTAT_PTPV1 0x0010
2606#define RXD_FLAG_PTPSTAT_PTPV2 0x0200
2607
2608 u32 ip_tcp_csum;
2609#define RXD_IPCSUM_MASK 0xffff0000
2610#define RXD_IPCSUM_SHIFT 16
2611#define RXD_TCPCSUM_MASK 0x0000ffff
2612#define RXD_TCPCSUM_SHIFT 0
2613
2614 u32 err_vlan;
2615
2616#define RXD_VLAN_MASK 0x0000ffff
2617
2618#define RXD_ERR_BAD_CRC 0x00010000
2619#define RXD_ERR_COLLISION 0x00020000
2620#define RXD_ERR_LINK_LOST 0x00040000
2621#define RXD_ERR_PHY_DECODE 0x00080000
2622#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2623#define RXD_ERR_MAC_ABRT 0x00200000
2624#define RXD_ERR_TOO_SMALL 0x00400000
2625#define RXD_ERR_NO_RESOURCES 0x00800000
2626#define RXD_ERR_HUGE_FRAME 0x01000000
2627
2628#define RXD_ERR_MASK (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION | \
2629 RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE | \
2630 RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL | \
2631 RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME)
2632
2633 u32 reserved;
2634 u32 opaque;
2635#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2636#define RXD_OPAQUE_INDEX_SHIFT 0
2637#define RXD_OPAQUE_RING_STD 0x00010000
2638#define RXD_OPAQUE_RING_JUMBO 0x00020000
2639#define RXD_OPAQUE_RING_MINI 0x00040000
2640#define RXD_OPAQUE_RING_MASK 0x00070000
2641};
2642
2643struct tg3_ext_rx_buffer_desc {
2644 struct {
2645 u32 addr_hi;
2646 u32 addr_lo;
2647 } addrlist[3];
2648 u32 len2_len1;
2649 u32 resv_len3;
2650 struct tg3_rx_buffer_desc std;
2651};
2652
2653/* We only use this when testing out the DMA engine
2654 * at probe time. This is the internal format of buffer
2655 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2656 */
2657struct tg3_internal_buffer_desc {
2658 u32 addr_hi;
2659 u32 addr_lo;
2660 u32 nic_mbuf;
2661 /* XXX FIX THIS */
2662#ifdef __BIG_ENDIAN
2663 u16 cqid_sqid;
2664 u16 len;
2665#else
2666 u16 len;
2667 u16 cqid_sqid;
2668#endif
2669 u32 flags;
2670 u32 __cookie1;
2671 u32 __cookie2;
2672 u32 __cookie3;
2673};
2674
2675#define TG3_HW_STATUS_SIZE 0x50
2676struct tg3_hw_status {
2677 u32 status;
2678#define SD_STATUS_UPDATED 0x00000001
2679#define SD_STATUS_LINK_CHG 0x00000002
2680#define SD_STATUS_ERROR 0x00000004
2681
2682 u32 status_tag;
2683
2684#ifdef __BIG_ENDIAN
2685 u16 rx_consumer;
2686 u16 rx_jumbo_consumer;
2687#else
2688 u16 rx_jumbo_consumer;
2689 u16 rx_consumer;
2690#endif
2691
2692#ifdef __BIG_ENDIAN
2693 u16 reserved;
2694 u16 rx_mini_consumer;
2695#else
2696 u16 rx_mini_consumer;
2697 u16 reserved;
2698#endif
2699 struct {
2700#ifdef __BIG_ENDIAN
2701 u16 tx_consumer;
2702 u16 rx_producer;
2703#else
2704 u16 rx_producer;
2705 u16 tx_consumer;
2706#endif
2707 } idx[16];
2708};
2709
2710typedef struct {
2711 u32 high, low;
2712} tg3_stat64_t;
2713
2714struct tg3_hw_stats {
2715 u8 __reserved0[0x400-0x300];
2716
2717 /* Statistics maintained by Receive MAC. */
2718 tg3_stat64_t rx_octets;
2719 u64 __reserved1;
2720 tg3_stat64_t rx_fragments;
2721 tg3_stat64_t rx_ucast_packets;
2722 tg3_stat64_t rx_mcast_packets;
2723 tg3_stat64_t rx_bcast_packets;
2724 tg3_stat64_t rx_fcs_errors;
2725 tg3_stat64_t rx_align_errors;
2726 tg3_stat64_t rx_xon_pause_rcvd;
2727 tg3_stat64_t rx_xoff_pause_rcvd;
2728 tg3_stat64_t rx_mac_ctrl_rcvd;
2729 tg3_stat64_t rx_xoff_entered;
2730 tg3_stat64_t rx_frame_too_long_errors;
2731 tg3_stat64_t rx_jabbers;
2732 tg3_stat64_t rx_undersize_packets;
2733 tg3_stat64_t rx_in_length_errors;
2734 tg3_stat64_t rx_out_length_errors;
2735 tg3_stat64_t rx_64_or_less_octet_packets;
2736 tg3_stat64_t rx_65_to_127_octet_packets;
2737 tg3_stat64_t rx_128_to_255_octet_packets;
2738 tg3_stat64_t rx_256_to_511_octet_packets;
2739 tg3_stat64_t rx_512_to_1023_octet_packets;
2740 tg3_stat64_t rx_1024_to_1522_octet_packets;
2741 tg3_stat64_t rx_1523_to_2047_octet_packets;
2742 tg3_stat64_t rx_2048_to_4095_octet_packets;
2743 tg3_stat64_t rx_4096_to_8191_octet_packets;
2744 tg3_stat64_t rx_8192_to_9022_octet_packets;
2745
2746 u64 __unused0[37];
2747
2748 /* Statistics maintained by Transmit MAC. */
2749 tg3_stat64_t tx_octets;
2750 u64 __reserved2;
2751 tg3_stat64_t tx_collisions;
2752 tg3_stat64_t tx_xon_sent;
2753 tg3_stat64_t tx_xoff_sent;
2754 tg3_stat64_t tx_flow_control;
2755 tg3_stat64_t tx_mac_errors;
2756 tg3_stat64_t tx_single_collisions;
2757 tg3_stat64_t tx_mult_collisions;
2758 tg3_stat64_t tx_deferred;
2759 u64 __reserved3;
2760 tg3_stat64_t tx_excessive_collisions;
2761 tg3_stat64_t tx_late_collisions;
2762 tg3_stat64_t tx_collide_2times;
2763 tg3_stat64_t tx_collide_3times;
2764 tg3_stat64_t tx_collide_4times;
2765 tg3_stat64_t tx_collide_5times;
2766 tg3_stat64_t tx_collide_6times;
2767 tg3_stat64_t tx_collide_7times;
2768 tg3_stat64_t tx_collide_8times;
2769 tg3_stat64_t tx_collide_9times;
2770 tg3_stat64_t tx_collide_10times;
2771 tg3_stat64_t tx_collide_11times;
2772 tg3_stat64_t tx_collide_12times;
2773 tg3_stat64_t tx_collide_13times;
2774 tg3_stat64_t tx_collide_14times;
2775 tg3_stat64_t tx_collide_15times;
2776 tg3_stat64_t tx_ucast_packets;
2777 tg3_stat64_t tx_mcast_packets;
2778 tg3_stat64_t tx_bcast_packets;
2779 tg3_stat64_t tx_carrier_sense_errors;
2780 tg3_stat64_t tx_discards;
2781 tg3_stat64_t tx_errors;
2782
2783 u64 __unused1[31];
2784
2785 /* Statistics maintained by Receive List Placement. */
2786 tg3_stat64_t COS_rx_packets[16];
2787 tg3_stat64_t COS_rx_filter_dropped;
2788 tg3_stat64_t dma_writeq_full;
2789 tg3_stat64_t dma_write_prioq_full;
2790 tg3_stat64_t rxbds_empty;
2791 tg3_stat64_t rx_discards;
2792 tg3_stat64_t rx_errors;
2793 tg3_stat64_t rx_threshold_hit;
2794
2795 u64 __unused2[9];
2796
2797 /* Statistics maintained by Send Data Initiator. */
2798 tg3_stat64_t COS_out_packets[16];
2799 tg3_stat64_t dma_readq_full;
2800 tg3_stat64_t dma_read_prioq_full;
2801 tg3_stat64_t tx_comp_queue_full;
2802
2803 /* Statistics maintained by Host Coalescing. */
2804 tg3_stat64_t ring_set_send_prod_index;
2805 tg3_stat64_t ring_status_update;
2806 tg3_stat64_t nic_irqs;
2807 tg3_stat64_t nic_avoided_irqs;
2808 tg3_stat64_t nic_tx_threshold_hit;
2809
2810 /* NOT a part of the hardware statistics block format.
2811 * These stats are here as storage for tg3_periodic_fetch_stats().
2812 */
2813 tg3_stat64_t mbuf_lwm_thresh_hit;
2814
2815 u8 __reserved4[0xb00-0x9c8];
2816};
2817
2818#define TG3_SD_NUM_RECS 3
2819#define TG3_OCIR_LEN (sizeof(struct tg3_ocir))
2820#define TG3_OCIR_SIG_MAGIC 0x5253434f
2821#define TG3_OCIR_FLAG_ACTIVE 0x00000001
2822
2823#define TG3_TEMP_CAUTION_OFFSET 0xc8
2824#define TG3_TEMP_MAX_OFFSET 0xcc
2825#define TG3_TEMP_SENSOR_OFFSET 0xd4
2826
2827
2828struct tg3_ocir {
2829 u32 signature;
2830 u16 version_flags;
2831 u16 refresh_int;
2832 u32 refresh_tmr;
2833 u32 update_tmr;
2834 u32 dst_base_addr;
2835 u16 src_hdr_offset;
2836 u16 src_hdr_length;
2837 u16 src_data_offset;
2838 u16 src_data_length;
2839 u16 dst_hdr_offset;
2840 u16 dst_data_offset;
2841 u16 dst_reg_upd_offset;
2842 u16 dst_sem_offset;
2843 u32 reserved1[2];
2844 u32 port0_flags;
2845 u32 port1_flags;
2846 u32 port2_flags;
2847 u32 port3_flags;
2848 u32 reserved2[1];
2849};
2850
2851
2852/* 'mapping' is superfluous as the chip does not write into
2853 * the tx/rx post rings so we could just fetch it from there.
2854 * But the cache behavior is better how we are doing it now.
2855 *
2856 * This driver uses new build_skb() API :
2857 * RX ring buffer contains pointer to kmalloc() data only,
2858 * skb are built only after Hardware filled the frame.
2859 */
2860struct ring_info {
2861 u8 *data;
2862 DEFINE_DMA_UNMAP_ADDR(mapping);
2863};
2864
2865struct tg3_tx_ring_info {
2866 struct sk_buff *skb;
2867 DEFINE_DMA_UNMAP_ADDR(mapping);
2868 bool fragmented;
2869};
2870
2871struct tg3_link_config {
2872 /* Describes what we're trying to get. */
2873 u32 advertising;
2874 u16 speed;
2875 u8 duplex;
2876 u8 autoneg;
2877 u8 flowctrl;
2878
2879 /* Describes what we actually have. */
2880 u8 active_flowctrl;
2881
2882 u8 active_duplex;
2883 u16 active_speed;
2884 u32 rmt_adv;
2885};
2886
2887struct tg3_bufmgr_config {
2888 u32 mbuf_read_dma_low_water;
2889 u32 mbuf_mac_rx_low_water;
2890 u32 mbuf_high_water;
2891
2892 u32 mbuf_read_dma_low_water_jumbo;
2893 u32 mbuf_mac_rx_low_water_jumbo;
2894 u32 mbuf_high_water_jumbo;
2895
2896 u32 dma_low_water;
2897 u32 dma_high_water;
2898};
2899
2900struct tg3_ethtool_stats {
2901 /* Statistics maintained by Receive MAC. */
2902 u64 rx_octets;
2903 u64 rx_fragments;
2904 u64 rx_ucast_packets;
2905 u64 rx_mcast_packets;
2906 u64 rx_bcast_packets;
2907 u64 rx_fcs_errors;
2908 u64 rx_align_errors;
2909 u64 rx_xon_pause_rcvd;
2910 u64 rx_xoff_pause_rcvd;
2911 u64 rx_mac_ctrl_rcvd;
2912 u64 rx_xoff_entered;
2913 u64 rx_frame_too_long_errors;
2914 u64 rx_jabbers;
2915 u64 rx_undersize_packets;
2916 u64 rx_in_length_errors;
2917 u64 rx_out_length_errors;
2918 u64 rx_64_or_less_octet_packets;
2919 u64 rx_65_to_127_octet_packets;
2920 u64 rx_128_to_255_octet_packets;
2921 u64 rx_256_to_511_octet_packets;
2922 u64 rx_512_to_1023_octet_packets;
2923 u64 rx_1024_to_1522_octet_packets;
2924 u64 rx_1523_to_2047_octet_packets;
2925 u64 rx_2048_to_4095_octet_packets;
2926 u64 rx_4096_to_8191_octet_packets;
2927 u64 rx_8192_to_9022_octet_packets;
2928
2929 /* Statistics maintained by Transmit MAC. */
2930 u64 tx_octets;
2931 u64 tx_collisions;
2932 u64 tx_xon_sent;
2933 u64 tx_xoff_sent;
2934 u64 tx_flow_control;
2935 u64 tx_mac_errors;
2936 u64 tx_single_collisions;
2937 u64 tx_mult_collisions;
2938 u64 tx_deferred;
2939 u64 tx_excessive_collisions;
2940 u64 tx_late_collisions;
2941 u64 tx_collide_2times;
2942 u64 tx_collide_3times;
2943 u64 tx_collide_4times;
2944 u64 tx_collide_5times;
2945 u64 tx_collide_6times;
2946 u64 tx_collide_7times;
2947 u64 tx_collide_8times;
2948 u64 tx_collide_9times;
2949 u64 tx_collide_10times;
2950 u64 tx_collide_11times;
2951 u64 tx_collide_12times;
2952 u64 tx_collide_13times;
2953 u64 tx_collide_14times;
2954 u64 tx_collide_15times;
2955 u64 tx_ucast_packets;
2956 u64 tx_mcast_packets;
2957 u64 tx_bcast_packets;
2958 u64 tx_carrier_sense_errors;
2959 u64 tx_discards;
2960 u64 tx_errors;
2961
2962 /* Statistics maintained by Receive List Placement. */
2963 u64 dma_writeq_full;
2964 u64 dma_write_prioq_full;
2965 u64 rxbds_empty;
2966 u64 rx_discards;
2967 u64 rx_errors;
2968 u64 rx_threshold_hit;
2969
2970 /* Statistics maintained by Send Data Initiator. */
2971 u64 dma_readq_full;
2972 u64 dma_read_prioq_full;
2973 u64 tx_comp_queue_full;
2974
2975 /* Statistics maintained by Host Coalescing. */
2976 u64 ring_set_send_prod_index;
2977 u64 ring_status_update;
2978 u64 nic_irqs;
2979 u64 nic_avoided_irqs;
2980 u64 nic_tx_threshold_hit;
2981
2982 u64 mbuf_lwm_thresh_hit;
2983};
2984
2985struct tg3_rx_prodring_set {
2986 u32 rx_std_prod_idx;
2987 u32 rx_std_cons_idx;
2988 u32 rx_jmb_prod_idx;
2989 u32 rx_jmb_cons_idx;
2990 struct tg3_rx_buffer_desc *rx_std;
2991 struct tg3_ext_rx_buffer_desc *rx_jmb;
2992 struct ring_info *rx_std_buffers;
2993 struct ring_info *rx_jmb_buffers;
2994 dma_addr_t rx_std_mapping;
2995 dma_addr_t rx_jmb_mapping;
2996};
2997
2998#define TG3_RSS_MAX_NUM_QS 4
2999#define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1)
3000#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
3001
3002struct tg3_napi {
3003 struct napi_struct napi ____cacheline_aligned;
3004 struct tg3 *tp;
3005 struct tg3_hw_status *hw_status;
3006
3007 u32 chk_msi_cnt;
3008 u32 last_tag;
3009 u32 last_irq_tag;
3010 u32 int_mbox;
3011 u32 coal_now;
3012
3013 u32 consmbox ____cacheline_aligned;
3014 u32 rx_rcb_ptr;
3015 u32 last_rx_cons;
3016 u16 *rx_rcb_prod_idx;
3017 struct tg3_rx_prodring_set prodring;
3018 struct tg3_rx_buffer_desc *rx_rcb;
3019
3020 u32 tx_prod ____cacheline_aligned;
3021 u32 tx_cons;
3022 u32 tx_pending;
3023 u32 last_tx_cons;
3024 u32 prodmbox;
3025 struct tg3_tx_buffer_desc *tx_ring;
3026 struct tg3_tx_ring_info *tx_buffers;
3027
3028 dma_addr_t status_mapping;
3029 dma_addr_t rx_rcb_mapping;
3030 dma_addr_t tx_desc_mapping;
3031
3032 char irq_lbl[IFNAMSIZ];
3033 unsigned int irq_vec;
3034};
3035
3036enum TG3_FLAGS {
3037 TG3_FLAG_TAGGED_STATUS = 0,
3038 TG3_FLAG_TXD_MBOX_HWBUG,
3039 TG3_FLAG_USE_LINKCHG_REG,
3040 TG3_FLAG_ERROR_PROCESSED,
3041 TG3_FLAG_ENABLE_ASF,
3042 TG3_FLAG_ASPM_WORKAROUND,
3043 TG3_FLAG_POLL_SERDES,
3044 TG3_FLAG_POLL_CPMU_LINK,
3045 TG3_FLAG_MBOX_WRITE_REORDER,
3046 TG3_FLAG_PCIX_TARGET_HWBUG,
3047 TG3_FLAG_WOL_SPEED_100MB,
3048 TG3_FLAG_WOL_ENABLE,
3049 TG3_FLAG_EEPROM_WRITE_PROT,
3050 TG3_FLAG_NVRAM,
3051 TG3_FLAG_NVRAM_BUFFERED,
3052 TG3_FLAG_SUPPORT_MSI,
3053 TG3_FLAG_SUPPORT_MSIX,
3054 TG3_FLAG_USING_MSI,
3055 TG3_FLAG_USING_MSIX,
3056 TG3_FLAG_PCIX_MODE,
3057 TG3_FLAG_PCI_HIGH_SPEED,
3058 TG3_FLAG_PCI_32BIT,
3059 TG3_FLAG_SRAM_USE_CONFIG,
3060 TG3_FLAG_TX_RECOVERY_PENDING,
3061 TG3_FLAG_WOL_CAP,
3062 TG3_FLAG_JUMBO_RING_ENABLE,
3063 TG3_FLAG_PAUSE_AUTONEG,
3064 TG3_FLAG_CPMU_PRESENT,
3065 TG3_FLAG_40BIT_DMA_BUG,
3066 TG3_FLAG_BROKEN_CHECKSUMS,
3067 TG3_FLAG_JUMBO_CAPABLE,
3068 TG3_FLAG_CHIP_RESETTING,
3069 TG3_FLAG_INIT_COMPLETE,
3070 TG3_FLAG_MAX_RXPEND_64,
3071 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
3072 TG3_FLAG_ASF_NEW_HANDSHAKE,
3073 TG3_FLAG_HW_AUTONEG,
3074 TG3_FLAG_IS_NIC,
3075 TG3_FLAG_FLASH,
3076 TG3_FLAG_FW_TSO,
3077 TG3_FLAG_HW_TSO_1,
3078 TG3_FLAG_HW_TSO_2,
3079 TG3_FLAG_HW_TSO_3,
3080 TG3_FLAG_TSO_CAPABLE,
3081 TG3_FLAG_TSO_BUG,
3082 TG3_FLAG_ICH_WORKAROUND,
3083 TG3_FLAG_1SHOT_MSI,
3084 TG3_FLAG_NO_FWARE_REPORTED,
3085 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
3086 TG3_FLAG_ENABLE_APE,
3087 TG3_FLAG_PROTECTED_NVRAM,
3088 TG3_FLAG_5701_DMA_BUG,
3089 TG3_FLAG_USE_PHYLIB,
3090 TG3_FLAG_MDIOBUS_INITED,
3091 TG3_FLAG_LRG_PROD_RING_CAP,
3092 TG3_FLAG_RGMII_INBAND_DISABLE,
3093 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
3094 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
3095 TG3_FLAG_CLKREQ_BUG,
3096 TG3_FLAG_NO_NVRAM,
3097 TG3_FLAG_ENABLE_RSS,
3098 TG3_FLAG_ENABLE_TSS,
3099 TG3_FLAG_SHORT_DMA_BUG,
3100 TG3_FLAG_USE_JUMBO_BDFLAG,
3101 TG3_FLAG_L1PLLPD_EN,
3102 TG3_FLAG_APE_HAS_NCSI,
3103 TG3_FLAG_TX_TSTAMP_EN,
3104 TG3_FLAG_4K_FIFO_LIMIT,
3105 TG3_FLAG_5719_5720_RDMA_BUG,
3106 TG3_FLAG_RESET_TASK_PENDING,
3107 TG3_FLAG_PTP_CAPABLE,
3108 TG3_FLAG_5705_PLUS,
3109 TG3_FLAG_IS_5788,
3110 TG3_FLAG_5750_PLUS,
3111 TG3_FLAG_5780_CLASS,
3112 TG3_FLAG_5755_PLUS,
3113 TG3_FLAG_57765_PLUS,
3114 TG3_FLAG_57765_CLASS,
3115 TG3_FLAG_5717_PLUS,
3116 TG3_FLAG_IS_SSB_CORE,
3117 TG3_FLAG_FLUSH_POSTED_WRITES,
3118 TG3_FLAG_ROBOSWITCH,
3119 TG3_FLAG_ONE_DMA_AT_ONCE,
3120 TG3_FLAG_RGMII_MODE,
3121
3122 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3123 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
3124};
3125
3126struct tg3_firmware_hdr {
3127 __be32 version; /* unused for fragments */
3128 __be32 base_addr;
3129 __be32 len;
3130};
3131#define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr))
3132
3133struct tg3 {
3134 /* begin "general, frequently-used members" cacheline section */
3135
3136 /* If the IRQ handler (which runs lockless) needs to be
3137 * quiesced, the following bitmask state is used. The
3138 * SYNC flag is set by non-IRQ context code to initiate
3139 * the quiescence.
3140 *
3141 * When the IRQ handler notices that SYNC is set, it
3142 * disables interrupts and returns.
3143 *
3144 * When all outstanding IRQ handlers have returned after
3145 * the SYNC flag has been set, the setter can be assured
3146 * that interrupts will no longer get run.
3147 *
3148 * In this way all SMP driver locks are never acquired
3149 * in hw IRQ context, only sw IRQ context or lower.
3150 */
3151 unsigned int irq_sync;
3152
3153 /* SMP locking strategy:
3154 *
3155 * lock: Held during reset, PHY access, timer, and when
3156 * updating tg3_flags.
3157 *
3158 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3159 * netif_tx_lock when it needs to call
3160 * netif_wake_queue.
3161 *
3162 * Both of these locks are to be held with BH safety.
3163 *
3164 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3165 * are running lockless, it is necessary to completely
3166 * quiesce the chip with tg3_netif_stop and tg3_full_lock
3167 * before reconfiguring the device.
3168 *
3169 * indirect_lock: Held when accessing registers indirectly
3170 * with IRQ disabling.
3171 */
3172 spinlock_t lock;
3173 spinlock_t indirect_lock;
3174
3175 u32 (*read32) (struct tg3 *, u32);
3176 void (*write32) (struct tg3 *, u32, u32);
3177 u32 (*read32_mbox) (struct tg3 *, u32);
3178 void (*write32_mbox) (struct tg3 *, u32,
3179 u32);
3180 void __iomem *regs;
3181 void __iomem *aperegs;
3182 struct net_device *dev;
3183 struct pci_dev *pdev;
3184
3185 u32 coal_now;
3186 u32 msg_enable;
3187
3188 struct ptp_clock_info ptp_info;
3189 struct ptp_clock *ptp_clock;
3190 s64 ptp_adjust;
3191
3192 /* begin "tx thread" cacheline section */
3193 void (*write32_tx_mbox) (struct tg3 *, u32,
3194 u32);
3195 u32 dma_limit;
3196 u32 txq_req;
3197 u32 txq_cnt;
3198 u32 txq_max;
3199
3200 /* begin "rx thread" cacheline section */
3201 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
3202 void (*write32_rx_mbox) (struct tg3 *, u32,
3203 u32);
3204 u32 rx_copy_thresh;
3205 u32 rx_std_ring_mask;
3206 u32 rx_jmb_ring_mask;
3207 u32 rx_ret_ring_mask;
3208 u32 rx_pending;
3209 u32 rx_jumbo_pending;
3210 u32 rx_std_max_post;
3211 u32 rx_offset;
3212 u32 rx_pkt_map_sz;
3213 u32 rxq_req;
3214 u32 rxq_cnt;
3215 u32 rxq_max;
3216 bool rx_refill;
3217
3218
3219 /* begin "everything else" cacheline(s) section */
3220 unsigned long rx_dropped;
3221 unsigned long tx_dropped;
3222 struct rtnl_link_stats64 net_stats_prev;
3223 struct tg3_ethtool_stats estats_prev;
3224
3225 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3226
3227 union {
3228 unsigned long phy_crc_errors;
3229 unsigned long last_event_jiffies;
3230 };
3231
3232 struct timer_list timer;
3233 u16 timer_counter;
3234 u16 timer_multiplier;
3235 u32 timer_offset;
3236 u16 asf_counter;
3237 u16 asf_multiplier;
3238
3239 /* 1 second counter for transient serdes link events */
3240 u32 serdes_counter;
3241#define SERDES_AN_TIMEOUT_5704S 2
3242#define SERDES_PARALLEL_DET_TIMEOUT 1
3243#define SERDES_AN_TIMEOUT_5714S 1
3244
3245 struct tg3_link_config link_config;
3246 struct tg3_bufmgr_config bufmgr_config;
3247
3248 /* cache h/w values, often passed straight to h/w */
3249 u32 rx_mode;
3250 u32 tx_mode;
3251 u32 mac_mode;
3252 u32 mi_mode;
3253 u32 misc_host_ctrl;
3254 u32 grc_mode;
3255 u32 grc_local_ctrl;
3256 u32 dma_rwctrl;
3257 u32 coalesce_mode;
3258 u32 pwrmgmt_thresh;
3259 u32 rxptpctl;
3260
3261 /* PCI block */
3262 u32 pci_chip_rev_id;
3263 u16 pci_cmd;
3264 u8 pci_cacheline_sz;
3265 u8 pci_lat_timer;
3266
3267 int pci_fn;
3268 int msi_cap;
3269 int pcix_cap;
3270 int pcie_readrq;
3271
3272 struct mii_bus *mdio_bus;
3273 int old_link;
3274
3275 u8 phy_addr;
3276 u8 phy_ape_lock;
3277
3278 /* PHY info */
3279 u32 phy_id;
3280#define TG3_PHY_ID_MASK 0xfffffff0
3281#define TG3_PHY_ID_BCM5400 0x60008040
3282#define TG3_PHY_ID_BCM5401 0x60008050
3283#define TG3_PHY_ID_BCM5411 0x60008070
3284#define TG3_PHY_ID_BCM5701 0x60008110
3285#define TG3_PHY_ID_BCM5703 0x60008160
3286#define TG3_PHY_ID_BCM5704 0x60008190
3287#define TG3_PHY_ID_BCM5705 0x600081a0
3288#define TG3_PHY_ID_BCM5750 0x60008180
3289#define TG3_PHY_ID_BCM5752 0x60008100
3290#define TG3_PHY_ID_BCM5714 0x60008340
3291#define TG3_PHY_ID_BCM5780 0x60008350
3292#define TG3_PHY_ID_BCM5755 0xbc050cc0
3293#define TG3_PHY_ID_BCM5787 0xbc050ce0
3294#define TG3_PHY_ID_BCM5756 0xbc050ed0
3295#define TG3_PHY_ID_BCM5784 0xbc050fa0
3296#define TG3_PHY_ID_BCM5761 0xbc050fd0
3297#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3298#define TG3_PHY_ID_BCM5718S 0xbc050ff0
3299#define TG3_PHY_ID_BCM57765 0x5c0d8a40
3300#define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3301#define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3302#define TG3_PHY_ID_BCM5762 0x85803780
3303#define TG3_PHY_ID_BCM5906 0xdc00ac40
3304#define TG3_PHY_ID_BCM8002 0x60010140
3305#define TG3_PHY_ID_INVALID 0xffffffff
3306
3307#define PHY_ID_RTL8211C 0x001cc910
3308#define PHY_ID_RTL8201E 0x00008200
3309
3310#define TG3_PHY_ID_REV_MASK 0x0000000f
3311#define TG3_PHY_REV_BCM5401_B0 0x1
3312
3313 /* This macro assumes the passed PHY ID is
3314 * already masked with TG3_PHY_ID_MASK.
3315 */
3316#define TG3_KNOWN_PHY_ID(X) \
3317 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3318 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3319 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3320 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3321 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3322 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3323 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3324 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3325 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3326 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3327 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \
3328 (X) == TG3_PHY_ID_BCM8002)
3329
3330 u32 phy_flags;
3331#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3332#define TG3_PHYFLG_IS_CONNECTED 0x00000002
3333#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3334#define TG3_PHYFLG_USER_CONFIGURED 0x00000008
3335#define TG3_PHYFLG_PHY_SERDES 0x00000010
3336#define TG3_PHYFLG_MII_SERDES 0x00000020
3337#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3338 TG3_PHYFLG_MII_SERDES)
3339#define TG3_PHYFLG_IS_FET 0x00000040
3340#define TG3_PHYFLG_10_100_ONLY 0x00000080
3341#define TG3_PHYFLG_ENABLE_APD 0x00000100
3342#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3343#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3344#define TG3_PHYFLG_JITTER_BUG 0x00000800
3345#define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3346#define TG3_PHYFLG_ADC_BUG 0x00002000
3347#define TG3_PHYFLG_5704_A0_BUG 0x00004000
3348#define TG3_PHYFLG_BER_BUG 0x00008000
3349#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3350#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3351#define TG3_PHYFLG_EEE_CAP 0x00040000
3352#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
3353#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
3354#define TG3_PHYFLG_MDIX_STATE 0x00200000
3355#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000
3356
3357 u32 led_ctrl;
3358 u32 phy_otp;
3359 u32 setlpicnt;
3360 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3361
3362#define TG3_BPN_SIZE 24
3363 char board_part_number[TG3_BPN_SIZE];
3364#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
3365 char fw_ver[TG3_VER_SIZE];
3366 u32 nic_sram_data_cfg;
3367 u32 pci_clock_ctrl;
3368 struct pci_dev *pdev_peer;
3369
3370 struct tg3_hw_stats *hw_stats;
3371 dma_addr_t stats_mapping;
3372 struct work_struct reset_task;
3373
3374 int nvram_lock_cnt;
3375 u32 nvram_size;
3376#define TG3_NVRAM_SIZE_2KB 0x00000800
3377#define TG3_NVRAM_SIZE_64KB 0x00010000
3378#define TG3_NVRAM_SIZE_128KB 0x00020000
3379#define TG3_NVRAM_SIZE_256KB 0x00040000
3380#define TG3_NVRAM_SIZE_512KB 0x00080000
3381#define TG3_NVRAM_SIZE_1MB 0x00100000
3382#define TG3_NVRAM_SIZE_2MB 0x00200000
3383
3384 u32 nvram_pagesize;
3385 u32 nvram_jedecnum;
3386
3387#define JEDEC_ATMEL 0x1f
3388#define JEDEC_ST 0x20
3389#define JEDEC_SAIFUN 0x4f
3390#define JEDEC_SST 0xbf
3391#define JEDEC_MACRONIX 0xc2
3392
3393#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3394#define ATMEL_AT24C02_PAGE_SIZE (8)
3395
3396#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3397#define ATMEL_AT24C64_PAGE_SIZE (32)
3398
3399#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3400#define ATMEL_AT24C512_PAGE_SIZE (128)
3401
3402#define ATMEL_AT45DB0X1B_PAGE_POS 9
3403#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3404
3405#define ATMEL_AT25F512_PAGE_SIZE 256
3406
3407#define ST_M45PEX0_PAGE_SIZE 256
3408
3409#define SAIFUN_SA25F0XX_PAGE_SIZE 256
3410
3411#define SST_25VF0X0_PAGE_SIZE 4098
3412
3413 unsigned int irq_max;
3414 unsigned int irq_cnt;
3415
3416 struct ethtool_coalesce coal;
3417 struct ethtool_eee eee;
3418
3419 /* firmware info */
3420 const char *fw_needed;
3421 const struct firmware *fw;
3422 u32 fw_len; /* includes BSS */
3423
3424 struct device *hwmon_dev;
3425 bool link_up;
3426 bool pcierr_recovery;
3427
3428 u32 ape_hb;
3429 unsigned long ape_hb_interval;
3430 unsigned long ape_hb_jiffies;
3431};
3432
3433/* Accessor macros for chip and asic attributes
3434 *
3435 * nb: Using static inlines equivalent to the accessor macros generates
3436 * larger object code with gcc 4.7.
3437 * Using statement expression macros to check tp with
3438 * typecheck(struct tg3 *, tp) also creates larger objects.
3439 */
3440#define tg3_chip_rev_id(tp) \
3441 ((tp)->pci_chip_rev_id)
3442#define tg3_asic_rev(tp) \
3443 ((tp)->pci_chip_rev_id >> 12)
3444#define tg3_chip_rev(tp) \
3445 ((tp)->pci_chip_rev_id >> 8)
3446
3447#endif /* !(_T3_H) */
1/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2007-2014 Broadcom Corporation.
8 */
9
10#ifndef _T3_H
11#define _T3_H
12
13#define TG3_64BIT_REG_HIGH 0x00UL
14#define TG3_64BIT_REG_LOW 0x04UL
15
16/* Descriptor block info. */
17#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
18#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
19#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
20#define BDINFO_FLAGS_DISABLED 0x00000002
21#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
22#define BDINFO_FLAGS_MAXLEN_SHIFT 16
23#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
24#define TG3_BDINFO_SIZE 0x10UL
25
26#define TG3_RX_STD_MAX_SIZE_5700 512
27#define TG3_RX_STD_MAX_SIZE_5717 2048
28#define TG3_RX_JMB_MAX_SIZE_5700 256
29#define TG3_RX_JMB_MAX_SIZE_5717 1024
30#define TG3_RX_RET_MAX_SIZE_5700 1024
31#define TG3_RX_RET_MAX_SIZE_5705 512
32#define TG3_RX_RET_MAX_SIZE_5717 4096
33
34#define TG3_RSS_INDIR_TBL_SIZE 128
35
36/* First 256 bytes are a mirror of PCI config space. */
37#define TG3PCI_VENDOR 0x00000000
38#define TG3PCI_VENDOR_BROADCOM 0x14e4
39#define TG3PCI_DEVICE 0x00000002
40#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
41#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
42#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
43#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
44#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
45#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
46#define TG3PCI_DEVICE_TIGON3_57780 0x1692
47#define TG3PCI_DEVICE_TIGON3_5787M 0x1693
48#define TG3PCI_DEVICE_TIGON3_57760 0x1690
49#define TG3PCI_DEVICE_TIGON3_57790 0x1694
50#define TG3PCI_DEVICE_TIGON3_57788 0x1691
51#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
52#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
53#define TG3PCI_DEVICE_TIGON3_5717 0x1655
54#define TG3PCI_DEVICE_TIGON3_5717_C 0x1665
55#define TG3PCI_DEVICE_TIGON3_5718 0x1656
56#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
57#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
58#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
59#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
60#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
61#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
62#define TG3PCI_DEVICE_TIGON3_5719 0x1657
63#define TG3PCI_DEVICE_TIGON3_5720 0x165f
64#define TG3PCI_DEVICE_TIGON3_57762 0x1682
65#define TG3PCI_DEVICE_TIGON3_57766 0x1686
66#define TG3PCI_DEVICE_TIGON3_57786 0x16b3
67#define TG3PCI_DEVICE_TIGON3_57782 0x16b7
68#define TG3PCI_DEVICE_TIGON3_5762 0x1687
69#define TG3PCI_DEVICE_TIGON3_5725 0x1643
70#define TG3PCI_DEVICE_TIGON3_5727 0x16f3
71#define TG3PCI_DEVICE_TIGON3_57764 0x1642
72#define TG3PCI_DEVICE_TIGON3_57767 0x1683
73#define TG3PCI_DEVICE_TIGON3_57787 0x1641
74/* 0x04 --> 0x2c unused */
75#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
76#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
77#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
78#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
79#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
80#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
81#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
82#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
83#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
84#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
85#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
86#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
87#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
88#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
89#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
90#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
91#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
92#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
93#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
94#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
95#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
96#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
97#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
98#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
99#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
100#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
101#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
102#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
103#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
104#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
105#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
106#define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601
107#define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612
108#define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056
109
110/* 0x30 --> 0x64 unused */
111#define TG3PCI_MSI_DATA 0x00000064
112/* 0x66 --> 0x68 unused */
113#define TG3PCI_MISC_HOST_CTRL 0x00000068
114#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
115#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
116#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
117#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
118#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
119#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
120#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
121#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
122#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
123#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
124#define MISC_HOST_CTRL_CHIPREV 0xffff0000
125#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
126
127#define CHIPREV_ID_5700_A0 0x7000
128#define CHIPREV_ID_5700_A1 0x7001
129#define CHIPREV_ID_5700_B0 0x7100
130#define CHIPREV_ID_5700_B1 0x7101
131#define CHIPREV_ID_5700_B3 0x7102
132#define CHIPREV_ID_5700_ALTIMA 0x7104
133#define CHIPREV_ID_5700_C0 0x7200
134#define CHIPREV_ID_5701_A0 0x0000
135#define CHIPREV_ID_5701_B0 0x0100
136#define CHIPREV_ID_5701_B2 0x0102
137#define CHIPREV_ID_5701_B5 0x0105
138#define CHIPREV_ID_5703_A0 0x1000
139#define CHIPREV_ID_5703_A1 0x1001
140#define CHIPREV_ID_5703_A2 0x1002
141#define CHIPREV_ID_5703_A3 0x1003
142#define CHIPREV_ID_5704_A0 0x2000
143#define CHIPREV_ID_5704_A1 0x2001
144#define CHIPREV_ID_5704_A2 0x2002
145#define CHIPREV_ID_5704_A3 0x2003
146#define CHIPREV_ID_5705_A0 0x3000
147#define CHIPREV_ID_5705_A1 0x3001
148#define CHIPREV_ID_5705_A2 0x3002
149#define CHIPREV_ID_5705_A3 0x3003
150#define CHIPREV_ID_5750_A0 0x4000
151#define CHIPREV_ID_5750_A1 0x4001
152#define CHIPREV_ID_5750_A3 0x4003
153#define CHIPREV_ID_5750_C2 0x4202
154#define CHIPREV_ID_5752_A0_HW 0x5000
155#define CHIPREV_ID_5752_A0 0x6000
156#define CHIPREV_ID_5752_A1 0x6001
157#define CHIPREV_ID_5714_A2 0x9002
158#define CHIPREV_ID_5906_A1 0xc001
159#define CHIPREV_ID_57780_A0 0x57780000
160#define CHIPREV_ID_57780_A1 0x57780001
161#define CHIPREV_ID_5717_A0 0x05717000
162#define CHIPREV_ID_5717_C0 0x05717200
163#define CHIPREV_ID_57765_A0 0x57785000
164#define CHIPREV_ID_5719_A0 0x05719000
165#define CHIPREV_ID_5720_A0 0x05720000
166#define CHIPREV_ID_5762_A0 0x05762000
167
168#define ASIC_REV_5700 0x07
169#define ASIC_REV_5701 0x00
170#define ASIC_REV_5703 0x01
171#define ASIC_REV_5704 0x02
172#define ASIC_REV_5705 0x03
173#define ASIC_REV_5750 0x04
174#define ASIC_REV_5752 0x06
175#define ASIC_REV_5780 0x08
176#define ASIC_REV_5714 0x09
177#define ASIC_REV_5755 0x0a
178#define ASIC_REV_5787 0x0b
179#define ASIC_REV_5906 0x0c
180#define ASIC_REV_USE_PROD_ID_REG 0x0f
181#define ASIC_REV_5784 0x5784
182#define ASIC_REV_5761 0x5761
183#define ASIC_REV_5785 0x5785
184#define ASIC_REV_57780 0x57780
185#define ASIC_REV_5717 0x5717
186#define ASIC_REV_57765 0x57785
187#define ASIC_REV_5719 0x5719
188#define ASIC_REV_5720 0x5720
189#define ASIC_REV_57766 0x57766
190#define ASIC_REV_5762 0x5762
191#define CHIPREV_5700_AX 0x70
192#define CHIPREV_5700_BX 0x71
193#define CHIPREV_5700_CX 0x72
194#define CHIPREV_5701_AX 0x00
195#define CHIPREV_5703_AX 0x10
196#define CHIPREV_5704_AX 0x20
197#define CHIPREV_5704_BX 0x21
198#define CHIPREV_5750_AX 0x40
199#define CHIPREV_5750_BX 0x41
200#define CHIPREV_5784_AX 0x57840
201#define CHIPREV_5761_AX 0x57610
202#define CHIPREV_57765_AX 0x577650
203#define METAL_REV_A0 0x00
204#define METAL_REV_A1 0x01
205#define METAL_REV_B0 0x00
206#define METAL_REV_B1 0x01
207#define METAL_REV_B2 0x02
208#define TG3PCI_DMA_RW_CTRL 0x0000006c
209#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
210#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
211#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
212#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
213#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
214#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
215#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
216#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
217#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
218#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
219#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
220#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
221#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
222#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
223#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
224#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
225#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
226#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
227#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
228#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
229#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
230#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
231#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
232#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
233#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
234#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
235#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
236#define DMA_RWCTRL_ONE_DMA 0x00004000
237#define DMA_RWCTRL_READ_WATER 0x00070000
238#define DMA_RWCTRL_READ_WATER_SHIFT 16
239#define DMA_RWCTRL_WRITE_WATER 0x00380000
240#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
241#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
242#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
243#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
244#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
245#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
246#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
247#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
248#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
249#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
250#define TG3PCI_PCISTATE 0x00000070
251#define PCISTATE_FORCE_RESET 0x00000001
252#define PCISTATE_INT_NOT_ACTIVE 0x00000002
253#define PCISTATE_CONV_PCI_MODE 0x00000004
254#define PCISTATE_BUS_SPEED_HIGH 0x00000008
255#define PCISTATE_BUS_32BIT 0x00000010
256#define PCISTATE_ROM_ENABLE 0x00000020
257#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
258#define PCISTATE_FLAT_VIEW 0x00000100
259#define PCISTATE_RETRY_SAME_DMA 0x00002000
260#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
261#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
262#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
263#define TG3PCI_CLOCK_CTRL 0x00000074
264#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
265#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
266#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
267#define CLOCK_CTRL_ALTCLK 0x00001000
268#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
269#define CLOCK_CTRL_44MHZ_CORE 0x00040000
270#define CLOCK_CTRL_625_CORE 0x00100000
271#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
272#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
273#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
274#define TG3PCI_REG_BASE_ADDR 0x00000078
275#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
276#define TG3PCI_REG_DATA 0x00000080
277#define TG3PCI_MEM_WIN_DATA 0x00000084
278#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
279/* 0x94 --> 0x98 unused */
280#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
281#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
282/* 0xa8 --> 0xb8 unused */
283#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
284#define DUAL_MAC_CTRL_CH_MASK 0x00000003
285#define DUAL_MAC_CTRL_ID 0x00000004
286#define TG3PCI_PRODID_ASICREV 0x000000bc
287#define PROD_ID_ASIC_REV_MASK 0x0fffffff
288/* 0xc0 --> 0xf4 unused */
289
290#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
291#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
292/* 0xf8 --> 0x200 unused */
293
294#define TG3_CORR_ERR_STAT 0x00000110
295#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
296/* 0x114 --> 0x200 unused */
297
298/* Mailbox registers */
299#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
300#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
301#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
302#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
303#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
304#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
305#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
306#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
307#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
308#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
309#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
310#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
311#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
312#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
313#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
314 TG3_64BIT_REG_LOW)
315#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
316#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
317 TG3_64BIT_REG_LOW)
318#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
319#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
320#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
321#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
322#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
323#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
324#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
325#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
326#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
327#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
328#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
329#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
330#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
331#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
332#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
333#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
334#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
335#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
336#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
337#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
338#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
339#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
340#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
341#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
342#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
343#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
344#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
345#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
346#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
347#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
348#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
349#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
350#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
351#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
352#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
353#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
354#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
355#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
356#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
357#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
358#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
359#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
360#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
361#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
362#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
363#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
364#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
365#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
366#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
367
368/* MAC control registers */
369#define MAC_MODE 0x00000400
370#define MAC_MODE_RESET 0x00000001
371#define MAC_MODE_HALF_DUPLEX 0x00000002
372#define MAC_MODE_PORT_MODE_MASK 0x0000000c
373#define MAC_MODE_PORT_MODE_TBI 0x0000000c
374#define MAC_MODE_PORT_MODE_GMII 0x00000008
375#define MAC_MODE_PORT_MODE_MII 0x00000004
376#define MAC_MODE_PORT_MODE_NONE 0x00000000
377#define MAC_MODE_PORT_INT_LPBACK 0x00000010
378#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
379#define MAC_MODE_TX_BURSTING 0x00000100
380#define MAC_MODE_MAX_DEFER 0x00000200
381#define MAC_MODE_LINK_POLARITY 0x00000400
382#define MAC_MODE_RXSTAT_ENABLE 0x00000800
383#define MAC_MODE_RXSTAT_CLEAR 0x00001000
384#define MAC_MODE_RXSTAT_FLUSH 0x00002000
385#define MAC_MODE_TXSTAT_ENABLE 0x00004000
386#define MAC_MODE_TXSTAT_CLEAR 0x00008000
387#define MAC_MODE_TXSTAT_FLUSH 0x00010000
388#define MAC_MODE_SEND_CONFIGS 0x00020000
389#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
390#define MAC_MODE_ACPI_ENABLE 0x00080000
391#define MAC_MODE_MIP_ENABLE 0x00100000
392#define MAC_MODE_TDE_ENABLE 0x00200000
393#define MAC_MODE_RDE_ENABLE 0x00400000
394#define MAC_MODE_FHDE_ENABLE 0x00800000
395#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
396#define MAC_MODE_APE_RX_EN 0x08000000
397#define MAC_MODE_APE_TX_EN 0x10000000
398#define MAC_STATUS 0x00000404
399#define MAC_STATUS_PCS_SYNCED 0x00000001
400#define MAC_STATUS_SIGNAL_DET 0x00000002
401#define MAC_STATUS_RCVD_CFG 0x00000004
402#define MAC_STATUS_CFG_CHANGED 0x00000008
403#define MAC_STATUS_SYNC_CHANGED 0x00000010
404#define MAC_STATUS_PORT_DEC_ERR 0x00000400
405#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
406#define MAC_STATUS_MI_COMPLETION 0x00400000
407#define MAC_STATUS_MI_INTERRUPT 0x00800000
408#define MAC_STATUS_AP_ERROR 0x01000000
409#define MAC_STATUS_ODI_ERROR 0x02000000
410#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
411#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
412#define MAC_EVENT 0x00000408
413#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
414#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
415#define MAC_EVENT_MI_COMPLETION 0x00400000
416#define MAC_EVENT_MI_INTERRUPT 0x00800000
417#define MAC_EVENT_AP_ERROR 0x01000000
418#define MAC_EVENT_ODI_ERROR 0x02000000
419#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
420#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
421#define MAC_LED_CTRL 0x0000040c
422#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
423#define LED_CTRL_1000MBPS_ON 0x00000002
424#define LED_CTRL_100MBPS_ON 0x00000004
425#define LED_CTRL_10MBPS_ON 0x00000008
426#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
427#define LED_CTRL_TRAFFIC_BLINK 0x00000020
428#define LED_CTRL_TRAFFIC_LED 0x00000040
429#define LED_CTRL_1000MBPS_STATUS 0x00000080
430#define LED_CTRL_100MBPS_STATUS 0x00000100
431#define LED_CTRL_10MBPS_STATUS 0x00000200
432#define LED_CTRL_TRAFFIC_STATUS 0x00000400
433#define LED_CTRL_MODE_MAC 0x00000000
434#define LED_CTRL_MODE_PHY_1 0x00000800
435#define LED_CTRL_MODE_PHY_2 0x00001000
436#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
437#define LED_CTRL_MODE_SHARED 0x00004000
438#define LED_CTRL_MODE_COMBO 0x00008000
439#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
440#define LED_CTRL_BLINK_RATE_SHIFT 19
441#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
442#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
443#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
444#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
445#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
446#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
447#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
448#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
449#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
450#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
451#define MAC_ACPI_MBUF_PTR 0x00000430
452#define MAC_ACPI_LEN_OFFSET 0x00000434
453#define ACPI_LENOFF_LEN_MASK 0x0000ffff
454#define ACPI_LENOFF_LEN_SHIFT 0
455#define ACPI_LENOFF_OFF_MASK 0x0fff0000
456#define ACPI_LENOFF_OFF_SHIFT 16
457#define MAC_TX_BACKOFF_SEED 0x00000438
458#define TX_BACKOFF_SEED_MASK 0x000003ff
459#define MAC_RX_MTU_SIZE 0x0000043c
460#define RX_MTU_SIZE_MASK 0x0000ffff
461#define MAC_PCS_TEST 0x00000440
462#define PCS_TEST_PATTERN_MASK 0x000fffff
463#define PCS_TEST_PATTERN_SHIFT 0
464#define PCS_TEST_ENABLE 0x00100000
465#define MAC_TX_AUTO_NEG 0x00000444
466#define TX_AUTO_NEG_MASK 0x0000ffff
467#define TX_AUTO_NEG_SHIFT 0
468#define MAC_RX_AUTO_NEG 0x00000448
469#define RX_AUTO_NEG_MASK 0x0000ffff
470#define RX_AUTO_NEG_SHIFT 0
471#define MAC_MI_COM 0x0000044c
472#define MI_COM_CMD_MASK 0x0c000000
473#define MI_COM_CMD_WRITE 0x04000000
474#define MI_COM_CMD_READ 0x08000000
475#define MI_COM_READ_FAILED 0x10000000
476#define MI_COM_START 0x20000000
477#define MI_COM_BUSY 0x20000000
478#define MI_COM_PHY_ADDR_MASK 0x03e00000
479#define MI_COM_PHY_ADDR_SHIFT 21
480#define MI_COM_REG_ADDR_MASK 0x001f0000
481#define MI_COM_REG_ADDR_SHIFT 16
482#define MI_COM_DATA_MASK 0x0000ffff
483#define MAC_MI_STAT 0x00000450
484#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
485#define MAC_MI_STAT_10MBPS_MODE 0x00000002
486#define MAC_MI_MODE 0x00000454
487#define MAC_MI_MODE_CLK_10MHZ 0x00000001
488#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
489#define MAC_MI_MODE_AUTO_POLL 0x00000010
490#define MAC_MI_MODE_500KHZ_CONST 0x00008000
491#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
492#define MAC_AUTO_POLL_STATUS 0x00000458
493#define MAC_AUTO_POLL_ERROR 0x00000001
494#define MAC_TX_MODE 0x0000045c
495#define TX_MODE_RESET 0x00000001
496#define TX_MODE_ENABLE 0x00000002
497#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
498#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
499#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
500#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
501#define TX_MODE_JMB_FRM_LEN 0x00400000
502#define TX_MODE_CNT_DN_MODE 0x00800000
503#define MAC_TX_STATUS 0x00000460
504#define TX_STATUS_XOFFED 0x00000001
505#define TX_STATUS_SENT_XOFF 0x00000002
506#define TX_STATUS_SENT_XON 0x00000004
507#define TX_STATUS_LINK_UP 0x00000008
508#define TX_STATUS_ODI_UNDERRUN 0x00000010
509#define TX_STATUS_ODI_OVERRUN 0x00000020
510#define MAC_TX_LENGTHS 0x00000464
511#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
512#define TX_LENGTHS_SLOT_TIME_SHIFT 0
513#define TX_LENGTHS_IPG_MASK 0x00000f00
514#define TX_LENGTHS_IPG_SHIFT 8
515#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
516#define TX_LENGTHS_IPG_CRS_SHIFT 12
517#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
518#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
519#define MAC_RX_MODE 0x00000468
520#define RX_MODE_RESET 0x00000001
521#define RX_MODE_ENABLE 0x00000002
522#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
523#define RX_MODE_KEEP_MAC_CTRL 0x00000008
524#define RX_MODE_KEEP_PAUSE 0x00000010
525#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
526#define RX_MODE_ACCEPT_RUNTS 0x00000040
527#define RX_MODE_LEN_CHECK 0x00000080
528#define RX_MODE_PROMISC 0x00000100
529#define RX_MODE_NO_CRC_CHECK 0x00000200
530#define RX_MODE_KEEP_VLAN_TAG 0x00000400
531#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
532#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
533#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
534#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
535#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
536#define RX_MODE_RSS_ENABLE 0x00800000
537#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
538#define RX_MODE_IPV4_FRAG_FIX 0x02000000
539#define MAC_RX_STATUS 0x0000046c
540#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
541#define RX_STATUS_XOFF_RCVD 0x00000002
542#define RX_STATUS_XON_RCVD 0x00000004
543#define MAC_HASH_REG_0 0x00000470
544#define MAC_HASH_REG_1 0x00000474
545#define MAC_HASH_REG_2 0x00000478
546#define MAC_HASH_REG_3 0x0000047c
547#define MAC_RCV_RULE_0 0x00000480
548#define MAC_RCV_VALUE_0 0x00000484
549#define MAC_RCV_RULE_1 0x00000488
550#define MAC_RCV_VALUE_1 0x0000048c
551#define MAC_RCV_RULE_2 0x00000490
552#define MAC_RCV_VALUE_2 0x00000494
553#define MAC_RCV_RULE_3 0x00000498
554#define MAC_RCV_VALUE_3 0x0000049c
555#define MAC_RCV_RULE_4 0x000004a0
556#define MAC_RCV_VALUE_4 0x000004a4
557#define MAC_RCV_RULE_5 0x000004a8
558#define MAC_RCV_VALUE_5 0x000004ac
559#define MAC_RCV_RULE_6 0x000004b0
560#define MAC_RCV_VALUE_6 0x000004b4
561#define MAC_RCV_RULE_7 0x000004b8
562#define MAC_RCV_VALUE_7 0x000004bc
563#define MAC_RCV_RULE_8 0x000004c0
564#define MAC_RCV_VALUE_8 0x000004c4
565#define MAC_RCV_RULE_9 0x000004c8
566#define MAC_RCV_VALUE_9 0x000004cc
567#define MAC_RCV_RULE_10 0x000004d0
568#define MAC_RCV_VALUE_10 0x000004d4
569#define MAC_RCV_RULE_11 0x000004d8
570#define MAC_RCV_VALUE_11 0x000004dc
571#define MAC_RCV_RULE_12 0x000004e0
572#define MAC_RCV_VALUE_12 0x000004e4
573#define MAC_RCV_RULE_13 0x000004e8
574#define MAC_RCV_VALUE_13 0x000004ec
575#define MAC_RCV_RULE_14 0x000004f0
576#define MAC_RCV_VALUE_14 0x000004f4
577#define MAC_RCV_RULE_15 0x000004f8
578#define MAC_RCV_VALUE_15 0x000004fc
579#define RCV_RULE_DISABLE_MASK 0x7fffffff
580#define MAC_RCV_RULE_CFG 0x00000500
581#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
582#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
583/* 0x508 --> 0x520 unused */
584#define MAC_HASHREGU_0 0x00000520
585#define MAC_HASHREGU_1 0x00000524
586#define MAC_HASHREGU_2 0x00000528
587#define MAC_HASHREGU_3 0x0000052c
588#define MAC_EXTADDR_0_HIGH 0x00000530
589#define MAC_EXTADDR_0_LOW 0x00000534
590#define MAC_EXTADDR_1_HIGH 0x00000538
591#define MAC_EXTADDR_1_LOW 0x0000053c
592#define MAC_EXTADDR_2_HIGH 0x00000540
593#define MAC_EXTADDR_2_LOW 0x00000544
594#define MAC_EXTADDR_3_HIGH 0x00000548
595#define MAC_EXTADDR_3_LOW 0x0000054c
596#define MAC_EXTADDR_4_HIGH 0x00000550
597#define MAC_EXTADDR_4_LOW 0x00000554
598#define MAC_EXTADDR_5_HIGH 0x00000558
599#define MAC_EXTADDR_5_LOW 0x0000055c
600#define MAC_EXTADDR_6_HIGH 0x00000560
601#define MAC_EXTADDR_6_LOW 0x00000564
602#define MAC_EXTADDR_7_HIGH 0x00000568
603#define MAC_EXTADDR_7_LOW 0x0000056c
604#define MAC_EXTADDR_8_HIGH 0x00000570
605#define MAC_EXTADDR_8_LOW 0x00000574
606#define MAC_EXTADDR_9_HIGH 0x00000578
607#define MAC_EXTADDR_9_LOW 0x0000057c
608#define MAC_EXTADDR_10_HIGH 0x00000580
609#define MAC_EXTADDR_10_LOW 0x00000584
610#define MAC_EXTADDR_11_HIGH 0x00000588
611#define MAC_EXTADDR_11_LOW 0x0000058c
612#define MAC_SERDES_CFG 0x00000590
613#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
614#define MAC_SERDES_STAT 0x00000594
615/* 0x598 --> 0x5a0 unused */
616#define MAC_PHYCFG1 0x000005a0
617#define MAC_PHYCFG1_RGMII_INT 0x00000001
618#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
619#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
620#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
621#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
622#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
623#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
624#define MAC_PHYCFG1_TXC_DRV 0x20000000
625#define MAC_PHYCFG2 0x000005a4
626#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
627#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
628#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
629#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
630#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
631#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
632#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
633#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
634#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
635#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
636#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
637#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
638#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
639#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
640#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
641#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
642#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
643#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
644#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
645#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
646#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
647#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
648#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
649#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
650#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
651#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
652#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
653#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
654#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
655#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
656#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
657#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
658#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
659#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
660#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
661#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
662#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
663#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
664#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
665#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
666#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
667#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
668#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
669#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
670#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
671#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
672#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
673#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
674#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
675#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
676#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
677#define MAC_PHYCFG2_50610_LED_MODES \
678 (MAC_PHYCFG2_EMODE_MASK_50610 | \
679 MAC_PHYCFG2_EMODE_COMP_50610 | \
680 MAC_PHYCFG2_FMODE_MASK_50610 | \
681 MAC_PHYCFG2_FMODE_COMP_50610 | \
682 MAC_PHYCFG2_GMODE_MASK_50610 | \
683 MAC_PHYCFG2_GMODE_COMP_50610 | \
684 MAC_PHYCFG2_ACT_MASK_50610 | \
685 MAC_PHYCFG2_ACT_COMP_50610 | \
686 MAC_PHYCFG2_QUAL_MASK_50610 | \
687 MAC_PHYCFG2_QUAL_COMP_50610)
688#define MAC_PHYCFG2_AC131_LED_MODES \
689 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
690 MAC_PHYCFG2_EMODE_COMP_AC131 | \
691 MAC_PHYCFG2_FMODE_MASK_AC131 | \
692 MAC_PHYCFG2_FMODE_COMP_AC131 | \
693 MAC_PHYCFG2_GMODE_MASK_AC131 | \
694 MAC_PHYCFG2_GMODE_COMP_AC131 | \
695 MAC_PHYCFG2_ACT_MASK_AC131 | \
696 MAC_PHYCFG2_ACT_COMP_AC131 | \
697 MAC_PHYCFG2_QUAL_MASK_AC131 | \
698 MAC_PHYCFG2_QUAL_COMP_AC131)
699#define MAC_PHYCFG2_RTL8211C_LED_MODES \
700 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
701 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
702 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
703 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
704 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
705 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
706 MAC_PHYCFG2_ACT_MASK_RT8211 | \
707 MAC_PHYCFG2_ACT_COMP_RT8211 | \
708 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
709 MAC_PHYCFG2_QUAL_COMP_RT8211)
710#define MAC_PHYCFG2_RTL8201E_LED_MODES \
711 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
712 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
713 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
714 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
715 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
716 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
717 MAC_PHYCFG2_ACT_MASK_RT8201 | \
718 MAC_PHYCFG2_ACT_COMP_RT8201 | \
719 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
720 MAC_PHYCFG2_QUAL_COMP_RT8201)
721#define MAC_EXT_RGMII_MODE 0x000005a8
722#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
723#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
724#define MAC_RGMII_MODE_TX_RESET 0x00000004
725#define MAC_RGMII_MODE_RX_INT_B 0x00000100
726#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
727#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
728#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
729/* 0x5ac --> 0x5b0 unused */
730#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
731#define SERDES_RX_SIG_DETECT 0x00000400
732#define SG_DIG_CTRL 0x000005b0
733#define SG_DIG_USING_HW_AUTONEG 0x80000000
734#define SG_DIG_SOFT_RESET 0x40000000
735#define SG_DIG_DISABLE_LINKRDY 0x20000000
736#define SG_DIG_CRC16_CLEAR_N 0x01000000
737#define SG_DIG_EN10B 0x00800000
738#define SG_DIG_CLEAR_STATUS 0x00400000
739#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
740#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
741#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
742#define SG_DIG_SPEED_STATUS_SHIFT 18
743#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
744#define SG_DIG_RESTART_AUTONEG 0x00010000
745#define SG_DIG_FIBER_MODE 0x00008000
746#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
747#define SG_DIG_PAUSE_MASK 0x00001800
748#define SG_DIG_PAUSE_CAP 0x00000800
749#define SG_DIG_ASYM_PAUSE 0x00001000
750#define SG_DIG_GBIC_ENABLE 0x00000400
751#define SG_DIG_CHECK_END_ENABLE 0x00000200
752#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
753#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
754#define SG_DIG_GMII_INPUT_SELECT 0x00000040
755#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
756#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
757#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
758#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
759#define SG_DIG_REMOTE_LOOPBACK 0x00000002
760#define SG_DIG_LOOPBACK 0x00000001
761#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
762 SG_DIG_LOCAL_DUPLEX_STATUS | \
763 SG_DIG_LOCAL_LINK_STATUS | \
764 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
765 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
766#define SG_DIG_STATUS 0x000005b4
767#define SG_DIG_CRC16_BUS_MASK 0xffff0000
768#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
769#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
770#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
771#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
772#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
773#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
774#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
775#define SG_DIG_IS_SERDES 0x00000100
776#define SG_DIG_COMMA_DETECTOR 0x00000008
777#define SG_DIG_MAC_ACK_STATUS 0x00000004
778#define SG_DIG_AUTONEG_COMPLETE 0x00000002
779#define SG_DIG_AUTONEG_ERROR 0x00000001
780#define TG3_TX_TSTAMP_LSB 0x000005c0
781#define TG3_TX_TSTAMP_MSB 0x000005c4
782#define TG3_TSTAMP_MASK 0x7fffffffffffffffLL
783/* 0x5c8 --> 0x600 unused */
784#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
785#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
786/* 0x624 --> 0x670 unused */
787
788#define MAC_RSS_INDIR_TBL_0 0x00000630
789
790#define MAC_RSS_HASH_KEY_0 0x00000670
791#define MAC_RSS_HASH_KEY_1 0x00000674
792#define MAC_RSS_HASH_KEY_2 0x00000678
793#define MAC_RSS_HASH_KEY_3 0x0000067c
794#define MAC_RSS_HASH_KEY_4 0x00000680
795#define MAC_RSS_HASH_KEY_5 0x00000684
796#define MAC_RSS_HASH_KEY_6 0x00000688
797#define MAC_RSS_HASH_KEY_7 0x0000068c
798#define MAC_RSS_HASH_KEY_8 0x00000690
799#define MAC_RSS_HASH_KEY_9 0x00000694
800/* 0x698 --> 0x6b0 unused */
801
802#define TG3_RX_TSTAMP_LSB 0x000006b0
803#define TG3_RX_TSTAMP_MSB 0x000006b4
804/* 0x6b8 --> 0x6c8 unused */
805
806#define TG3_RX_PTP_CTL 0x000006c8
807#define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001
808#define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002
809#define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004
810#define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008
811#define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
812 TG3_RX_PTP_CTL_DELAY_REQ)
813#define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
814 TG3_RX_PTP_CTL_DELAY_REQ | \
815 TG3_RX_PTP_CTL_PDLAY_REQ | \
816 TG3_RX_PTP_CTL_PDLAY_RES)
817#define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100
818#define TG3_RX_PTP_CTL_DELAY_RES 0x00000200
819#define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400
820#define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800
821#define TG3_RX_PTP_CTL_SIGNALING 0x00001000
822#define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000
823#define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000
824#define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000
825#define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \
826 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN)
827#define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000
828#define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000
829/* 0x6cc --> 0x800 unused */
830
831#define MAC_TX_STATS_OCTETS 0x00000800
832#define MAC_TX_STATS_RESV1 0x00000804
833#define MAC_TX_STATS_COLLISIONS 0x00000808
834#define MAC_TX_STATS_XON_SENT 0x0000080c
835#define MAC_TX_STATS_XOFF_SENT 0x00000810
836#define MAC_TX_STATS_RESV2 0x00000814
837#define MAC_TX_STATS_MAC_ERRORS 0x00000818
838#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
839#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
840#define MAC_TX_STATS_DEFERRED 0x00000824
841#define MAC_TX_STATS_RESV3 0x00000828
842#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
843#define MAC_TX_STATS_LATE_COL 0x00000830
844#define MAC_TX_STATS_RESV4_1 0x00000834
845#define MAC_TX_STATS_RESV4_2 0x00000838
846#define MAC_TX_STATS_RESV4_3 0x0000083c
847#define MAC_TX_STATS_RESV4_4 0x00000840
848#define MAC_TX_STATS_RESV4_5 0x00000844
849#define MAC_TX_STATS_RESV4_6 0x00000848
850#define MAC_TX_STATS_RESV4_7 0x0000084c
851#define MAC_TX_STATS_RESV4_8 0x00000850
852#define MAC_TX_STATS_RESV4_9 0x00000854
853#define MAC_TX_STATS_RESV4_10 0x00000858
854#define MAC_TX_STATS_RESV4_11 0x0000085c
855#define MAC_TX_STATS_RESV4_12 0x00000860
856#define MAC_TX_STATS_RESV4_13 0x00000864
857#define MAC_TX_STATS_RESV4_14 0x00000868
858#define MAC_TX_STATS_UCAST 0x0000086c
859#define MAC_TX_STATS_MCAST 0x00000870
860#define MAC_TX_STATS_BCAST 0x00000874
861#define MAC_TX_STATS_RESV5_1 0x00000878
862#define MAC_TX_STATS_RESV5_2 0x0000087c
863#define MAC_RX_STATS_OCTETS 0x00000880
864#define MAC_RX_STATS_RESV1 0x00000884
865#define MAC_RX_STATS_FRAGMENTS 0x00000888
866#define MAC_RX_STATS_UCAST 0x0000088c
867#define MAC_RX_STATS_MCAST 0x00000890
868#define MAC_RX_STATS_BCAST 0x00000894
869#define MAC_RX_STATS_FCS_ERRORS 0x00000898
870#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
871#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
872#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
873#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
874#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
875#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
876#define MAC_RX_STATS_JABBERS 0x000008b4
877#define MAC_RX_STATS_UNDERSIZE 0x000008b8
878/* 0x8bc --> 0xc00 unused */
879
880/* Send data initiator control registers */
881#define SNDDATAI_MODE 0x00000c00
882#define SNDDATAI_MODE_RESET 0x00000001
883#define SNDDATAI_MODE_ENABLE 0x00000002
884#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
885#define SNDDATAI_STATUS 0x00000c04
886#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
887#define SNDDATAI_STATSCTRL 0x00000c08
888#define SNDDATAI_SCTRL_ENABLE 0x00000001
889#define SNDDATAI_SCTRL_FASTUPD 0x00000002
890#define SNDDATAI_SCTRL_CLEAR 0x00000004
891#define SNDDATAI_SCTRL_FLUSH 0x00000008
892#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
893#define SNDDATAI_STATSENAB 0x00000c0c
894#define SNDDATAI_STATSINCMASK 0x00000c10
895#define ISO_PKT_TX 0x00000c20
896/* 0xc24 --> 0xc80 unused */
897#define SNDDATAI_COS_CNT_0 0x00000c80
898#define SNDDATAI_COS_CNT_1 0x00000c84
899#define SNDDATAI_COS_CNT_2 0x00000c88
900#define SNDDATAI_COS_CNT_3 0x00000c8c
901#define SNDDATAI_COS_CNT_4 0x00000c90
902#define SNDDATAI_COS_CNT_5 0x00000c94
903#define SNDDATAI_COS_CNT_6 0x00000c98
904#define SNDDATAI_COS_CNT_7 0x00000c9c
905#define SNDDATAI_COS_CNT_8 0x00000ca0
906#define SNDDATAI_COS_CNT_9 0x00000ca4
907#define SNDDATAI_COS_CNT_10 0x00000ca8
908#define SNDDATAI_COS_CNT_11 0x00000cac
909#define SNDDATAI_COS_CNT_12 0x00000cb0
910#define SNDDATAI_COS_CNT_13 0x00000cb4
911#define SNDDATAI_COS_CNT_14 0x00000cb8
912#define SNDDATAI_COS_CNT_15 0x00000cbc
913#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
914#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
915#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
916#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
917#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
918#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
919#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
920#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
921/* 0xce0 --> 0x1000 unused */
922
923/* Send data completion control registers */
924#define SNDDATAC_MODE 0x00001000
925#define SNDDATAC_MODE_RESET 0x00000001
926#define SNDDATAC_MODE_ENABLE 0x00000002
927#define SNDDATAC_MODE_CDELAY 0x00000010
928/* 0x1004 --> 0x1400 unused */
929
930/* Send BD ring selector */
931#define SNDBDS_MODE 0x00001400
932#define SNDBDS_MODE_RESET 0x00000001
933#define SNDBDS_MODE_ENABLE 0x00000002
934#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
935#define SNDBDS_STATUS 0x00001404
936#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
937#define SNDBDS_HWDIAG 0x00001408
938/* 0x140c --> 0x1440 */
939#define SNDBDS_SEL_CON_IDX_0 0x00001440
940#define SNDBDS_SEL_CON_IDX_1 0x00001444
941#define SNDBDS_SEL_CON_IDX_2 0x00001448
942#define SNDBDS_SEL_CON_IDX_3 0x0000144c
943#define SNDBDS_SEL_CON_IDX_4 0x00001450
944#define SNDBDS_SEL_CON_IDX_5 0x00001454
945#define SNDBDS_SEL_CON_IDX_6 0x00001458
946#define SNDBDS_SEL_CON_IDX_7 0x0000145c
947#define SNDBDS_SEL_CON_IDX_8 0x00001460
948#define SNDBDS_SEL_CON_IDX_9 0x00001464
949#define SNDBDS_SEL_CON_IDX_10 0x00001468
950#define SNDBDS_SEL_CON_IDX_11 0x0000146c
951#define SNDBDS_SEL_CON_IDX_12 0x00001470
952#define SNDBDS_SEL_CON_IDX_13 0x00001474
953#define SNDBDS_SEL_CON_IDX_14 0x00001478
954#define SNDBDS_SEL_CON_IDX_15 0x0000147c
955/* 0x1480 --> 0x1800 unused */
956
957/* Send BD initiator control registers */
958#define SNDBDI_MODE 0x00001800
959#define SNDBDI_MODE_RESET 0x00000001
960#define SNDBDI_MODE_ENABLE 0x00000002
961#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
962#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
963#define SNDBDI_STATUS 0x00001804
964#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
965#define SNDBDI_IN_PROD_IDX_0 0x00001808
966#define SNDBDI_IN_PROD_IDX_1 0x0000180c
967#define SNDBDI_IN_PROD_IDX_2 0x00001810
968#define SNDBDI_IN_PROD_IDX_3 0x00001814
969#define SNDBDI_IN_PROD_IDX_4 0x00001818
970#define SNDBDI_IN_PROD_IDX_5 0x0000181c
971#define SNDBDI_IN_PROD_IDX_6 0x00001820
972#define SNDBDI_IN_PROD_IDX_7 0x00001824
973#define SNDBDI_IN_PROD_IDX_8 0x00001828
974#define SNDBDI_IN_PROD_IDX_9 0x0000182c
975#define SNDBDI_IN_PROD_IDX_10 0x00001830
976#define SNDBDI_IN_PROD_IDX_11 0x00001834
977#define SNDBDI_IN_PROD_IDX_12 0x00001838
978#define SNDBDI_IN_PROD_IDX_13 0x0000183c
979#define SNDBDI_IN_PROD_IDX_14 0x00001840
980#define SNDBDI_IN_PROD_IDX_15 0x00001844
981/* 0x1848 --> 0x1c00 unused */
982
983/* Send BD completion control registers */
984#define SNDBDC_MODE 0x00001c00
985#define SNDBDC_MODE_RESET 0x00000001
986#define SNDBDC_MODE_ENABLE 0x00000002
987#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
988/* 0x1c04 --> 0x2000 unused */
989
990/* Receive list placement control registers */
991#define RCVLPC_MODE 0x00002000
992#define RCVLPC_MODE_RESET 0x00000001
993#define RCVLPC_MODE_ENABLE 0x00000002
994#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
995#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
996#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
997#define RCVLPC_STATUS 0x00002004
998#define RCVLPC_STATUS_CLASS0 0x00000004
999#define RCVLPC_STATUS_MAPOOR 0x00000008
1000#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1001#define RCVLPC_LOCK 0x00002008
1002#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1003#define RCVLPC_LOCK_REQ_SHIFT 0
1004#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1005#define RCVLPC_LOCK_GRANT_SHIFT 16
1006#define RCVLPC_NON_EMPTY_BITS 0x0000200c
1007#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1008#define RCVLPC_CONFIG 0x00002010
1009#define RCVLPC_STATSCTRL 0x00002014
1010#define RCVLPC_STATSCTRL_ENABLE 0x00000001
1011#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1012#define RCVLPC_STATS_ENABLE 0x00002018
1013#define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1014#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1015#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1016#define RCVLPC_STATS_INCMASK 0x0000201c
1017/* 0x2020 --> 0x2100 unused */
1018#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1019#define SELLST_TAIL 0x00000004
1020#define SELLST_CONT 0x00000008
1021#define SELLST_UNUSED 0x0000000c
1022#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1023#define RCVLPC_DROP_FILTER_CNT 0x00002240
1024#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1025#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1026#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1027#define RCVLPC_IN_DISCARDS_CNT 0x00002250
1028#define RCVLPC_IN_ERRORS_CNT 0x00002254
1029#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1030/* 0x225c --> 0x2400 unused */
1031
1032/* Receive Data and Receive BD Initiator Control */
1033#define RCVDBDI_MODE 0x00002400
1034#define RCVDBDI_MODE_RESET 0x00000001
1035#define RCVDBDI_MODE_ENABLE 0x00000002
1036#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1037#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1038#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1039#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1040#define RCVDBDI_STATUS 0x00002404
1041#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1042#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1043#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1044#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1045/* 0x240c --> 0x2440 unused */
1046#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1047#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1048#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1049#define RCVDBDI_JUMBO_CON_IDX 0x00002470
1050#define RCVDBDI_STD_CON_IDX 0x00002474
1051#define RCVDBDI_MINI_CON_IDX 0x00002478
1052/* 0x247c --> 0x2480 unused */
1053#define RCVDBDI_BD_PROD_IDX_0 0x00002480
1054#define RCVDBDI_BD_PROD_IDX_1 0x00002484
1055#define RCVDBDI_BD_PROD_IDX_2 0x00002488
1056#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1057#define RCVDBDI_BD_PROD_IDX_4 0x00002490
1058#define RCVDBDI_BD_PROD_IDX_5 0x00002494
1059#define RCVDBDI_BD_PROD_IDX_6 0x00002498
1060#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1061#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1062#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1063#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1064#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1065#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1066#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1067#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1068#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1069#define RCVDBDI_HWDIAG 0x000024c0
1070/* 0x24c4 --> 0x2800 unused */
1071
1072/* Receive Data Completion Control */
1073#define RCVDCC_MODE 0x00002800
1074#define RCVDCC_MODE_RESET 0x00000001
1075#define RCVDCC_MODE_ENABLE 0x00000002
1076#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1077/* 0x2804 --> 0x2c00 unused */
1078
1079/* Receive BD Initiator Control Registers */
1080#define RCVBDI_MODE 0x00002c00
1081#define RCVBDI_MODE_RESET 0x00000001
1082#define RCVBDI_MODE_ENABLE 0x00000002
1083#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1084#define RCVBDI_STATUS 0x00002c04
1085#define RCVBDI_STATUS_RCB_ATTN 0x00000004
1086#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1087#define RCVBDI_STD_PROD_IDX 0x00002c0c
1088#define RCVBDI_MINI_PROD_IDX 0x00002c10
1089#define RCVBDI_MINI_THRESH 0x00002c14
1090#define RCVBDI_STD_THRESH 0x00002c18
1091#define RCVBDI_JUMBO_THRESH 0x00002c1c
1092/* 0x2c20 --> 0x2d00 unused */
1093
1094#define STD_REPLENISH_LWM 0x00002d00
1095#define JMB_REPLENISH_LWM 0x00002d04
1096/* 0x2d08 --> 0x3000 unused */
1097
1098/* Receive BD Completion Control Registers */
1099#define RCVCC_MODE 0x00003000
1100#define RCVCC_MODE_RESET 0x00000001
1101#define RCVCC_MODE_ENABLE 0x00000002
1102#define RCVCC_MODE_ATTN_ENABLE 0x00000004
1103#define RCVCC_STATUS 0x00003004
1104#define RCVCC_STATUS_ERROR_ATTN 0x00000004
1105#define RCVCC_JUMP_PROD_IDX 0x00003008
1106#define RCVCC_STD_PROD_IDX 0x0000300c
1107#define RCVCC_MINI_PROD_IDX 0x00003010
1108/* 0x3014 --> 0x3400 unused */
1109
1110/* Receive list selector control registers */
1111#define RCVLSC_MODE 0x00003400
1112#define RCVLSC_MODE_RESET 0x00000001
1113#define RCVLSC_MODE_ENABLE 0x00000002
1114#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1115#define RCVLSC_STATUS 0x00003404
1116#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1117/* 0x3408 --> 0x3600 unused */
1118
1119#define TG3_CPMU_DRV_STATUS 0x0000344c
1120
1121/* CPMU registers */
1122#define TG3_CPMU_CTRL 0x00003600
1123#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1124#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1125#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1126#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1127#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1128#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1129#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1130/* 0x3608 --> 0x360c unused */
1131
1132#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1133#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1134#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1135#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1136#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1137#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1138#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1139/* 0x3614 --> 0x361c unused */
1140
1141#define TG3_CPMU_HST_ACC 0x0000361c
1142#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1143#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1144/* 0x3620 --> 0x3630 unused */
1145
1146#define TG3_CPMU_CLCK_ORIDE 0x00003624
1147#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1148
1149#define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628
1150#define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13)
1151
1152#define TG3_CPMU_STATUS 0x0000362c
1153#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1154#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1155#define TG3_CPMU_STATUS_FSHFT_5719 30
1156#define TG3_CPMU_STATUS_LINK_MASK 0x180000
1157
1158#define TG3_CPMU_CLCK_STAT 0x00003630
1159#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1160#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1161#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1162#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1163/* 0x3634 --> 0x365c unused */
1164
1165#define TG3_CPMU_MUTEX_REQ 0x0000365c
1166#define CPMU_MUTEX_REQ_DRIVER 0x00001000
1167#define TG3_CPMU_MUTEX_GNT 0x00003660
1168#define CPMU_MUTEX_GNT_DRIVER 0x00001000
1169#define TG3_CPMU_PHY_STRAP 0x00003664
1170#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1171#define TG3_CPMU_PADRNG_CTL 0x00003668
1172#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000
1173/* 0x3664 --> 0x36b0 unused */
1174
1175#define TG3_CPMU_EEE_MODE 0x000036b0
1176#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1177#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1178#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1179#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1180#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1181#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1182#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1183#define TG3_CPMU_EEE_DBTMR1 0x000036b4
1184#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1185#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
1186#define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff
1187#define TG3_CPMU_EEE_DBTMR2 0x000036b8
1188#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1189#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
1190#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1191#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1192#define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1193#define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002
1194/* 0x36c0 --> 0x36d0 unused */
1195
1196#define TG3_CPMU_EEE_CTRL 0x000036d0
1197#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1198#define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1199#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1200/* 0x36d4 --> 0x3800 unused */
1201
1202/* Mbuf cluster free registers */
1203#define MBFREE_MODE 0x00003800
1204#define MBFREE_MODE_RESET 0x00000001
1205#define MBFREE_MODE_ENABLE 0x00000002
1206#define MBFREE_STATUS 0x00003804
1207/* 0x3808 --> 0x3c00 unused */
1208
1209/* Host coalescing control registers */
1210#define HOSTCC_MODE 0x00003c00
1211#define HOSTCC_MODE_RESET 0x00000001
1212#define HOSTCC_MODE_ENABLE 0x00000002
1213#define HOSTCC_MODE_ATTN 0x00000004
1214#define HOSTCC_MODE_NOW 0x00000008
1215#define HOSTCC_MODE_FULL_STATUS 0x00000000
1216#define HOSTCC_MODE_64BYTE 0x00000080
1217#define HOSTCC_MODE_32BYTE 0x00000100
1218#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1219#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1220#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1221#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1222#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1223#define HOSTCC_STATUS 0x00003c04
1224#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1225#define HOSTCC_RXCOL_TICKS 0x00003c08
1226#define LOW_RXCOL_TICKS 0x00000032
1227#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1228#define DEFAULT_RXCOL_TICKS 0x00000048
1229#define HIGH_RXCOL_TICKS 0x00000096
1230#define MAX_RXCOL_TICKS 0x000003ff
1231#define HOSTCC_TXCOL_TICKS 0x00003c0c
1232#define LOW_TXCOL_TICKS 0x00000096
1233#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1234#define DEFAULT_TXCOL_TICKS 0x0000012c
1235#define HIGH_TXCOL_TICKS 0x00000145
1236#define MAX_TXCOL_TICKS 0x000003ff
1237#define HOSTCC_RXMAX_FRAMES 0x00003c10
1238#define LOW_RXMAX_FRAMES 0x00000005
1239#define DEFAULT_RXMAX_FRAMES 0x00000008
1240#define HIGH_RXMAX_FRAMES 0x00000012
1241#define MAX_RXMAX_FRAMES 0x000000ff
1242#define HOSTCC_TXMAX_FRAMES 0x00003c14
1243#define LOW_TXMAX_FRAMES 0x00000035
1244#define DEFAULT_TXMAX_FRAMES 0x0000004b
1245#define HIGH_TXMAX_FRAMES 0x00000052
1246#define MAX_TXMAX_FRAMES 0x000000ff
1247#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1248#define DEFAULT_RXCOAL_TICK_INT 0x00000019
1249#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1250#define MAX_RXCOAL_TICK_INT 0x000003ff
1251#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1252#define DEFAULT_TXCOAL_TICK_INT 0x00000019
1253#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1254#define MAX_TXCOAL_TICK_INT 0x000003ff
1255#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1256#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1257#define MAX_RXCOAL_MAXF_INT 0x000000ff
1258#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1259#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1260#define MAX_TXCOAL_MAXF_INT 0x000000ff
1261#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1262#define DEFAULT_STAT_COAL_TICKS 0x000f4240
1263#define MAX_STAT_COAL_TICKS 0xd693d400
1264#define MIN_STAT_COAL_TICKS 0x00000064
1265/* 0x3c2c --> 0x3c30 unused */
1266#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1267#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1268#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1269#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1270#define HOSTCC_FLOW_ATTN 0x00003c48
1271#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1272/* 0x3c4c --> 0x3c50 unused */
1273#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1274#define HOSTCC_STD_CON_IDX 0x00003c54
1275#define HOSTCC_MINI_CON_IDX 0x00003c58
1276/* 0x3c5c --> 0x3c80 unused */
1277#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1278#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1279#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1280#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1281#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1282#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1283#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1284#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1285#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1286#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1287#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1288#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1289#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1290#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1291#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1292#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1293#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1294#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1295#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1296#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1297#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1298#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1299#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1300#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1301#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1302#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1303#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1304#define HOSTCC_SND_CON_IDX_11 0x00003cec
1305#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1306#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1307#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1308#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1309#define HOSTCC_STATBLCK_RING1 0x00003d00
1310/* 0x3d00 --> 0x3d80 unused */
1311
1312#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1313#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1314#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1315#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1316#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1317#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1318/* 0x3d98 --> 0x4000 unused */
1319
1320/* Memory arbiter control registers */
1321#define MEMARB_MODE 0x00004000
1322#define MEMARB_MODE_RESET 0x00000001
1323#define MEMARB_MODE_ENABLE 0x00000002
1324#define MEMARB_STATUS 0x00004004
1325#define MEMARB_TRAP_ADDR_LOW 0x00004008
1326#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1327/* 0x4010 --> 0x4400 unused */
1328
1329/* Buffer manager control registers */
1330#define BUFMGR_MODE 0x00004400
1331#define BUFMGR_MODE_RESET 0x00000001
1332#define BUFMGR_MODE_ENABLE 0x00000002
1333#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1334#define BUFMGR_MODE_BM_TEST 0x00000008
1335#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1336#define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1337#define BUFMGR_STATUS 0x00004404
1338#define BUFMGR_STATUS_ERROR 0x00000004
1339#define BUFMGR_STATUS_MBLOW 0x00000010
1340#define BUFMGR_MB_POOL_ADDR 0x00004408
1341#define BUFMGR_MB_POOL_SIZE 0x0000440c
1342#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1343#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1344#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1345#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1346#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1347#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1348#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1349#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1350#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1351#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1352#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1353#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1354#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1355#define BUFMGR_MB_HIGH_WATER 0x00004418
1356#define DEFAULT_MB_HIGH_WATER 0x00000060
1357#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1358#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1359#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1360#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1361#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1362#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1363#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1364#define BUFMGR_MB_ALLOC_BIT 0x10000000
1365#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1366#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1367#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1368#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1369#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1370#define BUFMGR_DMA_LOW_WATER 0x00004434
1371#define DEFAULT_DMA_LOW_WATER 0x00000005
1372#define BUFMGR_DMA_HIGH_WATER 0x00004438
1373#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1374#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1375#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1376#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1377#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1378#define BUFMGR_HWDIAG_0 0x0000444c
1379#define BUFMGR_HWDIAG_1 0x00004450
1380#define BUFMGR_HWDIAG_2 0x00004454
1381/* 0x4458 --> 0x4800 unused */
1382
1383/* Read DMA control registers */
1384#define RDMAC_MODE 0x00004800
1385#define RDMAC_MODE_RESET 0x00000001
1386#define RDMAC_MODE_ENABLE 0x00000002
1387#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1388#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1389#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1390#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1391#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1392#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1393#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1394#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1395#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1396#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1397#define RDMAC_MODE_SPLIT_RESET 0x00001000
1398#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1399#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1400#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1401#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1402#define RDMAC_MODE_JMB_2K_MMRR 0x00800000
1403#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1404#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1405#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1406#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1407#define RDMAC_STATUS 0x00004804
1408#define RDMAC_STATUS_TGTABORT 0x00000004
1409#define RDMAC_STATUS_MSTABORT 0x00000008
1410#define RDMAC_STATUS_PARITYERR 0x00000010
1411#define RDMAC_STATUS_ADDROFLOW 0x00000020
1412#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1413#define RDMAC_STATUS_FIFOURUN 0x00000080
1414#define RDMAC_STATUS_FIFOOREAD 0x00000100
1415#define RDMAC_STATUS_LNGREAD 0x00000200
1416/* 0x4808 --> 0x4890 unused */
1417
1418#define TG3_RDMA_RSRVCTRL_REG2 0x00004890
1419#define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0
1420
1421#define TG3_RDMA_RSRVCTRL_REG 0x00004900
1422#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1423#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1424#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1425#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1426#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1427#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1428#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1429/* 0x4904 --> 0x4910 unused */
1430
1431#define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1432#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1433#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1434#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000
1435#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000
1436/* 0x4914 --> 0x4be0 unused */
1437
1438#define TG3_NUM_RDMA_CHANNELS 4
1439#define TG3_RDMA_LENGTH 0x00004be0
1440
1441/* Write DMA control registers */
1442#define WDMAC_MODE 0x00004c00
1443#define WDMAC_MODE_RESET 0x00000001
1444#define WDMAC_MODE_ENABLE 0x00000002
1445#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1446#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1447#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1448#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1449#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1450#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1451#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1452#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1453#define WDMAC_MODE_RX_ACCEL 0x00000400
1454#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1455#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1456#define WDMAC_STATUS 0x00004c04
1457#define WDMAC_STATUS_TGTABORT 0x00000004
1458#define WDMAC_STATUS_MSTABORT 0x00000008
1459#define WDMAC_STATUS_PARITYERR 0x00000010
1460#define WDMAC_STATUS_ADDROFLOW 0x00000020
1461#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1462#define WDMAC_STATUS_FIFOURUN 0x00000080
1463#define WDMAC_STATUS_FIFOOREAD 0x00000100
1464#define WDMAC_STATUS_LNGREAD 0x00000200
1465/* 0x4c08 --> 0x5000 unused */
1466
1467/* Per-cpu register offsets (arm9) */
1468#define CPU_MODE 0x00000000
1469#define CPU_MODE_RESET 0x00000001
1470#define CPU_MODE_HALT 0x00000400
1471#define CPU_STATE 0x00000004
1472#define CPU_EVTMASK 0x00000008
1473/* 0xc --> 0x1c reserved */
1474#define CPU_PC 0x0000001c
1475#define CPU_INSN 0x00000020
1476#define CPU_SPAD_UFLOW 0x00000024
1477#define CPU_WDOG_CLEAR 0x00000028
1478#define CPU_WDOG_VECTOR 0x0000002c
1479#define CPU_WDOG_PC 0x00000030
1480#define CPU_HW_BP 0x00000034
1481/* 0x38 --> 0x44 unused */
1482#define CPU_WDOG_SAVED_STATE 0x00000044
1483#define CPU_LAST_BRANCH_ADDR 0x00000048
1484#define CPU_SPAD_UFLOW_SET 0x0000004c
1485/* 0x50 --> 0x200 unused */
1486#define CPU_R0 0x00000200
1487#define CPU_R1 0x00000204
1488#define CPU_R2 0x00000208
1489#define CPU_R3 0x0000020c
1490#define CPU_R4 0x00000210
1491#define CPU_R5 0x00000214
1492#define CPU_R6 0x00000218
1493#define CPU_R7 0x0000021c
1494#define CPU_R8 0x00000220
1495#define CPU_R9 0x00000224
1496#define CPU_R10 0x00000228
1497#define CPU_R11 0x0000022c
1498#define CPU_R12 0x00000230
1499#define CPU_R13 0x00000234
1500#define CPU_R14 0x00000238
1501#define CPU_R15 0x0000023c
1502#define CPU_R16 0x00000240
1503#define CPU_R17 0x00000244
1504#define CPU_R18 0x00000248
1505#define CPU_R19 0x0000024c
1506#define CPU_R20 0x00000250
1507#define CPU_R21 0x00000254
1508#define CPU_R22 0x00000258
1509#define CPU_R23 0x0000025c
1510#define CPU_R24 0x00000260
1511#define CPU_R25 0x00000264
1512#define CPU_R26 0x00000268
1513#define CPU_R27 0x0000026c
1514#define CPU_R28 0x00000270
1515#define CPU_R29 0x00000274
1516#define CPU_R30 0x00000278
1517#define CPU_R31 0x0000027c
1518/* 0x280 --> 0x400 unused */
1519
1520#define RX_CPU_BASE 0x00005000
1521#define RX_CPU_MODE 0x00005000
1522#define RX_CPU_STATE 0x00005004
1523#define RX_CPU_PGMCTR 0x0000501c
1524#define RX_CPU_HWBKPT 0x00005034
1525#define TX_CPU_BASE 0x00005400
1526#define TX_CPU_MODE 0x00005400
1527#define TX_CPU_STATE 0x00005404
1528#define TX_CPU_PGMCTR 0x0000541c
1529
1530#define VCPU_STATUS 0x00005100
1531#define VCPU_STATUS_INIT_DONE 0x04000000
1532#define VCPU_STATUS_DRV_RESET 0x08000000
1533
1534#define VCPU_CFGSHDW 0x00005104
1535#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1536#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1537#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1538
1539/* Mailboxes */
1540#define GRCMBOX_BASE 0x00005600
1541#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1542#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1543#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1544#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1545#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1546#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1547#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1548#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1549#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1550#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1551#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1552#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1553#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1554#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1555#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1556#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1557#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1558#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1559#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1560#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1561#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1562#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1563#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1564#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1565#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1566#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1567#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1568#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1569#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1570#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1571#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1572#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1573#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1574#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1575#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1576#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1577#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1578#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1579#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1580#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1581#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1582#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1583#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1584#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1585#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1586#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1587#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1588#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1589#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1590#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1591#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1592#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1593#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1594#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1595#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1596#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1597#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1598#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1599#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1600#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1601#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1602#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1603#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1604#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1605#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1606#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1607#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1608#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1609/* 0x5a10 --> 0x5c00 */
1610
1611/* Flow Through queues */
1612#define FTQ_RESET 0x00005c00
1613/* 0x5c04 --> 0x5c10 unused */
1614#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1615#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1616#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1617#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1618#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1619#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1620#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1621#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1622#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1623#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1624#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1625#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1626#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1627#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1628#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1629#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1630#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1631#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1632#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1633#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1634#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1635#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1636#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1637#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1638#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1639#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1640#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1641#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1642#define FTQ_SWTYPE1_CTL 0x00005c80
1643#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1644#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1645#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1646#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1647#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1648#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1649#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1650#define FTQ_HOST_COAL_CTL 0x00005ca0
1651#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1652#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1653#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1654#define FTQ_MAC_TX_CTL 0x00005cb0
1655#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1656#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1657#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1658#define FTQ_MB_FREE_CTL 0x00005cc0
1659#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1660#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1661#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1662#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1663#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1664#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1665#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1666#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1667#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1668#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1669#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1670#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1671#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1672#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1673#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1674#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1675#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1676#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1677#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1678#define FTQ_SWTYPE2_CTL 0x00005d10
1679#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1680#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1681#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1682/* 0x5d20 --> 0x6000 unused */
1683
1684/* Message signaled interrupt registers */
1685#define MSGINT_MODE 0x00006000
1686#define MSGINT_MODE_RESET 0x00000001
1687#define MSGINT_MODE_ENABLE 0x00000002
1688#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1689#define MSGINT_MODE_MULTIVEC_EN 0x00000080
1690#define MSGINT_STATUS 0x00006004
1691#define MSGINT_STATUS_MSI_REQ 0x00000001
1692#define MSGINT_FIFO 0x00006008
1693/* 0x600c --> 0x6400 unused */
1694
1695/* DMA completion registers */
1696#define DMAC_MODE 0x00006400
1697#define DMAC_MODE_RESET 0x00000001
1698#define DMAC_MODE_ENABLE 0x00000002
1699/* 0x6404 --> 0x6800 unused */
1700
1701/* GRC registers */
1702#define GRC_MODE 0x00006800
1703#define GRC_MODE_UPD_ON_COAL 0x00000001
1704#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1705#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1706#define GRC_MODE_BSWAP_DATA 0x00000010
1707#define GRC_MODE_WSWAP_DATA 0x00000020
1708#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1709#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1710#define GRC_MODE_SPLITHDR 0x00000100
1711#define GRC_MODE_NOFRM_CRACKING 0x00000200
1712#define GRC_MODE_INCL_CRC 0x00000400
1713#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1714#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1715#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1716#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1717#define GRC_MODE_B2HRX_ENABLE 0x00008000
1718#define GRC_MODE_HOST_STACKUP 0x00010000
1719#define GRC_MODE_HOST_SENDBDS 0x00020000
1720#define GRC_MODE_HTX2B_ENABLE 0x00040000
1721#define GRC_MODE_TIME_SYNC_ENABLE 0x00080000
1722#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1723#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1724#define GRC_MODE_PCIE_TL_SEL 0x00000000
1725#define GRC_MODE_PCIE_PL_SEL 0x00400000
1726#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1727#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1728#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1729#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1730#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1731#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1732#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1733#define GRC_MODE_PCIE_DL_SEL 0x20000000
1734#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1735#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1736#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1737 GRC_MODE_PCIE_PL_SEL | \
1738 GRC_MODE_PCIE_DL_SEL | \
1739 GRC_MODE_PCIE_HI_1K_EN)
1740#define GRC_MISC_CFG 0x00006804
1741#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1742#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1743#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1744#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1745#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1746#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1747#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1748#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1749#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1750#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1751#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1752#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1753#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1754#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1755#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1756#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1757#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1758#define GRC_LOCAL_CTRL 0x00006808
1759#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1760#define GRC_LCLCTRL_CLEARINT 0x00000002
1761#define GRC_LCLCTRL_SETINT 0x00000004
1762#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1763#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1764#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1765#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1766#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1767#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1768#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1769#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1770#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1771#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1772#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1773#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1774#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1775#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1776#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1777#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1778#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1779#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1780#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1781#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1782#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1783#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1784#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1785#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1786#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1787#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1788#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1789#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1790#define GRC_TIMER 0x0000680c
1791#define GRC_RX_CPU_EVENT 0x00006810
1792#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1793#define GRC_RX_TIMER_REF 0x00006814
1794#define GRC_RX_CPU_SEM 0x00006818
1795#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1796#define GRC_TX_CPU_EVENT 0x00006820
1797#define GRC_TX_TIMER_REF 0x00006824
1798#define GRC_TX_CPU_SEM 0x00006828
1799#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1800#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1801#define GRC_EEPROM_ADDR 0x00006838
1802#define EEPROM_ADDR_WRITE 0x00000000
1803#define EEPROM_ADDR_READ 0x80000000
1804#define EEPROM_ADDR_COMPLETE 0x40000000
1805#define EEPROM_ADDR_FSM_RESET 0x20000000
1806#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1807#define EEPROM_ADDR_DEVID_SHIFT 26
1808#define EEPROM_ADDR_START 0x02000000
1809#define EEPROM_ADDR_CLKPERD_SHIFT 16
1810#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1811#define EEPROM_ADDR_ADDR_SHIFT 0
1812#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1813#define EEPROM_CHIP_SIZE (64 * 1024)
1814#define GRC_EEPROM_DATA 0x0000683c
1815#define GRC_EEPROM_CTRL 0x00006840
1816#define GRC_MDI_CTRL 0x00006844
1817#define GRC_SEEPROM_DELAY 0x00006848
1818/* 0x684c --> 0x6890 unused */
1819#define GRC_VCPU_EXT_CTRL 0x00006890
1820#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1821#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1822#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1823
1824#define TG3_EAV_REF_CLCK_LSB 0x00006900
1825#define TG3_EAV_REF_CLCK_MSB 0x00006904
1826#define TG3_EAV_REF_CLCK_CTL 0x00006908
1827#define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002
1828#define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004
1829#define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16)
1830#define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17)
1831
1832#define TG3_EAV_WATCHDOG0_LSB 0x00006918
1833#define TG3_EAV_WATCHDOG0_MSB 0x0000691c
1834#define TG3_EAV_WATCHDOG0_EN (1 << 31)
1835#define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff
1836
1837#define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928
1838#define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31)
1839#define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30)
1840
1841#define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff
1842
1843/* 0x692c --> 0x7000 unused */
1844
1845/* NVRAM Control registers */
1846#define NVRAM_CMD 0x00007000
1847#define NVRAM_CMD_RESET 0x00000001
1848#define NVRAM_CMD_DONE 0x00000008
1849#define NVRAM_CMD_GO 0x00000010
1850#define NVRAM_CMD_WR 0x00000020
1851#define NVRAM_CMD_RD 0x00000000
1852#define NVRAM_CMD_ERASE 0x00000040
1853#define NVRAM_CMD_FIRST 0x00000080
1854#define NVRAM_CMD_LAST 0x00000100
1855#define NVRAM_CMD_WREN 0x00010000
1856#define NVRAM_CMD_WRDI 0x00020000
1857#define NVRAM_STAT 0x00007004
1858#define NVRAM_WRDATA 0x00007008
1859#define NVRAM_ADDR 0x0000700c
1860#define NVRAM_ADDR_MSK 0x00ffffff
1861#define NVRAM_RDDATA 0x00007010
1862#define NVRAM_CFG1 0x00007014
1863#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1864#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1865#define NVRAM_CFG1_PASS_THRU 0x00000004
1866#define NVRAM_CFG1_STATUS_BITS 0x00000070
1867#define NVRAM_CFG1_BIT_BANG 0x00000008
1868#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1869#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1870#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1871#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1872#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1873#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1874#define FLASH_VENDOR_ST 0x03000001
1875#define FLASH_VENDOR_SAIFUN 0x01000003
1876#define FLASH_VENDOR_SST_SMALL 0x00000001
1877#define FLASH_VENDOR_SST_LARGE 0x02000001
1878#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1879#define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003
1880#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1881#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1882#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1883#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1884#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1885#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1886#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1887#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1888#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1889#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1890#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1891#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1892#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1893#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1894#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1895#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1896#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1897#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1898#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1899#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1900#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1901#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1902#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1903#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1904#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1905#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1906#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1907#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1908#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1909#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1910#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1911#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1912#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1913#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1914#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1915#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1916#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1917#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1918#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1919#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1920#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1921#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1922#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1923#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1924#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1925#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1926#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1927#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1928#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1929#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1930#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1931#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1932#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1933#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1934#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1935#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1936#define FLASH_5717VENDOR_ST_25USPT 0x03400002
1937#define FLASH_5717VENDOR_ST_45USPT 0x03400001
1938#define FLASH_5720_EEPROM_HD 0x00000001
1939#define FLASH_5720_EEPROM_LD 0x00000003
1940#define FLASH_5762_EEPROM_HD 0x02000001
1941#define FLASH_5762_EEPROM_LD 0x02000003
1942#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1943#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1944#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1945#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1946#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1947#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1948#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1949#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1950#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1951#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1952#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1953#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1954#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1955#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1956#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1957#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1958#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1959#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1960#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1961#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
1962#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
1963#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
1964#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
1965#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
1966#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
1967#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
1968#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
1969#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
1970#define FLASH_5720VENDOR_ST_25USPT 0x03c00002
1971#define FLASH_5720VENDOR_ST_45USPT 0x03c00001
1972#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1973#define FLASH_5752PAGE_SIZE_256 0x00000000
1974#define FLASH_5752PAGE_SIZE_512 0x10000000
1975#define FLASH_5752PAGE_SIZE_1K 0x20000000
1976#define FLASH_5752PAGE_SIZE_2K 0x30000000
1977#define FLASH_5752PAGE_SIZE_4K 0x40000000
1978#define FLASH_5752PAGE_SIZE_264 0x50000000
1979#define FLASH_5752PAGE_SIZE_528 0x60000000
1980#define NVRAM_CFG2 0x00007018
1981#define NVRAM_CFG3 0x0000701c
1982#define NVRAM_SWARB 0x00007020
1983#define SWARB_REQ_SET0 0x00000001
1984#define SWARB_REQ_SET1 0x00000002
1985#define SWARB_REQ_SET2 0x00000004
1986#define SWARB_REQ_SET3 0x00000008
1987#define SWARB_REQ_CLR0 0x00000010
1988#define SWARB_REQ_CLR1 0x00000020
1989#define SWARB_REQ_CLR2 0x00000040
1990#define SWARB_REQ_CLR3 0x00000080
1991#define SWARB_GNT0 0x00000100
1992#define SWARB_GNT1 0x00000200
1993#define SWARB_GNT2 0x00000400
1994#define SWARB_GNT3 0x00000800
1995#define SWARB_REQ0 0x00001000
1996#define SWARB_REQ1 0x00002000
1997#define SWARB_REQ2 0x00004000
1998#define SWARB_REQ3 0x00008000
1999#define NVRAM_ACCESS 0x00007024
2000#define ACCESS_ENABLE 0x00000001
2001#define ACCESS_WR_ENABLE 0x00000002
2002#define NVRAM_WRITE1 0x00007028
2003/* 0x702c unused */
2004
2005#define NVRAM_ADDR_LOCKOUT 0x00007030
2006/* 0x7034 --> 0x7500 unused */
2007
2008#define OTP_MODE 0x00007500
2009#define OTP_MODE_OTP_THRU_GRC 0x00000001
2010#define OTP_CTRL 0x00007504
2011#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
2012#define OTP_CTRL_OTP_CMD_READ 0x00000000
2013#define OTP_CTRL_OTP_CMD_INIT 0x00000008
2014#define OTP_CTRL_OTP_CMD_START 0x00000001
2015#define OTP_STATUS 0x00007508
2016#define OTP_STATUS_CMD_DONE 0x00000001
2017#define OTP_ADDRESS 0x0000750c
2018#define OTP_ADDRESS_MAGIC1 0x000000a0
2019#define OTP_ADDRESS_MAGIC2 0x00000080
2020/* 0x7510 unused */
2021
2022#define OTP_READ_DATA 0x00007514
2023/* 0x7518 --> 0x7c04 unused */
2024
2025#define PCIE_TRANSACTION_CFG 0x00007c04
2026#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
2027#define PCIE_TRANS_CFG_LOM 0x00000020
2028/* 0x7c08 --> 0x7d28 unused */
2029
2030#define PCIE_PWR_MGMT_THRESH 0x00007d28
2031#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2032#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2033#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2034/* 0x7d2c --> 0x7d54 unused */
2035
2036#define TG3_PCIE_LNKCTL 0x00007d54
2037#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2038#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2039/* 0x7d58 --> 0x7e70 unused */
2040
2041#define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2042#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2043#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2044
2045#define TG3_PCIE_EIDLE_DELAY 0x00007e70
2046#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2047#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2048/* 0x7e74 --> 0x8000 unused */
2049
2050
2051/* Alternate PCIE definitions */
2052#define TG3_PCIE_TLDLPL_PORT 0x00007c00
2053#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2054#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2055#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2056#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2057#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2058#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2059#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2060
2061#define TG3_REG_BLK_SIZE 0x00008000
2062
2063/* OTP bit definitions */
2064#define TG3_OTP_AGCTGT_MASK 0x000000e0
2065#define TG3_OTP_AGCTGT_SHIFT 1
2066#define TG3_OTP_HPFFLTR_MASK 0x00000300
2067#define TG3_OTP_HPFFLTR_SHIFT 1
2068#define TG3_OTP_HPFOVER_MASK 0x00000400
2069#define TG3_OTP_HPFOVER_SHIFT 1
2070#define TG3_OTP_LPFDIS_MASK 0x00000800
2071#define TG3_OTP_LPFDIS_SHIFT 11
2072#define TG3_OTP_VDAC_MASK 0xff000000
2073#define TG3_OTP_VDAC_SHIFT 24
2074#define TG3_OTP_10BTAMP_MASK 0x0000f000
2075#define TG3_OTP_10BTAMP_SHIFT 8
2076#define TG3_OTP_ROFF_MASK 0x00e00000
2077#define TG3_OTP_ROFF_SHIFT 11
2078#define TG3_OTP_RCOFF_MASK 0x001c0000
2079#define TG3_OTP_RCOFF_SHIFT 16
2080
2081#define TG3_OTP_DEFAULT 0x286c1640
2082
2083
2084/* Hardware Legacy NVRAM layout */
2085#define TG3_NVM_VPD_OFF 0x100
2086#define TG3_NVM_VPD_LEN 256
2087
2088/* Hardware Selfboot NVRAM layout */
2089#define TG3_NVM_HWSB_CFG1 0x00000004
2090#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2091#define TG3_NVM_HWSB_CFG1_MAJSFT 27
2092#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2093#define TG3_NVM_HWSB_CFG1_MINSFT 22
2094
2095#define TG3_EEPROM_MAGIC 0x669955aa
2096#define TG3_EEPROM_MAGIC_FW 0xa5000000
2097#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2098#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2099#define TG3_EEPROM_SB_FORMAT_1 0x00200000
2100#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2101#define TG3_EEPROM_SB_REVISION_0 0x00000000
2102#define TG3_EEPROM_SB_REVISION_2 0x00020000
2103#define TG3_EEPROM_SB_REVISION_3 0x00030000
2104#define TG3_EEPROM_SB_REVISION_4 0x00040000
2105#define TG3_EEPROM_SB_REVISION_5 0x00050000
2106#define TG3_EEPROM_SB_REVISION_6 0x00060000
2107#define TG3_EEPROM_MAGIC_HW 0xabcd
2108#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2109
2110#define TG3_NVM_DIR_START 0x18
2111#define TG3_NVM_DIR_END 0x78
2112#define TG3_NVM_DIRENT_SIZE 0xc
2113#define TG3_NVM_DIRTYPE_SHIFT 24
2114#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2115#define TG3_NVM_DIRTYPE_ASFINI 1
2116#define TG3_NVM_DIRTYPE_EXTVPD 20
2117#define TG3_NVM_PTREV_BCVER 0x94
2118#define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2119#define TG3_NVM_BCVER_MAJSFT 8
2120#define TG3_NVM_BCVER_MINMSK 0x000000ff
2121
2122#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2123#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2124#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2125#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2126#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2127#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2128#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2129#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2130#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2131#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2132#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2133#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2134
2135
2136/* 32K Window into NIC internal memory */
2137#define NIC_SRAM_WIN_BASE 0x00008000
2138
2139/* Offsets into first 32k of NIC internal memory. */
2140#define NIC_SRAM_PAGE_ZERO 0x00000000
2141#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
2142#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
2143#define NIC_SRAM_STATS_BLK 0x00000300
2144#define NIC_SRAM_STATUS_BLK 0x00000b00
2145
2146#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2147#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2148#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
2149
2150#define NIC_SRAM_DATA_SIG 0x00000b54
2151#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
2152
2153#define NIC_SRAM_DATA_CFG 0x00000b58
2154#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2155#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2156#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2157#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2158#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2159#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2160#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2161#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2162#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2163#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2164#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2165#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2166#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2167#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2168#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2169
2170#define NIC_SRAM_DATA_VER 0x00000b5c
2171#define NIC_SRAM_DATA_VER_SHIFT 16
2172
2173#define NIC_SRAM_DATA_PHY_ID 0x00000b74
2174#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2175#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2176
2177#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2178#define FWCMD_NICDRV_ALIVE 0x00000001
2179#define FWCMD_NICDRV_PAUSE_FW 0x00000002
2180#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2181#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2182#define FWCMD_NICDRV_FIX_DMAR 0x00000005
2183#define FWCMD_NICDRV_FIX_DMAW 0x00000006
2184#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2185#define FWCMD_NICDRV_ALIVE2 0x0000000d
2186#define FWCMD_NICDRV_ALIVE3 0x0000000e
2187#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2188#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2189#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2190#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2191#define DRV_STATE_START 0x00000001
2192#define DRV_STATE_START_DONE 0x80000001
2193#define DRV_STATE_UNLOAD 0x00000002
2194#define DRV_STATE_UNLOAD_DONE 0x80000002
2195#define DRV_STATE_WOL 0x00000003
2196#define DRV_STATE_SUSPEND 0x00000004
2197
2198#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2199
2200#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2201#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2202
2203#define NIC_SRAM_WOL_MBOX 0x00000d30
2204#define WOL_SIGNATURE 0x474c0000
2205#define WOL_DRV_STATE_SHUTDOWN 0x00000001
2206#define WOL_DRV_WOL 0x00000002
2207#define WOL_SET_MAGIC_PKT 0x00000004
2208
2209#define NIC_SRAM_DATA_CFG_2 0x00000d38
2210
2211#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000
2212#define SHASTA_EXT_LED_MODE_MASK 0x00018000
2213#define SHASTA_EXT_LED_LEGACY 0x00000000
2214#define SHASTA_EXT_LED_SHARED 0x00008000
2215#define SHASTA_EXT_LED_MAC 0x00010000
2216#define SHASTA_EXT_LED_COMBO 0x00018000
2217
2218#define NIC_SRAM_DATA_CFG_3 0x00000d3c
2219#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2220#define NIC_SRAM_LNK_FLAP_AVOID 0x00400000
2221#define NIC_SRAM_1G_ON_VAUX_OK 0x00800000
2222
2223#define NIC_SRAM_DATA_CFG_4 0x00000d60
2224#define NIC_SRAM_GMII_MODE 0x00000002
2225#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2226#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2227#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2228
2229#define NIC_SRAM_CPMU_STATUS 0x00000e00
2230#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2231#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2232
2233#define NIC_SRAM_DATA_CFG_5 0x00000e0c
2234#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002
2235
2236#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2237
2238#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2239#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2240#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2241#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2242#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2243#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2244#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2245#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2246#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2247#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2248
2249#define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000
2250#define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000
2251#define TG3_57766_FW_BASE_ADDR 0x00030000
2252#define TG3_57766_FW_HANDSHAKE 0x0003fccc
2253#define TG3_SBROM_IN_SERVICE_LOOP 0x51
2254
2255#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2256#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2257#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2258
2259#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2260#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2261
2262
2263/* Currently this is fixed. */
2264#define TG3_PHY_MII_ADDR 0x01
2265
2266
2267/*** Tigon3 specific PHY MII registers. ***/
2268#define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2269#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2270#define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2271
2272#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2273#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2274#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2275#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2276#define MII_TG3_EXT_CTRL_TBI 0x8000
2277
2278#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2279#define MII_TG3_EXT_STAT_MDIX 0x2000
2280#define MII_TG3_EXT_STAT_LPASS 0x0100
2281
2282#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2283#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2284#define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2285#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2286
2287#define MII_TG3_DSP_TAP1 0x0001
2288#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2289#define MII_TG3_DSP_TAP26 0x001a
2290#define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2291#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2292#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2293#define MII_TG3_DSP_AADJ1CH0 0x001f
2294#define MII_TG3_DSP_CH34TP2 0x4022
2295#define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff
2296#define MII_TG3_DSP_AADJ1CH3 0x601f
2297#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2298#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2299#define MII_TG3_DSP_EXP8 0x0f08
2300#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2301#define MII_TG3_DSP_EXP8_AEDW 0x0200
2302#define MII_TG3_DSP_EXP75 0x0f75
2303#define MII_TG3_DSP_EXP96 0x0f96
2304#define MII_TG3_DSP_EXP97 0x0f97
2305
2306#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
2307
2308#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2309#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2310#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2311#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2312#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
2313
2314#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2315#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2316#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2317#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2318#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2319#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2320
2321#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2322
2323#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2324#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2325#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2326#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2327#define MII_TG3_AUXCTL_MISC_WREN 0x8000
2328
2329
2330#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
2331#define MII_TG3_AUX_STAT_LPASS 0x0004
2332#define MII_TG3_AUX_STAT_SPDMASK 0x0700
2333#define MII_TG3_AUX_STAT_10HALF 0x0100
2334#define MII_TG3_AUX_STAT_10FULL 0x0200
2335#define MII_TG3_AUX_STAT_100HALF 0x0300
2336#define MII_TG3_AUX_STAT_100_4 0x0400
2337#define MII_TG3_AUX_STAT_100FULL 0x0500
2338#define MII_TG3_AUX_STAT_1000HALF 0x0600
2339#define MII_TG3_AUX_STAT_1000FULL 0x0700
2340#define MII_TG3_AUX_STAT_100 0x0008
2341#define MII_TG3_AUX_STAT_FULL 0x0001
2342
2343#define MII_TG3_ISTAT 0x1a /* IRQ status register */
2344#define MII_TG3_IMASK 0x1b /* IRQ mask register */
2345
2346/* ISTAT/IMASK event bits */
2347#define MII_TG3_INT_LINKCHG 0x0002
2348#define MII_TG3_INT_SPEEDCHG 0x0004
2349#define MII_TG3_INT_DUPLEXCHG 0x0008
2350#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2351
2352#define MII_TG3_MISC_SHDW 0x1c
2353#define MII_TG3_MISC_SHDW_WREN 0x8000
2354
2355#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2356#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2357#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2358
2359#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2360#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2361#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2362#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2363#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2364#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2365
2366#define MII_TG3_TEST1 0x1e
2367#define MII_TG3_TEST1_TRIM_EN 0x0010
2368#define MII_TG3_TEST1_CRC_EN 0x8000
2369
2370/* Clause 45 expansion registers */
2371#define TG3_CL45_D7_EEERES_STAT 0x803e
2372#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2373#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2374
2375
2376/* Fast Ethernet Tranceiver definitions */
2377#define MII_TG3_FET_PTEST 0x17
2378#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
2379#define MII_TG3_FET_PTEST_TRIM_2 0x0002
2380#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2381#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2382
2383#define MII_TG3_FET_GEN_STAT 0x1c
2384#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2385
2386#define MII_TG3_FET_TEST 0x1f
2387#define MII_TG3_FET_SHADOW_EN 0x0080
2388
2389#define MII_TG3_FET_SHDW_MISCCTRL 0x10
2390#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2391
2392#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2393#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2394
2395#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2396#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2397
2398/* Serdes PHY Register Definitions */
2399#define SERDES_TG3_1000X_STATUS 0x14
2400#define SERDES_TG3_SGMII_MODE 0x0001
2401#define SERDES_TG3_LINK_UP 0x0002
2402#define SERDES_TG3_FULL_DUPLEX 0x0004
2403#define SERDES_TG3_SPEED_100 0x0008
2404#define SERDES_TG3_SPEED_1000 0x0010
2405
2406/* APE registers. Accessible through BAR1 */
2407#define TG3_APE_GPIO_MSG 0x0008
2408#define TG3_APE_GPIO_MSG_SHIFT 4
2409#define TG3_APE_EVENT 0x000c
2410#define APE_EVENT_1 0x00000001
2411#define TG3_APE_LOCK_REQ 0x002c
2412#define APE_LOCK_REQ_DRIVER 0x00001000
2413#define TG3_APE_LOCK_GRANT 0x004c
2414#define APE_LOCK_GRANT_DRIVER 0x00001000
2415#define TG3_APE_OTP_CTRL 0x00e8
2416#define APE_OTP_CTRL_PROG_EN 0x200000
2417#define APE_OTP_CTRL_CMD_RD 0x000000
2418#define APE_OTP_CTRL_START 0x000001
2419#define TG3_APE_OTP_STATUS 0x00ec
2420#define APE_OTP_STATUS_CMD_DONE 0x000001
2421#define TG3_APE_OTP_ADDR 0x00f0
2422#define APE_OTP_ADDR_CPU_ENABLE 0x80000000
2423#define TG3_APE_OTP_RD_DATA 0x00f8
2424
2425#define OTP_ADDRESS_MAGIC0 0x00000050
2426#define TG3_OTP_MAGIC0_VALID(val) \
2427 ((((val) & 0xf0000000) == 0xa0000000) ||\
2428 (((val) & 0x0f000000) == 0x0a000000))
2429
2430/* APE shared memory. Accessible through BAR1 */
2431#define TG3_APE_SHMEM_BASE 0x4000
2432#define TG3_APE_SEG_SIG 0x4000
2433#define APE_SEG_SIG_MAGIC 0x41504521
2434#define TG3_APE_FW_STATUS 0x400c
2435#define APE_FW_STATUS_READY 0x00000100
2436#define TG3_APE_FW_FEATURES 0x4010
2437#define TG3_APE_FW_FEATURE_NCSI 0x00000002
2438#define TG3_APE_FW_VERSION 0x4018
2439#define APE_FW_VERSION_MAJMSK 0xff000000
2440#define APE_FW_VERSION_MAJSFT 24
2441#define APE_FW_VERSION_MINMSK 0x00ff0000
2442#define APE_FW_VERSION_MINSFT 16
2443#define APE_FW_VERSION_REVMSK 0x0000ff00
2444#define APE_FW_VERSION_REVSFT 8
2445#define APE_FW_VERSION_BLDMSK 0x000000ff
2446#define TG3_APE_SEG_MSG_BUF_OFF 0x401c
2447#define TG3_APE_SEG_MSG_BUF_LEN 0x4020
2448#define TG3_APE_HOST_SEG_SIG 0x4200
2449#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2450#define TG3_APE_HOST_SEG_LEN 0x4204
2451#define APE_HOST_SEG_LEN_MAGIC 0x00000020
2452#define TG3_APE_HOST_INIT_COUNT 0x4208
2453#define TG3_APE_HOST_DRIVER_ID 0x420c
2454#define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2455#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2456 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2457#define TG3_APE_HOST_BEHAVIOR 0x4210
2458#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2459#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2460#define APE_HOST_HEARTBEAT_INT_DISABLE 0
2461#define APE_HOST_HEARTBEAT_INT_5SEC 5000
2462#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2463#define TG3_APE_HOST_DRVR_STATE 0x421c
2464#define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2465#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2466#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2467#define TG3_APE_HOST_WOL_SPEED 0x4224
2468#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2469
2470#define TG3_APE_EVENT_STATUS 0x4300
2471
2472#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2473#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2474#define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600
2475#define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2476#define APE_EVENT_STATUS_STATE_START 0x00010000
2477#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2478#define APE_EVENT_STATUS_STATE_WOL 0x00030000
2479#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2480#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2481
2482#define TG3_APE_PER_LOCK_REQ 0x8400
2483#define APE_LOCK_PER_REQ_DRIVER 0x00001000
2484#define TG3_APE_PER_LOCK_GRANT 0x8420
2485#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2486
2487/* APE convenience enumerations. */
2488#define TG3_APE_LOCK_PHY0 0
2489#define TG3_APE_LOCK_GRC 1
2490#define TG3_APE_LOCK_PHY1 2
2491#define TG3_APE_LOCK_PHY2 3
2492#define TG3_APE_LOCK_MEM 4
2493#define TG3_APE_LOCK_PHY3 5
2494#define TG3_APE_LOCK_GPIO 7
2495
2496#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2497
2498
2499/* There are two ways to manage the TX descriptors on the tigon3.
2500 * Either the descriptors are in host DMA'able memory, or they
2501 * exist only in the cards on-chip SRAM. All 16 send bds are under
2502 * the same mode, they may not be configured individually.
2503 *
2504 * This driver always uses host memory TX descriptors.
2505 *
2506 * To use host memory TX descriptors:
2507 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2508 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2509 * 2) Allocate DMA'able memory.
2510 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2511 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2512 * obtained in step 2
2513 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2514 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2515 * of TX descriptors. Leave flags field clear.
2516 * 4) Access TX descriptors via host memory. The chip
2517 * will refetch into local SRAM as needed when producer
2518 * index mailboxes are updated.
2519 *
2520 * To use on-chip TX descriptors:
2521 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2522 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2523 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2524 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2525 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2526 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2527 * 3) Access TX descriptors directly in on-chip SRAM
2528 * using normal {read,write}l(). (and not using
2529 * pointer dereferencing of ioremap()'d memory like
2530 * the broken Broadcom driver does)
2531 *
2532 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2533 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2534 */
2535struct tg3_tx_buffer_desc {
2536 u32 addr_hi;
2537 u32 addr_lo;
2538
2539 u32 len_flags;
2540#define TXD_FLAG_TCPUDP_CSUM 0x0001
2541#define TXD_FLAG_IP_CSUM 0x0002
2542#define TXD_FLAG_END 0x0004
2543#define TXD_FLAG_IP_FRAG 0x0008
2544#define TXD_FLAG_JMB_PKT 0x0008
2545#define TXD_FLAG_IP_FRAG_END 0x0010
2546#define TXD_FLAG_HWTSTAMP 0x0020
2547#define TXD_FLAG_VLAN 0x0040
2548#define TXD_FLAG_COAL_NOW 0x0080
2549#define TXD_FLAG_CPU_PRE_DMA 0x0100
2550#define TXD_FLAG_CPU_POST_DMA 0x0200
2551#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2552#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2553#define TXD_FLAG_NO_CRC 0x8000
2554#define TXD_LEN_SHIFT 16
2555
2556 u32 vlan_tag;
2557#define TXD_VLAN_TAG_SHIFT 0
2558#define TXD_MSS_SHIFT 16
2559};
2560
2561#define TXD_ADDR 0x00UL /* 64-bit */
2562#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2563#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2564#define TXD_SIZE 0x10UL
2565
2566struct tg3_rx_buffer_desc {
2567 u32 addr_hi;
2568 u32 addr_lo;
2569
2570 u32 idx_len;
2571#define RXD_IDX_MASK 0xffff0000
2572#define RXD_IDX_SHIFT 16
2573#define RXD_LEN_MASK 0x0000ffff
2574#define RXD_LEN_SHIFT 0
2575
2576 u32 type_flags;
2577#define RXD_TYPE_SHIFT 16
2578#define RXD_FLAGS_SHIFT 0
2579
2580#define RXD_FLAG_END 0x0004
2581#define RXD_FLAG_MINI 0x0800
2582#define RXD_FLAG_JUMBO 0x0020
2583#define RXD_FLAG_VLAN 0x0040
2584#define RXD_FLAG_ERROR 0x0400
2585#define RXD_FLAG_IP_CSUM 0x1000
2586#define RXD_FLAG_TCPUDP_CSUM 0x2000
2587#define RXD_FLAG_IS_TCP 0x4000
2588#define RXD_FLAG_PTPSTAT_MASK 0x0210
2589#define RXD_FLAG_PTPSTAT_PTPV1 0x0010
2590#define RXD_FLAG_PTPSTAT_PTPV2 0x0200
2591
2592 u32 ip_tcp_csum;
2593#define RXD_IPCSUM_MASK 0xffff0000
2594#define RXD_IPCSUM_SHIFT 16
2595#define RXD_TCPCSUM_MASK 0x0000ffff
2596#define RXD_TCPCSUM_SHIFT 0
2597
2598 u32 err_vlan;
2599
2600#define RXD_VLAN_MASK 0x0000ffff
2601
2602#define RXD_ERR_BAD_CRC 0x00010000
2603#define RXD_ERR_COLLISION 0x00020000
2604#define RXD_ERR_LINK_LOST 0x00040000
2605#define RXD_ERR_PHY_DECODE 0x00080000
2606#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2607#define RXD_ERR_MAC_ABRT 0x00200000
2608#define RXD_ERR_TOO_SMALL 0x00400000
2609#define RXD_ERR_NO_RESOURCES 0x00800000
2610#define RXD_ERR_HUGE_FRAME 0x01000000
2611
2612#define RXD_ERR_MASK (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION | \
2613 RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE | \
2614 RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL | \
2615 RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME)
2616
2617 u32 reserved;
2618 u32 opaque;
2619#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2620#define RXD_OPAQUE_INDEX_SHIFT 0
2621#define RXD_OPAQUE_RING_STD 0x00010000
2622#define RXD_OPAQUE_RING_JUMBO 0x00020000
2623#define RXD_OPAQUE_RING_MINI 0x00040000
2624#define RXD_OPAQUE_RING_MASK 0x00070000
2625};
2626
2627struct tg3_ext_rx_buffer_desc {
2628 struct {
2629 u32 addr_hi;
2630 u32 addr_lo;
2631 } addrlist[3];
2632 u32 len2_len1;
2633 u32 resv_len3;
2634 struct tg3_rx_buffer_desc std;
2635};
2636
2637/* We only use this when testing out the DMA engine
2638 * at probe time. This is the internal format of buffer
2639 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2640 */
2641struct tg3_internal_buffer_desc {
2642 u32 addr_hi;
2643 u32 addr_lo;
2644 u32 nic_mbuf;
2645 /* XXX FIX THIS */
2646#ifdef __BIG_ENDIAN
2647 u16 cqid_sqid;
2648 u16 len;
2649#else
2650 u16 len;
2651 u16 cqid_sqid;
2652#endif
2653 u32 flags;
2654 u32 __cookie1;
2655 u32 __cookie2;
2656 u32 __cookie3;
2657};
2658
2659#define TG3_HW_STATUS_SIZE 0x50
2660struct tg3_hw_status {
2661 u32 status;
2662#define SD_STATUS_UPDATED 0x00000001
2663#define SD_STATUS_LINK_CHG 0x00000002
2664#define SD_STATUS_ERROR 0x00000004
2665
2666 u32 status_tag;
2667
2668#ifdef __BIG_ENDIAN
2669 u16 rx_consumer;
2670 u16 rx_jumbo_consumer;
2671#else
2672 u16 rx_jumbo_consumer;
2673 u16 rx_consumer;
2674#endif
2675
2676#ifdef __BIG_ENDIAN
2677 u16 reserved;
2678 u16 rx_mini_consumer;
2679#else
2680 u16 rx_mini_consumer;
2681 u16 reserved;
2682#endif
2683 struct {
2684#ifdef __BIG_ENDIAN
2685 u16 tx_consumer;
2686 u16 rx_producer;
2687#else
2688 u16 rx_producer;
2689 u16 tx_consumer;
2690#endif
2691 } idx[16];
2692};
2693
2694typedef struct {
2695 u32 high, low;
2696} tg3_stat64_t;
2697
2698struct tg3_hw_stats {
2699 u8 __reserved0[0x400-0x300];
2700
2701 /* Statistics maintained by Receive MAC. */
2702 tg3_stat64_t rx_octets;
2703 u64 __reserved1;
2704 tg3_stat64_t rx_fragments;
2705 tg3_stat64_t rx_ucast_packets;
2706 tg3_stat64_t rx_mcast_packets;
2707 tg3_stat64_t rx_bcast_packets;
2708 tg3_stat64_t rx_fcs_errors;
2709 tg3_stat64_t rx_align_errors;
2710 tg3_stat64_t rx_xon_pause_rcvd;
2711 tg3_stat64_t rx_xoff_pause_rcvd;
2712 tg3_stat64_t rx_mac_ctrl_rcvd;
2713 tg3_stat64_t rx_xoff_entered;
2714 tg3_stat64_t rx_frame_too_long_errors;
2715 tg3_stat64_t rx_jabbers;
2716 tg3_stat64_t rx_undersize_packets;
2717 tg3_stat64_t rx_in_length_errors;
2718 tg3_stat64_t rx_out_length_errors;
2719 tg3_stat64_t rx_64_or_less_octet_packets;
2720 tg3_stat64_t rx_65_to_127_octet_packets;
2721 tg3_stat64_t rx_128_to_255_octet_packets;
2722 tg3_stat64_t rx_256_to_511_octet_packets;
2723 tg3_stat64_t rx_512_to_1023_octet_packets;
2724 tg3_stat64_t rx_1024_to_1522_octet_packets;
2725 tg3_stat64_t rx_1523_to_2047_octet_packets;
2726 tg3_stat64_t rx_2048_to_4095_octet_packets;
2727 tg3_stat64_t rx_4096_to_8191_octet_packets;
2728 tg3_stat64_t rx_8192_to_9022_octet_packets;
2729
2730 u64 __unused0[37];
2731
2732 /* Statistics maintained by Transmit MAC. */
2733 tg3_stat64_t tx_octets;
2734 u64 __reserved2;
2735 tg3_stat64_t tx_collisions;
2736 tg3_stat64_t tx_xon_sent;
2737 tg3_stat64_t tx_xoff_sent;
2738 tg3_stat64_t tx_flow_control;
2739 tg3_stat64_t tx_mac_errors;
2740 tg3_stat64_t tx_single_collisions;
2741 tg3_stat64_t tx_mult_collisions;
2742 tg3_stat64_t tx_deferred;
2743 u64 __reserved3;
2744 tg3_stat64_t tx_excessive_collisions;
2745 tg3_stat64_t tx_late_collisions;
2746 tg3_stat64_t tx_collide_2times;
2747 tg3_stat64_t tx_collide_3times;
2748 tg3_stat64_t tx_collide_4times;
2749 tg3_stat64_t tx_collide_5times;
2750 tg3_stat64_t tx_collide_6times;
2751 tg3_stat64_t tx_collide_7times;
2752 tg3_stat64_t tx_collide_8times;
2753 tg3_stat64_t tx_collide_9times;
2754 tg3_stat64_t tx_collide_10times;
2755 tg3_stat64_t tx_collide_11times;
2756 tg3_stat64_t tx_collide_12times;
2757 tg3_stat64_t tx_collide_13times;
2758 tg3_stat64_t tx_collide_14times;
2759 tg3_stat64_t tx_collide_15times;
2760 tg3_stat64_t tx_ucast_packets;
2761 tg3_stat64_t tx_mcast_packets;
2762 tg3_stat64_t tx_bcast_packets;
2763 tg3_stat64_t tx_carrier_sense_errors;
2764 tg3_stat64_t tx_discards;
2765 tg3_stat64_t tx_errors;
2766
2767 u64 __unused1[31];
2768
2769 /* Statistics maintained by Receive List Placement. */
2770 tg3_stat64_t COS_rx_packets[16];
2771 tg3_stat64_t COS_rx_filter_dropped;
2772 tg3_stat64_t dma_writeq_full;
2773 tg3_stat64_t dma_write_prioq_full;
2774 tg3_stat64_t rxbds_empty;
2775 tg3_stat64_t rx_discards;
2776 tg3_stat64_t rx_errors;
2777 tg3_stat64_t rx_threshold_hit;
2778
2779 u64 __unused2[9];
2780
2781 /* Statistics maintained by Send Data Initiator. */
2782 tg3_stat64_t COS_out_packets[16];
2783 tg3_stat64_t dma_readq_full;
2784 tg3_stat64_t dma_read_prioq_full;
2785 tg3_stat64_t tx_comp_queue_full;
2786
2787 /* Statistics maintained by Host Coalescing. */
2788 tg3_stat64_t ring_set_send_prod_index;
2789 tg3_stat64_t ring_status_update;
2790 tg3_stat64_t nic_irqs;
2791 tg3_stat64_t nic_avoided_irqs;
2792 tg3_stat64_t nic_tx_threshold_hit;
2793
2794 /* NOT a part of the hardware statistics block format.
2795 * These stats are here as storage for tg3_periodic_fetch_stats().
2796 */
2797 tg3_stat64_t mbuf_lwm_thresh_hit;
2798
2799 u8 __reserved4[0xb00-0x9c8];
2800};
2801
2802#define TG3_SD_NUM_RECS 3
2803#define TG3_OCIR_LEN (sizeof(struct tg3_ocir))
2804#define TG3_OCIR_SIG_MAGIC 0x5253434f
2805#define TG3_OCIR_FLAG_ACTIVE 0x00000001
2806
2807#define TG3_TEMP_CAUTION_OFFSET 0xc8
2808#define TG3_TEMP_MAX_OFFSET 0xcc
2809#define TG3_TEMP_SENSOR_OFFSET 0xd4
2810
2811
2812struct tg3_ocir {
2813 u32 signature;
2814 u16 version_flags;
2815 u16 refresh_int;
2816 u32 refresh_tmr;
2817 u32 update_tmr;
2818 u32 dst_base_addr;
2819 u16 src_hdr_offset;
2820 u16 src_hdr_length;
2821 u16 src_data_offset;
2822 u16 src_data_length;
2823 u16 dst_hdr_offset;
2824 u16 dst_data_offset;
2825 u16 dst_reg_upd_offset;
2826 u16 dst_sem_offset;
2827 u32 reserved1[2];
2828 u32 port0_flags;
2829 u32 port1_flags;
2830 u32 port2_flags;
2831 u32 port3_flags;
2832 u32 reserved2[1];
2833};
2834
2835
2836/* 'mapping' is superfluous as the chip does not write into
2837 * the tx/rx post rings so we could just fetch it from there.
2838 * But the cache behavior is better how we are doing it now.
2839 *
2840 * This driver uses new build_skb() API :
2841 * RX ring buffer contains pointer to kmalloc() data only,
2842 * skb are built only after Hardware filled the frame.
2843 */
2844struct ring_info {
2845 u8 *data;
2846 DEFINE_DMA_UNMAP_ADDR(mapping);
2847};
2848
2849struct tg3_tx_ring_info {
2850 struct sk_buff *skb;
2851 DEFINE_DMA_UNMAP_ADDR(mapping);
2852 bool fragmented;
2853};
2854
2855struct tg3_link_config {
2856 /* Describes what we're trying to get. */
2857 u32 advertising;
2858 u16 speed;
2859 u8 duplex;
2860 u8 autoneg;
2861 u8 flowctrl;
2862
2863 /* Describes what we actually have. */
2864 u8 active_flowctrl;
2865
2866 u8 active_duplex;
2867 u16 active_speed;
2868 u32 rmt_adv;
2869};
2870
2871struct tg3_bufmgr_config {
2872 u32 mbuf_read_dma_low_water;
2873 u32 mbuf_mac_rx_low_water;
2874 u32 mbuf_high_water;
2875
2876 u32 mbuf_read_dma_low_water_jumbo;
2877 u32 mbuf_mac_rx_low_water_jumbo;
2878 u32 mbuf_high_water_jumbo;
2879
2880 u32 dma_low_water;
2881 u32 dma_high_water;
2882};
2883
2884struct tg3_ethtool_stats {
2885 /* Statistics maintained by Receive MAC. */
2886 u64 rx_octets;
2887 u64 rx_fragments;
2888 u64 rx_ucast_packets;
2889 u64 rx_mcast_packets;
2890 u64 rx_bcast_packets;
2891 u64 rx_fcs_errors;
2892 u64 rx_align_errors;
2893 u64 rx_xon_pause_rcvd;
2894 u64 rx_xoff_pause_rcvd;
2895 u64 rx_mac_ctrl_rcvd;
2896 u64 rx_xoff_entered;
2897 u64 rx_frame_too_long_errors;
2898 u64 rx_jabbers;
2899 u64 rx_undersize_packets;
2900 u64 rx_in_length_errors;
2901 u64 rx_out_length_errors;
2902 u64 rx_64_or_less_octet_packets;
2903 u64 rx_65_to_127_octet_packets;
2904 u64 rx_128_to_255_octet_packets;
2905 u64 rx_256_to_511_octet_packets;
2906 u64 rx_512_to_1023_octet_packets;
2907 u64 rx_1024_to_1522_octet_packets;
2908 u64 rx_1523_to_2047_octet_packets;
2909 u64 rx_2048_to_4095_octet_packets;
2910 u64 rx_4096_to_8191_octet_packets;
2911 u64 rx_8192_to_9022_octet_packets;
2912
2913 /* Statistics maintained by Transmit MAC. */
2914 u64 tx_octets;
2915 u64 tx_collisions;
2916 u64 tx_xon_sent;
2917 u64 tx_xoff_sent;
2918 u64 tx_flow_control;
2919 u64 tx_mac_errors;
2920 u64 tx_single_collisions;
2921 u64 tx_mult_collisions;
2922 u64 tx_deferred;
2923 u64 tx_excessive_collisions;
2924 u64 tx_late_collisions;
2925 u64 tx_collide_2times;
2926 u64 tx_collide_3times;
2927 u64 tx_collide_4times;
2928 u64 tx_collide_5times;
2929 u64 tx_collide_6times;
2930 u64 tx_collide_7times;
2931 u64 tx_collide_8times;
2932 u64 tx_collide_9times;
2933 u64 tx_collide_10times;
2934 u64 tx_collide_11times;
2935 u64 tx_collide_12times;
2936 u64 tx_collide_13times;
2937 u64 tx_collide_14times;
2938 u64 tx_collide_15times;
2939 u64 tx_ucast_packets;
2940 u64 tx_mcast_packets;
2941 u64 tx_bcast_packets;
2942 u64 tx_carrier_sense_errors;
2943 u64 tx_discards;
2944 u64 tx_errors;
2945
2946 /* Statistics maintained by Receive List Placement. */
2947 u64 dma_writeq_full;
2948 u64 dma_write_prioq_full;
2949 u64 rxbds_empty;
2950 u64 rx_discards;
2951 u64 rx_errors;
2952 u64 rx_threshold_hit;
2953
2954 /* Statistics maintained by Send Data Initiator. */
2955 u64 dma_readq_full;
2956 u64 dma_read_prioq_full;
2957 u64 tx_comp_queue_full;
2958
2959 /* Statistics maintained by Host Coalescing. */
2960 u64 ring_set_send_prod_index;
2961 u64 ring_status_update;
2962 u64 nic_irqs;
2963 u64 nic_avoided_irqs;
2964 u64 nic_tx_threshold_hit;
2965
2966 u64 mbuf_lwm_thresh_hit;
2967};
2968
2969struct tg3_rx_prodring_set {
2970 u32 rx_std_prod_idx;
2971 u32 rx_std_cons_idx;
2972 u32 rx_jmb_prod_idx;
2973 u32 rx_jmb_cons_idx;
2974 struct tg3_rx_buffer_desc *rx_std;
2975 struct tg3_ext_rx_buffer_desc *rx_jmb;
2976 struct ring_info *rx_std_buffers;
2977 struct ring_info *rx_jmb_buffers;
2978 dma_addr_t rx_std_mapping;
2979 dma_addr_t rx_jmb_mapping;
2980};
2981
2982#define TG3_RSS_MAX_NUM_QS 4
2983#define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1)
2984#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2985
2986struct tg3_napi {
2987 struct napi_struct napi ____cacheline_aligned;
2988 struct tg3 *tp;
2989 struct tg3_hw_status *hw_status;
2990
2991 u32 chk_msi_cnt;
2992 u32 last_tag;
2993 u32 last_irq_tag;
2994 u32 int_mbox;
2995 u32 coal_now;
2996
2997 u32 consmbox ____cacheline_aligned;
2998 u32 rx_rcb_ptr;
2999 u32 last_rx_cons;
3000 u16 *rx_rcb_prod_idx;
3001 struct tg3_rx_prodring_set prodring;
3002 struct tg3_rx_buffer_desc *rx_rcb;
3003
3004 u32 tx_prod ____cacheline_aligned;
3005 u32 tx_cons;
3006 u32 tx_pending;
3007 u32 last_tx_cons;
3008 u32 prodmbox;
3009 struct tg3_tx_buffer_desc *tx_ring;
3010 struct tg3_tx_ring_info *tx_buffers;
3011
3012 dma_addr_t status_mapping;
3013 dma_addr_t rx_rcb_mapping;
3014 dma_addr_t tx_desc_mapping;
3015
3016 char irq_lbl[IFNAMSIZ];
3017 unsigned int irq_vec;
3018};
3019
3020enum TG3_FLAGS {
3021 TG3_FLAG_TAGGED_STATUS = 0,
3022 TG3_FLAG_TXD_MBOX_HWBUG,
3023 TG3_FLAG_USE_LINKCHG_REG,
3024 TG3_FLAG_ERROR_PROCESSED,
3025 TG3_FLAG_ENABLE_ASF,
3026 TG3_FLAG_ASPM_WORKAROUND,
3027 TG3_FLAG_POLL_SERDES,
3028 TG3_FLAG_POLL_CPMU_LINK,
3029 TG3_FLAG_MBOX_WRITE_REORDER,
3030 TG3_FLAG_PCIX_TARGET_HWBUG,
3031 TG3_FLAG_WOL_SPEED_100MB,
3032 TG3_FLAG_WOL_ENABLE,
3033 TG3_FLAG_EEPROM_WRITE_PROT,
3034 TG3_FLAG_NVRAM,
3035 TG3_FLAG_NVRAM_BUFFERED,
3036 TG3_FLAG_SUPPORT_MSI,
3037 TG3_FLAG_SUPPORT_MSIX,
3038 TG3_FLAG_USING_MSI,
3039 TG3_FLAG_USING_MSIX,
3040 TG3_FLAG_PCIX_MODE,
3041 TG3_FLAG_PCI_HIGH_SPEED,
3042 TG3_FLAG_PCI_32BIT,
3043 TG3_FLAG_SRAM_USE_CONFIG,
3044 TG3_FLAG_TX_RECOVERY_PENDING,
3045 TG3_FLAG_WOL_CAP,
3046 TG3_FLAG_JUMBO_RING_ENABLE,
3047 TG3_FLAG_PAUSE_AUTONEG,
3048 TG3_FLAG_CPMU_PRESENT,
3049 TG3_FLAG_40BIT_DMA_BUG,
3050 TG3_FLAG_BROKEN_CHECKSUMS,
3051 TG3_FLAG_JUMBO_CAPABLE,
3052 TG3_FLAG_CHIP_RESETTING,
3053 TG3_FLAG_INIT_COMPLETE,
3054 TG3_FLAG_MAX_RXPEND_64,
3055 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
3056 TG3_FLAG_ASF_NEW_HANDSHAKE,
3057 TG3_FLAG_HW_AUTONEG,
3058 TG3_FLAG_IS_NIC,
3059 TG3_FLAG_FLASH,
3060 TG3_FLAG_FW_TSO,
3061 TG3_FLAG_HW_TSO_1,
3062 TG3_FLAG_HW_TSO_2,
3063 TG3_FLAG_HW_TSO_3,
3064 TG3_FLAG_TSO_CAPABLE,
3065 TG3_FLAG_TSO_BUG,
3066 TG3_FLAG_ICH_WORKAROUND,
3067 TG3_FLAG_1SHOT_MSI,
3068 TG3_FLAG_NO_FWARE_REPORTED,
3069 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
3070 TG3_FLAG_ENABLE_APE,
3071 TG3_FLAG_PROTECTED_NVRAM,
3072 TG3_FLAG_5701_DMA_BUG,
3073 TG3_FLAG_USE_PHYLIB,
3074 TG3_FLAG_MDIOBUS_INITED,
3075 TG3_FLAG_LRG_PROD_RING_CAP,
3076 TG3_FLAG_RGMII_INBAND_DISABLE,
3077 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
3078 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
3079 TG3_FLAG_CLKREQ_BUG,
3080 TG3_FLAG_NO_NVRAM,
3081 TG3_FLAG_ENABLE_RSS,
3082 TG3_FLAG_ENABLE_TSS,
3083 TG3_FLAG_SHORT_DMA_BUG,
3084 TG3_FLAG_USE_JUMBO_BDFLAG,
3085 TG3_FLAG_L1PLLPD_EN,
3086 TG3_FLAG_APE_HAS_NCSI,
3087 TG3_FLAG_TX_TSTAMP_EN,
3088 TG3_FLAG_4K_FIFO_LIMIT,
3089 TG3_FLAG_5719_5720_RDMA_BUG,
3090 TG3_FLAG_RESET_TASK_PENDING,
3091 TG3_FLAG_PTP_CAPABLE,
3092 TG3_FLAG_5705_PLUS,
3093 TG3_FLAG_IS_5788,
3094 TG3_FLAG_5750_PLUS,
3095 TG3_FLAG_5780_CLASS,
3096 TG3_FLAG_5755_PLUS,
3097 TG3_FLAG_57765_PLUS,
3098 TG3_FLAG_57765_CLASS,
3099 TG3_FLAG_5717_PLUS,
3100 TG3_FLAG_IS_SSB_CORE,
3101 TG3_FLAG_FLUSH_POSTED_WRITES,
3102 TG3_FLAG_ROBOSWITCH,
3103 TG3_FLAG_ONE_DMA_AT_ONCE,
3104 TG3_FLAG_RGMII_MODE,
3105
3106 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3107 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
3108};
3109
3110struct tg3_firmware_hdr {
3111 __be32 version; /* unused for fragments */
3112 __be32 base_addr;
3113 __be32 len;
3114};
3115#define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr))
3116
3117struct tg3 {
3118 /* begin "general, frequently-used members" cacheline section */
3119
3120 /* If the IRQ handler (which runs lockless) needs to be
3121 * quiesced, the following bitmask state is used. The
3122 * SYNC flag is set by non-IRQ context code to initiate
3123 * the quiescence.
3124 *
3125 * When the IRQ handler notices that SYNC is set, it
3126 * disables interrupts and returns.
3127 *
3128 * When all outstanding IRQ handlers have returned after
3129 * the SYNC flag has been set, the setter can be assured
3130 * that interrupts will no longer get run.
3131 *
3132 * In this way all SMP driver locks are never acquired
3133 * in hw IRQ context, only sw IRQ context or lower.
3134 */
3135 unsigned int irq_sync;
3136
3137 /* SMP locking strategy:
3138 *
3139 * lock: Held during reset, PHY access, timer, and when
3140 * updating tg3_flags.
3141 *
3142 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3143 * netif_tx_lock when it needs to call
3144 * netif_wake_queue.
3145 *
3146 * Both of these locks are to be held with BH safety.
3147 *
3148 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3149 * are running lockless, it is necessary to completely
3150 * quiesce the chip with tg3_netif_stop and tg3_full_lock
3151 * before reconfiguring the device.
3152 *
3153 * indirect_lock: Held when accessing registers indirectly
3154 * with IRQ disabling.
3155 */
3156 spinlock_t lock;
3157 spinlock_t indirect_lock;
3158
3159 u32 (*read32) (struct tg3 *, u32);
3160 void (*write32) (struct tg3 *, u32, u32);
3161 u32 (*read32_mbox) (struct tg3 *, u32);
3162 void (*write32_mbox) (struct tg3 *, u32,
3163 u32);
3164 void __iomem *regs;
3165 void __iomem *aperegs;
3166 struct net_device *dev;
3167 struct pci_dev *pdev;
3168
3169 u32 coal_now;
3170 u32 msg_enable;
3171
3172 struct ptp_clock_info ptp_info;
3173 struct ptp_clock *ptp_clock;
3174 s64 ptp_adjust;
3175
3176 /* begin "tx thread" cacheline section */
3177 void (*write32_tx_mbox) (struct tg3 *, u32,
3178 u32);
3179 u32 dma_limit;
3180 u32 txq_req;
3181 u32 txq_cnt;
3182 u32 txq_max;
3183
3184 /* begin "rx thread" cacheline section */
3185 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
3186 void (*write32_rx_mbox) (struct tg3 *, u32,
3187 u32);
3188 u32 rx_copy_thresh;
3189 u32 rx_std_ring_mask;
3190 u32 rx_jmb_ring_mask;
3191 u32 rx_ret_ring_mask;
3192 u32 rx_pending;
3193 u32 rx_jumbo_pending;
3194 u32 rx_std_max_post;
3195 u32 rx_offset;
3196 u32 rx_pkt_map_sz;
3197 u32 rxq_req;
3198 u32 rxq_cnt;
3199 u32 rxq_max;
3200 bool rx_refill;
3201
3202
3203 /* begin "everything else" cacheline(s) section */
3204 unsigned long rx_dropped;
3205 unsigned long tx_dropped;
3206 struct rtnl_link_stats64 net_stats_prev;
3207 struct tg3_ethtool_stats estats_prev;
3208
3209 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3210
3211 union {
3212 unsigned long phy_crc_errors;
3213 unsigned long last_event_jiffies;
3214 };
3215
3216 struct timer_list timer;
3217 u16 timer_counter;
3218 u16 timer_multiplier;
3219 u32 timer_offset;
3220 u16 asf_counter;
3221 u16 asf_multiplier;
3222
3223 /* 1 second counter for transient serdes link events */
3224 u32 serdes_counter;
3225#define SERDES_AN_TIMEOUT_5704S 2
3226#define SERDES_PARALLEL_DET_TIMEOUT 1
3227#define SERDES_AN_TIMEOUT_5714S 1
3228
3229 struct tg3_link_config link_config;
3230 struct tg3_bufmgr_config bufmgr_config;
3231
3232 /* cache h/w values, often passed straight to h/w */
3233 u32 rx_mode;
3234 u32 tx_mode;
3235 u32 mac_mode;
3236 u32 mi_mode;
3237 u32 misc_host_ctrl;
3238 u32 grc_mode;
3239 u32 grc_local_ctrl;
3240 u32 dma_rwctrl;
3241 u32 coalesce_mode;
3242 u32 pwrmgmt_thresh;
3243 u32 rxptpctl;
3244
3245 /* PCI block */
3246 u32 pci_chip_rev_id;
3247 u16 pci_cmd;
3248 u8 pci_cacheline_sz;
3249 u8 pci_lat_timer;
3250
3251 int pci_fn;
3252 int msi_cap;
3253 int pcix_cap;
3254 int pcie_readrq;
3255
3256 struct mii_bus *mdio_bus;
3257 int old_link;
3258
3259 u8 phy_addr;
3260 u8 phy_ape_lock;
3261
3262 /* PHY info */
3263 u32 phy_id;
3264#define TG3_PHY_ID_MASK 0xfffffff0
3265#define TG3_PHY_ID_BCM5400 0x60008040
3266#define TG3_PHY_ID_BCM5401 0x60008050
3267#define TG3_PHY_ID_BCM5411 0x60008070
3268#define TG3_PHY_ID_BCM5701 0x60008110
3269#define TG3_PHY_ID_BCM5703 0x60008160
3270#define TG3_PHY_ID_BCM5704 0x60008190
3271#define TG3_PHY_ID_BCM5705 0x600081a0
3272#define TG3_PHY_ID_BCM5750 0x60008180
3273#define TG3_PHY_ID_BCM5752 0x60008100
3274#define TG3_PHY_ID_BCM5714 0x60008340
3275#define TG3_PHY_ID_BCM5780 0x60008350
3276#define TG3_PHY_ID_BCM5755 0xbc050cc0
3277#define TG3_PHY_ID_BCM5787 0xbc050ce0
3278#define TG3_PHY_ID_BCM5756 0xbc050ed0
3279#define TG3_PHY_ID_BCM5784 0xbc050fa0
3280#define TG3_PHY_ID_BCM5761 0xbc050fd0
3281#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3282#define TG3_PHY_ID_BCM5718S 0xbc050ff0
3283#define TG3_PHY_ID_BCM57765 0x5c0d8a40
3284#define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3285#define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3286#define TG3_PHY_ID_BCM5762 0x85803780
3287#define TG3_PHY_ID_BCM5906 0xdc00ac40
3288#define TG3_PHY_ID_BCM8002 0x60010140
3289#define TG3_PHY_ID_INVALID 0xffffffff
3290
3291#define PHY_ID_RTL8211C 0x001cc910
3292#define PHY_ID_RTL8201E 0x00008200
3293
3294#define TG3_PHY_ID_REV_MASK 0x0000000f
3295#define TG3_PHY_REV_BCM5401_B0 0x1
3296
3297 /* This macro assumes the passed PHY ID is
3298 * already masked with TG3_PHY_ID_MASK.
3299 */
3300#define TG3_KNOWN_PHY_ID(X) \
3301 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3302 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3303 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3304 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3305 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3306 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3307 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3308 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3309 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3310 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3311 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \
3312 (X) == TG3_PHY_ID_BCM8002)
3313
3314 u32 phy_flags;
3315#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3316#define TG3_PHYFLG_IS_CONNECTED 0x00000002
3317#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3318#define TG3_PHYFLG_USER_CONFIGURED 0x00000008
3319#define TG3_PHYFLG_PHY_SERDES 0x00000010
3320#define TG3_PHYFLG_MII_SERDES 0x00000020
3321#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3322 TG3_PHYFLG_MII_SERDES)
3323#define TG3_PHYFLG_IS_FET 0x00000040
3324#define TG3_PHYFLG_10_100_ONLY 0x00000080
3325#define TG3_PHYFLG_ENABLE_APD 0x00000100
3326#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3327#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3328#define TG3_PHYFLG_JITTER_BUG 0x00000800
3329#define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3330#define TG3_PHYFLG_ADC_BUG 0x00002000
3331#define TG3_PHYFLG_5704_A0_BUG 0x00004000
3332#define TG3_PHYFLG_BER_BUG 0x00008000
3333#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3334#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3335#define TG3_PHYFLG_EEE_CAP 0x00040000
3336#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
3337#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
3338#define TG3_PHYFLG_MDIX_STATE 0x00200000
3339#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000
3340
3341 u32 led_ctrl;
3342 u32 phy_otp;
3343 u32 setlpicnt;
3344 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3345
3346#define TG3_BPN_SIZE 24
3347 char board_part_number[TG3_BPN_SIZE];
3348#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
3349 char fw_ver[TG3_VER_SIZE];
3350 u32 nic_sram_data_cfg;
3351 u32 pci_clock_ctrl;
3352 struct pci_dev *pdev_peer;
3353
3354 struct tg3_hw_stats *hw_stats;
3355 dma_addr_t stats_mapping;
3356 struct work_struct reset_task;
3357
3358 int nvram_lock_cnt;
3359 u32 nvram_size;
3360#define TG3_NVRAM_SIZE_2KB 0x00000800
3361#define TG3_NVRAM_SIZE_64KB 0x00010000
3362#define TG3_NVRAM_SIZE_128KB 0x00020000
3363#define TG3_NVRAM_SIZE_256KB 0x00040000
3364#define TG3_NVRAM_SIZE_512KB 0x00080000
3365#define TG3_NVRAM_SIZE_1MB 0x00100000
3366#define TG3_NVRAM_SIZE_2MB 0x00200000
3367
3368 u32 nvram_pagesize;
3369 u32 nvram_jedecnum;
3370
3371#define JEDEC_ATMEL 0x1f
3372#define JEDEC_ST 0x20
3373#define JEDEC_SAIFUN 0x4f
3374#define JEDEC_SST 0xbf
3375
3376#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3377#define ATMEL_AT24C02_PAGE_SIZE (8)
3378
3379#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3380#define ATMEL_AT24C64_PAGE_SIZE (32)
3381
3382#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3383#define ATMEL_AT24C512_PAGE_SIZE (128)
3384
3385#define ATMEL_AT45DB0X1B_PAGE_POS 9
3386#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3387
3388#define ATMEL_AT25F512_PAGE_SIZE 256
3389
3390#define ST_M45PEX0_PAGE_SIZE 256
3391
3392#define SAIFUN_SA25F0XX_PAGE_SIZE 256
3393
3394#define SST_25VF0X0_PAGE_SIZE 4098
3395
3396 unsigned int irq_max;
3397 unsigned int irq_cnt;
3398
3399 struct ethtool_coalesce coal;
3400 struct ethtool_eee eee;
3401
3402 /* firmware info */
3403 const char *fw_needed;
3404 const struct firmware *fw;
3405 u32 fw_len; /* includes BSS */
3406
3407 struct device *hwmon_dev;
3408 bool link_up;
3409 bool pcierr_recovery;
3410};
3411
3412/* Accessor macros for chip and asic attributes
3413 *
3414 * nb: Using static inlines equivalent to the accessor macros generates
3415 * larger object code with gcc 4.7.
3416 * Using statement expression macros to check tp with
3417 * typecheck(struct tg3 *, tp) also creates larger objects.
3418 */
3419#define tg3_chip_rev_id(tp) \
3420 ((tp)->pci_chip_rev_id)
3421#define tg3_asic_rev(tp) \
3422 ((tp)->pci_chip_rev_id >> 12)
3423#define tg3_chip_rev(tp) \
3424 ((tp)->pci_chip_rev_id >> 8)
3425
3426#endif /* !(_T3_H) */