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1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef _SLIC_H
4#define _SLIC_H
5
6#include <linux/types.h>
7#include <linux/netdevice.h>
8#include <linux/spinlock_types.h>
9#include <linux/dma-mapping.h>
10#include <linux/pci.h>
11#include <linux/netdevice.h>
12#include <linux/list.h>
13#include <linux/u64_stats_sync.h>
14
15#define SLIC_VGBSTAT_XPERR 0x40000000
16#define SLIC_VGBSTAT_XERRSHFT 25
17#define SLIC_VGBSTAT_XCSERR 0x23
18#define SLIC_VGBSTAT_XUFLOW 0x22
19#define SLIC_VGBSTAT_XHLEN 0x20
20#define SLIC_VGBSTAT_NETERR 0x01000000
21#define SLIC_VGBSTAT_NERRSHFT 16
22#define SLIC_VGBSTAT_NERRMSK 0x1ff
23#define SLIC_VGBSTAT_NCSERR 0x103
24#define SLIC_VGBSTAT_NUFLOW 0x102
25#define SLIC_VGBSTAT_NHLEN 0x100
26#define SLIC_VGBSTAT_LNKERR 0x00000080
27#define SLIC_VGBSTAT_LERRMSK 0xff
28#define SLIC_VGBSTAT_LDEARLY 0x86
29#define SLIC_VGBSTAT_LBOFLO 0x85
30#define SLIC_VGBSTAT_LCODERR 0x84
31#define SLIC_VGBSTAT_LDBLNBL 0x83
32#define SLIC_VGBSTAT_LCRCERR 0x82
33#define SLIC_VGBSTAT_LOFLO 0x81
34#define SLIC_VGBSTAT_LUFLO 0x80
35
36#define SLIC_IRHDDR_FLEN_MSK 0x0000ffff
37#define SLIC_IRHDDR_SVALID 0x80000000
38#define SLIC_IRHDDR_ERR 0x10000000
39
40#define SLIC_VRHSTAT_802OE 0x80000000
41#define SLIC_VRHSTAT_TPOFLO 0x10000000
42#define SLIC_VRHSTATB_802UE 0x80000000
43#define SLIC_VRHSTATB_RCVE 0x40000000
44#define SLIC_VRHSTATB_BUFF 0x20000000
45#define SLIC_VRHSTATB_CARRE 0x08000000
46#define SLIC_VRHSTATB_LONGE 0x02000000
47#define SLIC_VRHSTATB_PREA 0x01000000
48#define SLIC_VRHSTATB_CRC 0x00800000
49#define SLIC_VRHSTATB_DRBL 0x00400000
50#define SLIC_VRHSTATB_CODE 0x00200000
51#define SLIC_VRHSTATB_TPCSUM 0x00100000
52#define SLIC_VRHSTATB_TPHLEN 0x00080000
53#define SLIC_VRHSTATB_IPCSUM 0x00040000
54#define SLIC_VRHSTATB_IPLERR 0x00020000
55#define SLIC_VRHSTATB_IPHERR 0x00010000
56
57#define SLIC_CMD_XMT_REQ 0x01
58#define SLIC_CMD_TYPE_DUMB 3
59
60#define SLIC_RESET_MAGIC 0xDEAD
61#define SLIC_ICR_INT_OFF 0
62#define SLIC_ICR_INT_ON 1
63#define SLIC_ICR_INT_MASK 2
64
65#define SLIC_ISR_ERR 0x80000000
66#define SLIC_ISR_RCV 0x40000000
67#define SLIC_ISR_CMD 0x20000000
68#define SLIC_ISR_IO 0x60000000
69#define SLIC_ISR_UPC 0x10000000
70#define SLIC_ISR_LEVENT 0x08000000
71#define SLIC_ISR_RMISS 0x02000000
72#define SLIC_ISR_UPCERR 0x01000000
73#define SLIC_ISR_XDROP 0x00800000
74#define SLIC_ISR_UPCBSY 0x00020000
75
76#define SLIC_ISR_PING_MASK 0x00700000
77#define SLIC_ISR_UPCERR_MASK (SLIC_ISR_UPCERR | SLIC_ISR_UPCBSY)
78#define SLIC_ISR_UPC_MASK (SLIC_ISR_UPC | SLIC_ISR_UPCERR_MASK)
79#define SLIC_WCS_START 0x80000000
80#define SLIC_WCS_COMPARE 0x40000000
81#define SLIC_RCVWCS_BEGIN 0x40000000
82#define SLIC_RCVWCS_FINISH 0x80000000
83
84#define SLIC_MIICR_REG_16 0x00100000
85#define SLIC_MRV_REG16_XOVERON 0x0068
86
87#define SLIC_GIG_LINKUP 0x0001
88#define SLIC_GIG_FULLDUPLEX 0x0002
89#define SLIC_GIG_SPEED_MASK 0x000C
90#define SLIC_GIG_SPEED_1000 0x0008
91#define SLIC_GIG_SPEED_100 0x0004
92#define SLIC_GIG_SPEED_10 0x0000
93
94#define SLIC_GMCR_RESET 0x80000000
95#define SLIC_GMCR_GBIT 0x20000000
96#define SLIC_GMCR_FULLD 0x10000000
97#define SLIC_GMCR_GAPBB_SHIFT 14
98#define SLIC_GMCR_GAPR1_SHIFT 7
99#define SLIC_GMCR_GAPR2_SHIFT 0
100#define SLIC_GMCR_GAPBB_1000 0x60
101#define SLIC_GMCR_GAPR1_1000 0x2C
102#define SLIC_GMCR_GAPR2_1000 0x40
103#define SLIC_GMCR_GAPBB_100 0x70
104#define SLIC_GMCR_GAPR1_100 0x2C
105#define SLIC_GMCR_GAPR2_100 0x40
106
107#define SLIC_XCR_RESET 0x80000000
108#define SLIC_XCR_XMTEN 0x40000000
109#define SLIC_XCR_PAUSEEN 0x20000000
110#define SLIC_XCR_LOADRNG 0x10000000
111
112#define SLIC_GXCR_RESET 0x80000000
113#define SLIC_GXCR_XMTEN 0x40000000
114#define SLIC_GXCR_PAUSEEN 0x20000000
115
116#define SLIC_GRCR_RESET 0x80000000
117#define SLIC_GRCR_RCVEN 0x40000000
118#define SLIC_GRCR_RCVALL 0x20000000
119#define SLIC_GRCR_RCVBAD 0x10000000
120#define SLIC_GRCR_CTLEN 0x08000000
121#define SLIC_GRCR_ADDRAEN 0x02000000
122#define SLIC_GRCR_HASHSIZE_SHIFT 17
123#define SLIC_GRCR_HASHSIZE 14
124
125/* Reset Register */
126#define SLIC_REG_RESET 0x0000
127/* Interrupt Control Register */
128#define SLIC_REG_ICR 0x0008
129/* Interrupt status pointer */
130#define SLIC_REG_ISP 0x0010
131/* Interrupt status */
132#define SLIC_REG_ISR 0x0018
133/* Header buffer address reg
134 * 31-8 - phy addr of set of contiguous hdr buffers
135 * 7-0 - number of buffers passed
136 * Buffers are 256 bytes long on 256-byte boundaries.
137 */
138#define SLIC_REG_HBAR 0x0020
139/* Data buffer handle & address reg
140 * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.
141 */
142#define SLIC_REG_DBAR 0x0028
143/* Xmt Cmd buf addr regs.
144 * 1 per XMT interface
145 * 31-5 - phy addr of host command buffer
146 * 4-0 - length of cmd in multiples of 32 bytes
147 * Buffers are 32 bytes up to 512 bytes long
148 */
149#define SLIC_REG_CBAR 0x0030
150/* Write control store */
151#define SLIC_REG_WCS 0x0034
152/*Response buffer address reg.
153 * 31-8 - phy addr of set of contiguous response buffers
154 * 7-0 - number of buffers passed
155 * Buffers are 32 bytes long on 32-byte boundaries.
156 */
157#define SLIC_REG_RBAR 0x0038
158/* Read statistics (UPR) */
159#define SLIC_REG_RSTAT 0x0040
160/* Read link status */
161#define SLIC_REG_LSTAT 0x0048
162/* Write Mac Config */
163#define SLIC_REG_WMCFG 0x0050
164/* Write phy register */
165#define SLIC_REG_WPHY 0x0058
166/* Rcv Cmd buf addr reg */
167#define SLIC_REG_RCBAR 0x0060
168/* Read SLIC Config*/
169#define SLIC_REG_RCONFIG 0x0068
170/* Interrupt aggregation time */
171#define SLIC_REG_INTAGG 0x0070
172/* Write XMIT config reg */
173#define SLIC_REG_WXCFG 0x0078
174/* Write RCV config reg */
175#define SLIC_REG_WRCFG 0x0080
176/* Write rcv addr a low */
177#define SLIC_REG_WRADDRAL 0x0088
178/* Write rcv addr a high */
179#define SLIC_REG_WRADDRAH 0x0090
180/* Write rcv addr b low */
181#define SLIC_REG_WRADDRBL 0x0098
182/* Write rcv addr b high */
183#define SLIC_REG_WRADDRBH 0x00a0
184/* Low bits of mcast mask */
185#define SLIC_REG_MCASTLOW 0x00a8
186/* High bits of mcast mask */
187#define SLIC_REG_MCASTHIGH 0x00b0
188/* Ping the card */
189#define SLIC_REG_PING 0x00b8
190/* Dump command */
191#define SLIC_REG_DUMP_CMD 0x00c0
192/* Dump data pointer */
193#define SLIC_REG_DUMP_DATA 0x00c8
194/* Read card's pci_status register */
195#define SLIC_REG_PCISTATUS 0x00d0
196/* Write hostid field */
197#define SLIC_REG_WRHOSTID 0x00d8
198/* Put card in a low power state */
199#define SLIC_REG_LOW_POWER 0x00e0
200/* Force slic into quiescent state before soft reset */
201#define SLIC_REG_QUIESCE 0x00e8
202/* Reset interface queues */
203#define SLIC_REG_RESET_IFACE 0x00f0
204/* Register is only written when it has changed.
205 * Bits 63-32 for host i/f addrs.
206 */
207#define SLIC_REG_ADDR_UPPER 0x00f8
208/* 64 bit Header buffer address reg */
209#define SLIC_REG_HBAR64 0x0100
210/* 64 bit Data buffer handle & address reg */
211#define SLIC_REG_DBAR64 0x0108
212/* 64 bit Xmt Cmd buf addr regs. */
213#define SLIC_REG_CBAR64 0x0110
214/* 64 bit Response buffer address reg.*/
215#define SLIC_REG_RBAR64 0x0118
216/* 64 bit Rcv Cmd buf addr reg*/
217#define SLIC_REG_RCBAR64 0x0120
218/* Read statistics (64 bit UPR) */
219#define SLIC_REG_RSTAT64 0x0128
220/* Download Gigabit RCV sequencer ucode */
221#define SLIC_REG_RCV_WCS 0x0130
222/* Write VlanId field */
223#define SLIC_REG_WRVLANID 0x0138
224/* Read Transformer info */
225#define SLIC_REG_READ_XF_INFO 0x0140
226/* Write Transformer info */
227#define SLIC_REG_WRITE_XF_INFO 0x0148
228/* Write card ticks per second */
229#define SLIC_REG_TICKS_PER_SEC 0x0170
230#define SLIC_REG_HOSTID 0x1554
231
232#define PCI_VENDOR_ID_ALACRITECH 0x139A
233#define PCI_DEVICE_ID_ALACRITECH_MOJAVE 0x0005
234#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1 0x0005
235#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2 0x0006
236#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1F 0x0007
237#define PCI_SUBDEVICE_ID_ALACRITECH_CICADA 0x0008
238#define PCI_SUBDEVICE_ID_ALACRITECH_SES1001T 0x2006
239#define PCI_SUBDEVICE_ID_ALACRITECH_SES1001F 0x2007
240#define PCI_DEVICE_ID_ALACRITECH_OASIS 0x0007
241#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT 0x000B
242#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF 0x000C
243#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT 0x000D
244#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF 0x000E
245#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF 0x000F
246#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET 0x0010
247#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF 0x0011
248#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET 0x0012
249
250/* Note: power of two required for number descriptors */
251#define SLIC_NUM_RX_LES 256
252#define SLIC_RX_BUFF_SIZE 2048
253#define SLIC_RX_BUFF_ALIGN 256
254#define SLIC_RX_BUFF_HDR_SIZE 34
255#define SLIC_MAX_REQ_RX_DESCS 1
256
257#define SLIC_NUM_TX_DESCS 256
258#define SLIC_TX_DESC_ALIGN 32
259#define SLIC_MIN_TX_WAKEUP_DESCS 10
260#define SLIC_MAX_REQ_TX_DESCS 1
261#define SLIC_MAX_TX_COMPLETIONS 100
262
263#define SLIC_NUM_STAT_DESCS 128
264#define SLIC_STATS_DESC_ALIGN 256
265
266#define SLIC_NUM_STAT_DESC_ARRAYS 4
267#define SLIC_INVALID_STAT_DESC_IDX 0xffffffff
268
269#define SLIC_NAPI_WEIGHT 64
270
271#define SLIC_UPR_LSTAT 0
272#define SLIC_UPR_CONFIG 1
273
274#define SLIC_EEPROM_SIZE 128
275#define SLIC_EEPROM_MAGIC 0xa5a5
276
277#define SLIC_FIRMWARE_MOJAVE "slicoss/gbdownload.sys"
278#define SLIC_FIRMWARE_OASIS "slicoss/oasisdownload.sys"
279#define SLIC_RCV_FIRMWARE_MOJAVE "slicoss/gbrcvucode.sys"
280#define SLIC_RCV_FIRMWARE_OASIS "slicoss/oasisrcvucode.sys"
281#define SLIC_FIRMWARE_MIN_SIZE 64
282#define SLIC_FIRMWARE_MAX_SECTIONS 3
283
284#define SLIC_MODEL_MOJAVE 0
285#define SLIC_MODEL_OASIS 1
286
287#define SLIC_INC_STATS_COUNTER(st, counter) \
288do { \
289 u64_stats_update_begin(&(st)->syncp); \
290 (st)->counter++; \
291 u64_stats_update_end(&(st)->syncp); \
292} while (0)
293
294#define SLIC_GET_STATS_COUNTER(newst, st, counter) \
295{ \
296 unsigned int start; \
297 do { \
298 start = u64_stats_fetch_begin_irq(&(st)->syncp); \
299 newst = (st)->counter; \
300 } while (u64_stats_fetch_retry_irq(&(st)->syncp, start)); \
301}
302
303struct slic_upr {
304 dma_addr_t paddr;
305 unsigned int type;
306 struct list_head list;
307};
308
309struct slic_upr_list {
310 bool pending;
311 struct list_head list;
312 /* upr list lock */
313 spinlock_t lock;
314};
315
316/* SLIC EEPROM structure for Mojave */
317struct slic_mojave_eeprom {
318 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
319 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
320 __le16 flash_size; /* 02 Flash size */
321 __le16 eeprom_size; /* 03 EEPROM Size */
322 __le16 vendor_id; /* 04 Vendor ID */
323 __le16 dev_id; /* 05 Device ID */
324 u8 rev_id; /* 06 Revision ID */
325 u8 class_code[3]; /* 07 Class Code */
326 u8 irqpin_dbg; /* 08 Debug Interrupt pin */
327 u8 irqpin; /* Network Interrupt Pin */
328 u8 min_grant; /* 09 Minimum grant */
329 u8 max_lat; /* Maximum Latency */
330 __le16 pci_stat; /* 10 PCI Status */
331 __le16 sub_vendor_id; /* 11 Subsystem Vendor Id */
332 __le16 sub_id; /* 12 Subsystem ID */
333 __le16 dev_id_dbg; /* 13 Debug Device Id */
334 __le16 ramrom; /* 14 Dram/Rom function */
335 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes * 64K) */
336 __le16 rom_size2pci; /* 16 ROM extension size to PCI (bytes * 4k) */
337 u8 pad[2]; /* 17 Padding */
338 u8 freetime; /* 18 FreeTime setting */
339 u8 ifctrl; /* 10-bit interface control (Mojave only) */
340 __le16 dram_size; /* 19 DRAM size (bytes * 64k) */
341 u8 mac[ETH_ALEN]; /* 20 MAC addresses */
342 u8 mac2[ETH_ALEN];
343 u8 pad2[6];
344 u16 dev_id2; /* Device ID for 2nd PCI function */
345 u8 irqpin2; /* Interrupt pin for 2nd PCI function */
346 u8 class_code2[3]; /* Class Code for 2nd PCI function */
347 u16 cfg_byte6; /* Config Byte 6 */
348 u16 pme_cap; /* Power Mgment capabilities */
349 u16 nwclk_ctrl; /* NetworkClockControls */
350 u8 fru_format; /* Alacritech FRU format type */
351 u8 fru_assembly[6]; /* Alacritech FRU information */
352 u8 fru_rev[2];
353 u8 fru_serial[14];
354 u8 fru_pad[3];
355 u8 oem_fru[28]; /* optional OEM FRU format type */
356 u8 pad3[4]; /* Pad to 128 bytes - includes 2 cksum bytes
357 * (if OEM FRU info exists) and two unusable
358 * bytes at the end
359 */
360};
361
362/* SLIC EEPROM structure for Oasis */
363struct slic_oasis_eeprom {
364 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
365 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
366 __le16 spidev0_cfg; /* 02 Flash Config for SPI device 0 */
367 __le16 spidev1_cfg; /* 03 Flash Config for SPI device 1 */
368 __le16 vendor_id; /* 04 Vendor ID */
369 __le16 dev_id; /* 05 Device ID (function 0) */
370 u8 rev_id; /* 06 Revision ID */
371 u8 class_code0[3]; /* 07 Class Code for PCI function 0 */
372 u8 irqpin1; /* 08 Interrupt pin for PCI function 1*/
373 u8 class_code1[3]; /* 09 Class Code for PCI function 1 */
374 u8 irqpin2; /* 10 Interrupt pin for PCI function 2*/
375 u8 irqpin0; /* Interrupt pin for PCI function 0*/
376 u8 min_grant; /* 11 Minimum grant */
377 u8 max_lat; /* Maximum Latency */
378 __le16 sub_vendor_id; /* 12 Subsystem Vendor Id */
379 __le16 sub_id; /* 13 Subsystem ID */
380 __le16 flash_size; /* 14 Flash size (bytes / 4K) */
381 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes / 64K) */
382 __le16 rom_size2pci; /* 16 Flash (ROM extension) size to PCI
383 * (bytes / 4K)
384 */
385 __le16 dev_id1; /* 17 Device Id (function 1) */
386 __le16 dev_id2; /* 18 Device Id (function 2) */
387 __le16 dev_stat_cfg; /* 19 Device Status Config Bytes 6-7 */
388 __le16 pme_cap; /* 20 Power Mgment capabilities */
389 u8 msi_cap; /* 21 MSI capabilities */
390 u8 clock_div; /* Clock divider */
391 __le16 pci_stat_lo; /* 22 PCI Status bits 15:0 */
392 __le16 pci_stat_hi; /* 23 PCI Status bits 31:16 */
393 __le16 dram_cfg_lo; /* 24 DRAM Configuration bits 15:0 */
394 __le16 dram_cfg_hi; /* 25 DRAM Configuration bits 31:16 */
395 __le16 dram_size; /* 26 DRAM size (bytes / 64K) */
396 __le16 gpio_tbi_ctrl; /* 27 GPIO/TBI controls for functions 1/0 */
397 __le16 eeprom_size; /* 28 EEPROM Size */
398 u8 mac[ETH_ALEN]; /* 29 MAC addresses (2 ports) */
399 u8 mac2[ETH_ALEN];
400 u8 fru_format; /* 35 Alacritech FRU format type */
401 u8 fru_assembly[6]; /* Alacritech FRU information */
402 u8 fru_rev[2];
403 u8 fru_serial[14];
404 u8 fru_pad[3];
405 u8 oem_fru[28]; /* optional OEM FRU information */
406 u8 pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
407 * (if OEM FRU info exists) and two unusable
408 * bytes at the end
409 */
410};
411
412struct slic_stats {
413 u64 rx_packets;
414 u64 rx_bytes;
415 u64 rx_mcasts;
416 u64 rx_errors;
417 u64 tx_packets;
418 u64 tx_bytes;
419 /* HW STATS */
420 u64 rx_buff_miss;
421 u64 tx_dropped;
422 u64 irq_errs;
423 /* transport layer */
424 u64 rx_tpcsum;
425 u64 rx_tpoflow;
426 u64 rx_tphlen;
427 /* ip layer */
428 u64 rx_ipcsum;
429 u64 rx_iplen;
430 u64 rx_iphlen;
431 /* link layer */
432 u64 rx_early;
433 u64 rx_buffoflow;
434 u64 rx_lcode;
435 u64 rx_drbl;
436 u64 rx_crc;
437 u64 rx_oflow802;
438 u64 rx_uflow802;
439 /* oasis only */
440 u64 tx_carrier;
441 struct u64_stats_sync syncp;
442};
443
444struct slic_shmem_data {
445 __le32 isr;
446 __le32 link;
447};
448
449struct slic_shmem {
450 dma_addr_t isr_paddr;
451 dma_addr_t link_paddr;
452 struct slic_shmem_data *shmem_data;
453};
454
455struct slic_rx_info_oasis {
456 __le32 frame_status;
457 __le32 frame_status_b;
458 __le32 time_stamp;
459 __le32 checksum;
460};
461
462struct slic_rx_info_mojave {
463 __le32 frame_status;
464 __le16 byte_cnt;
465 __le16 tp_chksum;
466 __le16 ctx_hash;
467 __le16 mac_hash;
468 __le16 buff_lnk;
469};
470
471struct slic_stat_desc {
472 __le32 hnd;
473 __u8 pad[8];
474 __le32 status;
475 __u8 pad2[16];
476};
477
478struct slic_stat_queue {
479 struct slic_stat_desc *descs[SLIC_NUM_STAT_DESC_ARRAYS];
480 dma_addr_t paddr[SLIC_NUM_STAT_DESC_ARRAYS];
481 unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS];
482 unsigned int active_array;
483 unsigned int len;
484 unsigned int done_idx;
485 size_t mem_size;
486};
487
488struct slic_tx_desc {
489 __le32 hnd;
490 __le32 rsvd;
491 u8 cmd;
492 u8 flags;
493 __le16 rsvd2;
494 __le32 totlen;
495 __le32 paddrl;
496 __le32 paddrh;
497 __le32 len;
498 __le32 type;
499};
500
501struct slic_tx_buffer {
502 struct sk_buff *skb;
503 DEFINE_DMA_UNMAP_ADDR(map_addr);
504 DEFINE_DMA_UNMAP_LEN(map_len);
505 struct slic_tx_desc *desc;
506 dma_addr_t desc_paddr;
507};
508
509struct slic_tx_queue {
510 struct dma_pool *dma_pool;
511 struct slic_tx_buffer *txbuffs;
512 unsigned int len;
513 unsigned int put_idx;
514 unsigned int done_idx;
515};
516
517struct slic_rx_desc {
518 u8 pad[16];
519 __le32 buffer;
520 __le32 length;
521 __le32 status;
522};
523
524struct slic_rx_buffer {
525 struct sk_buff *skb;
526 DEFINE_DMA_UNMAP_ADDR(map_addr);
527 DEFINE_DMA_UNMAP_LEN(map_len);
528 unsigned int addr_offset;
529};
530
531struct slic_rx_queue {
532 struct slic_rx_buffer *rxbuffs;
533 unsigned int len;
534 unsigned int done_idx;
535 unsigned int put_idx;
536};
537
538struct slic_device {
539 struct pci_dev *pdev;
540 struct net_device *netdev;
541 void __iomem *regs;
542 /* upper address setting lock */
543 spinlock_t upper_lock;
544 struct slic_shmem shmem;
545 struct napi_struct napi;
546 struct slic_rx_queue rxq;
547 struct slic_tx_queue txq;
548 struct slic_stat_queue stq;
549 struct slic_stats stats;
550 struct slic_upr_list upr_list;
551 /* link configuration lock */
552 spinlock_t link_lock;
553 bool promisc;
554 int speed;
555 unsigned int duplex;
556 bool is_fiber;
557 unsigned char model;
558};
559
560static inline u32 slic_read(struct slic_device *sdev, unsigned int reg)
561{
562 return ioread32(sdev->regs + reg);
563}
564
565static inline void slic_write(struct slic_device *sdev, unsigned int reg,
566 u32 val)
567{
568 iowrite32(val, sdev->regs + reg);
569}
570
571static inline void slic_flush_write(struct slic_device *sdev)
572{
573 (void)ioread32(sdev->regs + SLIC_REG_HOSTID);
574}
575
576#endif /* _SLIC_H */