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1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include <drm/drm_crtc_helper.h>
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
47#include "amdgpu_amdkfd.h"
48
49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
55 * - 3.3.0 - Add VM support for UVD on supported hardware.
56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
57 * - 3.5.0 - Add support for new UVD_NO_OP register.
58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
59 * - 3.7.0 - Add support for VCE clock list packet
60 * - 3.8.0 - Add support raster config init in the kernel
61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
64 * - 3.12.0 - Add query for double offchip LDS buffers
65 * - 3.13.0 - Add PRT support
66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
67 * - 3.15.0 - Export more gpu info for gfx9
68 * - 3.16.0 - Add reserved vmid support
69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
70 * - 3.18.0 - Export gpu always on cu bitmap
71 * - 3.19.0 - Add support for UVD MJPEG decode
72 * - 3.20.0 - Add support for local BOs
73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
75 * - 3.23.0 - Add query for VRAM lost counter
76 * - 3.24.0 - Add high priority compute support for gfx9
77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
78 */
79#define KMS_DRIVER_MAJOR 3
80#define KMS_DRIVER_MINOR 25
81#define KMS_DRIVER_PATCHLEVEL 0
82
83int amdgpu_vram_limit = 0;
84int amdgpu_vis_vram_limit = 0;
85int amdgpu_gart_size = -1; /* auto */
86int amdgpu_gtt_size = -1; /* auto */
87int amdgpu_moverate = -1; /* auto */
88int amdgpu_benchmarking = 0;
89int amdgpu_testing = 0;
90int amdgpu_audio = -1;
91int amdgpu_disp_priority = 0;
92int amdgpu_hw_i2c = 0;
93int amdgpu_pcie_gen2 = -1;
94int amdgpu_msi = -1;
95int amdgpu_lockup_timeout = 10000;
96int amdgpu_dpm = -1;
97int amdgpu_fw_load_type = -1;
98int amdgpu_aspm = -1;
99int amdgpu_runtime_pm = -1;
100uint amdgpu_ip_block_mask = 0xffffffff;
101int amdgpu_bapm = -1;
102int amdgpu_deep_color = 0;
103int amdgpu_vm_size = -1;
104int amdgpu_vm_fragment_size = -1;
105int amdgpu_vm_block_size = -1;
106int amdgpu_vm_fault_stop = 0;
107int amdgpu_vm_debug = 0;
108int amdgpu_vram_page_split = 512;
109int amdgpu_vm_update_mode = -1;
110int amdgpu_exp_hw_support = 0;
111int amdgpu_dc = -1;
112int amdgpu_dc_log = 0;
113int amdgpu_sched_jobs = 32;
114int amdgpu_sched_hw_submission = 2;
115int amdgpu_no_evict = 0;
116int amdgpu_direct_gma_size = 0;
117uint amdgpu_pcie_gen_cap = 0;
118uint amdgpu_pcie_lane_cap = 0;
119uint amdgpu_cg_mask = 0xffffffff;
120uint amdgpu_pg_mask = 0xffffffff;
121uint amdgpu_sdma_phase_quantum = 32;
122char *amdgpu_disable_cu = NULL;
123char *amdgpu_virtual_display = NULL;
124uint amdgpu_pp_feature_mask = 0xffffbfff;
125int amdgpu_ngg = 0;
126int amdgpu_prim_buf_per_se = 0;
127int amdgpu_pos_buf_per_se = 0;
128int amdgpu_cntl_sb_buf_per_se = 0;
129int amdgpu_param_buf_per_se = 0;
130int amdgpu_job_hang_limit = 0;
131int amdgpu_lbpw = -1;
132int amdgpu_compute_multipipe = -1;
133int amdgpu_gpu_recovery = -1; /* auto */
134int amdgpu_emu_mode = 0;
135
136MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
137module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
138
139MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
140module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
141
142MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
143module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
144
145MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
146module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
147
148MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
149module_param_named(moverate, amdgpu_moverate, int, 0600);
150
151MODULE_PARM_DESC(benchmark, "Run benchmark");
152module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
153
154MODULE_PARM_DESC(test, "Run tests");
155module_param_named(test, amdgpu_testing, int, 0444);
156
157MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
158module_param_named(audio, amdgpu_audio, int, 0444);
159
160MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
161module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
162
163MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
164module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
165
166MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
167module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
168
169MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
170module_param_named(msi, amdgpu_msi, int, 0444);
171
172MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
173module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
174
175MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
176module_param_named(dpm, amdgpu_dpm, int, 0444);
177
178MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
179module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
180
181MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
182module_param_named(aspm, amdgpu_aspm, int, 0444);
183
184MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
185module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
186
187MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
188module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
189
190MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
191module_param_named(bapm, amdgpu_bapm, int, 0444);
192
193MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
194module_param_named(deep_color, amdgpu_deep_color, int, 0444);
195
196MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
197module_param_named(vm_size, amdgpu_vm_size, int, 0444);
198
199MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
200module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
201
202MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
203module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
204
205MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
206module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
207
208MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
209module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
210
211MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
212module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
213
214MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
215module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
216
217MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
218module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
219
220MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
221module_param_named(dc, amdgpu_dc, int, 0444);
222
223MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty");
224module_param_named(dc_log, amdgpu_dc_log, int, 0444);
225
226MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
227module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
228
229MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
230module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
231
232MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
233module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
234
235MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
236module_param_named(no_evict, amdgpu_no_evict, int, 0444);
237
238MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
239module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
240
241MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
242module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
243
244MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
245module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
246
247MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
248module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
249
250MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
251module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
252
253MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
254module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
255
256MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
257module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
258
259MODULE_PARM_DESC(virtual_display,
260 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
261module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
262
263MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
264module_param_named(ngg, amdgpu_ngg, int, 0444);
265
266MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
267module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
268
269MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
270module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
271
272MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
273module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
274
275MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
276module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
277
278MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
279module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
280
281MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
282module_param_named(lbpw, amdgpu_lbpw, int, 0444);
283
284MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
285module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
286
287MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
288module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
289
290MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
291module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
292
293#ifdef CONFIG_DRM_AMDGPU_SI
294
295#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
296int amdgpu_si_support = 0;
297MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
298#else
299int amdgpu_si_support = 1;
300MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
301#endif
302
303module_param_named(si_support, amdgpu_si_support, int, 0444);
304#endif
305
306#ifdef CONFIG_DRM_AMDGPU_CIK
307
308#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
309int amdgpu_cik_support = 0;
310MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
311#else
312int amdgpu_cik_support = 1;
313MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
314#endif
315
316module_param_named(cik_support, amdgpu_cik_support, int, 0444);
317#endif
318
319static const struct pci_device_id pciidlist[] = {
320#ifdef CONFIG_DRM_AMDGPU_SI
321 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
322 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
323 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
324 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
325 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
326 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
327 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
328 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
329 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
330 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
331 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
332 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
333 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
334 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
335 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
336 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
337 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
338 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
339 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
340 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
341 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
342 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
343 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
344 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
345 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
346 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
347 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
348 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
349 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
350 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
351 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
352 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
353 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
354 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
355 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
356 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
357 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
358 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
359 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
360 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
361 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
362 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
363 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
364 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
365 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
366 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
367 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
368 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
369 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
370 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
371 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
372 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
373 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
374 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
375 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
376 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
377 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
378 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
379 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
380 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
381 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
382 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
383 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
384 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
385 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
386 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
387 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
388 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
389 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
390 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
391 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
392 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
393#endif
394#ifdef CONFIG_DRM_AMDGPU_CIK
395 /* Kaveri */
396 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
397 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
398 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
399 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
400 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
401 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
402 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
403 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
404 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
405 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
406 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
407 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
408 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
409 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
410 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
411 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
412 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
413 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
414 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
415 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
416 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
417 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
418 /* Bonaire */
419 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
420 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
421 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
422 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
423 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
424 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
425 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
426 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
427 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
428 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
429 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
430 /* Hawaii */
431 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
432 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
433 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
434 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
435 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
436 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
437 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
438 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
439 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
440 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
441 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
442 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
443 /* Kabini */
444 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
445 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
446 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
447 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
448 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
449 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
450 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
451 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
452 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
453 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
454 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
455 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
456 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
457 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
458 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
459 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
460 /* mullins */
461 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
462 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
463 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
464 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
465 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
466 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
467 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
468 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
469 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
470 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
471 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
472 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
473 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
474 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
475 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
476 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
477#endif
478 /* topaz */
479 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
480 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
481 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
482 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
483 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
484 /* tonga */
485 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
486 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
487 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
488 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
489 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
490 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
491 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
492 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
493 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
494 /* fiji */
495 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
496 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
497 /* carrizo */
498 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
499 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
500 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
501 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
502 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
503 /* stoney */
504 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
505 /* Polaris11 */
506 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
507 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
508 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
509 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
510 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
511 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
512 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
513 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
514 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
515 /* Polaris10 */
516 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
517 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
518 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
519 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
520 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
521 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
522 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
523 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
524 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
525 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
526 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
527 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
528 /* Polaris12 */
529 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
530 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
531 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
532 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
533 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
534 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
535 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
536 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
537 /* Vega 10 */
538 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
539 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
540 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
541 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
542 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
543 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
544 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
545 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
546 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
547 /* Vega 12 */
548 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
549 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
550 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
551 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
552 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
553 /* Raven */
554 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
555
556 {0, 0, 0}
557};
558
559MODULE_DEVICE_TABLE(pci, pciidlist);
560
561static struct drm_driver kms_driver;
562
563static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
564{
565 struct apertures_struct *ap;
566 bool primary = false;
567
568 ap = alloc_apertures(1);
569 if (!ap)
570 return -ENOMEM;
571
572 ap->ranges[0].base = pci_resource_start(pdev, 0);
573 ap->ranges[0].size = pci_resource_len(pdev, 0);
574
575#ifdef CONFIG_X86
576 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
577#endif
578 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
579 kfree(ap);
580
581 return 0;
582}
583
584
585static int amdgpu_pci_probe(struct pci_dev *pdev,
586 const struct pci_device_id *ent)
587{
588 struct drm_device *dev;
589 unsigned long flags = ent->driver_data;
590 int ret, retry = 0;
591 bool supports_atomic = false;
592
593 if (!amdgpu_virtual_display &&
594 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
595 supports_atomic = true;
596
597 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
598 DRM_INFO("This hardware requires experimental hardware support.\n"
599 "See modparam exp_hw_support\n");
600 return -ENODEV;
601 }
602
603 /*
604 * Initialize amdkfd before starting radeon. If it was not loaded yet,
605 * defer radeon probing
606 */
607 ret = amdgpu_amdkfd_init();
608 if (ret == -EPROBE_DEFER)
609 return ret;
610
611 /* Get rid of things like offb */
612 ret = amdgpu_kick_out_firmware_fb(pdev);
613 if (ret)
614 return ret;
615
616 /* warn the user if they mix atomic and non-atomic capable GPUs */
617 if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic)
618 DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n");
619 /* support atomic early so the atomic debugfs stuff gets created */
620 if (supports_atomic)
621 kms_driver.driver_features |= DRIVER_ATOMIC;
622
623 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
624 if (IS_ERR(dev))
625 return PTR_ERR(dev);
626
627 ret = pci_enable_device(pdev);
628 if (ret)
629 goto err_free;
630
631 dev->pdev = pdev;
632
633 pci_set_drvdata(pdev, dev);
634
635retry_init:
636 ret = drm_dev_register(dev, ent->driver_data);
637 if (ret == -EAGAIN && ++retry <= 3) {
638 DRM_INFO("retry init %d\n", retry);
639 /* Don't request EX mode too frequently which is attacking */
640 msleep(5000);
641 goto retry_init;
642 } else if (ret)
643 goto err_pci;
644
645 return 0;
646
647err_pci:
648 pci_disable_device(pdev);
649err_free:
650 drm_dev_unref(dev);
651 return ret;
652}
653
654static void
655amdgpu_pci_remove(struct pci_dev *pdev)
656{
657 struct drm_device *dev = pci_get_drvdata(pdev);
658
659 drm_dev_unregister(dev);
660 drm_dev_unref(dev);
661 pci_disable_device(pdev);
662 pci_set_drvdata(pdev, NULL);
663}
664
665static void
666amdgpu_pci_shutdown(struct pci_dev *pdev)
667{
668 struct drm_device *dev = pci_get_drvdata(pdev);
669 struct amdgpu_device *adev = dev->dev_private;
670
671 /* if we are running in a VM, make sure the device
672 * torn down properly on reboot/shutdown.
673 * unfortunately we can't detect certain
674 * hypervisors so just do this all the time.
675 */
676 amdgpu_device_ip_suspend(adev);
677}
678
679static int amdgpu_pmops_suspend(struct device *dev)
680{
681 struct pci_dev *pdev = to_pci_dev(dev);
682
683 struct drm_device *drm_dev = pci_get_drvdata(pdev);
684 return amdgpu_device_suspend(drm_dev, true, true);
685}
686
687static int amdgpu_pmops_resume(struct device *dev)
688{
689 struct pci_dev *pdev = to_pci_dev(dev);
690 struct drm_device *drm_dev = pci_get_drvdata(pdev);
691
692 /* GPU comes up enabled by the bios on resume */
693 if (amdgpu_device_is_px(drm_dev)) {
694 pm_runtime_disable(dev);
695 pm_runtime_set_active(dev);
696 pm_runtime_enable(dev);
697 }
698
699 return amdgpu_device_resume(drm_dev, true, true);
700}
701
702static int amdgpu_pmops_freeze(struct device *dev)
703{
704 struct pci_dev *pdev = to_pci_dev(dev);
705
706 struct drm_device *drm_dev = pci_get_drvdata(pdev);
707 return amdgpu_device_suspend(drm_dev, false, true);
708}
709
710static int amdgpu_pmops_thaw(struct device *dev)
711{
712 struct pci_dev *pdev = to_pci_dev(dev);
713
714 struct drm_device *drm_dev = pci_get_drvdata(pdev);
715 return amdgpu_device_resume(drm_dev, false, true);
716}
717
718static int amdgpu_pmops_poweroff(struct device *dev)
719{
720 struct pci_dev *pdev = to_pci_dev(dev);
721
722 struct drm_device *drm_dev = pci_get_drvdata(pdev);
723 return amdgpu_device_suspend(drm_dev, true, true);
724}
725
726static int amdgpu_pmops_restore(struct device *dev)
727{
728 struct pci_dev *pdev = to_pci_dev(dev);
729
730 struct drm_device *drm_dev = pci_get_drvdata(pdev);
731 return amdgpu_device_resume(drm_dev, false, true);
732}
733
734static int amdgpu_pmops_runtime_suspend(struct device *dev)
735{
736 struct pci_dev *pdev = to_pci_dev(dev);
737 struct drm_device *drm_dev = pci_get_drvdata(pdev);
738 int ret;
739
740 if (!amdgpu_device_is_px(drm_dev)) {
741 pm_runtime_forbid(dev);
742 return -EBUSY;
743 }
744
745 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
746 drm_kms_helper_poll_disable(drm_dev);
747
748 ret = amdgpu_device_suspend(drm_dev, false, false);
749 pci_save_state(pdev);
750 pci_disable_device(pdev);
751 pci_ignore_hotplug(pdev);
752 if (amdgpu_is_atpx_hybrid())
753 pci_set_power_state(pdev, PCI_D3cold);
754 else if (!amdgpu_has_atpx_dgpu_power_cntl())
755 pci_set_power_state(pdev, PCI_D3hot);
756 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
757
758 return 0;
759}
760
761static int amdgpu_pmops_runtime_resume(struct device *dev)
762{
763 struct pci_dev *pdev = to_pci_dev(dev);
764 struct drm_device *drm_dev = pci_get_drvdata(pdev);
765 int ret;
766
767 if (!amdgpu_device_is_px(drm_dev))
768 return -EINVAL;
769
770 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
771
772 if (amdgpu_is_atpx_hybrid() ||
773 !amdgpu_has_atpx_dgpu_power_cntl())
774 pci_set_power_state(pdev, PCI_D0);
775 pci_restore_state(pdev);
776 ret = pci_enable_device(pdev);
777 if (ret)
778 return ret;
779 pci_set_master(pdev);
780
781 ret = amdgpu_device_resume(drm_dev, false, false);
782 drm_kms_helper_poll_enable(drm_dev);
783 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
784 return 0;
785}
786
787static int amdgpu_pmops_runtime_idle(struct device *dev)
788{
789 struct pci_dev *pdev = to_pci_dev(dev);
790 struct drm_device *drm_dev = pci_get_drvdata(pdev);
791 struct drm_crtc *crtc;
792
793 if (!amdgpu_device_is_px(drm_dev)) {
794 pm_runtime_forbid(dev);
795 return -EBUSY;
796 }
797
798 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
799 if (crtc->enabled) {
800 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
801 return -EBUSY;
802 }
803 }
804
805 pm_runtime_mark_last_busy(dev);
806 pm_runtime_autosuspend(dev);
807 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
808 return 1;
809}
810
811long amdgpu_drm_ioctl(struct file *filp,
812 unsigned int cmd, unsigned long arg)
813{
814 struct drm_file *file_priv = filp->private_data;
815 struct drm_device *dev;
816 long ret;
817 dev = file_priv->minor->dev;
818 ret = pm_runtime_get_sync(dev->dev);
819 if (ret < 0)
820 return ret;
821
822 ret = drm_ioctl(filp, cmd, arg);
823
824 pm_runtime_mark_last_busy(dev->dev);
825 pm_runtime_put_autosuspend(dev->dev);
826 return ret;
827}
828
829static const struct dev_pm_ops amdgpu_pm_ops = {
830 .suspend = amdgpu_pmops_suspend,
831 .resume = amdgpu_pmops_resume,
832 .freeze = amdgpu_pmops_freeze,
833 .thaw = amdgpu_pmops_thaw,
834 .poweroff = amdgpu_pmops_poweroff,
835 .restore = amdgpu_pmops_restore,
836 .runtime_suspend = amdgpu_pmops_runtime_suspend,
837 .runtime_resume = amdgpu_pmops_runtime_resume,
838 .runtime_idle = amdgpu_pmops_runtime_idle,
839};
840
841static const struct file_operations amdgpu_driver_kms_fops = {
842 .owner = THIS_MODULE,
843 .open = drm_open,
844 .release = drm_release,
845 .unlocked_ioctl = amdgpu_drm_ioctl,
846 .mmap = amdgpu_mmap,
847 .poll = drm_poll,
848 .read = drm_read,
849#ifdef CONFIG_COMPAT
850 .compat_ioctl = amdgpu_kms_compat_ioctl,
851#endif
852};
853
854static bool
855amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
856 bool in_vblank_irq, int *vpos, int *hpos,
857 ktime_t *stime, ktime_t *etime,
858 const struct drm_display_mode *mode)
859{
860 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
861 stime, etime, mode);
862}
863
864static struct drm_driver kms_driver = {
865 .driver_features =
866 DRIVER_USE_AGP |
867 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
868 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
869 .load = amdgpu_driver_load_kms,
870 .open = amdgpu_driver_open_kms,
871 .postclose = amdgpu_driver_postclose_kms,
872 .lastclose = amdgpu_driver_lastclose_kms,
873 .unload = amdgpu_driver_unload_kms,
874 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
875 .enable_vblank = amdgpu_enable_vblank_kms,
876 .disable_vblank = amdgpu_disable_vblank_kms,
877 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
878 .get_scanout_position = amdgpu_get_crtc_scanout_position,
879 .irq_handler = amdgpu_irq_handler,
880 .ioctls = amdgpu_ioctls_kms,
881 .gem_free_object_unlocked = amdgpu_gem_object_free,
882 .gem_open_object = amdgpu_gem_object_open,
883 .gem_close_object = amdgpu_gem_object_close,
884 .dumb_create = amdgpu_mode_dumb_create,
885 .dumb_map_offset = amdgpu_mode_dumb_mmap,
886 .fops = &amdgpu_driver_kms_fops,
887
888 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
889 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
890 .gem_prime_export = amdgpu_gem_prime_export,
891 .gem_prime_import = amdgpu_gem_prime_import,
892 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
893 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
894 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
895 .gem_prime_vmap = amdgpu_gem_prime_vmap,
896 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
897 .gem_prime_mmap = amdgpu_gem_prime_mmap,
898
899 .name = DRIVER_NAME,
900 .desc = DRIVER_DESC,
901 .date = DRIVER_DATE,
902 .major = KMS_DRIVER_MAJOR,
903 .minor = KMS_DRIVER_MINOR,
904 .patchlevel = KMS_DRIVER_PATCHLEVEL,
905};
906
907static struct drm_driver *driver;
908static struct pci_driver *pdriver;
909
910static struct pci_driver amdgpu_kms_pci_driver = {
911 .name = DRIVER_NAME,
912 .id_table = pciidlist,
913 .probe = amdgpu_pci_probe,
914 .remove = amdgpu_pci_remove,
915 .shutdown = amdgpu_pci_shutdown,
916 .driver.pm = &amdgpu_pm_ops,
917};
918
919
920
921static int __init amdgpu_init(void)
922{
923 int r;
924
925 if (vgacon_text_force()) {
926 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
927 return -EINVAL;
928 }
929
930 r = amdgpu_sync_init();
931 if (r)
932 goto error_sync;
933
934 r = amdgpu_fence_slab_init();
935 if (r)
936 goto error_fence;
937
938 DRM_INFO("amdgpu kernel modesetting enabled.\n");
939 driver = &kms_driver;
940 pdriver = &amdgpu_kms_pci_driver;
941 driver->num_ioctls = amdgpu_max_kms_ioctl;
942 amdgpu_register_atpx_handler();
943 /* let modprobe override vga console setting */
944 return pci_register_driver(pdriver);
945
946error_fence:
947 amdgpu_sync_fini();
948
949error_sync:
950 return r;
951}
952
953static void __exit amdgpu_exit(void)
954{
955 amdgpu_amdkfd_fini();
956 pci_unregister_driver(pdriver);
957 amdgpu_unregister_atpx_handler();
958 amdgpu_sync_fini();
959 amdgpu_fence_slab_fini();
960}
961
962module_init(amdgpu_init);
963module_exit(amdgpu_exit);
964
965MODULE_AUTHOR(DRIVER_AUTHOR);
966MODULE_DESCRIPTION(DRIVER_DESC);
967MODULE_LICENSE("GPL and additional rights");
1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
47#include "amdgpu_amdkfd.h"
48
49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 */
54#define KMS_DRIVER_MAJOR 3
55#define KMS_DRIVER_MINOR 1
56#define KMS_DRIVER_PATCHLEVEL 0
57
58int amdgpu_vram_limit = 0;
59int amdgpu_gart_size = -1; /* auto */
60int amdgpu_benchmarking = 0;
61int amdgpu_testing = 0;
62int amdgpu_audio = -1;
63int amdgpu_disp_priority = 0;
64int amdgpu_hw_i2c = 0;
65int amdgpu_pcie_gen2 = -1;
66int amdgpu_msi = -1;
67int amdgpu_lockup_timeout = 0;
68int amdgpu_dpm = -1;
69int amdgpu_smc_load_fw = 1;
70int amdgpu_aspm = -1;
71int amdgpu_runtime_pm = -1;
72unsigned amdgpu_ip_block_mask = 0xffffffff;
73int amdgpu_bapm = -1;
74int amdgpu_deep_color = 0;
75int amdgpu_vm_size = 64;
76int amdgpu_vm_block_size = -1;
77int amdgpu_vm_fault_stop = 0;
78int amdgpu_vm_debug = 0;
79int amdgpu_exp_hw_support = 0;
80int amdgpu_sched_jobs = 32;
81int amdgpu_sched_hw_submission = 2;
82int amdgpu_powerplay = -1;
83unsigned amdgpu_pcie_gen_cap = 0;
84unsigned amdgpu_pcie_lane_cap = 0;
85
86MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
87module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
88
89MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
90module_param_named(gartsize, amdgpu_gart_size, int, 0600);
91
92MODULE_PARM_DESC(benchmark, "Run benchmark");
93module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
94
95MODULE_PARM_DESC(test, "Run tests");
96module_param_named(test, amdgpu_testing, int, 0444);
97
98MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
99module_param_named(audio, amdgpu_audio, int, 0444);
100
101MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
102module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
103
104MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
105module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
106
107MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
108module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
109
110MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
111module_param_named(msi, amdgpu_msi, int, 0444);
112
113MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
114module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
115
116MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
117module_param_named(dpm, amdgpu_dpm, int, 0444);
118
119MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
120module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
121
122MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
123module_param_named(aspm, amdgpu_aspm, int, 0444);
124
125MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
126module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
127
128MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
129module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
130
131MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
132module_param_named(bapm, amdgpu_bapm, int, 0444);
133
134MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
135module_param_named(deep_color, amdgpu_deep_color, int, 0444);
136
137MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
138module_param_named(vm_size, amdgpu_vm_size, int, 0444);
139
140MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
141module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
142
143MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
144module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
145
146MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
147module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
148
149MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
150module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
151
152MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
153module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
154
155MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
156module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
157
158#ifdef CONFIG_DRM_AMD_POWERPLAY
159MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
160module_param_named(powerplay, amdgpu_powerplay, int, 0444);
161#endif
162
163MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
164module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
165
166MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
167module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
168
169static struct pci_device_id pciidlist[] = {
170#ifdef CONFIG_DRM_AMDGPU_CIK
171 /* Kaveri */
172 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
173 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
174 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
175 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
176 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
177 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
178 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
179 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
180 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
181 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
182 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
183 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
184 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
185 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
186 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
187 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
188 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
189 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
190 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
191 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
192 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
193 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
194 /* Bonaire */
195 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
196 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
197 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
198 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
199 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
200 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
201 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
202 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
203 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
204 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
205 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
206 /* Hawaii */
207 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
208 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
209 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
210 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
211 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
212 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
213 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
214 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
215 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
216 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
217 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
218 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
219 /* Kabini */
220 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
221 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
222 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
223 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
224 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
225 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
226 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
227 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
228 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
229 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
230 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
231 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
232 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
233 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
234 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
235 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
236 /* mullins */
237 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
238 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
239 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
240 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
241 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
242 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
243 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
244 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
245 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
246 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
247 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
248 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
249 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
250 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
251 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
252 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
253#endif
254 /* topaz */
255 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
256 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
257 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
258 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
259 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260 /* tonga */
261 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
262 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
263 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
264 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
265 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
266 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
267 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
268 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
269 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
270 /* fiji */
271 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
272 /* carrizo */
273 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
274 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
275 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
276 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
277 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
278 /* stoney */
279 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
280
281 {0, 0, 0}
282};
283
284MODULE_DEVICE_TABLE(pci, pciidlist);
285
286static struct drm_driver kms_driver;
287
288static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
289{
290 struct apertures_struct *ap;
291 bool primary = false;
292
293 ap = alloc_apertures(1);
294 if (!ap)
295 return -ENOMEM;
296
297 ap->ranges[0].base = pci_resource_start(pdev, 0);
298 ap->ranges[0].size = pci_resource_len(pdev, 0);
299
300#ifdef CONFIG_X86
301 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
302#endif
303 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
304 kfree(ap);
305
306 return 0;
307}
308
309static int amdgpu_pci_probe(struct pci_dev *pdev,
310 const struct pci_device_id *ent)
311{
312 unsigned long flags = ent->driver_data;
313 int ret;
314
315 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
316 DRM_INFO("This hardware requires experimental hardware support.\n"
317 "See modparam exp_hw_support\n");
318 return -ENODEV;
319 }
320
321 /*
322 * Initialize amdkfd before starting radeon. If it was not loaded yet,
323 * defer radeon probing
324 */
325 ret = amdgpu_amdkfd_init();
326 if (ret == -EPROBE_DEFER)
327 return ret;
328
329 /* Get rid of things like offb */
330 ret = amdgpu_kick_out_firmware_fb(pdev);
331 if (ret)
332 return ret;
333
334 return drm_get_pci_dev(pdev, ent, &kms_driver);
335}
336
337static void
338amdgpu_pci_remove(struct pci_dev *pdev)
339{
340 struct drm_device *dev = pci_get_drvdata(pdev);
341
342 drm_put_dev(dev);
343}
344
345static int amdgpu_pmops_suspend(struct device *dev)
346{
347 struct pci_dev *pdev = to_pci_dev(dev);
348 struct drm_device *drm_dev = pci_get_drvdata(pdev);
349 return amdgpu_suspend_kms(drm_dev, true, true);
350}
351
352static int amdgpu_pmops_resume(struct device *dev)
353{
354 struct pci_dev *pdev = to_pci_dev(dev);
355 struct drm_device *drm_dev = pci_get_drvdata(pdev);
356 return amdgpu_resume_kms(drm_dev, true, true);
357}
358
359static int amdgpu_pmops_freeze(struct device *dev)
360{
361 struct pci_dev *pdev = to_pci_dev(dev);
362 struct drm_device *drm_dev = pci_get_drvdata(pdev);
363 return amdgpu_suspend_kms(drm_dev, false, true);
364}
365
366static int amdgpu_pmops_thaw(struct device *dev)
367{
368 struct pci_dev *pdev = to_pci_dev(dev);
369 struct drm_device *drm_dev = pci_get_drvdata(pdev);
370 return amdgpu_resume_kms(drm_dev, false, true);
371}
372
373static int amdgpu_pmops_runtime_suspend(struct device *dev)
374{
375 struct pci_dev *pdev = to_pci_dev(dev);
376 struct drm_device *drm_dev = pci_get_drvdata(pdev);
377 int ret;
378
379 if (!amdgpu_device_is_px(drm_dev)) {
380 pm_runtime_forbid(dev);
381 return -EBUSY;
382 }
383
384 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
385 drm_kms_helper_poll_disable(drm_dev);
386 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
387
388 ret = amdgpu_suspend_kms(drm_dev, false, false);
389 pci_save_state(pdev);
390 pci_disable_device(pdev);
391 pci_ignore_hotplug(pdev);
392 pci_set_power_state(pdev, PCI_D3cold);
393 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
394
395 return 0;
396}
397
398static int amdgpu_pmops_runtime_resume(struct device *dev)
399{
400 struct pci_dev *pdev = to_pci_dev(dev);
401 struct drm_device *drm_dev = pci_get_drvdata(pdev);
402 int ret;
403
404 if (!amdgpu_device_is_px(drm_dev))
405 return -EINVAL;
406
407 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
408
409 pci_set_power_state(pdev, PCI_D0);
410 pci_restore_state(pdev);
411 ret = pci_enable_device(pdev);
412 if (ret)
413 return ret;
414 pci_set_master(pdev);
415
416 ret = amdgpu_resume_kms(drm_dev, false, false);
417 drm_kms_helper_poll_enable(drm_dev);
418 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
419 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
420 return 0;
421}
422
423static int amdgpu_pmops_runtime_idle(struct device *dev)
424{
425 struct pci_dev *pdev = to_pci_dev(dev);
426 struct drm_device *drm_dev = pci_get_drvdata(pdev);
427 struct drm_crtc *crtc;
428
429 if (!amdgpu_device_is_px(drm_dev)) {
430 pm_runtime_forbid(dev);
431 return -EBUSY;
432 }
433
434 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
435 if (crtc->enabled) {
436 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
437 return -EBUSY;
438 }
439 }
440
441 pm_runtime_mark_last_busy(dev);
442 pm_runtime_autosuspend(dev);
443 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
444 return 1;
445}
446
447long amdgpu_drm_ioctl(struct file *filp,
448 unsigned int cmd, unsigned long arg)
449{
450 struct drm_file *file_priv = filp->private_data;
451 struct drm_device *dev;
452 long ret;
453 dev = file_priv->minor->dev;
454 ret = pm_runtime_get_sync(dev->dev);
455 if (ret < 0)
456 return ret;
457
458 ret = drm_ioctl(filp, cmd, arg);
459
460 pm_runtime_mark_last_busy(dev->dev);
461 pm_runtime_put_autosuspend(dev->dev);
462 return ret;
463}
464
465static const struct dev_pm_ops amdgpu_pm_ops = {
466 .suspend = amdgpu_pmops_suspend,
467 .resume = amdgpu_pmops_resume,
468 .freeze = amdgpu_pmops_freeze,
469 .thaw = amdgpu_pmops_thaw,
470 .poweroff = amdgpu_pmops_freeze,
471 .restore = amdgpu_pmops_resume,
472 .runtime_suspend = amdgpu_pmops_runtime_suspend,
473 .runtime_resume = amdgpu_pmops_runtime_resume,
474 .runtime_idle = amdgpu_pmops_runtime_idle,
475};
476
477static const struct file_operations amdgpu_driver_kms_fops = {
478 .owner = THIS_MODULE,
479 .open = drm_open,
480 .release = drm_release,
481 .unlocked_ioctl = amdgpu_drm_ioctl,
482 .mmap = amdgpu_mmap,
483 .poll = drm_poll,
484 .read = drm_read,
485#ifdef CONFIG_COMPAT
486 .compat_ioctl = amdgpu_kms_compat_ioctl,
487#endif
488};
489
490static struct drm_driver kms_driver = {
491 .driver_features =
492 DRIVER_USE_AGP |
493 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
494 DRIVER_PRIME | DRIVER_RENDER,
495 .dev_priv_size = 0,
496 .load = amdgpu_driver_load_kms,
497 .open = amdgpu_driver_open_kms,
498 .preclose = amdgpu_driver_preclose_kms,
499 .postclose = amdgpu_driver_postclose_kms,
500 .lastclose = amdgpu_driver_lastclose_kms,
501 .set_busid = drm_pci_set_busid,
502 .unload = amdgpu_driver_unload_kms,
503 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
504 .enable_vblank = amdgpu_enable_vblank_kms,
505 .disable_vblank = amdgpu_disable_vblank_kms,
506 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
507 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
508#if defined(CONFIG_DEBUG_FS)
509 .debugfs_init = amdgpu_debugfs_init,
510 .debugfs_cleanup = amdgpu_debugfs_cleanup,
511#endif
512 .irq_preinstall = amdgpu_irq_preinstall,
513 .irq_postinstall = amdgpu_irq_postinstall,
514 .irq_uninstall = amdgpu_irq_uninstall,
515 .irq_handler = amdgpu_irq_handler,
516 .ioctls = amdgpu_ioctls_kms,
517 .gem_free_object = amdgpu_gem_object_free,
518 .gem_open_object = amdgpu_gem_object_open,
519 .gem_close_object = amdgpu_gem_object_close,
520 .dumb_create = amdgpu_mode_dumb_create,
521 .dumb_map_offset = amdgpu_mode_dumb_mmap,
522 .dumb_destroy = drm_gem_dumb_destroy,
523 .fops = &amdgpu_driver_kms_fops,
524
525 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
526 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
527 .gem_prime_export = amdgpu_gem_prime_export,
528 .gem_prime_import = drm_gem_prime_import,
529 .gem_prime_pin = amdgpu_gem_prime_pin,
530 .gem_prime_unpin = amdgpu_gem_prime_unpin,
531 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
532 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
533 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
534 .gem_prime_vmap = amdgpu_gem_prime_vmap,
535 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
536
537 .name = DRIVER_NAME,
538 .desc = DRIVER_DESC,
539 .date = DRIVER_DATE,
540 .major = KMS_DRIVER_MAJOR,
541 .minor = KMS_DRIVER_MINOR,
542 .patchlevel = KMS_DRIVER_PATCHLEVEL,
543};
544
545static struct drm_driver *driver;
546static struct pci_driver *pdriver;
547
548static struct pci_driver amdgpu_kms_pci_driver = {
549 .name = DRIVER_NAME,
550 .id_table = pciidlist,
551 .probe = amdgpu_pci_probe,
552 .remove = amdgpu_pci_remove,
553 .driver.pm = &amdgpu_pm_ops,
554};
555
556static int __init amdgpu_init(void)
557{
558 amdgpu_sync_init();
559#ifdef CONFIG_VGA_CONSOLE
560 if (vgacon_text_force()) {
561 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
562 return -EINVAL;
563 }
564#endif
565 DRM_INFO("amdgpu kernel modesetting enabled.\n");
566 driver = &kms_driver;
567 pdriver = &amdgpu_kms_pci_driver;
568 driver->driver_features |= DRIVER_MODESET;
569 driver->num_ioctls = amdgpu_max_kms_ioctl;
570 amdgpu_register_atpx_handler();
571
572 /* let modprobe override vga console setting */
573 return drm_pci_init(driver, pdriver);
574}
575
576static void __exit amdgpu_exit(void)
577{
578 amdgpu_amdkfd_fini();
579 drm_pci_exit(driver, pdriver);
580 amdgpu_unregister_atpx_handler();
581 amdgpu_sync_fini();
582}
583
584module_init(amdgpu_init);
585module_exit(amdgpu_exit);
586
587MODULE_AUTHOR(DRIVER_AUTHOR);
588MODULE_DESCRIPTION(DRIVER_DESC);
589MODULE_LICENSE("GPL and additional rights");