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1// SPDX-License-Identifier: GPL-2.0
2
3#include <linux/sched.h>
4#include <linux/sched/clock.h>
5
6#include <asm/cpufeature.h>
7#include <asm/e820/api.h>
8#include <asm/mtrr.h>
9#include <asm/msr.h>
10
11#include "cpu.h"
12
13#define ACE_PRESENT (1 << 6)
14#define ACE_ENABLED (1 << 7)
15#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
16
17#define RNG_PRESENT (1 << 2)
18#define RNG_ENABLED (1 << 3)
19#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
20
21static void init_c3(struct cpuinfo_x86 *c)
22{
23 u32 lo, hi;
24
25 /* Test for Centaur Extended Feature Flags presence */
26 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
27 u32 tmp = cpuid_edx(0xC0000001);
28
29 /* enable ACE unit, if present and disabled */
30 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
31 rdmsr(MSR_VIA_FCR, lo, hi);
32 lo |= ACE_FCR; /* enable ACE unit */
33 wrmsr(MSR_VIA_FCR, lo, hi);
34 pr_info("CPU: Enabled ACE h/w crypto\n");
35 }
36
37 /* enable RNG unit, if present and disabled */
38 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
39 rdmsr(MSR_VIA_RNG, lo, hi);
40 lo |= RNG_ENABLE; /* enable RNG unit */
41 wrmsr(MSR_VIA_RNG, lo, hi);
42 pr_info("CPU: Enabled h/w RNG\n");
43 }
44
45 /* store Centaur Extended Feature Flags as
46 * word 5 of the CPU capability bit array
47 */
48 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
49 }
50#ifdef CONFIG_X86_32
51 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
52 if (c->x86_model >= 6 && c->x86_model <= 13) {
53 rdmsr(MSR_VIA_FCR, lo, hi);
54 lo |= (1<<1 | 1<<7);
55 wrmsr(MSR_VIA_FCR, lo, hi);
56 set_cpu_cap(c, X86_FEATURE_CX8);
57 }
58
59 /* Before Nehemiah, the C3's had 3dNOW! */
60 if (c->x86_model >= 6 && c->x86_model < 9)
61 set_cpu_cap(c, X86_FEATURE_3DNOW);
62#endif
63 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
64 c->x86_cache_alignment = c->x86_clflush_size * 2;
65 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
66 }
67
68 cpu_detect_cache_sizes(c);
69}
70
71enum {
72 ECX8 = 1<<1,
73 EIERRINT = 1<<2,
74 DPM = 1<<3,
75 DMCE = 1<<4,
76 DSTPCLK = 1<<5,
77 ELINEAR = 1<<6,
78 DSMC = 1<<7,
79 DTLOCK = 1<<8,
80 EDCTLB = 1<<8,
81 EMMX = 1<<9,
82 DPDC = 1<<11,
83 EBRPRED = 1<<12,
84 DIC = 1<<13,
85 DDC = 1<<14,
86 DNA = 1<<15,
87 ERETSTK = 1<<16,
88 E2MMX = 1<<19,
89 EAMD3D = 1<<20,
90};
91
92static void early_init_centaur(struct cpuinfo_x86 *c)
93{
94 switch (c->x86) {
95#ifdef CONFIG_X86_32
96 case 5:
97 /* Emulate MTRRs using Centaur's MCR. */
98 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
99 break;
100#endif
101 case 6:
102 if (c->x86_model >= 0xf)
103 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
104 break;
105 }
106#ifdef CONFIG_X86_64
107 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
108#endif
109 if (c->x86_power & (1 << 8)) {
110 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
111 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
112 }
113}
114
115static void init_centaur(struct cpuinfo_x86 *c)
116{
117#ifdef CONFIG_X86_32
118 char *name;
119 u32 fcr_set = 0;
120 u32 fcr_clr = 0;
121 u32 lo, hi, newlo;
122 u32 aa, bb, cc, dd;
123
124 /*
125 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
126 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
127 */
128 clear_cpu_cap(c, 0*32+31);
129#endif
130 early_init_centaur(c);
131 switch (c->x86) {
132#ifdef CONFIG_X86_32
133 case 5:
134 switch (c->x86_model) {
135 case 4:
136 name = "C6";
137 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
138 fcr_clr = DPDC;
139 pr_notice("Disabling bugged TSC.\n");
140 clear_cpu_cap(c, X86_FEATURE_TSC);
141 break;
142 case 8:
143 switch (c->x86_stepping) {
144 default:
145 name = "2";
146 break;
147 case 7 ... 9:
148 name = "2A";
149 break;
150 case 10 ... 15:
151 name = "2B";
152 break;
153 }
154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
155 E2MMX|EAMD3D;
156 fcr_clr = DPDC;
157 break;
158 case 9:
159 name = "3";
160 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
161 E2MMX|EAMD3D;
162 fcr_clr = DPDC;
163 break;
164 default:
165 name = "??";
166 }
167
168 rdmsr(MSR_IDT_FCR1, lo, hi);
169 newlo = (lo|fcr_set) & (~fcr_clr);
170
171 if (newlo != lo) {
172 pr_info("Centaur FCR was 0x%X now 0x%X\n",
173 lo, newlo);
174 wrmsr(MSR_IDT_FCR1, newlo, hi);
175 } else {
176 pr_info("Centaur FCR is 0x%X\n", lo);
177 }
178 /* Emulate MTRRs using Centaur's MCR. */
179 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
180 /* Report CX8 */
181 set_cpu_cap(c, X86_FEATURE_CX8);
182 /* Set 3DNow! on Winchip 2 and above. */
183 if (c->x86_model >= 8)
184 set_cpu_cap(c, X86_FEATURE_3DNOW);
185 /* See if we can find out some more. */
186 if (cpuid_eax(0x80000000) >= 0x80000005) {
187 /* Yes, we can. */
188 cpuid(0x80000005, &aa, &bb, &cc, &dd);
189 /* Add L1 data and code cache sizes. */
190 c->x86_cache_size = (cc>>24)+(dd>>24);
191 }
192 sprintf(c->x86_model_id, "WinChip %s", name);
193 break;
194#endif
195 case 6:
196 init_c3(c);
197 break;
198 }
199#ifdef CONFIG_X86_64
200 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
201#endif
202}
203
204#ifdef CONFIG_X86_32
205static unsigned int
206centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
207{
208 /* VIA C3 CPUs (670-68F) need further shifting. */
209 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
210 size >>= 8;
211
212 /*
213 * There's also an erratum in Nehemiah stepping 1, which
214 * returns '65KB' instead of '64KB'
215 * - Note, it seems this may only be in engineering samples.
216 */
217 if ((c->x86 == 6) && (c->x86_model == 9) &&
218 (c->x86_stepping == 1) && (size == 65))
219 size -= 1;
220 return size;
221}
222#endif
223
224static const struct cpu_dev centaur_cpu_dev = {
225 .c_vendor = "Centaur",
226 .c_ident = { "CentaurHauls" },
227 .c_early_init = early_init_centaur,
228 .c_init = init_centaur,
229#ifdef CONFIG_X86_32
230 .legacy_cache_size = centaur_size_cache,
231#endif
232 .c_x86_vendor = X86_VENDOR_CENTAUR,
233};
234
235cpu_dev_register(centaur_cpu_dev);
1#include <linux/bitops.h>
2#include <linux/kernel.h>
3
4#include <asm/cpufeature.h>
5#include <asm/e820.h>
6#include <asm/mtrr.h>
7#include <asm/msr.h>
8
9#include "cpu.h"
10
11#define ACE_PRESENT (1 << 6)
12#define ACE_ENABLED (1 << 7)
13#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
14
15#define RNG_PRESENT (1 << 2)
16#define RNG_ENABLED (1 << 3)
17#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
18
19static void init_c3(struct cpuinfo_x86 *c)
20{
21 u32 lo, hi;
22
23 /* Test for Centaur Extended Feature Flags presence */
24 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
25 u32 tmp = cpuid_edx(0xC0000001);
26
27 /* enable ACE unit, if present and disabled */
28 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
29 rdmsr(MSR_VIA_FCR, lo, hi);
30 lo |= ACE_FCR; /* enable ACE unit */
31 wrmsr(MSR_VIA_FCR, lo, hi);
32 pr_info("CPU: Enabled ACE h/w crypto\n");
33 }
34
35 /* enable RNG unit, if present and disabled */
36 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
37 rdmsr(MSR_VIA_RNG, lo, hi);
38 lo |= RNG_ENABLE; /* enable RNG unit */
39 wrmsr(MSR_VIA_RNG, lo, hi);
40 pr_info("CPU: Enabled h/w RNG\n");
41 }
42
43 /* store Centaur Extended Feature Flags as
44 * word 5 of the CPU capability bit array
45 */
46 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
47 }
48#ifdef CONFIG_X86_32
49 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
50 if (c->x86_model >= 6 && c->x86_model <= 13) {
51 rdmsr(MSR_VIA_FCR, lo, hi);
52 lo |= (1<<1 | 1<<7);
53 wrmsr(MSR_VIA_FCR, lo, hi);
54 set_cpu_cap(c, X86_FEATURE_CX8);
55 }
56
57 /* Before Nehemiah, the C3's had 3dNOW! */
58 if (c->x86_model >= 6 && c->x86_model < 9)
59 set_cpu_cap(c, X86_FEATURE_3DNOW);
60#endif
61 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
62 c->x86_cache_alignment = c->x86_clflush_size * 2;
63 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
64 }
65
66 cpu_detect_cache_sizes(c);
67}
68
69enum {
70 ECX8 = 1<<1,
71 EIERRINT = 1<<2,
72 DPM = 1<<3,
73 DMCE = 1<<4,
74 DSTPCLK = 1<<5,
75 ELINEAR = 1<<6,
76 DSMC = 1<<7,
77 DTLOCK = 1<<8,
78 EDCTLB = 1<<8,
79 EMMX = 1<<9,
80 DPDC = 1<<11,
81 EBRPRED = 1<<12,
82 DIC = 1<<13,
83 DDC = 1<<14,
84 DNA = 1<<15,
85 ERETSTK = 1<<16,
86 E2MMX = 1<<19,
87 EAMD3D = 1<<20,
88};
89
90static void early_init_centaur(struct cpuinfo_x86 *c)
91{
92 switch (c->x86) {
93#ifdef CONFIG_X86_32
94 case 5:
95 /* Emulate MTRRs using Centaur's MCR. */
96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
97 break;
98#endif
99 case 6:
100 if (c->x86_model >= 0xf)
101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
102 break;
103 }
104#ifdef CONFIG_X86_64
105 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
106#endif
107}
108
109static void init_centaur(struct cpuinfo_x86 *c)
110{
111#ifdef CONFIG_X86_32
112 char *name;
113 u32 fcr_set = 0;
114 u32 fcr_clr = 0;
115 u32 lo, hi, newlo;
116 u32 aa, bb, cc, dd;
117
118 /*
119 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
120 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
121 */
122 clear_cpu_cap(c, 0*32+31);
123#endif
124 early_init_centaur(c);
125 switch (c->x86) {
126#ifdef CONFIG_X86_32
127 case 5:
128 switch (c->x86_model) {
129 case 4:
130 name = "C6";
131 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
132 fcr_clr = DPDC;
133 pr_notice("Disabling bugged TSC.\n");
134 clear_cpu_cap(c, X86_FEATURE_TSC);
135 break;
136 case 8:
137 switch (c->x86_mask) {
138 default:
139 name = "2";
140 break;
141 case 7 ... 9:
142 name = "2A";
143 break;
144 case 10 ... 15:
145 name = "2B";
146 break;
147 }
148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
149 E2MMX|EAMD3D;
150 fcr_clr = DPDC;
151 break;
152 case 9:
153 name = "3";
154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
155 E2MMX|EAMD3D;
156 fcr_clr = DPDC;
157 break;
158 default:
159 name = "??";
160 }
161
162 rdmsr(MSR_IDT_FCR1, lo, hi);
163 newlo = (lo|fcr_set) & (~fcr_clr);
164
165 if (newlo != lo) {
166 pr_info("Centaur FCR was 0x%X now 0x%X\n",
167 lo, newlo);
168 wrmsr(MSR_IDT_FCR1, newlo, hi);
169 } else {
170 pr_info("Centaur FCR is 0x%X\n", lo);
171 }
172 /* Emulate MTRRs using Centaur's MCR. */
173 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
174 /* Report CX8 */
175 set_cpu_cap(c, X86_FEATURE_CX8);
176 /* Set 3DNow! on Winchip 2 and above. */
177 if (c->x86_model >= 8)
178 set_cpu_cap(c, X86_FEATURE_3DNOW);
179 /* See if we can find out some more. */
180 if (cpuid_eax(0x80000000) >= 0x80000005) {
181 /* Yes, we can. */
182 cpuid(0x80000005, &aa, &bb, &cc, &dd);
183 /* Add L1 data and code cache sizes. */
184 c->x86_cache_size = (cc>>24)+(dd>>24);
185 }
186 sprintf(c->x86_model_id, "WinChip %s", name);
187 break;
188#endif
189 case 6:
190 init_c3(c);
191 break;
192 }
193#ifdef CONFIG_X86_64
194 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
195#endif
196}
197
198#ifdef CONFIG_X86_32
199static unsigned int
200centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
201{
202 /* VIA C3 CPUs (670-68F) need further shifting. */
203 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
204 size >>= 8;
205
206 /*
207 * There's also an erratum in Nehemiah stepping 1, which
208 * returns '65KB' instead of '64KB'
209 * - Note, it seems this may only be in engineering samples.
210 */
211 if ((c->x86 == 6) && (c->x86_model == 9) &&
212 (c->x86_mask == 1) && (size == 65))
213 size -= 1;
214 return size;
215}
216#endif
217
218static const struct cpu_dev centaur_cpu_dev = {
219 .c_vendor = "Centaur",
220 .c_ident = { "CentaurHauls" },
221 .c_early_init = early_init_centaur,
222 .c_init = init_centaur,
223#ifdef CONFIG_X86_32
224 .legacy_cache_size = centaur_size_cache,
225#endif
226 .c_x86_vendor = X86_VENDOR_CENTAUR,
227};
228
229cpu_dev_register(centaur_cpu_dev);