Loading...
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/perf_event.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/acpi_pmtmr.h>
21#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24#include <linux/ftrace.h>
25#include <linux/ioport.h>
26#include <linux/export.h>
27#include <linux/syscore_ops.h>
28#include <linux/delay.h>
29#include <linux/timex.h>
30#include <linux/i8253.h>
31#include <linux/dmar.h>
32#include <linux/init.h>
33#include <linux/cpu.h>
34#include <linux/dmi.h>
35#include <linux/smp.h>
36#include <linux/mm.h>
37
38#include <asm/trace/irq_vectors.h>
39#include <asm/irq_remapping.h>
40#include <asm/perf_event.h>
41#include <asm/x86_init.h>
42#include <asm/pgalloc.h>
43#include <linux/atomic.h>
44#include <asm/mpspec.h>
45#include <asm/i8259.h>
46#include <asm/proto.h>
47#include <asm/apic.h>
48#include <asm/io_apic.h>
49#include <asm/desc.h>
50#include <asm/hpet.h>
51#include <asm/mtrr.h>
52#include <asm/time.h>
53#include <asm/smp.h>
54#include <asm/mce.h>
55#include <asm/tsc.h>
56#include <asm/hypervisor.h>
57#include <asm/cpu_device_id.h>
58#include <asm/intel-family.h>
59
60unsigned int num_processors;
61
62unsigned disabled_cpus;
63
64/* Processor that is doing the boot up */
65unsigned int boot_cpu_physical_apicid = -1U;
66EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
67
68u8 boot_cpu_apic_version;
69
70/*
71 * The highest APIC ID seen during enumeration.
72 */
73static unsigned int max_physical_apicid;
74
75/*
76 * Bitmask of physically existing CPUs:
77 */
78physid_mask_t phys_cpu_present_map;
79
80/*
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
84 */
85static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
86
87/*
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
90 */
91static int apic_extnmi = APIC_EXTNMI_BSP;
92
93/*
94 * Map cpu index to physical APIC ID
95 */
96DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
97DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
98DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
99EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
100EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
101EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
102
103#ifdef CONFIG_X86_32
104
105/*
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
110 */
111DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
112
113/* Local APIC was disabled by the BIOS and enabled by the kernel */
114static int enabled_via_apicbase;
115
116/*
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
123 */
124static inline void imcr_pic_to_apic(void)
125{
126 /* select IMCR register */
127 outb(0x70, 0x22);
128 /* NMI and 8259 INTR go through APIC */
129 outb(0x01, 0x23);
130}
131
132static inline void imcr_apic_to_pic(void)
133{
134 /* select IMCR register */
135 outb(0x70, 0x22);
136 /* NMI and 8259 INTR go directly to BSP */
137 outb(0x00, 0x23);
138}
139#endif
140
141/*
142 * Knob to control our willingness to enable the local APIC.
143 *
144 * +1=force-enable
145 */
146static int force_enable_local_apic __initdata;
147
148/*
149 * APIC command line parameters
150 */
151static int __init parse_lapic(char *arg)
152{
153 if (IS_ENABLED(CONFIG_X86_32) && !arg)
154 force_enable_local_apic = 1;
155 else if (arg && !strncmp(arg, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
157 return 0;
158}
159early_param("lapic", parse_lapic);
160
161#ifdef CONFIG_X86_64
162static int apic_calibrate_pmtmr __initdata;
163static __init int setup_apicpmtimer(char *s)
164{
165 apic_calibrate_pmtmr = 1;
166 notsc_setup(NULL);
167 return 0;
168}
169__setup("apicpmtimer", setup_apicpmtimer);
170#endif
171
172unsigned long mp_lapic_addr;
173int disable_apic;
174/* Disable local APIC timer from the kernel commandline or via dmi quirk */
175static int disable_apic_timer __initdata;
176/* Local APIC timer works in C2 */
177int local_apic_timer_c2_ok;
178EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
179
180/*
181 * Debug level, exported for io_apic.c
182 */
183unsigned int apic_verbosity;
184
185int pic_mode;
186
187/* Have we found an MP table */
188int smp_found_config;
189
190static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
193};
194
195unsigned int lapic_timer_frequency = 0;
196
197static void apic_pm_activate(void);
198
199static unsigned long apic_phys;
200
201/*
202 * Get the LAPIC version
203 */
204static inline int lapic_get_version(void)
205{
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
207}
208
209/*
210 * Check, if the APIC is integrated or a separate chip
211 */
212static inline int lapic_is_integrated(void)
213{
214 return APIC_INTEGRATED(lapic_get_version());
215}
216
217/*
218 * Check, whether this is a modern or a first generation APIC
219 */
220static int modern_apic(void)
221{
222 /* AMD systems use old APIC versions, so check the CPU */
223 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
224 boot_cpu_data.x86 >= 0xf)
225 return 1;
226 return lapic_get_version() >= 0x14;
227}
228
229/*
230 * right after this call apic become NOOP driven
231 * so apic->write/read doesn't do anything
232 */
233static void __init apic_disable(void)
234{
235 pr_info("APIC: switched to apic NOOP\n");
236 apic = &apic_noop;
237}
238
239void native_apic_wait_icr_idle(void)
240{
241 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
242 cpu_relax();
243}
244
245u32 native_safe_apic_wait_icr_idle(void)
246{
247 u32 send_status;
248 int timeout;
249
250 timeout = 0;
251 do {
252 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
253 if (!send_status)
254 break;
255 inc_irq_stat(icr_read_retry_count);
256 udelay(100);
257 } while (timeout++ < 1000);
258
259 return send_status;
260}
261
262void native_apic_icr_write(u32 low, u32 id)
263{
264 unsigned long flags;
265
266 local_irq_save(flags);
267 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
268 apic_write(APIC_ICR, low);
269 local_irq_restore(flags);
270}
271
272u64 native_apic_icr_read(void)
273{
274 u32 icr1, icr2;
275
276 icr2 = apic_read(APIC_ICR2);
277 icr1 = apic_read(APIC_ICR);
278
279 return icr1 | ((u64)icr2 << 32);
280}
281
282#ifdef CONFIG_X86_32
283/**
284 * get_physical_broadcast - Get number of physical broadcast IDs
285 */
286int get_physical_broadcast(void)
287{
288 return modern_apic() ? 0xff : 0xf;
289}
290#endif
291
292/**
293 * lapic_get_maxlvt - get the maximum number of local vector table entries
294 */
295int lapic_get_maxlvt(void)
296{
297 /*
298 * - we always have APIC integrated on 64bit mode
299 * - 82489DXs do not report # of LVT entries
300 */
301 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
302}
303
304/*
305 * Local APIC timer
306 */
307
308/* Clock divisor */
309#define APIC_DIVISOR 16
310#define TSC_DIVISOR 8
311
312/*
313 * This function sets up the local APIC timer, with a timeout of
314 * 'clocks' APIC bus clock. During calibration we actually call
315 * this function twice on the boot CPU, once with a bogus timeout
316 * value, second time for real. The other (noncalibrating) CPUs
317 * call this function only once, with the real, calibrated value.
318 *
319 * We do reads before writes even if unnecessary, to get around the
320 * P5 APIC double write bug.
321 */
322static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
323{
324 unsigned int lvtt_value, tmp_value;
325
326 lvtt_value = LOCAL_TIMER_VECTOR;
327 if (!oneshot)
328 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
329 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
330 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
331
332 if (!lapic_is_integrated())
333 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
334
335 if (!irqen)
336 lvtt_value |= APIC_LVT_MASKED;
337
338 apic_write(APIC_LVTT, lvtt_value);
339
340 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
341 /*
342 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
343 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
344 * According to Intel, MFENCE can do the serialization here.
345 */
346 asm volatile("mfence" : : : "memory");
347
348 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
349 return;
350 }
351
352 /*
353 * Divide PICLK by 16
354 */
355 tmp_value = apic_read(APIC_TDCR);
356 apic_write(APIC_TDCR,
357 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
358 APIC_TDR_DIV_16);
359
360 if (!oneshot)
361 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
362}
363
364/*
365 * Setup extended LVT, AMD specific
366 *
367 * Software should use the LVT offsets the BIOS provides. The offsets
368 * are determined by the subsystems using it like those for MCE
369 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
370 * are supported. Beginning with family 10h at least 4 offsets are
371 * available.
372 *
373 * Since the offsets must be consistent for all cores, we keep track
374 * of the LVT offsets in software and reserve the offset for the same
375 * vector also to be used on other cores. An offset is freed by
376 * setting the entry to APIC_EILVT_MASKED.
377 *
378 * If the BIOS is right, there should be no conflicts. Otherwise a
379 * "[Firmware Bug]: ..." error message is generated. However, if
380 * software does not properly determines the offsets, it is not
381 * necessarily a BIOS bug.
382 */
383
384static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
385
386static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
387{
388 return (old & APIC_EILVT_MASKED)
389 || (new == APIC_EILVT_MASKED)
390 || ((new & ~APIC_EILVT_MASKED) == old);
391}
392
393static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
394{
395 unsigned int rsvd, vector;
396
397 if (offset >= APIC_EILVT_NR_MAX)
398 return ~0;
399
400 rsvd = atomic_read(&eilvt_offsets[offset]);
401 do {
402 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
403 if (vector && !eilvt_entry_is_changeable(vector, new))
404 /* may not change if vectors are different */
405 return rsvd;
406 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
407 } while (rsvd != new);
408
409 rsvd &= ~APIC_EILVT_MASKED;
410 if (rsvd && rsvd != vector)
411 pr_info("LVT offset %d assigned for vector 0x%02x\n",
412 offset, rsvd);
413
414 return new;
415}
416
417/*
418 * If mask=1, the LVT entry does not generate interrupts while mask=0
419 * enables the vector. See also the BKDGs. Must be called with
420 * preemption disabled.
421 */
422
423int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
424{
425 unsigned long reg = APIC_EILVTn(offset);
426 unsigned int new, old, reserved;
427
428 new = (mask << 16) | (msg_type << 8) | vector;
429 old = apic_read(reg);
430 reserved = reserve_eilvt_offset(offset, new);
431
432 if (reserved != new) {
433 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
434 "vector 0x%x, but the register is already in use for "
435 "vector 0x%x on another cpu\n",
436 smp_processor_id(), reg, offset, new, reserved);
437 return -EINVAL;
438 }
439
440 if (!eilvt_entry_is_changeable(old, new)) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on this cpu\n",
444 smp_processor_id(), reg, offset, new, old);
445 return -EBUSY;
446 }
447
448 apic_write(reg, new);
449
450 return 0;
451}
452EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
453
454/*
455 * Program the next event, relative to now
456 */
457static int lapic_next_event(unsigned long delta,
458 struct clock_event_device *evt)
459{
460 apic_write(APIC_TMICT, delta);
461 return 0;
462}
463
464static int lapic_next_deadline(unsigned long delta,
465 struct clock_event_device *evt)
466{
467 u64 tsc;
468
469 tsc = rdtsc();
470 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
471 return 0;
472}
473
474static int lapic_timer_shutdown(struct clock_event_device *evt)
475{
476 unsigned int v;
477
478 /* Lapic used as dummy for broadcast ? */
479 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
480 return 0;
481
482 v = apic_read(APIC_LVTT);
483 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
484 apic_write(APIC_LVTT, v);
485 apic_write(APIC_TMICT, 0);
486 return 0;
487}
488
489static inline int
490lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
491{
492 /* Lapic used as dummy for broadcast ? */
493 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
494 return 0;
495
496 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
497 return 0;
498}
499
500static int lapic_timer_set_periodic(struct clock_event_device *evt)
501{
502 return lapic_timer_set_periodic_oneshot(evt, false);
503}
504
505static int lapic_timer_set_oneshot(struct clock_event_device *evt)
506{
507 return lapic_timer_set_periodic_oneshot(evt, true);
508}
509
510/*
511 * Local APIC timer broadcast function
512 */
513static void lapic_timer_broadcast(const struct cpumask *mask)
514{
515#ifdef CONFIG_SMP
516 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
517#endif
518}
519
520
521/*
522 * The local apic timer can be used for any function which is CPU local.
523 */
524static struct clock_event_device lapic_clockevent = {
525 .name = "lapic",
526 .features = CLOCK_EVT_FEAT_PERIODIC |
527 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
528 | CLOCK_EVT_FEAT_DUMMY,
529 .shift = 32,
530 .set_state_shutdown = lapic_timer_shutdown,
531 .set_state_periodic = lapic_timer_set_periodic,
532 .set_state_oneshot = lapic_timer_set_oneshot,
533 .set_state_oneshot_stopped = lapic_timer_shutdown,
534 .set_next_event = lapic_next_event,
535 .broadcast = lapic_timer_broadcast,
536 .rating = 100,
537 .irq = -1,
538};
539static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
540
541#define DEADLINE_MODEL_MATCH_FUNC(model, func) \
542 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
543
544#define DEADLINE_MODEL_MATCH_REV(model, rev) \
545 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
546
547static u32 hsx_deadline_rev(void)
548{
549 switch (boot_cpu_data.x86_stepping) {
550 case 0x02: return 0x3a; /* EP */
551 case 0x04: return 0x0f; /* EX */
552 }
553
554 return ~0U;
555}
556
557static u32 bdx_deadline_rev(void)
558{
559 switch (boot_cpu_data.x86_stepping) {
560 case 0x02: return 0x00000011;
561 case 0x03: return 0x0700000e;
562 case 0x04: return 0x0f00000c;
563 case 0x05: return 0x0e000003;
564 }
565
566 return ~0U;
567}
568
569static u32 skx_deadline_rev(void)
570{
571 switch (boot_cpu_data.x86_stepping) {
572 case 0x03: return 0x01000136;
573 case 0x04: return 0x02000014;
574 }
575
576 return ~0U;
577}
578
579static const struct x86_cpu_id deadline_match[] = {
580 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
581 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
582 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
583 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
584
585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
588
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
591
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
594
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
597
598 {},
599};
600
601static void apic_check_deadline_errata(void)
602{
603 const struct x86_cpu_id *m;
604 u32 rev;
605
606 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
607 boot_cpu_has(X86_FEATURE_HYPERVISOR))
608 return;
609
610 m = x86_match_cpu(deadline_match);
611 if (!m)
612 return;
613
614 /*
615 * Function pointers will have the MSB set due to address layout,
616 * immediate revisions will not.
617 */
618 if ((long)m->driver_data < 0)
619 rev = ((u32 (*)(void))(m->driver_data))();
620 else
621 rev = (u32)m->driver_data;
622
623 if (boot_cpu_data.microcode >= rev)
624 return;
625
626 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
627 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
628 "please update microcode to version: 0x%x (or later)\n", rev);
629}
630
631/*
632 * Setup the local APIC timer for this CPU. Copy the initialized values
633 * of the boot CPU and register the clock event in the framework.
634 */
635static void setup_APIC_timer(void)
636{
637 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
638
639 if (this_cpu_has(X86_FEATURE_ARAT)) {
640 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
641 /* Make LAPIC timer preferrable over percpu HPET */
642 lapic_clockevent.rating = 150;
643 }
644
645 memcpy(levt, &lapic_clockevent, sizeof(*levt));
646 levt->cpumask = cpumask_of(smp_processor_id());
647
648 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
649 levt->name = "lapic-deadline";
650 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
651 CLOCK_EVT_FEAT_DUMMY);
652 levt->set_next_event = lapic_next_deadline;
653 clockevents_config_and_register(levt,
654 tsc_khz * (1000 / TSC_DIVISOR),
655 0xF, ~0UL);
656 } else
657 clockevents_register_device(levt);
658}
659
660/*
661 * Install the updated TSC frequency from recalibration at the TSC
662 * deadline clockevent devices.
663 */
664static void __lapic_update_tsc_freq(void *info)
665{
666 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
667
668 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
669 return;
670
671 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
672}
673
674void lapic_update_tsc_freq(void)
675{
676 /*
677 * The clockevent device's ->mult and ->shift can both be
678 * changed. In order to avoid races, schedule the frequency
679 * update code on each CPU.
680 */
681 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
682}
683
684/*
685 * In this functions we calibrate APIC bus clocks to the external timer.
686 *
687 * We want to do the calibration only once since we want to have local timer
688 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
689 * frequency.
690 *
691 * This was previously done by reading the PIT/HPET and waiting for a wrap
692 * around to find out, that a tick has elapsed. I have a box, where the PIT
693 * readout is broken, so it never gets out of the wait loop again. This was
694 * also reported by others.
695 *
696 * Monitoring the jiffies value is inaccurate and the clockevents
697 * infrastructure allows us to do a simple substitution of the interrupt
698 * handler.
699 *
700 * The calibration routine also uses the pm_timer when possible, as the PIT
701 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
702 * back to normal later in the boot process).
703 */
704
705#define LAPIC_CAL_LOOPS (HZ/10)
706
707static __initdata int lapic_cal_loops = -1;
708static __initdata long lapic_cal_t1, lapic_cal_t2;
709static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
710static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
711static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
712
713/*
714 * Temporary interrupt handler.
715 */
716static void __init lapic_cal_handler(struct clock_event_device *dev)
717{
718 unsigned long long tsc = 0;
719 long tapic = apic_read(APIC_TMCCT);
720 unsigned long pm = acpi_pm_read_early();
721
722 if (boot_cpu_has(X86_FEATURE_TSC))
723 tsc = rdtsc();
724
725 switch (lapic_cal_loops++) {
726 case 0:
727 lapic_cal_t1 = tapic;
728 lapic_cal_tsc1 = tsc;
729 lapic_cal_pm1 = pm;
730 lapic_cal_j1 = jiffies;
731 break;
732
733 case LAPIC_CAL_LOOPS:
734 lapic_cal_t2 = tapic;
735 lapic_cal_tsc2 = tsc;
736 if (pm < lapic_cal_pm1)
737 pm += ACPI_PM_OVRRUN;
738 lapic_cal_pm2 = pm;
739 lapic_cal_j2 = jiffies;
740 break;
741 }
742}
743
744static int __init
745calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
746{
747 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
748 const long pm_thresh = pm_100ms / 100;
749 unsigned long mult;
750 u64 res;
751
752#ifndef CONFIG_X86_PM_TIMER
753 return -1;
754#endif
755
756 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
757
758 /* Check, if the PM timer is available */
759 if (!deltapm)
760 return -1;
761
762 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
763
764 if (deltapm > (pm_100ms - pm_thresh) &&
765 deltapm < (pm_100ms + pm_thresh)) {
766 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
767 return 0;
768 }
769
770 res = (((u64)deltapm) * mult) >> 22;
771 do_div(res, 1000000);
772 pr_warning("APIC calibration not consistent "
773 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
774
775 /* Correct the lapic counter value */
776 res = (((u64)(*delta)) * pm_100ms);
777 do_div(res, deltapm);
778 pr_info("APIC delta adjusted to PM-Timer: "
779 "%lu (%ld)\n", (unsigned long)res, *delta);
780 *delta = (long)res;
781
782 /* Correct the tsc counter value */
783 if (boot_cpu_has(X86_FEATURE_TSC)) {
784 res = (((u64)(*deltatsc)) * pm_100ms);
785 do_div(res, deltapm);
786 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
787 "PM-Timer: %lu (%ld)\n",
788 (unsigned long)res, *deltatsc);
789 *deltatsc = (long)res;
790 }
791
792 return 0;
793}
794
795static int __init calibrate_APIC_clock(void)
796{
797 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
798 void (*real_handler)(struct clock_event_device *dev);
799 unsigned long deltaj;
800 long delta, deltatsc;
801 int pm_referenced = 0;
802
803 /**
804 * check if lapic timer has already been calibrated by platform
805 * specific routine, such as tsc calibration code. if so, we just fill
806 * in the clockevent structure and return.
807 */
808
809 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
810 return 0;
811 } else if (lapic_timer_frequency) {
812 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
813 lapic_timer_frequency);
814 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
815 TICK_NSEC, lapic_clockevent.shift);
816 lapic_clockevent.max_delta_ns =
817 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
818 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
819 lapic_clockevent.min_delta_ns =
820 clockevent_delta2ns(0xF, &lapic_clockevent);
821 lapic_clockevent.min_delta_ticks = 0xF;
822 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
823 return 0;
824 }
825
826 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
827 "calibrating APIC timer ...\n");
828
829 local_irq_disable();
830
831 /* Replace the global interrupt handler */
832 real_handler = global_clock_event->event_handler;
833 global_clock_event->event_handler = lapic_cal_handler;
834
835 /*
836 * Setup the APIC counter to maximum. There is no way the lapic
837 * can underflow in the 100ms detection time frame
838 */
839 __setup_APIC_LVTT(0xffffffff, 0, 0);
840
841 /* Let the interrupts run */
842 local_irq_enable();
843
844 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
845 cpu_relax();
846
847 local_irq_disable();
848
849 /* Restore the real event handler */
850 global_clock_event->event_handler = real_handler;
851
852 /* Build delta t1-t2 as apic timer counts down */
853 delta = lapic_cal_t1 - lapic_cal_t2;
854 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
855
856 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
857
858 /* we trust the PM based calibration if possible */
859 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
860 &delta, &deltatsc);
861
862 /* Calculate the scaled math multiplication factor */
863 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
864 lapic_clockevent.shift);
865 lapic_clockevent.max_delta_ns =
866 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
867 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
868 lapic_clockevent.min_delta_ns =
869 clockevent_delta2ns(0xF, &lapic_clockevent);
870 lapic_clockevent.min_delta_ticks = 0xF;
871
872 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
873
874 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
875 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
876 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
877 lapic_timer_frequency);
878
879 if (boot_cpu_has(X86_FEATURE_TSC)) {
880 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
881 "%ld.%04ld MHz.\n",
882 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
883 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
884 }
885
886 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
887 "%u.%04u MHz.\n",
888 lapic_timer_frequency / (1000000 / HZ),
889 lapic_timer_frequency % (1000000 / HZ));
890
891 /*
892 * Do a sanity check on the APIC calibration result
893 */
894 if (lapic_timer_frequency < (1000000 / HZ)) {
895 local_irq_enable();
896 pr_warning("APIC frequency too slow, disabling apic timer\n");
897 return -1;
898 }
899
900 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
901
902 /*
903 * PM timer calibration failed or not turned on
904 * so lets try APIC timer based calibration
905 */
906 if (!pm_referenced) {
907 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
908
909 /*
910 * Setup the apic timer manually
911 */
912 levt->event_handler = lapic_cal_handler;
913 lapic_timer_set_periodic(levt);
914 lapic_cal_loops = -1;
915
916 /* Let the interrupts run */
917 local_irq_enable();
918
919 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
920 cpu_relax();
921
922 /* Stop the lapic timer */
923 local_irq_disable();
924 lapic_timer_shutdown(levt);
925
926 /* Jiffies delta */
927 deltaj = lapic_cal_j2 - lapic_cal_j1;
928 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
929
930 /* Check, if the jiffies result is consistent */
931 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
932 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
933 else
934 levt->features |= CLOCK_EVT_FEAT_DUMMY;
935 }
936 local_irq_enable();
937
938 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
939 pr_warning("APIC timer disabled due to verification failure\n");
940 return -1;
941 }
942
943 return 0;
944}
945
946/*
947 * Setup the boot APIC
948 *
949 * Calibrate and verify the result.
950 */
951void __init setup_boot_APIC_clock(void)
952{
953 /*
954 * The local apic timer can be disabled via the kernel
955 * commandline or from the CPU detection code. Register the lapic
956 * timer as a dummy clock event source on SMP systems, so the
957 * broadcast mechanism is used. On UP systems simply ignore it.
958 */
959 if (disable_apic_timer) {
960 pr_info("Disabling APIC timer\n");
961 /* No broadcast on UP ! */
962 if (num_possible_cpus() > 1) {
963 lapic_clockevent.mult = 1;
964 setup_APIC_timer();
965 }
966 return;
967 }
968
969 if (calibrate_APIC_clock()) {
970 /* No broadcast on UP ! */
971 if (num_possible_cpus() > 1)
972 setup_APIC_timer();
973 return;
974 }
975
976 /*
977 * If nmi_watchdog is set to IO_APIC, we need the
978 * PIT/HPET going. Otherwise register lapic as a dummy
979 * device.
980 */
981 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
982
983 /* Setup the lapic or request the broadcast */
984 setup_APIC_timer();
985 amd_e400_c1e_apic_setup();
986}
987
988void setup_secondary_APIC_clock(void)
989{
990 setup_APIC_timer();
991 amd_e400_c1e_apic_setup();
992}
993
994/*
995 * The guts of the apic timer interrupt
996 */
997static void local_apic_timer_interrupt(void)
998{
999 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1000
1001 /*
1002 * Normally we should not be here till LAPIC has been initialized but
1003 * in some cases like kdump, its possible that there is a pending LAPIC
1004 * timer interrupt from previous kernel's context and is delivered in
1005 * new kernel the moment interrupts are enabled.
1006 *
1007 * Interrupts are enabled early and LAPIC is setup much later, hence
1008 * its possible that when we get here evt->event_handler is NULL.
1009 * Check for event_handler being NULL and discard the interrupt as
1010 * spurious.
1011 */
1012 if (!evt->event_handler) {
1013 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1014 smp_processor_id());
1015 /* Switch it off */
1016 lapic_timer_shutdown(evt);
1017 return;
1018 }
1019
1020 /*
1021 * the NMI deadlock-detector uses this.
1022 */
1023 inc_irq_stat(apic_timer_irqs);
1024
1025 evt->event_handler(evt);
1026}
1027
1028/*
1029 * Local APIC timer interrupt. This is the most natural way for doing
1030 * local interrupts, but local timer interrupts can be emulated by
1031 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1032 *
1033 * [ if a single-CPU system runs an SMP kernel then we call the local
1034 * interrupt as well. Thus we cannot inline the local irq ... ]
1035 */
1036__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1037{
1038 struct pt_regs *old_regs = set_irq_regs(regs);
1039
1040 /*
1041 * NOTE! We'd better ACK the irq immediately,
1042 * because timer handling can be slow.
1043 *
1044 * update_process_times() expects us to have done irq_enter().
1045 * Besides, if we don't timer interrupts ignore the global
1046 * interrupt lock, which is the WrongThing (tm) to do.
1047 */
1048 entering_ack_irq();
1049 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1050 local_apic_timer_interrupt();
1051 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1052 exiting_irq();
1053
1054 set_irq_regs(old_regs);
1055}
1056
1057int setup_profiling_timer(unsigned int multiplier)
1058{
1059 return -EINVAL;
1060}
1061
1062/*
1063 * Local APIC start and shutdown
1064 */
1065
1066/**
1067 * clear_local_APIC - shutdown the local APIC
1068 *
1069 * This is called, when a CPU is disabled and before rebooting, so the state of
1070 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1071 * leftovers during boot.
1072 */
1073void clear_local_APIC(void)
1074{
1075 int maxlvt;
1076 u32 v;
1077
1078 /* APIC hasn't been mapped yet */
1079 if (!x2apic_mode && !apic_phys)
1080 return;
1081
1082 maxlvt = lapic_get_maxlvt();
1083 /*
1084 * Masking an LVT entry can trigger a local APIC error
1085 * if the vector is zero. Mask LVTERR first to prevent this.
1086 */
1087 if (maxlvt >= 3) {
1088 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1089 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1090 }
1091 /*
1092 * Careful: we have to set masks only first to deassert
1093 * any level-triggered sources.
1094 */
1095 v = apic_read(APIC_LVTT);
1096 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1097 v = apic_read(APIC_LVT0);
1098 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1099 v = apic_read(APIC_LVT1);
1100 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1101 if (maxlvt >= 4) {
1102 v = apic_read(APIC_LVTPC);
1103 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1104 }
1105
1106 /* lets not touch this if we didn't frob it */
1107#ifdef CONFIG_X86_THERMAL_VECTOR
1108 if (maxlvt >= 5) {
1109 v = apic_read(APIC_LVTTHMR);
1110 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1111 }
1112#endif
1113#ifdef CONFIG_X86_MCE_INTEL
1114 if (maxlvt >= 6) {
1115 v = apic_read(APIC_LVTCMCI);
1116 if (!(v & APIC_LVT_MASKED))
1117 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1118 }
1119#endif
1120
1121 /*
1122 * Clean APIC state for other OSs:
1123 */
1124 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1125 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1126 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1127 if (maxlvt >= 3)
1128 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1129 if (maxlvt >= 4)
1130 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1131
1132 /* Integrated APIC (!82489DX) ? */
1133 if (lapic_is_integrated()) {
1134 if (maxlvt > 3)
1135 /* Clear ESR due to Pentium errata 3AP and 11AP */
1136 apic_write(APIC_ESR, 0);
1137 apic_read(APIC_ESR);
1138 }
1139}
1140
1141/**
1142 * disable_local_APIC - clear and disable the local APIC
1143 */
1144void disable_local_APIC(void)
1145{
1146 unsigned int value;
1147
1148 /* APIC hasn't been mapped yet */
1149 if (!x2apic_mode && !apic_phys)
1150 return;
1151
1152 clear_local_APIC();
1153
1154 /*
1155 * Disable APIC (implies clearing of registers
1156 * for 82489DX!).
1157 */
1158 value = apic_read(APIC_SPIV);
1159 value &= ~APIC_SPIV_APIC_ENABLED;
1160 apic_write(APIC_SPIV, value);
1161
1162#ifdef CONFIG_X86_32
1163 /*
1164 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1165 * restore the disabled state.
1166 */
1167 if (enabled_via_apicbase) {
1168 unsigned int l, h;
1169
1170 rdmsr(MSR_IA32_APICBASE, l, h);
1171 l &= ~MSR_IA32_APICBASE_ENABLE;
1172 wrmsr(MSR_IA32_APICBASE, l, h);
1173 }
1174#endif
1175}
1176
1177/*
1178 * If Linux enabled the LAPIC against the BIOS default disable it down before
1179 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1180 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1181 * for the case where Linux didn't enable the LAPIC.
1182 */
1183void lapic_shutdown(void)
1184{
1185 unsigned long flags;
1186
1187 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1188 return;
1189
1190 local_irq_save(flags);
1191
1192#ifdef CONFIG_X86_32
1193 if (!enabled_via_apicbase)
1194 clear_local_APIC();
1195 else
1196#endif
1197 disable_local_APIC();
1198
1199
1200 local_irq_restore(flags);
1201}
1202
1203/**
1204 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1205 */
1206void __init sync_Arb_IDs(void)
1207{
1208 /*
1209 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1210 * needed on AMD.
1211 */
1212 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1213 return;
1214
1215 /*
1216 * Wait for idle.
1217 */
1218 apic_wait_icr_idle();
1219
1220 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1221 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1222 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1223}
1224
1225enum apic_intr_mode_id apic_intr_mode;
1226
1227static int __init apic_intr_mode_select(void)
1228{
1229 /* Check kernel option */
1230 if (disable_apic) {
1231 pr_info("APIC disabled via kernel command line\n");
1232 return APIC_PIC;
1233 }
1234
1235 /* Check BIOS */
1236#ifdef CONFIG_X86_64
1237 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1238 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1239 disable_apic = 1;
1240 pr_info("APIC disabled by BIOS\n");
1241 return APIC_PIC;
1242 }
1243#else
1244 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1245
1246 /* Neither 82489DX nor integrated APIC ? */
1247 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1248 disable_apic = 1;
1249 return APIC_PIC;
1250 }
1251
1252 /* If the BIOS pretends there is an integrated APIC ? */
1253 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1254 APIC_INTEGRATED(boot_cpu_apic_version)) {
1255 disable_apic = 1;
1256 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1257 boot_cpu_physical_apicid);
1258 return APIC_PIC;
1259 }
1260#endif
1261
1262 /* Check MP table or ACPI MADT configuration */
1263 if (!smp_found_config) {
1264 disable_ioapic_support();
1265 if (!acpi_lapic) {
1266 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1267 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1268 }
1269 return APIC_VIRTUAL_WIRE;
1270 }
1271
1272#ifdef CONFIG_SMP
1273 /* If SMP should be disabled, then really disable it! */
1274 if (!setup_max_cpus) {
1275 pr_info("APIC: SMP mode deactivated\n");
1276 return APIC_SYMMETRIC_IO_NO_ROUTING;
1277 }
1278
1279 if (read_apic_id() != boot_cpu_physical_apicid) {
1280 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1281 read_apic_id(), boot_cpu_physical_apicid);
1282 /* Or can we switch back to PIC here? */
1283 }
1284#endif
1285
1286 return APIC_SYMMETRIC_IO;
1287}
1288
1289/*
1290 * An initial setup of the virtual wire mode.
1291 */
1292void __init init_bsp_APIC(void)
1293{
1294 unsigned int value;
1295
1296 /*
1297 * Don't do the setup now if we have a SMP BIOS as the
1298 * through-I/O-APIC virtual wire mode might be active.
1299 */
1300 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1301 return;
1302
1303 /*
1304 * Do not trust the local APIC being empty at bootup.
1305 */
1306 clear_local_APIC();
1307
1308 /*
1309 * Enable APIC.
1310 */
1311 value = apic_read(APIC_SPIV);
1312 value &= ~APIC_VECTOR_MASK;
1313 value |= APIC_SPIV_APIC_ENABLED;
1314
1315#ifdef CONFIG_X86_32
1316 /* This bit is reserved on P4/Xeon and should be cleared */
1317 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1318 (boot_cpu_data.x86 == 15))
1319 value &= ~APIC_SPIV_FOCUS_DISABLED;
1320 else
1321#endif
1322 value |= APIC_SPIV_FOCUS_DISABLED;
1323 value |= SPURIOUS_APIC_VECTOR;
1324 apic_write(APIC_SPIV, value);
1325
1326 /*
1327 * Set up the virtual wire mode.
1328 */
1329 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1330 value = APIC_DM_NMI;
1331 if (!lapic_is_integrated()) /* 82489DX */
1332 value |= APIC_LVT_LEVEL_TRIGGER;
1333 if (apic_extnmi == APIC_EXTNMI_NONE)
1334 value |= APIC_LVT_MASKED;
1335 apic_write(APIC_LVT1, value);
1336}
1337
1338/* Init the interrupt delivery mode for the BSP */
1339void __init apic_intr_mode_init(void)
1340{
1341 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1342
1343 apic_intr_mode = apic_intr_mode_select();
1344
1345 switch (apic_intr_mode) {
1346 case APIC_PIC:
1347 pr_info("APIC: Keep in PIC mode(8259)\n");
1348 return;
1349 case APIC_VIRTUAL_WIRE:
1350 pr_info("APIC: Switch to virtual wire mode setup\n");
1351 default_setup_apic_routing();
1352 break;
1353 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1354 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1355 upmode = true;
1356 default_setup_apic_routing();
1357 break;
1358 case APIC_SYMMETRIC_IO:
1359 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1360 default_setup_apic_routing();
1361 break;
1362 case APIC_SYMMETRIC_IO_NO_ROUTING:
1363 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1364 break;
1365 }
1366
1367 apic_bsp_setup(upmode);
1368}
1369
1370static void lapic_setup_esr(void)
1371{
1372 unsigned int oldvalue, value, maxlvt;
1373
1374 if (!lapic_is_integrated()) {
1375 pr_info("No ESR for 82489DX.\n");
1376 return;
1377 }
1378
1379 if (apic->disable_esr) {
1380 /*
1381 * Something untraceable is creating bad interrupts on
1382 * secondary quads ... for the moment, just leave the
1383 * ESR disabled - we can't do anything useful with the
1384 * errors anyway - mbligh
1385 */
1386 pr_info("Leaving ESR disabled.\n");
1387 return;
1388 }
1389
1390 maxlvt = lapic_get_maxlvt();
1391 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1392 apic_write(APIC_ESR, 0);
1393 oldvalue = apic_read(APIC_ESR);
1394
1395 /* enables sending errors */
1396 value = ERROR_APIC_VECTOR;
1397 apic_write(APIC_LVTERR, value);
1398
1399 /*
1400 * spec says clear errors after enabling vector.
1401 */
1402 if (maxlvt > 3)
1403 apic_write(APIC_ESR, 0);
1404 value = apic_read(APIC_ESR);
1405 if (value != oldvalue)
1406 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1407 "vector: 0x%08x after: 0x%08x\n",
1408 oldvalue, value);
1409}
1410
1411static void apic_pending_intr_clear(void)
1412{
1413 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1414 unsigned long long tsc = 0, ntsc;
1415 unsigned int queued;
1416 unsigned long value;
1417 int i, j, acked = 0;
1418
1419 if (boot_cpu_has(X86_FEATURE_TSC))
1420 tsc = rdtsc();
1421 /*
1422 * After a crash, we no longer service the interrupts and a pending
1423 * interrupt from previous kernel might still have ISR bit set.
1424 *
1425 * Most probably by now CPU has serviced that pending interrupt and
1426 * it might not have done the ack_APIC_irq() because it thought,
1427 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1428 * does not clear the ISR bit and cpu thinks it has already serivced
1429 * the interrupt. Hence a vector might get locked. It was noticed
1430 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1431 */
1432 do {
1433 queued = 0;
1434 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1435 queued |= apic_read(APIC_IRR + i*0x10);
1436
1437 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1438 value = apic_read(APIC_ISR + i*0x10);
1439 for_each_set_bit(j, &value, 32) {
1440 ack_APIC_irq();
1441 acked++;
1442 }
1443 }
1444 if (acked > 256) {
1445 pr_err("LAPIC pending interrupts after %d EOI\n", acked);
1446 break;
1447 }
1448 if (queued) {
1449 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1450 ntsc = rdtsc();
1451 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1452 } else {
1453 max_loops--;
1454 }
1455 }
1456 } while (queued && max_loops > 0);
1457 WARN_ON(max_loops <= 0);
1458}
1459
1460/**
1461 * setup_local_APIC - setup the local APIC
1462 *
1463 * Used to setup local APIC while initializing BSP or bringing up APs.
1464 * Always called with preemption disabled.
1465 */
1466static void setup_local_APIC(void)
1467{
1468 int cpu = smp_processor_id();
1469 unsigned int value;
1470#ifdef CONFIG_X86_32
1471 int logical_apicid, ldr_apicid;
1472#endif
1473
1474
1475 if (disable_apic) {
1476 disable_ioapic_support();
1477 return;
1478 }
1479
1480#ifdef CONFIG_X86_32
1481 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1482 if (lapic_is_integrated() && apic->disable_esr) {
1483 apic_write(APIC_ESR, 0);
1484 apic_write(APIC_ESR, 0);
1485 apic_write(APIC_ESR, 0);
1486 apic_write(APIC_ESR, 0);
1487 }
1488#endif
1489 perf_events_lapic_init();
1490
1491 /*
1492 * Double-check whether this APIC is really registered.
1493 * This is meaningless in clustered apic mode, so we skip it.
1494 */
1495 BUG_ON(!apic->apic_id_registered());
1496
1497 /*
1498 * Intel recommends to set DFR, LDR and TPR before enabling
1499 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1500 * document number 292116). So here it goes...
1501 */
1502 apic->init_apic_ldr();
1503
1504#ifdef CONFIG_X86_32
1505 /*
1506 * APIC LDR is initialized. If logical_apicid mapping was
1507 * initialized during get_smp_config(), make sure it matches the
1508 * actual value.
1509 */
1510 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1511 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1512 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1513 /* always use the value from LDR */
1514 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1515#endif
1516
1517 /*
1518 * Set Task Priority to 'accept all'. We never change this
1519 * later on.
1520 */
1521 value = apic_read(APIC_TASKPRI);
1522 value &= ~APIC_TPRI_MASK;
1523 apic_write(APIC_TASKPRI, value);
1524
1525 apic_pending_intr_clear();
1526
1527 /*
1528 * Now that we are all set up, enable the APIC
1529 */
1530 value = apic_read(APIC_SPIV);
1531 value &= ~APIC_VECTOR_MASK;
1532 /*
1533 * Enable APIC
1534 */
1535 value |= APIC_SPIV_APIC_ENABLED;
1536
1537#ifdef CONFIG_X86_32
1538 /*
1539 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1540 * certain networking cards. If high frequency interrupts are
1541 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1542 * entry is masked/unmasked at a high rate as well then sooner or
1543 * later IOAPIC line gets 'stuck', no more interrupts are received
1544 * from the device. If focus CPU is disabled then the hang goes
1545 * away, oh well :-(
1546 *
1547 * [ This bug can be reproduced easily with a level-triggered
1548 * PCI Ne2000 networking cards and PII/PIII processors, dual
1549 * BX chipset. ]
1550 */
1551 /*
1552 * Actually disabling the focus CPU check just makes the hang less
1553 * frequent as it makes the interrupt distributon model be more
1554 * like LRU than MRU (the short-term load is more even across CPUs).
1555 */
1556
1557 /*
1558 * - enable focus processor (bit==0)
1559 * - 64bit mode always use processor focus
1560 * so no need to set it
1561 */
1562 value &= ~APIC_SPIV_FOCUS_DISABLED;
1563#endif
1564
1565 /*
1566 * Set spurious IRQ vector
1567 */
1568 value |= SPURIOUS_APIC_VECTOR;
1569 apic_write(APIC_SPIV, value);
1570
1571 /*
1572 * Set up LVT0, LVT1:
1573 *
1574 * set up through-local-APIC on the boot CPU's LINT0. This is not
1575 * strictly necessary in pure symmetric-IO mode, but sometimes
1576 * we delegate interrupts to the 8259A.
1577 */
1578 /*
1579 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1580 */
1581 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1582 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1583 value = APIC_DM_EXTINT;
1584 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1585 } else {
1586 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1587 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1588 }
1589 apic_write(APIC_LVT0, value);
1590
1591 /*
1592 * Only the BSP sees the LINT1 NMI signal by default. This can be
1593 * modified by apic_extnmi= boot option.
1594 */
1595 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1596 apic_extnmi == APIC_EXTNMI_ALL)
1597 value = APIC_DM_NMI;
1598 else
1599 value = APIC_DM_NMI | APIC_LVT_MASKED;
1600
1601 /* Is 82489DX ? */
1602 if (!lapic_is_integrated())
1603 value |= APIC_LVT_LEVEL_TRIGGER;
1604 apic_write(APIC_LVT1, value);
1605
1606#ifdef CONFIG_X86_MCE_INTEL
1607 /* Recheck CMCI information after local APIC is up on CPU #0 */
1608 if (!cpu)
1609 cmci_recheck();
1610#endif
1611}
1612
1613static void end_local_APIC_setup(void)
1614{
1615 lapic_setup_esr();
1616
1617#ifdef CONFIG_X86_32
1618 {
1619 unsigned int value;
1620 /* Disable the local apic timer */
1621 value = apic_read(APIC_LVTT);
1622 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1623 apic_write(APIC_LVTT, value);
1624 }
1625#endif
1626
1627 apic_pm_activate();
1628}
1629
1630/*
1631 * APIC setup function for application processors. Called from smpboot.c
1632 */
1633void apic_ap_setup(void)
1634{
1635 setup_local_APIC();
1636 end_local_APIC_setup();
1637}
1638
1639#ifdef CONFIG_X86_X2APIC
1640int x2apic_mode;
1641
1642enum {
1643 X2APIC_OFF,
1644 X2APIC_ON,
1645 X2APIC_DISABLED,
1646};
1647static int x2apic_state;
1648
1649static void __x2apic_disable(void)
1650{
1651 u64 msr;
1652
1653 if (!boot_cpu_has(X86_FEATURE_APIC))
1654 return;
1655
1656 rdmsrl(MSR_IA32_APICBASE, msr);
1657 if (!(msr & X2APIC_ENABLE))
1658 return;
1659 /* Disable xapic and x2apic first and then reenable xapic mode */
1660 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1661 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1662 printk_once(KERN_INFO "x2apic disabled\n");
1663}
1664
1665static void __x2apic_enable(void)
1666{
1667 u64 msr;
1668
1669 rdmsrl(MSR_IA32_APICBASE, msr);
1670 if (msr & X2APIC_ENABLE)
1671 return;
1672 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1673 printk_once(KERN_INFO "x2apic enabled\n");
1674}
1675
1676static int __init setup_nox2apic(char *str)
1677{
1678 if (x2apic_enabled()) {
1679 int apicid = native_apic_msr_read(APIC_ID);
1680
1681 if (apicid >= 255) {
1682 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1683 apicid);
1684 return 0;
1685 }
1686 pr_warning("x2apic already enabled.\n");
1687 __x2apic_disable();
1688 }
1689 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1690 x2apic_state = X2APIC_DISABLED;
1691 x2apic_mode = 0;
1692 return 0;
1693}
1694early_param("nox2apic", setup_nox2apic);
1695
1696/* Called from cpu_init() to enable x2apic on (secondary) cpus */
1697void x2apic_setup(void)
1698{
1699 /*
1700 * If x2apic is not in ON state, disable it if already enabled
1701 * from BIOS.
1702 */
1703 if (x2apic_state != X2APIC_ON) {
1704 __x2apic_disable();
1705 return;
1706 }
1707 __x2apic_enable();
1708}
1709
1710static __init void x2apic_disable(void)
1711{
1712 u32 x2apic_id, state = x2apic_state;
1713
1714 x2apic_mode = 0;
1715 x2apic_state = X2APIC_DISABLED;
1716
1717 if (state != X2APIC_ON)
1718 return;
1719
1720 x2apic_id = read_apic_id();
1721 if (x2apic_id >= 255)
1722 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1723
1724 __x2apic_disable();
1725 register_lapic_address(mp_lapic_addr);
1726}
1727
1728static __init void x2apic_enable(void)
1729{
1730 if (x2apic_state != X2APIC_OFF)
1731 return;
1732
1733 x2apic_mode = 1;
1734 x2apic_state = X2APIC_ON;
1735 __x2apic_enable();
1736}
1737
1738static __init void try_to_enable_x2apic(int remap_mode)
1739{
1740 if (x2apic_state == X2APIC_DISABLED)
1741 return;
1742
1743 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1744 /* IR is required if there is APIC ID > 255 even when running
1745 * under KVM
1746 */
1747 if (max_physical_apicid > 255 ||
1748 !x86_init.hyper.x2apic_available()) {
1749 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1750 x2apic_disable();
1751 return;
1752 }
1753
1754 /*
1755 * without IR all CPUs can be addressed by IOAPIC/MSI
1756 * only in physical mode
1757 */
1758 x2apic_phys = 1;
1759 }
1760 x2apic_enable();
1761}
1762
1763void __init check_x2apic(void)
1764{
1765 if (x2apic_enabled()) {
1766 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1767 x2apic_mode = 1;
1768 x2apic_state = X2APIC_ON;
1769 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1770 x2apic_state = X2APIC_DISABLED;
1771 }
1772}
1773#else /* CONFIG_X86_X2APIC */
1774static int __init validate_x2apic(void)
1775{
1776 if (!apic_is_x2apic_enabled())
1777 return 0;
1778 /*
1779 * Checkme: Can we simply turn off x2apic here instead of panic?
1780 */
1781 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1782}
1783early_initcall(validate_x2apic);
1784
1785static inline void try_to_enable_x2apic(int remap_mode) { }
1786static inline void __x2apic_enable(void) { }
1787#endif /* !CONFIG_X86_X2APIC */
1788
1789void __init enable_IR_x2apic(void)
1790{
1791 unsigned long flags;
1792 int ret, ir_stat;
1793
1794 if (skip_ioapic_setup) {
1795 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1796 return;
1797 }
1798
1799 ir_stat = irq_remapping_prepare();
1800 if (ir_stat < 0 && !x2apic_supported())
1801 return;
1802
1803 ret = save_ioapic_entries();
1804 if (ret) {
1805 pr_info("Saving IO-APIC state failed: %d\n", ret);
1806 return;
1807 }
1808
1809 local_irq_save(flags);
1810 legacy_pic->mask_all();
1811 mask_ioapic_entries();
1812
1813 /* If irq_remapping_prepare() succeeded, try to enable it */
1814 if (ir_stat >= 0)
1815 ir_stat = irq_remapping_enable();
1816 /* ir_stat contains the remap mode or an error code */
1817 try_to_enable_x2apic(ir_stat);
1818
1819 if (ir_stat < 0)
1820 restore_ioapic_entries();
1821 legacy_pic->restore_mask();
1822 local_irq_restore(flags);
1823}
1824
1825#ifdef CONFIG_X86_64
1826/*
1827 * Detect and enable local APICs on non-SMP boards.
1828 * Original code written by Keir Fraser.
1829 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1830 * not correctly set up (usually the APIC timer won't work etc.)
1831 */
1832static int __init detect_init_APIC(void)
1833{
1834 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1835 pr_info("No local APIC present\n");
1836 return -1;
1837 }
1838
1839 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1840 return 0;
1841}
1842#else
1843
1844static int __init apic_verify(void)
1845{
1846 u32 features, h, l;
1847
1848 /*
1849 * The APIC feature bit should now be enabled
1850 * in `cpuid'
1851 */
1852 features = cpuid_edx(1);
1853 if (!(features & (1 << X86_FEATURE_APIC))) {
1854 pr_warning("Could not enable APIC!\n");
1855 return -1;
1856 }
1857 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1858 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1859
1860 /* The BIOS may have set up the APIC at some other address */
1861 if (boot_cpu_data.x86 >= 6) {
1862 rdmsr(MSR_IA32_APICBASE, l, h);
1863 if (l & MSR_IA32_APICBASE_ENABLE)
1864 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1865 }
1866
1867 pr_info("Found and enabled local APIC!\n");
1868 return 0;
1869}
1870
1871int __init apic_force_enable(unsigned long addr)
1872{
1873 u32 h, l;
1874
1875 if (disable_apic)
1876 return -1;
1877
1878 /*
1879 * Some BIOSes disable the local APIC in the APIC_BASE
1880 * MSR. This can only be done in software for Intel P6 or later
1881 * and AMD K7 (Model > 1) or later.
1882 */
1883 if (boot_cpu_data.x86 >= 6) {
1884 rdmsr(MSR_IA32_APICBASE, l, h);
1885 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1886 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1887 l &= ~MSR_IA32_APICBASE_BASE;
1888 l |= MSR_IA32_APICBASE_ENABLE | addr;
1889 wrmsr(MSR_IA32_APICBASE, l, h);
1890 enabled_via_apicbase = 1;
1891 }
1892 }
1893 return apic_verify();
1894}
1895
1896/*
1897 * Detect and initialize APIC
1898 */
1899static int __init detect_init_APIC(void)
1900{
1901 /* Disabled by kernel option? */
1902 if (disable_apic)
1903 return -1;
1904
1905 switch (boot_cpu_data.x86_vendor) {
1906 case X86_VENDOR_AMD:
1907 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1908 (boot_cpu_data.x86 >= 15))
1909 break;
1910 goto no_apic;
1911 case X86_VENDOR_INTEL:
1912 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1913 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1914 break;
1915 goto no_apic;
1916 default:
1917 goto no_apic;
1918 }
1919
1920 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1921 /*
1922 * Over-ride BIOS and try to enable the local APIC only if
1923 * "lapic" specified.
1924 */
1925 if (!force_enable_local_apic) {
1926 pr_info("Local APIC disabled by BIOS -- "
1927 "you can enable it with \"lapic\"\n");
1928 return -1;
1929 }
1930 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1931 return -1;
1932 } else {
1933 if (apic_verify())
1934 return -1;
1935 }
1936
1937 apic_pm_activate();
1938
1939 return 0;
1940
1941no_apic:
1942 pr_info("No local APIC present or hardware disabled\n");
1943 return -1;
1944}
1945#endif
1946
1947/**
1948 * init_apic_mappings - initialize APIC mappings
1949 */
1950void __init init_apic_mappings(void)
1951{
1952 unsigned int new_apicid;
1953
1954 apic_check_deadline_errata();
1955
1956 if (x2apic_mode) {
1957 boot_cpu_physical_apicid = read_apic_id();
1958 return;
1959 }
1960
1961 /* If no local APIC can be found return early */
1962 if (!smp_found_config && detect_init_APIC()) {
1963 /* lets NOP'ify apic operations */
1964 pr_info("APIC: disable apic facility\n");
1965 apic_disable();
1966 } else {
1967 apic_phys = mp_lapic_addr;
1968
1969 /*
1970 * If the system has ACPI MADT tables or MP info, the LAPIC
1971 * address is already registered.
1972 */
1973 if (!acpi_lapic && !smp_found_config)
1974 register_lapic_address(apic_phys);
1975 }
1976
1977 /*
1978 * Fetch the APIC ID of the BSP in case we have a
1979 * default configuration (or the MP table is broken).
1980 */
1981 new_apicid = read_apic_id();
1982 if (boot_cpu_physical_apicid != new_apicid) {
1983 boot_cpu_physical_apicid = new_apicid;
1984 /*
1985 * yeah -- we lie about apic_version
1986 * in case if apic was disabled via boot option
1987 * but it's not a problem for SMP compiled kernel
1988 * since apic_intr_mode_select is prepared for such
1989 * a case and disable smp mode
1990 */
1991 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1992 }
1993}
1994
1995void __init register_lapic_address(unsigned long address)
1996{
1997 mp_lapic_addr = address;
1998
1999 if (!x2apic_mode) {
2000 set_fixmap_nocache(FIX_APIC_BASE, address);
2001 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2002 APIC_BASE, address);
2003 }
2004 if (boot_cpu_physical_apicid == -1U) {
2005 boot_cpu_physical_apicid = read_apic_id();
2006 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2007 }
2008}
2009
2010/*
2011 * Local APIC interrupts
2012 */
2013
2014/*
2015 * This interrupt should _never_ happen with our APIC/SMP architecture
2016 */
2017__visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2018{
2019 u8 vector = ~regs->orig_ax;
2020 u32 v;
2021
2022 entering_irq();
2023 trace_spurious_apic_entry(vector);
2024
2025 /*
2026 * Check if this really is a spurious interrupt and ACK it
2027 * if it is a vectored one. Just in case...
2028 * Spurious interrupts should not be ACKed.
2029 */
2030 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2031 if (v & (1 << (vector & 0x1f)))
2032 ack_APIC_irq();
2033
2034 inc_irq_stat(irq_spurious_count);
2035
2036 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
2037 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
2038 "should never happen.\n", vector, smp_processor_id());
2039
2040 trace_spurious_apic_exit(vector);
2041 exiting_irq();
2042}
2043
2044/*
2045 * This interrupt should never happen with our APIC/SMP architecture
2046 */
2047__visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2048{
2049 static const char * const error_interrupt_reason[] = {
2050 "Send CS error", /* APIC Error Bit 0 */
2051 "Receive CS error", /* APIC Error Bit 1 */
2052 "Send accept error", /* APIC Error Bit 2 */
2053 "Receive accept error", /* APIC Error Bit 3 */
2054 "Redirectable IPI", /* APIC Error Bit 4 */
2055 "Send illegal vector", /* APIC Error Bit 5 */
2056 "Received illegal vector", /* APIC Error Bit 6 */
2057 "Illegal register address", /* APIC Error Bit 7 */
2058 };
2059 u32 v, i = 0;
2060
2061 entering_irq();
2062 trace_error_apic_entry(ERROR_APIC_VECTOR);
2063
2064 /* First tickle the hardware, only then report what went on. -- REW */
2065 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2066 apic_write(APIC_ESR, 0);
2067 v = apic_read(APIC_ESR);
2068 ack_APIC_irq();
2069 atomic_inc(&irq_err_count);
2070
2071 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2072 smp_processor_id(), v);
2073
2074 v &= 0xff;
2075 while (v) {
2076 if (v & 0x1)
2077 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2078 i++;
2079 v >>= 1;
2080 }
2081
2082 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2083
2084 trace_error_apic_exit(ERROR_APIC_VECTOR);
2085 exiting_irq();
2086}
2087
2088/**
2089 * connect_bsp_APIC - attach the APIC to the interrupt system
2090 */
2091static void __init connect_bsp_APIC(void)
2092{
2093#ifdef CONFIG_X86_32
2094 if (pic_mode) {
2095 /*
2096 * Do not trust the local APIC being empty at bootup.
2097 */
2098 clear_local_APIC();
2099 /*
2100 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2101 * local APIC to INT and NMI lines.
2102 */
2103 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2104 "enabling APIC mode.\n");
2105 imcr_pic_to_apic();
2106 }
2107#endif
2108}
2109
2110/**
2111 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2112 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2113 *
2114 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2115 * APIC is disabled.
2116 */
2117void disconnect_bsp_APIC(int virt_wire_setup)
2118{
2119 unsigned int value;
2120
2121#ifdef CONFIG_X86_32
2122 if (pic_mode) {
2123 /*
2124 * Put the board back into PIC mode (has an effect only on
2125 * certain older boards). Note that APIC interrupts, including
2126 * IPIs, won't work beyond this point! The only exception are
2127 * INIT IPIs.
2128 */
2129 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2130 "entering PIC mode.\n");
2131 imcr_apic_to_pic();
2132 return;
2133 }
2134#endif
2135
2136 /* Go back to Virtual Wire compatibility mode */
2137
2138 /* For the spurious interrupt use vector F, and enable it */
2139 value = apic_read(APIC_SPIV);
2140 value &= ~APIC_VECTOR_MASK;
2141 value |= APIC_SPIV_APIC_ENABLED;
2142 value |= 0xf;
2143 apic_write(APIC_SPIV, value);
2144
2145 if (!virt_wire_setup) {
2146 /*
2147 * For LVT0 make it edge triggered, active high,
2148 * external and enabled
2149 */
2150 value = apic_read(APIC_LVT0);
2151 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2152 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2153 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2154 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2155 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2156 apic_write(APIC_LVT0, value);
2157 } else {
2158 /* Disable LVT0 */
2159 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2160 }
2161
2162 /*
2163 * For LVT1 make it edge triggered, active high,
2164 * nmi and enabled
2165 */
2166 value = apic_read(APIC_LVT1);
2167 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2168 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2169 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2170 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2171 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2172 apic_write(APIC_LVT1, value);
2173}
2174
2175/*
2176 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2177 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2178 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2179 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2180 *
2181 * NOTE: Reserve 0 for BSP.
2182 */
2183static int nr_logical_cpuids = 1;
2184
2185/*
2186 * Used to store mapping between logical CPU IDs and APIC IDs.
2187 */
2188static int cpuid_to_apicid[] = {
2189 [0 ... NR_CPUS - 1] = -1,
2190};
2191
2192/*
2193 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2194 * and cpuid_to_apicid[] synchronized.
2195 */
2196static int allocate_logical_cpuid(int apicid)
2197{
2198 int i;
2199
2200 /*
2201 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2202 * check if the kernel has allocated a cpuid for it.
2203 */
2204 for (i = 0; i < nr_logical_cpuids; i++) {
2205 if (cpuid_to_apicid[i] == apicid)
2206 return i;
2207 }
2208
2209 /* Allocate a new cpuid. */
2210 if (nr_logical_cpuids >= nr_cpu_ids) {
2211 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2212 "Processor %d/0x%x and the rest are ignored.\n",
2213 nr_cpu_ids, nr_logical_cpuids, apicid);
2214 return -EINVAL;
2215 }
2216
2217 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2218 return nr_logical_cpuids++;
2219}
2220
2221int generic_processor_info(int apicid, int version)
2222{
2223 int cpu, max = nr_cpu_ids;
2224 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2225 phys_cpu_present_map);
2226
2227 /*
2228 * boot_cpu_physical_apicid is designed to have the apicid
2229 * returned by read_apic_id(), i.e, the apicid of the
2230 * currently booting-up processor. However, on some platforms,
2231 * it is temporarily modified by the apicid reported as BSP
2232 * through MP table. Concretely:
2233 *
2234 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2235 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2236 *
2237 * This function is executed with the modified
2238 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2239 * parameter doesn't work to disable APs on kdump 2nd kernel.
2240 *
2241 * Since fixing handling of boot_cpu_physical_apicid requires
2242 * another discussion and tests on each platform, we leave it
2243 * for now and here we use read_apic_id() directly in this
2244 * function, generic_processor_info().
2245 */
2246 if (disabled_cpu_apicid != BAD_APICID &&
2247 disabled_cpu_apicid != read_apic_id() &&
2248 disabled_cpu_apicid == apicid) {
2249 int thiscpu = num_processors + disabled_cpus;
2250
2251 pr_warning("APIC: Disabling requested cpu."
2252 " Processor %d/0x%x ignored.\n",
2253 thiscpu, apicid);
2254
2255 disabled_cpus++;
2256 return -ENODEV;
2257 }
2258
2259 /*
2260 * If boot cpu has not been detected yet, then only allow upto
2261 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2262 */
2263 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2264 apicid != boot_cpu_physical_apicid) {
2265 int thiscpu = max + disabled_cpus - 1;
2266
2267 pr_warning(
2268 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2269 " reached. Keeping one slot for boot cpu."
2270 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2271
2272 disabled_cpus++;
2273 return -ENODEV;
2274 }
2275
2276 if (num_processors >= nr_cpu_ids) {
2277 int thiscpu = max + disabled_cpus;
2278
2279 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2280 "reached. Processor %d/0x%x ignored.\n",
2281 max, thiscpu, apicid);
2282
2283 disabled_cpus++;
2284 return -EINVAL;
2285 }
2286
2287 if (apicid == boot_cpu_physical_apicid) {
2288 /*
2289 * x86_bios_cpu_apicid is required to have processors listed
2290 * in same order as logical cpu numbers. Hence the first
2291 * entry is BSP, and so on.
2292 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2293 * for BSP.
2294 */
2295 cpu = 0;
2296
2297 /* Logical cpuid 0 is reserved for BSP. */
2298 cpuid_to_apicid[0] = apicid;
2299 } else {
2300 cpu = allocate_logical_cpuid(apicid);
2301 if (cpu < 0) {
2302 disabled_cpus++;
2303 return -EINVAL;
2304 }
2305 }
2306
2307 /*
2308 * Validate version
2309 */
2310 if (version == 0x0) {
2311 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2312 cpu, apicid);
2313 version = 0x10;
2314 }
2315
2316 if (version != boot_cpu_apic_version) {
2317 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2318 boot_cpu_apic_version, cpu, version);
2319 }
2320
2321 if (apicid > max_physical_apicid)
2322 max_physical_apicid = apicid;
2323
2324#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2325 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2326 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2327#endif
2328#ifdef CONFIG_X86_32
2329 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2330 apic->x86_32_early_logical_apicid(cpu);
2331#endif
2332 set_cpu_possible(cpu, true);
2333 physid_set(apicid, phys_cpu_present_map);
2334 set_cpu_present(cpu, true);
2335 num_processors++;
2336
2337 return cpu;
2338}
2339
2340int hard_smp_processor_id(void)
2341{
2342 return read_apic_id();
2343}
2344
2345/*
2346 * Override the generic EOI implementation with an optimized version.
2347 * Only called during early boot when only one CPU is active and with
2348 * interrupts disabled, so we know this does not race with actual APIC driver
2349 * use.
2350 */
2351void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2352{
2353 struct apic **drv;
2354
2355 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2356 /* Should happen once for each apic */
2357 WARN_ON((*drv)->eoi_write == eoi_write);
2358 (*drv)->native_eoi_write = (*drv)->eoi_write;
2359 (*drv)->eoi_write = eoi_write;
2360 }
2361}
2362
2363static void __init apic_bsp_up_setup(void)
2364{
2365#ifdef CONFIG_X86_64
2366 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2367#else
2368 /*
2369 * Hack: In case of kdump, after a crash, kernel might be booting
2370 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2371 * might be zero if read from MP tables. Get it from LAPIC.
2372 */
2373# ifdef CONFIG_CRASH_DUMP
2374 boot_cpu_physical_apicid = read_apic_id();
2375# endif
2376#endif
2377 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2378}
2379
2380/**
2381 * apic_bsp_setup - Setup function for local apic and io-apic
2382 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2383 *
2384 * Returns:
2385 * apic_id of BSP APIC
2386 */
2387void __init apic_bsp_setup(bool upmode)
2388{
2389 connect_bsp_APIC();
2390 if (upmode)
2391 apic_bsp_up_setup();
2392 setup_local_APIC();
2393
2394 enable_IO_APIC();
2395 end_local_APIC_setup();
2396 irq_remap_enable_fault_handling();
2397 setup_IO_APIC();
2398}
2399
2400#ifdef CONFIG_UP_LATE_INIT
2401void __init up_late_init(void)
2402{
2403 if (apic_intr_mode == APIC_PIC)
2404 return;
2405
2406 /* Setup local timer */
2407 x86_init.timers.setup_percpu_clockev();
2408}
2409#endif
2410
2411/*
2412 * Power management
2413 */
2414#ifdef CONFIG_PM
2415
2416static struct {
2417 /*
2418 * 'active' is true if the local APIC was enabled by us and
2419 * not the BIOS; this signifies that we are also responsible
2420 * for disabling it before entering apm/acpi suspend
2421 */
2422 int active;
2423 /* r/w apic fields */
2424 unsigned int apic_id;
2425 unsigned int apic_taskpri;
2426 unsigned int apic_ldr;
2427 unsigned int apic_dfr;
2428 unsigned int apic_spiv;
2429 unsigned int apic_lvtt;
2430 unsigned int apic_lvtpc;
2431 unsigned int apic_lvt0;
2432 unsigned int apic_lvt1;
2433 unsigned int apic_lvterr;
2434 unsigned int apic_tmict;
2435 unsigned int apic_tdcr;
2436 unsigned int apic_thmr;
2437 unsigned int apic_cmci;
2438} apic_pm_state;
2439
2440static int lapic_suspend(void)
2441{
2442 unsigned long flags;
2443 int maxlvt;
2444
2445 if (!apic_pm_state.active)
2446 return 0;
2447
2448 maxlvt = lapic_get_maxlvt();
2449
2450 apic_pm_state.apic_id = apic_read(APIC_ID);
2451 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2452 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2453 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2454 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2455 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2456 if (maxlvt >= 4)
2457 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2458 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2459 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2460 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2461 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2462 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2463#ifdef CONFIG_X86_THERMAL_VECTOR
2464 if (maxlvt >= 5)
2465 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2466#endif
2467#ifdef CONFIG_X86_MCE_INTEL
2468 if (maxlvt >= 6)
2469 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2470#endif
2471
2472 local_irq_save(flags);
2473 disable_local_APIC();
2474
2475 irq_remapping_disable();
2476
2477 local_irq_restore(flags);
2478 return 0;
2479}
2480
2481static void lapic_resume(void)
2482{
2483 unsigned int l, h;
2484 unsigned long flags;
2485 int maxlvt;
2486
2487 if (!apic_pm_state.active)
2488 return;
2489
2490 local_irq_save(flags);
2491
2492 /*
2493 * IO-APIC and PIC have their own resume routines.
2494 * We just mask them here to make sure the interrupt
2495 * subsystem is completely quiet while we enable x2apic
2496 * and interrupt-remapping.
2497 */
2498 mask_ioapic_entries();
2499 legacy_pic->mask_all();
2500
2501 if (x2apic_mode) {
2502 __x2apic_enable();
2503 } else {
2504 /*
2505 * Make sure the APICBASE points to the right address
2506 *
2507 * FIXME! This will be wrong if we ever support suspend on
2508 * SMP! We'll need to do this as part of the CPU restore!
2509 */
2510 if (boot_cpu_data.x86 >= 6) {
2511 rdmsr(MSR_IA32_APICBASE, l, h);
2512 l &= ~MSR_IA32_APICBASE_BASE;
2513 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2514 wrmsr(MSR_IA32_APICBASE, l, h);
2515 }
2516 }
2517
2518 maxlvt = lapic_get_maxlvt();
2519 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2520 apic_write(APIC_ID, apic_pm_state.apic_id);
2521 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2522 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2523 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2524 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2525 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2526 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2527#ifdef CONFIG_X86_THERMAL_VECTOR
2528 if (maxlvt >= 5)
2529 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2530#endif
2531#ifdef CONFIG_X86_MCE_INTEL
2532 if (maxlvt >= 6)
2533 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2534#endif
2535 if (maxlvt >= 4)
2536 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2537 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2538 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2539 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2540 apic_write(APIC_ESR, 0);
2541 apic_read(APIC_ESR);
2542 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2543 apic_write(APIC_ESR, 0);
2544 apic_read(APIC_ESR);
2545
2546 irq_remapping_reenable(x2apic_mode);
2547
2548 local_irq_restore(flags);
2549}
2550
2551/*
2552 * This device has no shutdown method - fully functioning local APICs
2553 * are needed on every CPU up until machine_halt/restart/poweroff.
2554 */
2555
2556static struct syscore_ops lapic_syscore_ops = {
2557 .resume = lapic_resume,
2558 .suspend = lapic_suspend,
2559};
2560
2561static void apic_pm_activate(void)
2562{
2563 apic_pm_state.active = 1;
2564}
2565
2566static int __init init_lapic_sysfs(void)
2567{
2568 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2569 if (boot_cpu_has(X86_FEATURE_APIC))
2570 register_syscore_ops(&lapic_syscore_ops);
2571
2572 return 0;
2573}
2574
2575/* local apic needs to resume before other devices access its registers. */
2576core_initcall(init_lapic_sysfs);
2577
2578#else /* CONFIG_PM */
2579
2580static void apic_pm_activate(void) { }
2581
2582#endif /* CONFIG_PM */
2583
2584#ifdef CONFIG_X86_64
2585
2586static int multi_checked;
2587static int multi;
2588
2589static int set_multi(const struct dmi_system_id *d)
2590{
2591 if (multi)
2592 return 0;
2593 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2594 multi = 1;
2595 return 0;
2596}
2597
2598static const struct dmi_system_id multi_dmi_table[] = {
2599 {
2600 .callback = set_multi,
2601 .ident = "IBM System Summit2",
2602 .matches = {
2603 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2604 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2605 },
2606 },
2607 {}
2608};
2609
2610static void dmi_check_multi(void)
2611{
2612 if (multi_checked)
2613 return;
2614
2615 dmi_check_system(multi_dmi_table);
2616 multi_checked = 1;
2617}
2618
2619/*
2620 * apic_is_clustered_box() -- Check if we can expect good TSC
2621 *
2622 * Thus far, the major user of this is IBM's Summit2 series:
2623 * Clustered boxes may have unsynced TSC problems if they are
2624 * multi-chassis.
2625 * Use DMI to check them
2626 */
2627int apic_is_clustered_box(void)
2628{
2629 dmi_check_multi();
2630 return multi;
2631}
2632#endif
2633
2634/*
2635 * APIC command line parameters
2636 */
2637static int __init setup_disableapic(char *arg)
2638{
2639 disable_apic = 1;
2640 setup_clear_cpu_cap(X86_FEATURE_APIC);
2641 return 0;
2642}
2643early_param("disableapic", setup_disableapic);
2644
2645/* same as disableapic, for compatibility */
2646static int __init setup_nolapic(char *arg)
2647{
2648 return setup_disableapic(arg);
2649}
2650early_param("nolapic", setup_nolapic);
2651
2652static int __init parse_lapic_timer_c2_ok(char *arg)
2653{
2654 local_apic_timer_c2_ok = 1;
2655 return 0;
2656}
2657early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2658
2659static int __init parse_disable_apic_timer(char *arg)
2660{
2661 disable_apic_timer = 1;
2662 return 0;
2663}
2664early_param("noapictimer", parse_disable_apic_timer);
2665
2666static int __init parse_nolapic_timer(char *arg)
2667{
2668 disable_apic_timer = 1;
2669 return 0;
2670}
2671early_param("nolapic_timer", parse_nolapic_timer);
2672
2673static int __init apic_set_verbosity(char *arg)
2674{
2675 if (!arg) {
2676#ifdef CONFIG_X86_64
2677 skip_ioapic_setup = 0;
2678 return 0;
2679#endif
2680 return -EINVAL;
2681 }
2682
2683 if (strcmp("debug", arg) == 0)
2684 apic_verbosity = APIC_DEBUG;
2685 else if (strcmp("verbose", arg) == 0)
2686 apic_verbosity = APIC_VERBOSE;
2687#ifdef CONFIG_X86_64
2688 else {
2689 pr_warning("APIC Verbosity level %s not recognised"
2690 " use apic=verbose or apic=debug\n", arg);
2691 return -EINVAL;
2692 }
2693#endif
2694
2695 return 0;
2696}
2697early_param("apic", apic_set_verbosity);
2698
2699static int __init lapic_insert_resource(void)
2700{
2701 if (!apic_phys)
2702 return -1;
2703
2704 /* Put local APIC into the resource map. */
2705 lapic_resource.start = apic_phys;
2706 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2707 insert_resource(&iomem_resource, &lapic_resource);
2708
2709 return 0;
2710}
2711
2712/*
2713 * need call insert after e820__reserve_resources()
2714 * that is using request_resource
2715 */
2716late_initcall(lapic_insert_resource);
2717
2718static int __init apic_set_disabled_cpu_apicid(char *arg)
2719{
2720 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2721 return -EINVAL;
2722
2723 return 0;
2724}
2725early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2726
2727static int __init apic_set_extnmi(char *arg)
2728{
2729 if (!arg)
2730 return -EINVAL;
2731
2732 if (!strncmp("all", arg, 3))
2733 apic_extnmi = APIC_EXTNMI_ALL;
2734 else if (!strncmp("none", arg, 4))
2735 apic_extnmi = APIC_EXTNMI_NONE;
2736 else if (!strncmp("bsp", arg, 3))
2737 apic_extnmi = APIC_EXTNMI_BSP;
2738 else {
2739 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2740 return -EINVAL;
2741 }
2742
2743 return 0;
2744}
2745early_param("apic_extnmi", apic_set_extnmi);
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/perf_event.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/acpi_pmtmr.h>
21#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24#include <linux/ftrace.h>
25#include <linux/ioport.h>
26#include <linux/module.h>
27#include <linux/syscore_ops.h>
28#include <linux/delay.h>
29#include <linux/timex.h>
30#include <linux/i8253.h>
31#include <linux/dmar.h>
32#include <linux/init.h>
33#include <linux/cpu.h>
34#include <linux/dmi.h>
35#include <linux/smp.h>
36#include <linux/mm.h>
37
38#include <asm/trace/irq_vectors.h>
39#include <asm/irq_remapping.h>
40#include <asm/perf_event.h>
41#include <asm/x86_init.h>
42#include <asm/pgalloc.h>
43#include <linux/atomic.h>
44#include <asm/mpspec.h>
45#include <asm/i8259.h>
46#include <asm/proto.h>
47#include <asm/apic.h>
48#include <asm/io_apic.h>
49#include <asm/desc.h>
50#include <asm/hpet.h>
51#include <asm/idle.h>
52#include <asm/mtrr.h>
53#include <asm/time.h>
54#include <asm/smp.h>
55#include <asm/mce.h>
56#include <asm/tsc.h>
57#include <asm/hypervisor.h>
58
59unsigned int num_processors;
60
61unsigned disabled_cpus;
62
63/* Processor that is doing the boot up */
64unsigned int boot_cpu_physical_apicid = -1U;
65EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
66
67/*
68 * The highest APIC ID seen during enumeration.
69 */
70static unsigned int max_physical_apicid;
71
72/*
73 * Bitmask of physically existing CPUs:
74 */
75physid_mask_t phys_cpu_present_map;
76
77/*
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
81 */
82static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
83
84/*
85 * This variable controls which CPUs receive external NMIs. By default,
86 * external NMIs are delivered only to the BSP.
87 */
88static int apic_extnmi = APIC_EXTNMI_BSP;
89
90/*
91 * Map cpu index to physical APIC ID
92 */
93DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
94DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
95EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
96EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
97
98#ifdef CONFIG_X86_32
99
100/*
101 * On x86_32, the mapping between cpu and logical apicid may vary
102 * depending on apic in use. The following early percpu variable is
103 * used for the mapping. This is where the behaviors of x86_64 and 32
104 * actually diverge. Let's keep it ugly for now.
105 */
106DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
107
108/* Local APIC was disabled by the BIOS and enabled by the kernel */
109static int enabled_via_apicbase;
110
111/*
112 * Handle interrupt mode configuration register (IMCR).
113 * This register controls whether the interrupt signals
114 * that reach the BSP come from the master PIC or from the
115 * local APIC. Before entering Symmetric I/O Mode, either
116 * the BIOS or the operating system must switch out of
117 * PIC Mode by changing the IMCR.
118 */
119static inline void imcr_pic_to_apic(void)
120{
121 /* select IMCR register */
122 outb(0x70, 0x22);
123 /* NMI and 8259 INTR go through APIC */
124 outb(0x01, 0x23);
125}
126
127static inline void imcr_apic_to_pic(void)
128{
129 /* select IMCR register */
130 outb(0x70, 0x22);
131 /* NMI and 8259 INTR go directly to BSP */
132 outb(0x00, 0x23);
133}
134#endif
135
136/*
137 * Knob to control our willingness to enable the local APIC.
138 *
139 * +1=force-enable
140 */
141static int force_enable_local_apic __initdata;
142
143/*
144 * APIC command line parameters
145 */
146static int __init parse_lapic(char *arg)
147{
148 if (config_enabled(CONFIG_X86_32) && !arg)
149 force_enable_local_apic = 1;
150 else if (arg && !strncmp(arg, "notscdeadline", 13))
151 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
152 return 0;
153}
154early_param("lapic", parse_lapic);
155
156#ifdef CONFIG_X86_64
157static int apic_calibrate_pmtmr __initdata;
158static __init int setup_apicpmtimer(char *s)
159{
160 apic_calibrate_pmtmr = 1;
161 notsc_setup(NULL);
162 return 0;
163}
164__setup("apicpmtimer", setup_apicpmtimer);
165#endif
166
167unsigned long mp_lapic_addr;
168int disable_apic;
169/* Disable local APIC timer from the kernel commandline or via dmi quirk */
170static int disable_apic_timer __initdata;
171/* Local APIC timer works in C2 */
172int local_apic_timer_c2_ok;
173EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
174
175int first_system_vector = FIRST_SYSTEM_VECTOR;
176
177/*
178 * Debug level, exported for io_apic.c
179 */
180unsigned int apic_verbosity;
181
182int pic_mode;
183
184/* Have we found an MP table */
185int smp_found_config;
186
187static struct resource lapic_resource = {
188 .name = "Local APIC",
189 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
190};
191
192unsigned int lapic_timer_frequency = 0;
193
194static void apic_pm_activate(void);
195
196static unsigned long apic_phys;
197
198/*
199 * Get the LAPIC version
200 */
201static inline int lapic_get_version(void)
202{
203 return GET_APIC_VERSION(apic_read(APIC_LVR));
204}
205
206/*
207 * Check, if the APIC is integrated or a separate chip
208 */
209static inline int lapic_is_integrated(void)
210{
211#ifdef CONFIG_X86_64
212 return 1;
213#else
214 return APIC_INTEGRATED(lapic_get_version());
215#endif
216}
217
218/*
219 * Check, whether this is a modern or a first generation APIC
220 */
221static int modern_apic(void)
222{
223 /* AMD systems use old APIC versions, so check the CPU */
224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
225 boot_cpu_data.x86 >= 0xf)
226 return 1;
227 return lapic_get_version() >= 0x14;
228}
229
230/*
231 * right after this call apic become NOOP driven
232 * so apic->write/read doesn't do anything
233 */
234static void __init apic_disable(void)
235{
236 pr_info("APIC: switched to apic NOOP\n");
237 apic = &apic_noop;
238}
239
240void native_apic_wait_icr_idle(void)
241{
242 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
243 cpu_relax();
244}
245
246u32 native_safe_apic_wait_icr_idle(void)
247{
248 u32 send_status;
249 int timeout;
250
251 timeout = 0;
252 do {
253 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
254 if (!send_status)
255 break;
256 inc_irq_stat(icr_read_retry_count);
257 udelay(100);
258 } while (timeout++ < 1000);
259
260 return send_status;
261}
262
263void native_apic_icr_write(u32 low, u32 id)
264{
265 unsigned long flags;
266
267 local_irq_save(flags);
268 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
269 apic_write(APIC_ICR, low);
270 local_irq_restore(flags);
271}
272
273u64 native_apic_icr_read(void)
274{
275 u32 icr1, icr2;
276
277 icr2 = apic_read(APIC_ICR2);
278 icr1 = apic_read(APIC_ICR);
279
280 return icr1 | ((u64)icr2 << 32);
281}
282
283#ifdef CONFIG_X86_32
284/**
285 * get_physical_broadcast - Get number of physical broadcast IDs
286 */
287int get_physical_broadcast(void)
288{
289 return modern_apic() ? 0xff : 0xf;
290}
291#endif
292
293/**
294 * lapic_get_maxlvt - get the maximum number of local vector table entries
295 */
296int lapic_get_maxlvt(void)
297{
298 unsigned int v;
299
300 v = apic_read(APIC_LVR);
301 /*
302 * - we always have APIC integrated on 64bit mode
303 * - 82489DXs do not report # of LVT entries
304 */
305 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
306}
307
308/*
309 * Local APIC timer
310 */
311
312/* Clock divisor */
313#define APIC_DIVISOR 16
314#define TSC_DIVISOR 32
315
316/*
317 * This function sets up the local APIC timer, with a timeout of
318 * 'clocks' APIC bus clock. During calibration we actually call
319 * this function twice on the boot CPU, once with a bogus timeout
320 * value, second time for real. The other (noncalibrating) CPUs
321 * call this function only once, with the real, calibrated value.
322 *
323 * We do reads before writes even if unnecessary, to get around the
324 * P5 APIC double write bug.
325 */
326static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
327{
328 unsigned int lvtt_value, tmp_value;
329
330 lvtt_value = LOCAL_TIMER_VECTOR;
331 if (!oneshot)
332 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
333 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
334 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
335
336 if (!lapic_is_integrated())
337 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
338
339 if (!irqen)
340 lvtt_value |= APIC_LVT_MASKED;
341
342 apic_write(APIC_LVTT, lvtt_value);
343
344 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
345 /*
346 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
347 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
348 * According to Intel, MFENCE can do the serialization here.
349 */
350 asm volatile("mfence" : : : "memory");
351
352 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
353 return;
354 }
355
356 /*
357 * Divide PICLK by 16
358 */
359 tmp_value = apic_read(APIC_TDCR);
360 apic_write(APIC_TDCR,
361 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
362 APIC_TDR_DIV_16);
363
364 if (!oneshot)
365 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
366}
367
368/*
369 * Setup extended LVT, AMD specific
370 *
371 * Software should use the LVT offsets the BIOS provides. The offsets
372 * are determined by the subsystems using it like those for MCE
373 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
374 * are supported. Beginning with family 10h at least 4 offsets are
375 * available.
376 *
377 * Since the offsets must be consistent for all cores, we keep track
378 * of the LVT offsets in software and reserve the offset for the same
379 * vector also to be used on other cores. An offset is freed by
380 * setting the entry to APIC_EILVT_MASKED.
381 *
382 * If the BIOS is right, there should be no conflicts. Otherwise a
383 * "[Firmware Bug]: ..." error message is generated. However, if
384 * software does not properly determines the offsets, it is not
385 * necessarily a BIOS bug.
386 */
387
388static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
389
390static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
391{
392 return (old & APIC_EILVT_MASKED)
393 || (new == APIC_EILVT_MASKED)
394 || ((new & ~APIC_EILVT_MASKED) == old);
395}
396
397static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
398{
399 unsigned int rsvd, vector;
400
401 if (offset >= APIC_EILVT_NR_MAX)
402 return ~0;
403
404 rsvd = atomic_read(&eilvt_offsets[offset]);
405 do {
406 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
407 if (vector && !eilvt_entry_is_changeable(vector, new))
408 /* may not change if vectors are different */
409 return rsvd;
410 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
411 } while (rsvd != new);
412
413 rsvd &= ~APIC_EILVT_MASKED;
414 if (rsvd && rsvd != vector)
415 pr_info("LVT offset %d assigned for vector 0x%02x\n",
416 offset, rsvd);
417
418 return new;
419}
420
421/*
422 * If mask=1, the LVT entry does not generate interrupts while mask=0
423 * enables the vector. See also the BKDGs. Must be called with
424 * preemption disabled.
425 */
426
427int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
428{
429 unsigned long reg = APIC_EILVTn(offset);
430 unsigned int new, old, reserved;
431
432 new = (mask << 16) | (msg_type << 8) | vector;
433 old = apic_read(reg);
434 reserved = reserve_eilvt_offset(offset, new);
435
436 if (reserved != new) {
437 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
438 "vector 0x%x, but the register is already in use for "
439 "vector 0x%x on another cpu\n",
440 smp_processor_id(), reg, offset, new, reserved);
441 return -EINVAL;
442 }
443
444 if (!eilvt_entry_is_changeable(old, new)) {
445 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
446 "vector 0x%x, but the register is already in use for "
447 "vector 0x%x on this cpu\n",
448 smp_processor_id(), reg, offset, new, old);
449 return -EBUSY;
450 }
451
452 apic_write(reg, new);
453
454 return 0;
455}
456EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
457
458/*
459 * Program the next event, relative to now
460 */
461static int lapic_next_event(unsigned long delta,
462 struct clock_event_device *evt)
463{
464 apic_write(APIC_TMICT, delta);
465 return 0;
466}
467
468static int lapic_next_deadline(unsigned long delta,
469 struct clock_event_device *evt)
470{
471 u64 tsc;
472
473 tsc = rdtsc();
474 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
475 return 0;
476}
477
478static int lapic_timer_shutdown(struct clock_event_device *evt)
479{
480 unsigned int v;
481
482 /* Lapic used as dummy for broadcast ? */
483 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
484 return 0;
485
486 v = apic_read(APIC_LVTT);
487 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
488 apic_write(APIC_LVTT, v);
489 apic_write(APIC_TMICT, 0);
490 return 0;
491}
492
493static inline int
494lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
495{
496 /* Lapic used as dummy for broadcast ? */
497 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
498 return 0;
499
500 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
501 return 0;
502}
503
504static int lapic_timer_set_periodic(struct clock_event_device *evt)
505{
506 return lapic_timer_set_periodic_oneshot(evt, false);
507}
508
509static int lapic_timer_set_oneshot(struct clock_event_device *evt)
510{
511 return lapic_timer_set_periodic_oneshot(evt, true);
512}
513
514/*
515 * Local APIC timer broadcast function
516 */
517static void lapic_timer_broadcast(const struct cpumask *mask)
518{
519#ifdef CONFIG_SMP
520 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
521#endif
522}
523
524
525/*
526 * The local apic timer can be used for any function which is CPU local.
527 */
528static struct clock_event_device lapic_clockevent = {
529 .name = "lapic",
530 .features = CLOCK_EVT_FEAT_PERIODIC |
531 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
532 | CLOCK_EVT_FEAT_DUMMY,
533 .shift = 32,
534 .set_state_shutdown = lapic_timer_shutdown,
535 .set_state_periodic = lapic_timer_set_periodic,
536 .set_state_oneshot = lapic_timer_set_oneshot,
537 .set_next_event = lapic_next_event,
538 .broadcast = lapic_timer_broadcast,
539 .rating = 100,
540 .irq = -1,
541};
542static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
543
544/*
545 * Setup the local APIC timer for this CPU. Copy the initialized values
546 * of the boot CPU and register the clock event in the framework.
547 */
548static void setup_APIC_timer(void)
549{
550 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
551
552 if (this_cpu_has(X86_FEATURE_ARAT)) {
553 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
554 /* Make LAPIC timer preferrable over percpu HPET */
555 lapic_clockevent.rating = 150;
556 }
557
558 memcpy(levt, &lapic_clockevent, sizeof(*levt));
559 levt->cpumask = cpumask_of(smp_processor_id());
560
561 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
562 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
563 CLOCK_EVT_FEAT_DUMMY);
564 levt->set_next_event = lapic_next_deadline;
565 clockevents_config_and_register(levt,
566 (tsc_khz / TSC_DIVISOR) * 1000,
567 0xF, ~0UL);
568 } else
569 clockevents_register_device(levt);
570}
571
572/*
573 * In this functions we calibrate APIC bus clocks to the external timer.
574 *
575 * We want to do the calibration only once since we want to have local timer
576 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
577 * frequency.
578 *
579 * This was previously done by reading the PIT/HPET and waiting for a wrap
580 * around to find out, that a tick has elapsed. I have a box, where the PIT
581 * readout is broken, so it never gets out of the wait loop again. This was
582 * also reported by others.
583 *
584 * Monitoring the jiffies value is inaccurate and the clockevents
585 * infrastructure allows us to do a simple substitution of the interrupt
586 * handler.
587 *
588 * The calibration routine also uses the pm_timer when possible, as the PIT
589 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
590 * back to normal later in the boot process).
591 */
592
593#define LAPIC_CAL_LOOPS (HZ/10)
594
595static __initdata int lapic_cal_loops = -1;
596static __initdata long lapic_cal_t1, lapic_cal_t2;
597static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
598static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
599static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
600
601/*
602 * Temporary interrupt handler.
603 */
604static void __init lapic_cal_handler(struct clock_event_device *dev)
605{
606 unsigned long long tsc = 0;
607 long tapic = apic_read(APIC_TMCCT);
608 unsigned long pm = acpi_pm_read_early();
609
610 if (cpu_has_tsc)
611 tsc = rdtsc();
612
613 switch (lapic_cal_loops++) {
614 case 0:
615 lapic_cal_t1 = tapic;
616 lapic_cal_tsc1 = tsc;
617 lapic_cal_pm1 = pm;
618 lapic_cal_j1 = jiffies;
619 break;
620
621 case LAPIC_CAL_LOOPS:
622 lapic_cal_t2 = tapic;
623 lapic_cal_tsc2 = tsc;
624 if (pm < lapic_cal_pm1)
625 pm += ACPI_PM_OVRRUN;
626 lapic_cal_pm2 = pm;
627 lapic_cal_j2 = jiffies;
628 break;
629 }
630}
631
632static int __init
633calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
634{
635 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
636 const long pm_thresh = pm_100ms / 100;
637 unsigned long mult;
638 u64 res;
639
640#ifndef CONFIG_X86_PM_TIMER
641 return -1;
642#endif
643
644 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
645
646 /* Check, if the PM timer is available */
647 if (!deltapm)
648 return -1;
649
650 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
651
652 if (deltapm > (pm_100ms - pm_thresh) &&
653 deltapm < (pm_100ms + pm_thresh)) {
654 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
655 return 0;
656 }
657
658 res = (((u64)deltapm) * mult) >> 22;
659 do_div(res, 1000000);
660 pr_warning("APIC calibration not consistent "
661 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
662
663 /* Correct the lapic counter value */
664 res = (((u64)(*delta)) * pm_100ms);
665 do_div(res, deltapm);
666 pr_info("APIC delta adjusted to PM-Timer: "
667 "%lu (%ld)\n", (unsigned long)res, *delta);
668 *delta = (long)res;
669
670 /* Correct the tsc counter value */
671 if (cpu_has_tsc) {
672 res = (((u64)(*deltatsc)) * pm_100ms);
673 do_div(res, deltapm);
674 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
675 "PM-Timer: %lu (%ld)\n",
676 (unsigned long)res, *deltatsc);
677 *deltatsc = (long)res;
678 }
679
680 return 0;
681}
682
683static int __init calibrate_APIC_clock(void)
684{
685 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
686 void (*real_handler)(struct clock_event_device *dev);
687 unsigned long deltaj;
688 long delta, deltatsc;
689 int pm_referenced = 0;
690
691 /**
692 * check if lapic timer has already been calibrated by platform
693 * specific routine, such as tsc calibration code. if so, we just fill
694 * in the clockevent structure and return.
695 */
696
697 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
698 return 0;
699 } else if (lapic_timer_frequency) {
700 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
701 lapic_timer_frequency);
702 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
703 TICK_NSEC, lapic_clockevent.shift);
704 lapic_clockevent.max_delta_ns =
705 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
706 lapic_clockevent.min_delta_ns =
707 clockevent_delta2ns(0xF, &lapic_clockevent);
708 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
709 return 0;
710 }
711
712 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
713 "calibrating APIC timer ...\n");
714
715 local_irq_disable();
716
717 /* Replace the global interrupt handler */
718 real_handler = global_clock_event->event_handler;
719 global_clock_event->event_handler = lapic_cal_handler;
720
721 /*
722 * Setup the APIC counter to maximum. There is no way the lapic
723 * can underflow in the 100ms detection time frame
724 */
725 __setup_APIC_LVTT(0xffffffff, 0, 0);
726
727 /* Let the interrupts run */
728 local_irq_enable();
729
730 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
731 cpu_relax();
732
733 local_irq_disable();
734
735 /* Restore the real event handler */
736 global_clock_event->event_handler = real_handler;
737
738 /* Build delta t1-t2 as apic timer counts down */
739 delta = lapic_cal_t1 - lapic_cal_t2;
740 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
741
742 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
743
744 /* we trust the PM based calibration if possible */
745 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
746 &delta, &deltatsc);
747
748 /* Calculate the scaled math multiplication factor */
749 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
750 lapic_clockevent.shift);
751 lapic_clockevent.max_delta_ns =
752 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
753 lapic_clockevent.min_delta_ns =
754 clockevent_delta2ns(0xF, &lapic_clockevent);
755
756 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
757
758 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
759 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
760 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
761 lapic_timer_frequency);
762
763 if (cpu_has_tsc) {
764 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
765 "%ld.%04ld MHz.\n",
766 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
767 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
768 }
769
770 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
771 "%u.%04u MHz.\n",
772 lapic_timer_frequency / (1000000 / HZ),
773 lapic_timer_frequency % (1000000 / HZ));
774
775 /*
776 * Do a sanity check on the APIC calibration result
777 */
778 if (lapic_timer_frequency < (1000000 / HZ)) {
779 local_irq_enable();
780 pr_warning("APIC frequency too slow, disabling apic timer\n");
781 return -1;
782 }
783
784 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
785
786 /*
787 * PM timer calibration failed or not turned on
788 * so lets try APIC timer based calibration
789 */
790 if (!pm_referenced) {
791 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
792
793 /*
794 * Setup the apic timer manually
795 */
796 levt->event_handler = lapic_cal_handler;
797 lapic_timer_set_periodic(levt);
798 lapic_cal_loops = -1;
799
800 /* Let the interrupts run */
801 local_irq_enable();
802
803 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
804 cpu_relax();
805
806 /* Stop the lapic timer */
807 local_irq_disable();
808 lapic_timer_shutdown(levt);
809
810 /* Jiffies delta */
811 deltaj = lapic_cal_j2 - lapic_cal_j1;
812 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
813
814 /* Check, if the jiffies result is consistent */
815 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
816 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
817 else
818 levt->features |= CLOCK_EVT_FEAT_DUMMY;
819 }
820 local_irq_enable();
821
822 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
823 pr_warning("APIC timer disabled due to verification failure\n");
824 return -1;
825 }
826
827 return 0;
828}
829
830/*
831 * Setup the boot APIC
832 *
833 * Calibrate and verify the result.
834 */
835void __init setup_boot_APIC_clock(void)
836{
837 /*
838 * The local apic timer can be disabled via the kernel
839 * commandline or from the CPU detection code. Register the lapic
840 * timer as a dummy clock event source on SMP systems, so the
841 * broadcast mechanism is used. On UP systems simply ignore it.
842 */
843 if (disable_apic_timer) {
844 pr_info("Disabling APIC timer\n");
845 /* No broadcast on UP ! */
846 if (num_possible_cpus() > 1) {
847 lapic_clockevent.mult = 1;
848 setup_APIC_timer();
849 }
850 return;
851 }
852
853 if (calibrate_APIC_clock()) {
854 /* No broadcast on UP ! */
855 if (num_possible_cpus() > 1)
856 setup_APIC_timer();
857 return;
858 }
859
860 /*
861 * If nmi_watchdog is set to IO_APIC, we need the
862 * PIT/HPET going. Otherwise register lapic as a dummy
863 * device.
864 */
865 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
866
867 /* Setup the lapic or request the broadcast */
868 setup_APIC_timer();
869}
870
871void setup_secondary_APIC_clock(void)
872{
873 setup_APIC_timer();
874}
875
876/*
877 * The guts of the apic timer interrupt
878 */
879static void local_apic_timer_interrupt(void)
880{
881 int cpu = smp_processor_id();
882 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
883
884 /*
885 * Normally we should not be here till LAPIC has been initialized but
886 * in some cases like kdump, its possible that there is a pending LAPIC
887 * timer interrupt from previous kernel's context and is delivered in
888 * new kernel the moment interrupts are enabled.
889 *
890 * Interrupts are enabled early and LAPIC is setup much later, hence
891 * its possible that when we get here evt->event_handler is NULL.
892 * Check for event_handler being NULL and discard the interrupt as
893 * spurious.
894 */
895 if (!evt->event_handler) {
896 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
897 /* Switch it off */
898 lapic_timer_shutdown(evt);
899 return;
900 }
901
902 /*
903 * the NMI deadlock-detector uses this.
904 */
905 inc_irq_stat(apic_timer_irqs);
906
907 evt->event_handler(evt);
908}
909
910/*
911 * Local APIC timer interrupt. This is the most natural way for doing
912 * local interrupts, but local timer interrupts can be emulated by
913 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
914 *
915 * [ if a single-CPU system runs an SMP kernel then we call the local
916 * interrupt as well. Thus we cannot inline the local irq ... ]
917 */
918__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
919{
920 struct pt_regs *old_regs = set_irq_regs(regs);
921
922 /*
923 * NOTE! We'd better ACK the irq immediately,
924 * because timer handling can be slow.
925 *
926 * update_process_times() expects us to have done irq_enter().
927 * Besides, if we don't timer interrupts ignore the global
928 * interrupt lock, which is the WrongThing (tm) to do.
929 */
930 entering_ack_irq();
931 local_apic_timer_interrupt();
932 exiting_irq();
933
934 set_irq_regs(old_regs);
935}
936
937__visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
938{
939 struct pt_regs *old_regs = set_irq_regs(regs);
940
941 /*
942 * NOTE! We'd better ACK the irq immediately,
943 * because timer handling can be slow.
944 *
945 * update_process_times() expects us to have done irq_enter().
946 * Besides, if we don't timer interrupts ignore the global
947 * interrupt lock, which is the WrongThing (tm) to do.
948 */
949 entering_ack_irq();
950 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
951 local_apic_timer_interrupt();
952 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
953 exiting_irq();
954
955 set_irq_regs(old_regs);
956}
957
958int setup_profiling_timer(unsigned int multiplier)
959{
960 return -EINVAL;
961}
962
963/*
964 * Local APIC start and shutdown
965 */
966
967/**
968 * clear_local_APIC - shutdown the local APIC
969 *
970 * This is called, when a CPU is disabled and before rebooting, so the state of
971 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
972 * leftovers during boot.
973 */
974void clear_local_APIC(void)
975{
976 int maxlvt;
977 u32 v;
978
979 /* APIC hasn't been mapped yet */
980 if (!x2apic_mode && !apic_phys)
981 return;
982
983 maxlvt = lapic_get_maxlvt();
984 /*
985 * Masking an LVT entry can trigger a local APIC error
986 * if the vector is zero. Mask LVTERR first to prevent this.
987 */
988 if (maxlvt >= 3) {
989 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
990 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
991 }
992 /*
993 * Careful: we have to set masks only first to deassert
994 * any level-triggered sources.
995 */
996 v = apic_read(APIC_LVTT);
997 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
998 v = apic_read(APIC_LVT0);
999 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1000 v = apic_read(APIC_LVT1);
1001 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1002 if (maxlvt >= 4) {
1003 v = apic_read(APIC_LVTPC);
1004 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1005 }
1006
1007 /* lets not touch this if we didn't frob it */
1008#ifdef CONFIG_X86_THERMAL_VECTOR
1009 if (maxlvt >= 5) {
1010 v = apic_read(APIC_LVTTHMR);
1011 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1012 }
1013#endif
1014#ifdef CONFIG_X86_MCE_INTEL
1015 if (maxlvt >= 6) {
1016 v = apic_read(APIC_LVTCMCI);
1017 if (!(v & APIC_LVT_MASKED))
1018 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1019 }
1020#endif
1021
1022 /*
1023 * Clean APIC state for other OSs:
1024 */
1025 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1026 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1027 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1028 if (maxlvt >= 3)
1029 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1030 if (maxlvt >= 4)
1031 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1032
1033 /* Integrated APIC (!82489DX) ? */
1034 if (lapic_is_integrated()) {
1035 if (maxlvt > 3)
1036 /* Clear ESR due to Pentium errata 3AP and 11AP */
1037 apic_write(APIC_ESR, 0);
1038 apic_read(APIC_ESR);
1039 }
1040}
1041
1042/**
1043 * disable_local_APIC - clear and disable the local APIC
1044 */
1045void disable_local_APIC(void)
1046{
1047 unsigned int value;
1048
1049 /* APIC hasn't been mapped yet */
1050 if (!x2apic_mode && !apic_phys)
1051 return;
1052
1053 clear_local_APIC();
1054
1055 /*
1056 * Disable APIC (implies clearing of registers
1057 * for 82489DX!).
1058 */
1059 value = apic_read(APIC_SPIV);
1060 value &= ~APIC_SPIV_APIC_ENABLED;
1061 apic_write(APIC_SPIV, value);
1062
1063#ifdef CONFIG_X86_32
1064 /*
1065 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1066 * restore the disabled state.
1067 */
1068 if (enabled_via_apicbase) {
1069 unsigned int l, h;
1070
1071 rdmsr(MSR_IA32_APICBASE, l, h);
1072 l &= ~MSR_IA32_APICBASE_ENABLE;
1073 wrmsr(MSR_IA32_APICBASE, l, h);
1074 }
1075#endif
1076}
1077
1078/*
1079 * If Linux enabled the LAPIC against the BIOS default disable it down before
1080 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1081 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1082 * for the case where Linux didn't enable the LAPIC.
1083 */
1084void lapic_shutdown(void)
1085{
1086 unsigned long flags;
1087
1088 if (!cpu_has_apic && !apic_from_smp_config())
1089 return;
1090
1091 local_irq_save(flags);
1092
1093#ifdef CONFIG_X86_32
1094 if (!enabled_via_apicbase)
1095 clear_local_APIC();
1096 else
1097#endif
1098 disable_local_APIC();
1099
1100
1101 local_irq_restore(flags);
1102}
1103
1104/**
1105 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1106 */
1107void __init sync_Arb_IDs(void)
1108{
1109 /*
1110 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1111 * needed on AMD.
1112 */
1113 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1114 return;
1115
1116 /*
1117 * Wait for idle.
1118 */
1119 apic_wait_icr_idle();
1120
1121 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1122 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1123 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1124}
1125
1126/*
1127 * An initial setup of the virtual wire mode.
1128 */
1129void __init init_bsp_APIC(void)
1130{
1131 unsigned int value;
1132
1133 /*
1134 * Don't do the setup now if we have a SMP BIOS as the
1135 * through-I/O-APIC virtual wire mode might be active.
1136 */
1137 if (smp_found_config || !cpu_has_apic)
1138 return;
1139
1140 /*
1141 * Do not trust the local APIC being empty at bootup.
1142 */
1143 clear_local_APIC();
1144
1145 /*
1146 * Enable APIC.
1147 */
1148 value = apic_read(APIC_SPIV);
1149 value &= ~APIC_VECTOR_MASK;
1150 value |= APIC_SPIV_APIC_ENABLED;
1151
1152#ifdef CONFIG_X86_32
1153 /* This bit is reserved on P4/Xeon and should be cleared */
1154 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1155 (boot_cpu_data.x86 == 15))
1156 value &= ~APIC_SPIV_FOCUS_DISABLED;
1157 else
1158#endif
1159 value |= APIC_SPIV_FOCUS_DISABLED;
1160 value |= SPURIOUS_APIC_VECTOR;
1161 apic_write(APIC_SPIV, value);
1162
1163 /*
1164 * Set up the virtual wire mode.
1165 */
1166 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1167 value = APIC_DM_NMI;
1168 if (!lapic_is_integrated()) /* 82489DX */
1169 value |= APIC_LVT_LEVEL_TRIGGER;
1170 if (apic_extnmi == APIC_EXTNMI_NONE)
1171 value |= APIC_LVT_MASKED;
1172 apic_write(APIC_LVT1, value);
1173}
1174
1175static void lapic_setup_esr(void)
1176{
1177 unsigned int oldvalue, value, maxlvt;
1178
1179 if (!lapic_is_integrated()) {
1180 pr_info("No ESR for 82489DX.\n");
1181 return;
1182 }
1183
1184 if (apic->disable_esr) {
1185 /*
1186 * Something untraceable is creating bad interrupts on
1187 * secondary quads ... for the moment, just leave the
1188 * ESR disabled - we can't do anything useful with the
1189 * errors anyway - mbligh
1190 */
1191 pr_info("Leaving ESR disabled.\n");
1192 return;
1193 }
1194
1195 maxlvt = lapic_get_maxlvt();
1196 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1197 apic_write(APIC_ESR, 0);
1198 oldvalue = apic_read(APIC_ESR);
1199
1200 /* enables sending errors */
1201 value = ERROR_APIC_VECTOR;
1202 apic_write(APIC_LVTERR, value);
1203
1204 /*
1205 * spec says clear errors after enabling vector.
1206 */
1207 if (maxlvt > 3)
1208 apic_write(APIC_ESR, 0);
1209 value = apic_read(APIC_ESR);
1210 if (value != oldvalue)
1211 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1212 "vector: 0x%08x after: 0x%08x\n",
1213 oldvalue, value);
1214}
1215
1216/**
1217 * setup_local_APIC - setup the local APIC
1218 *
1219 * Used to setup local APIC while initializing BSP or bringin up APs.
1220 * Always called with preemption disabled.
1221 */
1222void setup_local_APIC(void)
1223{
1224 int cpu = smp_processor_id();
1225 unsigned int value, queued;
1226 int i, j, acked = 0;
1227 unsigned long long tsc = 0, ntsc;
1228 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1229
1230 if (cpu_has_tsc)
1231 tsc = rdtsc();
1232
1233 if (disable_apic) {
1234 disable_ioapic_support();
1235 return;
1236 }
1237
1238#ifdef CONFIG_X86_32
1239 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1240 if (lapic_is_integrated() && apic->disable_esr) {
1241 apic_write(APIC_ESR, 0);
1242 apic_write(APIC_ESR, 0);
1243 apic_write(APIC_ESR, 0);
1244 apic_write(APIC_ESR, 0);
1245 }
1246#endif
1247 perf_events_lapic_init();
1248
1249 /*
1250 * Double-check whether this APIC is really registered.
1251 * This is meaningless in clustered apic mode, so we skip it.
1252 */
1253 BUG_ON(!apic->apic_id_registered());
1254
1255 /*
1256 * Intel recommends to set DFR, LDR and TPR before enabling
1257 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1258 * document number 292116). So here it goes...
1259 */
1260 apic->init_apic_ldr();
1261
1262#ifdef CONFIG_X86_32
1263 /*
1264 * APIC LDR is initialized. If logical_apicid mapping was
1265 * initialized during get_smp_config(), make sure it matches the
1266 * actual value.
1267 */
1268 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1269 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1270 /* always use the value from LDR */
1271 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1272 logical_smp_processor_id();
1273#endif
1274
1275 /*
1276 * Set Task Priority to 'accept all'. We never change this
1277 * later on.
1278 */
1279 value = apic_read(APIC_TASKPRI);
1280 value &= ~APIC_TPRI_MASK;
1281 apic_write(APIC_TASKPRI, value);
1282
1283 /*
1284 * After a crash, we no longer service the interrupts and a pending
1285 * interrupt from previous kernel might still have ISR bit set.
1286 *
1287 * Most probably by now CPU has serviced that pending interrupt and
1288 * it might not have done the ack_APIC_irq() because it thought,
1289 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1290 * does not clear the ISR bit and cpu thinks it has already serivced
1291 * the interrupt. Hence a vector might get locked. It was noticed
1292 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1293 */
1294 do {
1295 queued = 0;
1296 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1297 queued |= apic_read(APIC_IRR + i*0x10);
1298
1299 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1300 value = apic_read(APIC_ISR + i*0x10);
1301 for (j = 31; j >= 0; j--) {
1302 if (value & (1<<j)) {
1303 ack_APIC_irq();
1304 acked++;
1305 }
1306 }
1307 }
1308 if (acked > 256) {
1309 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1310 acked);
1311 break;
1312 }
1313 if (queued) {
1314 if (cpu_has_tsc && cpu_khz) {
1315 ntsc = rdtsc();
1316 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1317 } else
1318 max_loops--;
1319 }
1320 } while (queued && max_loops > 0);
1321 WARN_ON(max_loops <= 0);
1322
1323 /*
1324 * Now that we are all set up, enable the APIC
1325 */
1326 value = apic_read(APIC_SPIV);
1327 value &= ~APIC_VECTOR_MASK;
1328 /*
1329 * Enable APIC
1330 */
1331 value |= APIC_SPIV_APIC_ENABLED;
1332
1333#ifdef CONFIG_X86_32
1334 /*
1335 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1336 * certain networking cards. If high frequency interrupts are
1337 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1338 * entry is masked/unmasked at a high rate as well then sooner or
1339 * later IOAPIC line gets 'stuck', no more interrupts are received
1340 * from the device. If focus CPU is disabled then the hang goes
1341 * away, oh well :-(
1342 *
1343 * [ This bug can be reproduced easily with a level-triggered
1344 * PCI Ne2000 networking cards and PII/PIII processors, dual
1345 * BX chipset. ]
1346 */
1347 /*
1348 * Actually disabling the focus CPU check just makes the hang less
1349 * frequent as it makes the interrupt distributon model be more
1350 * like LRU than MRU (the short-term load is more even across CPUs).
1351 * See also the comment in end_level_ioapic_irq(). --macro
1352 */
1353
1354 /*
1355 * - enable focus processor (bit==0)
1356 * - 64bit mode always use processor focus
1357 * so no need to set it
1358 */
1359 value &= ~APIC_SPIV_FOCUS_DISABLED;
1360#endif
1361
1362 /*
1363 * Set spurious IRQ vector
1364 */
1365 value |= SPURIOUS_APIC_VECTOR;
1366 apic_write(APIC_SPIV, value);
1367
1368 /*
1369 * Set up LVT0, LVT1:
1370 *
1371 * set up through-local-APIC on the BP's LINT0. This is not
1372 * strictly necessary in pure symmetric-IO mode, but sometimes
1373 * we delegate interrupts to the 8259A.
1374 */
1375 /*
1376 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1377 */
1378 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1379 if (!cpu && (pic_mode || !value)) {
1380 value = APIC_DM_EXTINT;
1381 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1382 } else {
1383 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1384 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1385 }
1386 apic_write(APIC_LVT0, value);
1387
1388 /*
1389 * Only the BSP sees the LINT1 NMI signal by default. This can be
1390 * modified by apic_extnmi= boot option.
1391 */
1392 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1393 apic_extnmi == APIC_EXTNMI_ALL)
1394 value = APIC_DM_NMI;
1395 else
1396 value = APIC_DM_NMI | APIC_LVT_MASKED;
1397 if (!lapic_is_integrated()) /* 82489DX */
1398 value |= APIC_LVT_LEVEL_TRIGGER;
1399 apic_write(APIC_LVT1, value);
1400
1401#ifdef CONFIG_X86_MCE_INTEL
1402 /* Recheck CMCI information after local APIC is up on CPU #0 */
1403 if (!cpu)
1404 cmci_recheck();
1405#endif
1406}
1407
1408static void end_local_APIC_setup(void)
1409{
1410 lapic_setup_esr();
1411
1412#ifdef CONFIG_X86_32
1413 {
1414 unsigned int value;
1415 /* Disable the local apic timer */
1416 value = apic_read(APIC_LVTT);
1417 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1418 apic_write(APIC_LVTT, value);
1419 }
1420#endif
1421
1422 apic_pm_activate();
1423}
1424
1425/*
1426 * APIC setup function for application processors. Called from smpboot.c
1427 */
1428void apic_ap_setup(void)
1429{
1430 setup_local_APIC();
1431 end_local_APIC_setup();
1432}
1433
1434#ifdef CONFIG_X86_X2APIC
1435int x2apic_mode;
1436
1437enum {
1438 X2APIC_OFF,
1439 X2APIC_ON,
1440 X2APIC_DISABLED,
1441};
1442static int x2apic_state;
1443
1444static void __x2apic_disable(void)
1445{
1446 u64 msr;
1447
1448 if (!cpu_has_apic)
1449 return;
1450
1451 rdmsrl(MSR_IA32_APICBASE, msr);
1452 if (!(msr & X2APIC_ENABLE))
1453 return;
1454 /* Disable xapic and x2apic first and then reenable xapic mode */
1455 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1456 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1457 printk_once(KERN_INFO "x2apic disabled\n");
1458}
1459
1460static void __x2apic_enable(void)
1461{
1462 u64 msr;
1463
1464 rdmsrl(MSR_IA32_APICBASE, msr);
1465 if (msr & X2APIC_ENABLE)
1466 return;
1467 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1468 printk_once(KERN_INFO "x2apic enabled\n");
1469}
1470
1471static int __init setup_nox2apic(char *str)
1472{
1473 if (x2apic_enabled()) {
1474 int apicid = native_apic_msr_read(APIC_ID);
1475
1476 if (apicid >= 255) {
1477 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1478 apicid);
1479 return 0;
1480 }
1481 pr_warning("x2apic already enabled.\n");
1482 __x2apic_disable();
1483 }
1484 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1485 x2apic_state = X2APIC_DISABLED;
1486 x2apic_mode = 0;
1487 return 0;
1488}
1489early_param("nox2apic", setup_nox2apic);
1490
1491/* Called from cpu_init() to enable x2apic on (secondary) cpus */
1492void x2apic_setup(void)
1493{
1494 /*
1495 * If x2apic is not in ON state, disable it if already enabled
1496 * from BIOS.
1497 */
1498 if (x2apic_state != X2APIC_ON) {
1499 __x2apic_disable();
1500 return;
1501 }
1502 __x2apic_enable();
1503}
1504
1505static __init void x2apic_disable(void)
1506{
1507 u32 x2apic_id, state = x2apic_state;
1508
1509 x2apic_mode = 0;
1510 x2apic_state = X2APIC_DISABLED;
1511
1512 if (state != X2APIC_ON)
1513 return;
1514
1515 x2apic_id = read_apic_id();
1516 if (x2apic_id >= 255)
1517 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1518
1519 __x2apic_disable();
1520 register_lapic_address(mp_lapic_addr);
1521}
1522
1523static __init void x2apic_enable(void)
1524{
1525 if (x2apic_state != X2APIC_OFF)
1526 return;
1527
1528 x2apic_mode = 1;
1529 x2apic_state = X2APIC_ON;
1530 __x2apic_enable();
1531}
1532
1533static __init void try_to_enable_x2apic(int remap_mode)
1534{
1535 if (x2apic_state == X2APIC_DISABLED)
1536 return;
1537
1538 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1539 /* IR is required if there is APIC ID > 255 even when running
1540 * under KVM
1541 */
1542 if (max_physical_apicid > 255 ||
1543 !hypervisor_x2apic_available()) {
1544 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1545 x2apic_disable();
1546 return;
1547 }
1548
1549 /*
1550 * without IR all CPUs can be addressed by IOAPIC/MSI
1551 * only in physical mode
1552 */
1553 x2apic_phys = 1;
1554 }
1555 x2apic_enable();
1556}
1557
1558void __init check_x2apic(void)
1559{
1560 if (x2apic_enabled()) {
1561 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1562 x2apic_mode = 1;
1563 x2apic_state = X2APIC_ON;
1564 } else if (!cpu_has_x2apic) {
1565 x2apic_state = X2APIC_DISABLED;
1566 }
1567}
1568#else /* CONFIG_X86_X2APIC */
1569static int __init validate_x2apic(void)
1570{
1571 if (!apic_is_x2apic_enabled())
1572 return 0;
1573 /*
1574 * Checkme: Can we simply turn off x2apic here instead of panic?
1575 */
1576 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1577}
1578early_initcall(validate_x2apic);
1579
1580static inline void try_to_enable_x2apic(int remap_mode) { }
1581static inline void __x2apic_enable(void) { }
1582#endif /* !CONFIG_X86_X2APIC */
1583
1584static int __init try_to_enable_IR(void)
1585{
1586#ifdef CONFIG_X86_IO_APIC
1587 if (!x2apic_enabled() && skip_ioapic_setup) {
1588 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1589 return -1;
1590 }
1591#endif
1592 return irq_remapping_enable();
1593}
1594
1595void __init enable_IR_x2apic(void)
1596{
1597 unsigned long flags;
1598 int ret, ir_stat;
1599
1600 ir_stat = irq_remapping_prepare();
1601 if (ir_stat < 0 && !x2apic_supported())
1602 return;
1603
1604 ret = save_ioapic_entries();
1605 if (ret) {
1606 pr_info("Saving IO-APIC state failed: %d\n", ret);
1607 return;
1608 }
1609
1610 local_irq_save(flags);
1611 legacy_pic->mask_all();
1612 mask_ioapic_entries();
1613
1614 /* If irq_remapping_prepare() succeeded, try to enable it */
1615 if (ir_stat >= 0)
1616 ir_stat = try_to_enable_IR();
1617 /* ir_stat contains the remap mode or an error code */
1618 try_to_enable_x2apic(ir_stat);
1619
1620 if (ir_stat < 0)
1621 restore_ioapic_entries();
1622 legacy_pic->restore_mask();
1623 local_irq_restore(flags);
1624}
1625
1626#ifdef CONFIG_X86_64
1627/*
1628 * Detect and enable local APICs on non-SMP boards.
1629 * Original code written by Keir Fraser.
1630 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1631 * not correctly set up (usually the APIC timer won't work etc.)
1632 */
1633static int __init detect_init_APIC(void)
1634{
1635 if (!cpu_has_apic) {
1636 pr_info("No local APIC present\n");
1637 return -1;
1638 }
1639
1640 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1641 return 0;
1642}
1643#else
1644
1645static int __init apic_verify(void)
1646{
1647 u32 features, h, l;
1648
1649 /*
1650 * The APIC feature bit should now be enabled
1651 * in `cpuid'
1652 */
1653 features = cpuid_edx(1);
1654 if (!(features & (1 << X86_FEATURE_APIC))) {
1655 pr_warning("Could not enable APIC!\n");
1656 return -1;
1657 }
1658 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1659 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1660
1661 /* The BIOS may have set up the APIC at some other address */
1662 if (boot_cpu_data.x86 >= 6) {
1663 rdmsr(MSR_IA32_APICBASE, l, h);
1664 if (l & MSR_IA32_APICBASE_ENABLE)
1665 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1666 }
1667
1668 pr_info("Found and enabled local APIC!\n");
1669 return 0;
1670}
1671
1672int __init apic_force_enable(unsigned long addr)
1673{
1674 u32 h, l;
1675
1676 if (disable_apic)
1677 return -1;
1678
1679 /*
1680 * Some BIOSes disable the local APIC in the APIC_BASE
1681 * MSR. This can only be done in software for Intel P6 or later
1682 * and AMD K7 (Model > 1) or later.
1683 */
1684 if (boot_cpu_data.x86 >= 6) {
1685 rdmsr(MSR_IA32_APICBASE, l, h);
1686 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1687 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1688 l &= ~MSR_IA32_APICBASE_BASE;
1689 l |= MSR_IA32_APICBASE_ENABLE | addr;
1690 wrmsr(MSR_IA32_APICBASE, l, h);
1691 enabled_via_apicbase = 1;
1692 }
1693 }
1694 return apic_verify();
1695}
1696
1697/*
1698 * Detect and initialize APIC
1699 */
1700static int __init detect_init_APIC(void)
1701{
1702 /* Disabled by kernel option? */
1703 if (disable_apic)
1704 return -1;
1705
1706 switch (boot_cpu_data.x86_vendor) {
1707 case X86_VENDOR_AMD:
1708 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1709 (boot_cpu_data.x86 >= 15))
1710 break;
1711 goto no_apic;
1712 case X86_VENDOR_INTEL:
1713 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1714 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1715 break;
1716 goto no_apic;
1717 default:
1718 goto no_apic;
1719 }
1720
1721 if (!cpu_has_apic) {
1722 /*
1723 * Over-ride BIOS and try to enable the local APIC only if
1724 * "lapic" specified.
1725 */
1726 if (!force_enable_local_apic) {
1727 pr_info("Local APIC disabled by BIOS -- "
1728 "you can enable it with \"lapic\"\n");
1729 return -1;
1730 }
1731 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1732 return -1;
1733 } else {
1734 if (apic_verify())
1735 return -1;
1736 }
1737
1738 apic_pm_activate();
1739
1740 return 0;
1741
1742no_apic:
1743 pr_info("No local APIC present or hardware disabled\n");
1744 return -1;
1745}
1746#endif
1747
1748/**
1749 * init_apic_mappings - initialize APIC mappings
1750 */
1751void __init init_apic_mappings(void)
1752{
1753 unsigned int new_apicid;
1754
1755 if (x2apic_mode) {
1756 boot_cpu_physical_apicid = read_apic_id();
1757 return;
1758 }
1759
1760 /* If no local APIC can be found return early */
1761 if (!smp_found_config && detect_init_APIC()) {
1762 /* lets NOP'ify apic operations */
1763 pr_info("APIC: disable apic facility\n");
1764 apic_disable();
1765 } else {
1766 apic_phys = mp_lapic_addr;
1767
1768 /*
1769 * acpi lapic path already maps that address in
1770 * acpi_register_lapic_address()
1771 */
1772 if (!acpi_lapic && !smp_found_config)
1773 register_lapic_address(apic_phys);
1774 }
1775
1776 /*
1777 * Fetch the APIC ID of the BSP in case we have a
1778 * default configuration (or the MP table is broken).
1779 */
1780 new_apicid = read_apic_id();
1781 if (boot_cpu_physical_apicid != new_apicid) {
1782 boot_cpu_physical_apicid = new_apicid;
1783 /*
1784 * yeah -- we lie about apic_version
1785 * in case if apic was disabled via boot option
1786 * but it's not a problem for SMP compiled kernel
1787 * since smp_sanity_check is prepared for such a case
1788 * and disable smp mode
1789 */
1790 apic_version[new_apicid] =
1791 GET_APIC_VERSION(apic_read(APIC_LVR));
1792 }
1793}
1794
1795void __init register_lapic_address(unsigned long address)
1796{
1797 mp_lapic_addr = address;
1798
1799 if (!x2apic_mode) {
1800 set_fixmap_nocache(FIX_APIC_BASE, address);
1801 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1802 APIC_BASE, mp_lapic_addr);
1803 }
1804 if (boot_cpu_physical_apicid == -1U) {
1805 boot_cpu_physical_apicid = read_apic_id();
1806 apic_version[boot_cpu_physical_apicid] =
1807 GET_APIC_VERSION(apic_read(APIC_LVR));
1808 }
1809}
1810
1811int apic_version[MAX_LOCAL_APIC];
1812
1813/*
1814 * Local APIC interrupts
1815 */
1816
1817/*
1818 * This interrupt should _never_ happen with our APIC/SMP architecture
1819 */
1820static void __smp_spurious_interrupt(u8 vector)
1821{
1822 u32 v;
1823
1824 /*
1825 * Check if this really is a spurious interrupt and ACK it
1826 * if it is a vectored one. Just in case...
1827 * Spurious interrupts should not be ACKed.
1828 */
1829 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1830 if (v & (1 << (vector & 0x1f)))
1831 ack_APIC_irq();
1832
1833 inc_irq_stat(irq_spurious_count);
1834
1835 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1836 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1837 "should never happen.\n", vector, smp_processor_id());
1838}
1839
1840__visible void smp_spurious_interrupt(struct pt_regs *regs)
1841{
1842 entering_irq();
1843 __smp_spurious_interrupt(~regs->orig_ax);
1844 exiting_irq();
1845}
1846
1847__visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1848{
1849 u8 vector = ~regs->orig_ax;
1850
1851 entering_irq();
1852 trace_spurious_apic_entry(vector);
1853 __smp_spurious_interrupt(vector);
1854 trace_spurious_apic_exit(vector);
1855 exiting_irq();
1856}
1857
1858/*
1859 * This interrupt should never happen with our APIC/SMP architecture
1860 */
1861static void __smp_error_interrupt(struct pt_regs *regs)
1862{
1863 u32 v;
1864 u32 i = 0;
1865 static const char * const error_interrupt_reason[] = {
1866 "Send CS error", /* APIC Error Bit 0 */
1867 "Receive CS error", /* APIC Error Bit 1 */
1868 "Send accept error", /* APIC Error Bit 2 */
1869 "Receive accept error", /* APIC Error Bit 3 */
1870 "Redirectable IPI", /* APIC Error Bit 4 */
1871 "Send illegal vector", /* APIC Error Bit 5 */
1872 "Received illegal vector", /* APIC Error Bit 6 */
1873 "Illegal register address", /* APIC Error Bit 7 */
1874 };
1875
1876 /* First tickle the hardware, only then report what went on. -- REW */
1877 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1878 apic_write(APIC_ESR, 0);
1879 v = apic_read(APIC_ESR);
1880 ack_APIC_irq();
1881 atomic_inc(&irq_err_count);
1882
1883 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1884 smp_processor_id(), v);
1885
1886 v &= 0xff;
1887 while (v) {
1888 if (v & 0x1)
1889 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1890 i++;
1891 v >>= 1;
1892 }
1893
1894 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1895
1896}
1897
1898__visible void smp_error_interrupt(struct pt_regs *regs)
1899{
1900 entering_irq();
1901 __smp_error_interrupt(regs);
1902 exiting_irq();
1903}
1904
1905__visible void smp_trace_error_interrupt(struct pt_regs *regs)
1906{
1907 entering_irq();
1908 trace_error_apic_entry(ERROR_APIC_VECTOR);
1909 __smp_error_interrupt(regs);
1910 trace_error_apic_exit(ERROR_APIC_VECTOR);
1911 exiting_irq();
1912}
1913
1914/**
1915 * connect_bsp_APIC - attach the APIC to the interrupt system
1916 */
1917static void __init connect_bsp_APIC(void)
1918{
1919#ifdef CONFIG_X86_32
1920 if (pic_mode) {
1921 /*
1922 * Do not trust the local APIC being empty at bootup.
1923 */
1924 clear_local_APIC();
1925 /*
1926 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1927 * local APIC to INT and NMI lines.
1928 */
1929 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1930 "enabling APIC mode.\n");
1931 imcr_pic_to_apic();
1932 }
1933#endif
1934}
1935
1936/**
1937 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1938 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1939 *
1940 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1941 * APIC is disabled.
1942 */
1943void disconnect_bsp_APIC(int virt_wire_setup)
1944{
1945 unsigned int value;
1946
1947#ifdef CONFIG_X86_32
1948 if (pic_mode) {
1949 /*
1950 * Put the board back into PIC mode (has an effect only on
1951 * certain older boards). Note that APIC interrupts, including
1952 * IPIs, won't work beyond this point! The only exception are
1953 * INIT IPIs.
1954 */
1955 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1956 "entering PIC mode.\n");
1957 imcr_apic_to_pic();
1958 return;
1959 }
1960#endif
1961
1962 /* Go back to Virtual Wire compatibility mode */
1963
1964 /* For the spurious interrupt use vector F, and enable it */
1965 value = apic_read(APIC_SPIV);
1966 value &= ~APIC_VECTOR_MASK;
1967 value |= APIC_SPIV_APIC_ENABLED;
1968 value |= 0xf;
1969 apic_write(APIC_SPIV, value);
1970
1971 if (!virt_wire_setup) {
1972 /*
1973 * For LVT0 make it edge triggered, active high,
1974 * external and enabled
1975 */
1976 value = apic_read(APIC_LVT0);
1977 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1978 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1979 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1980 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1981 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1982 apic_write(APIC_LVT0, value);
1983 } else {
1984 /* Disable LVT0 */
1985 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1986 }
1987
1988 /*
1989 * For LVT1 make it edge triggered, active high,
1990 * nmi and enabled
1991 */
1992 value = apic_read(APIC_LVT1);
1993 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1994 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1995 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1996 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1997 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1998 apic_write(APIC_LVT1, value);
1999}
2000
2001int generic_processor_info(int apicid, int version)
2002{
2003 int cpu, max = nr_cpu_ids;
2004 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2005 phys_cpu_present_map);
2006
2007 /*
2008 * boot_cpu_physical_apicid is designed to have the apicid
2009 * returned by read_apic_id(), i.e, the apicid of the
2010 * currently booting-up processor. However, on some platforms,
2011 * it is temporarily modified by the apicid reported as BSP
2012 * through MP table. Concretely:
2013 *
2014 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2015 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2016 *
2017 * This function is executed with the modified
2018 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2019 * parameter doesn't work to disable APs on kdump 2nd kernel.
2020 *
2021 * Since fixing handling of boot_cpu_physical_apicid requires
2022 * another discussion and tests on each platform, we leave it
2023 * for now and here we use read_apic_id() directly in this
2024 * function, generic_processor_info().
2025 */
2026 if (disabled_cpu_apicid != BAD_APICID &&
2027 disabled_cpu_apicid != read_apic_id() &&
2028 disabled_cpu_apicid == apicid) {
2029 int thiscpu = num_processors + disabled_cpus;
2030
2031 pr_warning("APIC: Disabling requested cpu."
2032 " Processor %d/0x%x ignored.\n",
2033 thiscpu, apicid);
2034
2035 disabled_cpus++;
2036 return -ENODEV;
2037 }
2038
2039 /*
2040 * If boot cpu has not been detected yet, then only allow upto
2041 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2042 */
2043 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2044 apicid != boot_cpu_physical_apicid) {
2045 int thiscpu = max + disabled_cpus - 1;
2046
2047 pr_warning(
2048 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2049 " reached. Keeping one slot for boot cpu."
2050 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2051
2052 disabled_cpus++;
2053 return -ENODEV;
2054 }
2055
2056 if (num_processors >= nr_cpu_ids) {
2057 int thiscpu = max + disabled_cpus;
2058
2059 pr_warning(
2060 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2061 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2062
2063 disabled_cpus++;
2064 return -EINVAL;
2065 }
2066
2067 num_processors++;
2068 if (apicid == boot_cpu_physical_apicid) {
2069 /*
2070 * x86_bios_cpu_apicid is required to have processors listed
2071 * in same order as logical cpu numbers. Hence the first
2072 * entry is BSP, and so on.
2073 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2074 * for BSP.
2075 */
2076 cpu = 0;
2077 } else
2078 cpu = cpumask_next_zero(-1, cpu_present_mask);
2079
2080 /*
2081 * This can happen on physical hotplug. The sanity check at boot time
2082 * is done from native_smp_prepare_cpus() after num_possible_cpus() is
2083 * established.
2084 */
2085 if (topology_update_package_map(apicid, cpu) < 0) {
2086 int thiscpu = max + disabled_cpus;
2087
2088 pr_warning("ACPI: Package limit reached. Processor %d/0x%x ignored.\n",
2089 thiscpu, apicid);
2090 disabled_cpus++;
2091 return -ENOSPC;
2092 }
2093
2094 /*
2095 * Validate version
2096 */
2097 if (version == 0x0) {
2098 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2099 cpu, apicid);
2100 version = 0x10;
2101 }
2102 apic_version[apicid] = version;
2103
2104 if (version != apic_version[boot_cpu_physical_apicid]) {
2105 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2106 apic_version[boot_cpu_physical_apicid], cpu, version);
2107 }
2108
2109 physid_set(apicid, phys_cpu_present_map);
2110 if (apicid > max_physical_apicid)
2111 max_physical_apicid = apicid;
2112
2113#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2114 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2115 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2116#endif
2117#ifdef CONFIG_X86_32
2118 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2119 apic->x86_32_early_logical_apicid(cpu);
2120#endif
2121 set_cpu_possible(cpu, true);
2122 set_cpu_present(cpu, true);
2123
2124 return cpu;
2125}
2126
2127int hard_smp_processor_id(void)
2128{
2129 return read_apic_id();
2130}
2131
2132void default_init_apic_ldr(void)
2133{
2134 unsigned long val;
2135
2136 apic_write(APIC_DFR, APIC_DFR_VALUE);
2137 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2138 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2139 apic_write(APIC_LDR, val);
2140}
2141
2142int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2143 const struct cpumask *andmask,
2144 unsigned int *apicid)
2145{
2146 unsigned int cpu;
2147
2148 for_each_cpu_and(cpu, cpumask, andmask) {
2149 if (cpumask_test_cpu(cpu, cpu_online_mask))
2150 break;
2151 }
2152
2153 if (likely(cpu < nr_cpu_ids)) {
2154 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2155 return 0;
2156 }
2157
2158 return -EINVAL;
2159}
2160
2161/*
2162 * Override the generic EOI implementation with an optimized version.
2163 * Only called during early boot when only one CPU is active and with
2164 * interrupts disabled, so we know this does not race with actual APIC driver
2165 * use.
2166 */
2167void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2168{
2169 struct apic **drv;
2170
2171 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2172 /* Should happen once for each apic */
2173 WARN_ON((*drv)->eoi_write == eoi_write);
2174 (*drv)->eoi_write = eoi_write;
2175 }
2176}
2177
2178static void __init apic_bsp_up_setup(void)
2179{
2180#ifdef CONFIG_X86_64
2181 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2182#else
2183 /*
2184 * Hack: In case of kdump, after a crash, kernel might be booting
2185 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2186 * might be zero if read from MP tables. Get it from LAPIC.
2187 */
2188# ifdef CONFIG_CRASH_DUMP
2189 boot_cpu_physical_apicid = read_apic_id();
2190# endif
2191#endif
2192 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2193}
2194
2195/**
2196 * apic_bsp_setup - Setup function for local apic and io-apic
2197 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2198 *
2199 * Returns:
2200 * apic_id of BSP APIC
2201 */
2202int __init apic_bsp_setup(bool upmode)
2203{
2204 int id;
2205
2206 connect_bsp_APIC();
2207 if (upmode)
2208 apic_bsp_up_setup();
2209 setup_local_APIC();
2210
2211 if (x2apic_mode)
2212 id = apic_read(APIC_LDR);
2213 else
2214 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2215
2216 enable_IO_APIC();
2217 end_local_APIC_setup();
2218 irq_remap_enable_fault_handling();
2219 setup_IO_APIC();
2220 /* Setup local timer */
2221 x86_init.timers.setup_percpu_clockev();
2222 return id;
2223}
2224
2225/*
2226 * This initializes the IO-APIC and APIC hardware if this is
2227 * a UP kernel.
2228 */
2229int __init APIC_init_uniprocessor(void)
2230{
2231 if (disable_apic) {
2232 pr_info("Apic disabled\n");
2233 return -1;
2234 }
2235#ifdef CONFIG_X86_64
2236 if (!cpu_has_apic) {
2237 disable_apic = 1;
2238 pr_info("Apic disabled by BIOS\n");
2239 return -1;
2240 }
2241#else
2242 if (!smp_found_config && !cpu_has_apic)
2243 return -1;
2244
2245 /*
2246 * Complain if the BIOS pretends there is one.
2247 */
2248 if (!cpu_has_apic &&
2249 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
2250 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2251 boot_cpu_physical_apicid);
2252 return -1;
2253 }
2254#endif
2255
2256 if (!smp_found_config)
2257 disable_ioapic_support();
2258
2259 default_setup_apic_routing();
2260 apic_bsp_setup(true);
2261 return 0;
2262}
2263
2264#ifdef CONFIG_UP_LATE_INIT
2265void __init up_late_init(void)
2266{
2267 APIC_init_uniprocessor();
2268}
2269#endif
2270
2271/*
2272 * Power management
2273 */
2274#ifdef CONFIG_PM
2275
2276static struct {
2277 /*
2278 * 'active' is true if the local APIC was enabled by us and
2279 * not the BIOS; this signifies that we are also responsible
2280 * for disabling it before entering apm/acpi suspend
2281 */
2282 int active;
2283 /* r/w apic fields */
2284 unsigned int apic_id;
2285 unsigned int apic_taskpri;
2286 unsigned int apic_ldr;
2287 unsigned int apic_dfr;
2288 unsigned int apic_spiv;
2289 unsigned int apic_lvtt;
2290 unsigned int apic_lvtpc;
2291 unsigned int apic_lvt0;
2292 unsigned int apic_lvt1;
2293 unsigned int apic_lvterr;
2294 unsigned int apic_tmict;
2295 unsigned int apic_tdcr;
2296 unsigned int apic_thmr;
2297 unsigned int apic_cmci;
2298} apic_pm_state;
2299
2300static int lapic_suspend(void)
2301{
2302 unsigned long flags;
2303 int maxlvt;
2304
2305 if (!apic_pm_state.active)
2306 return 0;
2307
2308 maxlvt = lapic_get_maxlvt();
2309
2310 apic_pm_state.apic_id = apic_read(APIC_ID);
2311 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2312 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2313 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2314 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2315 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2316 if (maxlvt >= 4)
2317 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2318 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2319 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2320 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2321 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2322 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2323#ifdef CONFIG_X86_THERMAL_VECTOR
2324 if (maxlvt >= 5)
2325 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2326#endif
2327#ifdef CONFIG_X86_MCE_INTEL
2328 if (maxlvt >= 6)
2329 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2330#endif
2331
2332 local_irq_save(flags);
2333 disable_local_APIC();
2334
2335 irq_remapping_disable();
2336
2337 local_irq_restore(flags);
2338 return 0;
2339}
2340
2341static void lapic_resume(void)
2342{
2343 unsigned int l, h;
2344 unsigned long flags;
2345 int maxlvt;
2346
2347 if (!apic_pm_state.active)
2348 return;
2349
2350 local_irq_save(flags);
2351
2352 /*
2353 * IO-APIC and PIC have their own resume routines.
2354 * We just mask them here to make sure the interrupt
2355 * subsystem is completely quiet while we enable x2apic
2356 * and interrupt-remapping.
2357 */
2358 mask_ioapic_entries();
2359 legacy_pic->mask_all();
2360
2361 if (x2apic_mode) {
2362 __x2apic_enable();
2363 } else {
2364 /*
2365 * Make sure the APICBASE points to the right address
2366 *
2367 * FIXME! This will be wrong if we ever support suspend on
2368 * SMP! We'll need to do this as part of the CPU restore!
2369 */
2370 if (boot_cpu_data.x86 >= 6) {
2371 rdmsr(MSR_IA32_APICBASE, l, h);
2372 l &= ~MSR_IA32_APICBASE_BASE;
2373 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2374 wrmsr(MSR_IA32_APICBASE, l, h);
2375 }
2376 }
2377
2378 maxlvt = lapic_get_maxlvt();
2379 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2380 apic_write(APIC_ID, apic_pm_state.apic_id);
2381 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2382 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2383 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2384 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2385 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2386 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2387#ifdef CONFIG_X86_THERMAL_VECTOR
2388 if (maxlvt >= 5)
2389 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2390#endif
2391#ifdef CONFIG_X86_MCE_INTEL
2392 if (maxlvt >= 6)
2393 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2394#endif
2395 if (maxlvt >= 4)
2396 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2397 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2398 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2399 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2400 apic_write(APIC_ESR, 0);
2401 apic_read(APIC_ESR);
2402 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2403 apic_write(APIC_ESR, 0);
2404 apic_read(APIC_ESR);
2405
2406 irq_remapping_reenable(x2apic_mode);
2407
2408 local_irq_restore(flags);
2409}
2410
2411/*
2412 * This device has no shutdown method - fully functioning local APICs
2413 * are needed on every CPU up until machine_halt/restart/poweroff.
2414 */
2415
2416static struct syscore_ops lapic_syscore_ops = {
2417 .resume = lapic_resume,
2418 .suspend = lapic_suspend,
2419};
2420
2421static void apic_pm_activate(void)
2422{
2423 apic_pm_state.active = 1;
2424}
2425
2426static int __init init_lapic_sysfs(void)
2427{
2428 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2429 if (cpu_has_apic)
2430 register_syscore_ops(&lapic_syscore_ops);
2431
2432 return 0;
2433}
2434
2435/* local apic needs to resume before other devices access its registers. */
2436core_initcall(init_lapic_sysfs);
2437
2438#else /* CONFIG_PM */
2439
2440static void apic_pm_activate(void) { }
2441
2442#endif /* CONFIG_PM */
2443
2444#ifdef CONFIG_X86_64
2445
2446static int multi_checked;
2447static int multi;
2448
2449static int set_multi(const struct dmi_system_id *d)
2450{
2451 if (multi)
2452 return 0;
2453 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2454 multi = 1;
2455 return 0;
2456}
2457
2458static const struct dmi_system_id multi_dmi_table[] = {
2459 {
2460 .callback = set_multi,
2461 .ident = "IBM System Summit2",
2462 .matches = {
2463 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2464 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2465 },
2466 },
2467 {}
2468};
2469
2470static void dmi_check_multi(void)
2471{
2472 if (multi_checked)
2473 return;
2474
2475 dmi_check_system(multi_dmi_table);
2476 multi_checked = 1;
2477}
2478
2479/*
2480 * apic_is_clustered_box() -- Check if we can expect good TSC
2481 *
2482 * Thus far, the major user of this is IBM's Summit2 series:
2483 * Clustered boxes may have unsynced TSC problems if they are
2484 * multi-chassis.
2485 * Use DMI to check them
2486 */
2487int apic_is_clustered_box(void)
2488{
2489 dmi_check_multi();
2490 return multi;
2491}
2492#endif
2493
2494/*
2495 * APIC command line parameters
2496 */
2497static int __init setup_disableapic(char *arg)
2498{
2499 disable_apic = 1;
2500 setup_clear_cpu_cap(X86_FEATURE_APIC);
2501 return 0;
2502}
2503early_param("disableapic", setup_disableapic);
2504
2505/* same as disableapic, for compatibility */
2506static int __init setup_nolapic(char *arg)
2507{
2508 return setup_disableapic(arg);
2509}
2510early_param("nolapic", setup_nolapic);
2511
2512static int __init parse_lapic_timer_c2_ok(char *arg)
2513{
2514 local_apic_timer_c2_ok = 1;
2515 return 0;
2516}
2517early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2518
2519static int __init parse_disable_apic_timer(char *arg)
2520{
2521 disable_apic_timer = 1;
2522 return 0;
2523}
2524early_param("noapictimer", parse_disable_apic_timer);
2525
2526static int __init parse_nolapic_timer(char *arg)
2527{
2528 disable_apic_timer = 1;
2529 return 0;
2530}
2531early_param("nolapic_timer", parse_nolapic_timer);
2532
2533static int __init apic_set_verbosity(char *arg)
2534{
2535 if (!arg) {
2536#ifdef CONFIG_X86_64
2537 skip_ioapic_setup = 0;
2538 return 0;
2539#endif
2540 return -EINVAL;
2541 }
2542
2543 if (strcmp("debug", arg) == 0)
2544 apic_verbosity = APIC_DEBUG;
2545 else if (strcmp("verbose", arg) == 0)
2546 apic_verbosity = APIC_VERBOSE;
2547 else {
2548 pr_warning("APIC Verbosity level %s not recognised"
2549 " use apic=verbose or apic=debug\n", arg);
2550 return -EINVAL;
2551 }
2552
2553 return 0;
2554}
2555early_param("apic", apic_set_verbosity);
2556
2557static int __init lapic_insert_resource(void)
2558{
2559 if (!apic_phys)
2560 return -1;
2561
2562 /* Put local APIC into the resource map. */
2563 lapic_resource.start = apic_phys;
2564 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2565 insert_resource(&iomem_resource, &lapic_resource);
2566
2567 return 0;
2568}
2569
2570/*
2571 * need call insert after e820_reserve_resources()
2572 * that is using request_resource
2573 */
2574late_initcall(lapic_insert_resource);
2575
2576static int __init apic_set_disabled_cpu_apicid(char *arg)
2577{
2578 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2579 return -EINVAL;
2580
2581 return 0;
2582}
2583early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2584
2585static int __init apic_set_extnmi(char *arg)
2586{
2587 if (!arg)
2588 return -EINVAL;
2589
2590 if (!strncmp("all", arg, 3))
2591 apic_extnmi = APIC_EXTNMI_ALL;
2592 else if (!strncmp("none", arg, 4))
2593 apic_extnmi = APIC_EXTNMI_NONE;
2594 else if (!strncmp("bsp", arg, 3))
2595 apic_extnmi = APIC_EXTNMI_BSP;
2596 else {
2597 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2598 return -EINVAL;
2599 }
2600
2601 return 0;
2602}
2603early_param("apic_extnmi", apic_set_extnmi);