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1// SPDX-License-Identifier: GPL-2.0
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm7358";
6
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 mips-hpt-frequency = <375000000>;
12
13 cpu@0 {
14 compatible = "brcm,bmips3300";
15 device_type = "cpu";
16 reg = <0>;
17 };
18 };
19
20 aliases {
21 uart0 = &uart0;
22 };
23
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
27
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 };
31
32 clocks {
33 uart_clk: uart_clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <81000000>;
37 };
38
39 upg_clk: upg_clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <27000000>;
43 };
44 };
45
46 rdb {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
50 compatible = "simple-bus";
51 ranges = <0 0x10000000 0x01000000>;
52
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
55 reg = <0x411400 0x30>;
56
57 interrupt-controller;
58 #interrupt-cells = <1>;
59
60 interrupt-parent = <&cpu_intc>;
61 interrupts = <2>;
62 };
63
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
66 reg = <0x403000 0x30>;
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
70 interrupts = <48>;
71 };
72
73 gisb-arb@400000 {
74 compatible = "brcm,bcm7400-gisb-arb";
75 reg = <0x400000 0xdc>;
76 native-endian;
77 interrupt-parent = <&sun_l2_intc>;
78 interrupts = <0>, <2>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
81 "rdc_0", "raaga_0",
82 "avd_0", "jtag_0";
83 };
84
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
87 reg = <0x406600 0x8>;
88
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
91
92 interrupt-controller;
93 #interrupt-cells = <1>;
94
95 interrupt-parent = <&periph_intc>;
96 interrupts = <56>, <54>;
97 interrupt-names = "upg_main", "upg_bsc";
98 };
99
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
102 reg = <0x408b80 0x8>;
103
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
106 brcm,irq-can-wake;
107
108 interrupt-controller;
109 #interrupt-cells = <1>;
110
111 interrupt-parent = <&periph_intc>;
112 interrupts = <57>, <55>, <59>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
114 "upg_spi";
115 };
116
117 sun_top_ctrl: syscon@404000 {
118 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
119 reg = <0x404000 0x51c>;
120 native-endian;
121 };
122
123 reboot {
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
126 };
127
128 uart0: serial@406800 {
129 compatible = "ns16550a";
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
132 reg-shift = <0x2>;
133 native-endian;
134 interrupt-parent = <&periph_intc>;
135 interrupts = <61>;
136 clocks = <&uart_clk>;
137 status = "disabled";
138 };
139
140 uart1: serial@406840 {
141 compatible = "ns16550a";
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
144 reg-shift = <0x2>;
145 native-endian;
146 interrupt-parent = <&periph_intc>;
147 interrupts = <62>;
148 clocks = <&uart_clk>;
149 status = "disabled";
150 };
151
152 uart2: serial@406880 {
153 compatible = "ns16550a";
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
156 reg-shift = <0x2>;
157 native-endian;
158 interrupt-parent = <&periph_intc>;
159 interrupts = <63>;
160 clocks = <&uart_clk>;
161 status = "disabled";
162 };
163
164 bsca: i2c@406200 {
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
169 interrupts = <24>;
170 interrupt-names = "upg_bsca";
171 status = "disabled";
172 };
173
174 bscb: i2c@406280 {
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
179 interrupts = <25>;
180 interrupt-names = "upg_bscb";
181 status = "disabled";
182 };
183
184 bscc: i2c@406300 {
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
189 interrupts = <26>;
190 interrupt-names = "upg_bscc";
191 status = "disabled";
192 };
193
194 bscd: i2c@408980 {
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x408980 0x58>;
199 interrupts = <27>;
200 interrupt-names = "upg_bscd";
201 status = "disabled";
202 };
203
204 pwma: pwm@406400 {
205 compatible = "brcm,bcm7038-pwm";
206 reg = <0x406400 0x28>;
207 #pwm-cells = <2>;
208 clocks = <&upg_clk>;
209 status = "disabled";
210 };
211
212 pwmb: pwm@406700 {
213 compatible = "brcm,bcm7038-pwm";
214 reg = <0x406700 0x28>;
215 #pwm-cells = <2>;
216 clocks = <&upg_clk>;
217 status = "disabled";
218 };
219
220 watchdog: watchdog@4066a8 {
221 clocks = <&upg_clk>;
222 compatible = "brcm,bcm7038-wdt";
223 reg = <0x4066a8 0x14>;
224 status = "disabled";
225 };
226
227 aon_pm_l2_intc: interrupt-controller@408240 {
228 compatible = "brcm,l2-intc";
229 reg = <0x408240 0x30>;
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 interrupt-parent = <&periph_intc>;
233 interrupts = <50>;
234 brcm,irq-can-wake;
235 };
236
237 upg_gio: gpio@406500 {
238 compatible = "brcm,brcmstb-gpio";
239 reg = <0x406500 0xa0>;
240 #gpio-cells = <2>;
241 #interrupt-cells = <2>;
242 gpio-controller;
243 interrupt-controller;
244 interrupt-parent = <&upg_irq0_intc>;
245 interrupts = <6>;
246 brcm,gpio-bank-widths = <32 32 32 29 4>;
247 };
248
249 upg_gio_aon: gpio@408c00 {
250 compatible = "brcm,brcmstb-gpio";
251 reg = <0x408c00 0x60>;
252 #gpio-cells = <2>;
253 #interrupt-cells = <2>;
254 gpio-controller;
255 interrupt-controller;
256 interrupt-parent = <&upg_aon_irq0_intc>;
257 interrupts = <6>;
258 interrupts-extended = <&upg_aon_irq0_intc 6>,
259 <&aon_pm_l2_intc 5>;
260 wakeup-source;
261 brcm,gpio-bank-widths = <21 32 2>;
262 };
263
264 enet0: ethernet@430000 {
265 phy-mode = "internal";
266 phy-handle = <&phy1>;
267 mac-address = [ 00 10 18 36 23 1a ];
268 compatible = "brcm,genet-v2";
269 #address-cells = <0x1>;
270 #size-cells = <0x1>;
271 reg = <0x430000 0x4c8c>;
272 interrupts = <24>, <25>;
273 interrupt-parent = <&periph_intc>;
274 status = "disabled";
275
276 mdio@e14 {
277 compatible = "brcm,genet-mdio-v2";
278 #address-cells = <0x1>;
279 #size-cells = <0x0>;
280 reg = <0xe14 0x8>;
281
282 phy1: ethernet-phy@1 {
283 max-speed = <100>;
284 reg = <0x1>;
285 compatible = "brcm,40nm-ephy",
286 "ethernet-phy-ieee802.3-c22";
287 };
288 };
289 };
290
291 ehci0: usb@480300 {
292 compatible = "brcm,bcm7358-ehci", "generic-ehci";
293 reg = <0x480300 0x100>;
294 native-endian;
295 interrupt-parent = <&periph_intc>;
296 interrupts = <65>;
297 status = "disabled";
298 };
299
300 ohci0: usb@480400 {
301 compatible = "brcm,bcm7358-ohci", "generic-ohci";
302 reg = <0x480400 0x100>;
303 native-endian;
304 no-big-frame-no;
305 interrupt-parent = <&periph_intc>;
306 interrupts = <66>;
307 status = "disabled";
308 };
309
310 hif_l2_intc: interrupt-controller@411000 {
311 compatible = "brcm,l2-intc";
312 reg = <0x411000 0x30>;
313 interrupt-controller;
314 #interrupt-cells = <1>;
315 interrupt-parent = <&periph_intc>;
316 interrupts = <30>;
317 };
318
319 nand: nand@412800 {
320 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg-names = "nand";
324 reg = <0x412800 0x400>;
325 interrupt-parent = <&hif_l2_intc>;
326 interrupts = <24>;
327 status = "disabled";
328 };
329
330 spi_l2_intc: interrupt-controller@411d00 {
331 compatible = "brcm,l2-intc";
332 reg = <0x411d00 0x30>;
333 interrupt-controller;
334 #interrupt-cells = <1>;
335 interrupt-parent = <&periph_intc>;
336 interrupts = <31>;
337 };
338
339 qspi: spi@413000 {
340 #address-cells = <0x1>;
341 #size-cells = <0x0>;
342 compatible = "brcm,spi-bcm-qspi",
343 "brcm,spi-brcmstb-qspi";
344 clocks = <&upg_clk>;
345 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
346 reg-names = "cs_reg", "hif_mspi", "bspi";
347 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
348 interrupt-parent = <&spi_l2_intc>;
349 interrupt-names = "spi_lr_fullness_reached",
350 "spi_lr_session_aborted",
351 "spi_lr_impatient",
352 "spi_lr_session_done",
353 "spi_lr_overread",
354 "mspi_done",
355 "mspi_halted";
356 status = "disabled";
357 };
358
359 mspi: spi@408a00 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 compatible = "brcm,spi-bcm-qspi",
363 "brcm,spi-brcmstb-mspi";
364 clocks = <&upg_clk>;
365 reg = <0x408a00 0x180>;
366 reg-names = "mspi";
367 interrupts = <0x14>;
368 interrupt-parent = <&upg_aon_irq0_intc>;
369 interrupt-names = "mspi_done";
370 status = "disabled";
371 };
372
373 waketimer: waketimer@408e80 {
374 compatible = "brcm,brcmstb-waketimer";
375 reg = <0x408e80 0x14>;
376 interrupts = <0x3>;
377 interrupt-parent = <&aon_pm_l2_intc>;
378 interrupt-names = "timer";
379 clocks = <&upg_clk>;
380 status = "disabled";
381 };
382 };
383};
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7358";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <375000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips3300";
14 device_type = "cpu";
15 reg = <0>;
16 };
17 };
18
19 aliases {
20 uart0 = &uart0;
21 uart1 = &uart1;
22 uart2 = &uart2;
23 };
24
25 cpu_intc: cpu_intc {
26 #address-cells = <0>;
27 compatible = "mti,cpu-interrupt-controller";
28
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 };
32
33 clocks {
34 uart_clk: uart_clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <81000000>;
38 };
39 };
40
41 rdb {
42 #address-cells = <1>;
43 #size-cells = <1>;
44
45 compatible = "simple-bus";
46 ranges = <0 0x10000000 0x01000000>;
47
48 periph_intc: periph_intc@411400 {
49 compatible = "brcm,bcm7038-l1-intc";
50 reg = <0x411400 0x30>;
51
52 interrupt-controller;
53 #interrupt-cells = <1>;
54
55 interrupt-parent = <&cpu_intc>;
56 interrupts = <2>;
57 };
58
59 sun_l2_intc: sun_l2_intc@403000 {
60 compatible = "brcm,l2-intc";
61 reg = <0x403000 0x30>;
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 interrupt-parent = <&periph_intc>;
65 interrupts = <48>;
66 };
67
68 gisb-arb@400000 {
69 compatible = "brcm,bcm7400-gisb-arb";
70 reg = <0x400000 0xdc>;
71 native-endian;
72 interrupt-parent = <&sun_l2_intc>;
73 interrupts = <0>, <2>;
74 brcm,gisb-arb-master-mask = <0x2f3>;
75 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
76 "rdc_0", "raaga_0",
77 "avd_0", "jtag_0";
78 };
79
80 upg_irq0_intc: upg_irq0_intc@406600 {
81 compatible = "brcm,bcm7120-l2-intc";
82 reg = <0x406600 0x8>;
83
84 brcm,int-map-mask = <0x44>, <0x7000000>;
85 brcm,int-fwd-mask = <0x70000>;
86
87 interrupt-controller;
88 #interrupt-cells = <1>;
89
90 interrupt-parent = <&periph_intc>;
91 interrupts = <56>, <54>;
92 interrupt-names = "upg_main", "upg_bsc";
93 };
94
95 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
96 compatible = "brcm,bcm7120-l2-intc";
97 reg = <0x408b80 0x8>;
98
99 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
100 brcm,int-fwd-mask = <0>;
101 brcm,irq-can-wake;
102
103 interrupt-controller;
104 #interrupt-cells = <1>;
105
106 interrupt-parent = <&periph_intc>;
107 interrupts = <57>, <55>, <59>;
108 interrupt-names = "upg_main_aon", "upg_bsc_aon",
109 "upg_spi";
110 };
111
112 sun_top_ctrl: syscon@404000 {
113 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
114 reg = <0x404000 0x51c>;
115 native-endian;
116 };
117
118 reboot {
119 compatible = "brcm,brcmstb-reboot";
120 syscon = <&sun_top_ctrl 0x304 0x308>;
121 };
122
123 uart0: serial@406800 {
124 compatible = "ns16550a";
125 reg = <0x406800 0x20>;
126 reg-io-width = <0x4>;
127 reg-shift = <0x2>;
128 native-endian;
129 interrupt-parent = <&periph_intc>;
130 interrupts = <61>;
131 clocks = <&uart_clk>;
132 status = "disabled";
133 };
134
135 uart1: serial@406840 {
136 compatible = "ns16550a";
137 reg = <0x406840 0x20>;
138 reg-io-width = <0x4>;
139 reg-shift = <0x2>;
140 native-endian;
141 interrupt-parent = <&periph_intc>;
142 interrupts = <62>;
143 clocks = <&uart_clk>;
144 status = "disabled";
145 };
146
147 uart2: serial@406880 {
148 compatible = "ns16550a";
149 reg = <0x406880 0x20>;
150 reg-io-width = <0x4>;
151 reg-shift = <0x2>;
152 native-endian;
153 interrupt-parent = <&periph_intc>;
154 interrupts = <63>;
155 clocks = <&uart_clk>;
156 status = "disabled";
157 };
158
159 bsca: i2c@406200 {
160 clock-frequency = <390000>;
161 compatible = "brcm,brcmstb-i2c";
162 interrupt-parent = <&upg_irq0_intc>;
163 reg = <0x406200 0x58>;
164 interrupts = <24>;
165 interrupt-names = "upg_bsca";
166 status = "disabled";
167 };
168
169 bscb: i2c@406280 {
170 clock-frequency = <390000>;
171 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg_irq0_intc>;
173 reg = <0x406280 0x58>;
174 interrupts = <25>;
175 interrupt-names = "upg_bscb";
176 status = "disabled";
177 };
178
179 bscc: i2c@406300 {
180 clock-frequency = <390000>;
181 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg_irq0_intc>;
183 reg = <0x406300 0x58>;
184 interrupts = <26>;
185 interrupt-names = "upg_bscc";
186 status = "disabled";
187 };
188
189 bscd: i2c@408980 {
190 clock-frequency = <390000>;
191 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg_aon_irq0_intc>;
193 reg = <0x408980 0x58>;
194 interrupts = <27>;
195 interrupt-names = "upg_bscd";
196 status = "disabled";
197 };
198
199 enet0: ethernet@430000 {
200 phy-mode = "internal";
201 phy-handle = <&phy1>;
202 mac-address = [ 00 10 18 36 23 1a ];
203 compatible = "brcm,genet-v2";
204 #address-cells = <0x1>;
205 #size-cells = <0x1>;
206 reg = <0x430000 0x4c8c>;
207 interrupts = <24>, <25>;
208 interrupt-parent = <&periph_intc>;
209 status = "disabled";
210
211 mdio@e14 {
212 compatible = "brcm,genet-mdio-v2";
213 #address-cells = <0x1>;
214 #size-cells = <0x0>;
215 reg = <0xe14 0x8>;
216
217 phy1: ethernet-phy@1 {
218 max-speed = <100>;
219 reg = <0x1>;
220 compatible = "brcm,40nm-ephy",
221 "ethernet-phy-ieee802.3-c22";
222 };
223 };
224 };
225
226 ehci0: usb@480300 {
227 compatible = "brcm,bcm7358-ehci", "generic-ehci";
228 reg = <0x480300 0x100>;
229 native-endian;
230 interrupt-parent = <&periph_intc>;
231 interrupts = <65>;
232 status = "disabled";
233 };
234
235 ohci0: usb@480400 {
236 compatible = "brcm,bcm7358-ohci", "generic-ohci";
237 reg = <0x480400 0x100>;
238 native-endian;
239 no-big-frame-no;
240 interrupt-parent = <&periph_intc>;
241 interrupts = <66>;
242 status = "disabled";
243 };
244 };
245};