1/*
  2 * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
  3 *
  4 * Copyright 2004-2008 Analog Devices Inc.
  5 *
  6 * Licensed under the GPL-2 or later.
  7 */
  8
  9#include <linux/linkage.h>
 10#include <asm/blackfin.h>
 11
 12#include <asm/dma.h>
 13#include <asm/clocks.h>
 14#include <asm/mem_init.h>
 15#include <asm/dpmc.h>
 16
 17#ifdef CONFIG_BF60x
 18
 19#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
 20#define CGU_DIV_VAL \
 21	((CONFIG_CCLK_DIV   << CSEL_OFFSET)   | \
 22	(CONFIG_SCLK_DIV << SYSSEL_OFFSET)   | \
 23	(CONFIG_SCLK0_DIV  << S0SEL_OFFSET)  | \
 24	(CONFIG_SCLK1_DIV  << S1SEL_OFFSET)  | \
 25	(CONFIG_DCLK_DIV   << DSEL_OFFSET))
 26
 27#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
 28#if ((CONFIG_BFIN_DCLK != 125) && \
 29	(CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
 30	(CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
 31	(CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
 32#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
 33#endif
 34
 35#else
 36#define SDGCTL_WIDTH (1 << 31)	/* SDRAM external data path width */
 37#define PLL_CTL_VAL \
 38	(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
 39		(PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
 40#endif
 41
 42__attribute__((l1_text))
 43static void do_sync(void)
 44{
 45	__builtin_bfin_ssync();
 46}
 47
 48__attribute__((l1_text))
 49void init_clocks(void)
 50{
 51	/* Kill any active DMAs as they may trigger external memory accesses
 52	 * in the middle of reprogramming things, and that'll screw us up.
 53	 * For example, any automatic DMAs left by U-Boot for splash screens.
 54	 */
 55#ifdef CONFIG_BF60x
 56	init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
 57	init_dmc(CONFIG_BFIN_DCLK);
 58#else
 59	size_t i;
 60	for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
 61		struct dma_register *dma = dma_io_base_addr[i];
 62		dma->cfg = 0;
 63	}
 64
 65	do_sync();
 66
 67#ifdef SIC_IWR0
 68	bfin_write_SIC_IWR0(IWR_ENABLE(0));
 69# ifdef SIC_IWR1
 70	/* BF52x system reset does not properly reset SIC_IWR1 which
 71	 * will screw up the bootrom as it relies on MDMA0/1 waking it
 72	 * up from IDLE instructions.  See this report for more info:
 73	 * http://blackfin.uclinux.org/gf/tracker/4323
 74	 */
 75	if (ANOMALY_05000435)
 76		bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
 77	else
 78		bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 79# endif
 80# ifdef SIC_IWR2
 81	bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 82# endif
 83#else
 84	bfin_write_SIC_IWR(IWR_ENABLE(0));
 85#endif
 86	do_sync();
 87#ifdef EBIU_SDGCTL
 88	bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 89	do_sync();
 90#endif
 91
 92#ifdef CLKBUFOE
 93	bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
 94	do_sync();
 95	__asm__ __volatile__("IDLE;");
 96#endif
 97	bfin_write_PLL_LOCKCNT(0x300);
 98	do_sync();
 99	/* We always write PLL_CTL thus avoiding Anomaly 05000242 */
100	bfin_write16(PLL_CTL, PLL_CTL_VAL);
101	__asm__ __volatile__("IDLE;");
102	bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
103#ifdef EBIU_SDGCTL
104	bfin_write_EBIU_SDRRC(mem_SDRRC);
105	bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
106#else
107	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
108	do_sync();
109	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
110	bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
111	bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
112	bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
113#ifdef CONFIG_MEM_EBIU_DDRQUE
114	bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
115#endif
116#endif
117#endif
118	do_sync();
119	bfin_read16(0);
120
121}