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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * CoreTile Express A15x2 A7x3
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
7 *
8 * HBI-0249A
9 */
10
11/dts-v1/;
12
13/ {
14 model = "V2P-CA15_CA7";
15 arm,hbi = <0x249>;
16 arm,vexpress,site = <0xf>;
17 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 chosen { };
23
24 aliases {
25 serial0 = &v2m_serial0;
26 serial1 = &v2m_serial1;
27 serial2 = &v2m_serial2;
28 serial3 = &v2m_serial3;
29 i2c0 = &v2m_i2c_dvi;
30 i2c1 = &v2m_i2c_pcie;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu0: cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a15";
40 reg = <0>;
41 cci-control-port = <&cci_control1>;
42 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
43 capacity-dmips-mhz = <1024>;
44 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <1>;
50 cci-control-port = <&cci_control1>;
51 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
52 capacity-dmips-mhz = <1024>;
53 };
54
55 cpu2: cpu@2 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <0x100>;
59 cci-control-port = <&cci_control2>;
60 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
61 capacity-dmips-mhz = <516>;
62 };
63
64 cpu3: cpu@3 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0x101>;
68 cci-control-port = <&cci_control2>;
69 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
70 capacity-dmips-mhz = <516>;
71 };
72
73 cpu4: cpu@4 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a7";
76 reg = <0x102>;
77 cci-control-port = <&cci_control2>;
78 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
79 capacity-dmips-mhz = <516>;
80 };
81
82 idle-states {
83 CLUSTER_SLEEP_BIG: cluster-sleep-big {
84 compatible = "arm,idle-state";
85 local-timer-stop;
86 entry-latency-us = <1000>;
87 exit-latency-us = <700>;
88 min-residency-us = <2000>;
89 };
90
91 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
92 compatible = "arm,idle-state";
93 local-timer-stop;
94 entry-latency-us = <1000>;
95 exit-latency-us = <500>;
96 min-residency-us = <2500>;
97 };
98 };
99 };
100
101 memory@80000000 {
102 device_type = "memory";
103 reg = <0 0x80000000 0 0x40000000>;
104 };
105
106 wdt@2a490000 {
107 compatible = "arm,sp805", "arm,primecell";
108 reg = <0 0x2a490000 0 0x1000>;
109 interrupts = <0 98 4>;
110 clocks = <&oscclk6a>, <&oscclk6a>;
111 clock-names = "wdogclk", "apb_pclk";
112 };
113
114 hdlcd@2b000000 {
115 compatible = "arm,hdlcd";
116 reg = <0 0x2b000000 0 0x1000>;
117 interrupts = <0 85 4>;
118 clocks = <&hdlcd_clk>;
119 clock-names = "pxlclk";
120 };
121
122 memory-controller@2b0a0000 {
123 compatible = "arm,pl341", "arm,primecell";
124 reg = <0 0x2b0a0000 0 0x1000>;
125 clocks = <&oscclk6a>;
126 clock-names = "apb_pclk";
127 };
128
129 gic: interrupt-controller@2c001000 {
130 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
131 #interrupt-cells = <3>;
132 #address-cells = <0>;
133 interrupt-controller;
134 reg = <0 0x2c001000 0 0x1000>,
135 <0 0x2c002000 0 0x2000>,
136 <0 0x2c004000 0 0x2000>,
137 <0 0x2c006000 0 0x2000>;
138 interrupts = <1 9 0xf04>;
139 };
140
141 cci@2c090000 {
142 compatible = "arm,cci-400";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 reg = <0 0x2c090000 0 0x1000>;
146 ranges = <0x0 0x0 0x2c090000 0x10000>;
147
148 cci_control1: slave-if@4000 {
149 compatible = "arm,cci-400-ctrl-if";
150 interface-type = "ace";
151 reg = <0x4000 0x1000>;
152 };
153
154 cci_control2: slave-if@5000 {
155 compatible = "arm,cci-400-ctrl-if";
156 interface-type = "ace";
157 reg = <0x5000 0x1000>;
158 };
159
160 pmu@9000 {
161 compatible = "arm,cci-400-pmu,r0";
162 reg = <0x9000 0x5000>;
163 interrupts = <0 105 4>,
164 <0 101 4>,
165 <0 102 4>,
166 <0 103 4>,
167 <0 104 4>;
168 };
169 };
170
171 memory-controller@7ffd0000 {
172 compatible = "arm,pl354", "arm,primecell";
173 reg = <0 0x7ffd0000 0 0x1000>;
174 interrupts = <0 86 4>,
175 <0 87 4>;
176 clocks = <&oscclk6a>;
177 clock-names = "apb_pclk";
178 };
179
180 dma@7ff00000 {
181 compatible = "arm,pl330", "arm,primecell";
182 reg = <0 0x7ff00000 0 0x1000>;
183 interrupts = <0 92 4>,
184 <0 88 4>,
185 <0 89 4>,
186 <0 90 4>,
187 <0 91 4>;
188 clocks = <&oscclk6a>;
189 clock-names = "apb_pclk";
190 };
191
192 scc@7fff0000 {
193 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
194 reg = <0 0x7fff0000 0 0x1000>;
195 interrupts = <0 95 4>;
196 };
197
198 timer {
199 compatible = "arm,armv7-timer";
200 interrupts = <1 13 0xf08>,
201 <1 14 0xf08>,
202 <1 11 0xf08>,
203 <1 10 0xf08>;
204 };
205
206 pmu_a15 {
207 compatible = "arm,cortex-a15-pmu";
208 interrupts = <0 68 4>,
209 <0 69 4>;
210 interrupt-affinity = <&cpu0>,
211 <&cpu1>;
212 };
213
214 pmu_a7 {
215 compatible = "arm,cortex-a7-pmu";
216 interrupts = <0 128 4>,
217 <0 129 4>,
218 <0 130 4>;
219 interrupt-affinity = <&cpu2>,
220 <&cpu3>,
221 <&cpu4>;
222 };
223
224 oscclk6a: oscclk6a {
225 /* Reference 24MHz clock */
226 compatible = "fixed-clock";
227 #clock-cells = <0>;
228 clock-frequency = <24000000>;
229 clock-output-names = "oscclk6a";
230 };
231
232 dcc {
233 compatible = "arm,vexpress,config-bus";
234 arm,vexpress,config-bridge = <&v2m_sysreg>;
235
236 oscclk0 {
237 /* A15 PLL 0 reference clock */
238 compatible = "arm,vexpress-osc";
239 arm,vexpress-sysreg,func = <1 0>;
240 freq-range = <17000000 50000000>;
241 #clock-cells = <0>;
242 clock-output-names = "oscclk0";
243 };
244
245 oscclk1 {
246 /* A15 PLL 1 reference clock */
247 compatible = "arm,vexpress-osc";
248 arm,vexpress-sysreg,func = <1 1>;
249 freq-range = <17000000 50000000>;
250 #clock-cells = <0>;
251 clock-output-names = "oscclk1";
252 };
253
254 oscclk2 {
255 /* A7 PLL 0 reference clock */
256 compatible = "arm,vexpress-osc";
257 arm,vexpress-sysreg,func = <1 2>;
258 freq-range = <17000000 50000000>;
259 #clock-cells = <0>;
260 clock-output-names = "oscclk2";
261 };
262
263 oscclk3 {
264 /* A7 PLL 1 reference clock */
265 compatible = "arm,vexpress-osc";
266 arm,vexpress-sysreg,func = <1 3>;
267 freq-range = <17000000 50000000>;
268 #clock-cells = <0>;
269 clock-output-names = "oscclk3";
270 };
271
272 oscclk4 {
273 /* External AXI master clock */
274 compatible = "arm,vexpress-osc";
275 arm,vexpress-sysreg,func = <1 4>;
276 freq-range = <20000000 40000000>;
277 #clock-cells = <0>;
278 clock-output-names = "oscclk4";
279 };
280
281 hdlcd_clk: oscclk5 {
282 /* HDLCD PLL reference clock */
283 compatible = "arm,vexpress-osc";
284 arm,vexpress-sysreg,func = <1 5>;
285 freq-range = <23750000 165000000>;
286 #clock-cells = <0>;
287 clock-output-names = "oscclk5";
288 };
289
290 smbclk: oscclk6 {
291 /* Static memory controller clock */
292 compatible = "arm,vexpress-osc";
293 arm,vexpress-sysreg,func = <1 6>;
294 freq-range = <20000000 40000000>;
295 #clock-cells = <0>;
296 clock-output-names = "oscclk6";
297 };
298
299 oscclk7 {
300 /* SYS PLL reference clock */
301 compatible = "arm,vexpress-osc";
302 arm,vexpress-sysreg,func = <1 7>;
303 freq-range = <17000000 50000000>;
304 #clock-cells = <0>;
305 clock-output-names = "oscclk7";
306 };
307
308 oscclk8 {
309 /* DDR2 PLL reference clock */
310 compatible = "arm,vexpress-osc";
311 arm,vexpress-sysreg,func = <1 8>;
312 freq-range = <20000000 50000000>;
313 #clock-cells = <0>;
314 clock-output-names = "oscclk8";
315 };
316
317 volt-a15 {
318 /* A15 CPU core voltage */
319 compatible = "arm,vexpress-volt";
320 arm,vexpress-sysreg,func = <2 0>;
321 regulator-name = "A15 Vcore";
322 regulator-min-microvolt = <800000>;
323 regulator-max-microvolt = <1050000>;
324 regulator-always-on;
325 label = "A15 Vcore";
326 };
327
328 volt-a7 {
329 /* A7 CPU core voltage */
330 compatible = "arm,vexpress-volt";
331 arm,vexpress-sysreg,func = <2 1>;
332 regulator-name = "A7 Vcore";
333 regulator-min-microvolt = <800000>;
334 regulator-max-microvolt = <1050000>;
335 regulator-always-on;
336 label = "A7 Vcore";
337 };
338
339 amp-a15 {
340 /* Total current for the two A15 cores */
341 compatible = "arm,vexpress-amp";
342 arm,vexpress-sysreg,func = <3 0>;
343 label = "A15 Icore";
344 };
345
346 amp-a7 {
347 /* Total current for the three A7 cores */
348 compatible = "arm,vexpress-amp";
349 arm,vexpress-sysreg,func = <3 1>;
350 label = "A7 Icore";
351 };
352
353 temp-dcc {
354 /* DCC internal temperature */
355 compatible = "arm,vexpress-temp";
356 arm,vexpress-sysreg,func = <4 0>;
357 label = "DCC";
358 };
359
360 power-a15 {
361 /* Total power for the two A15 cores */
362 compatible = "arm,vexpress-power";
363 arm,vexpress-sysreg,func = <12 0>;
364 label = "A15 Pcore";
365 };
366
367 power-a7 {
368 /* Total power for the three A7 cores */
369 compatible = "arm,vexpress-power";
370 arm,vexpress-sysreg,func = <12 1>;
371 label = "A7 Pcore";
372 };
373
374 energy-a15 {
375 /* Total energy for the two A15 cores */
376 compatible = "arm,vexpress-energy";
377 arm,vexpress-sysreg,func = <13 0>, <13 1>;
378 label = "A15 Jcore";
379 };
380
381 energy-a7 {
382 /* Total energy for the three A7 cores */
383 compatible = "arm,vexpress-energy";
384 arm,vexpress-sysreg,func = <13 2>, <13 3>;
385 label = "A7 Jcore";
386 };
387 };
388
389 etb@20010000 {
390 compatible = "arm,coresight-etb10", "arm,primecell";
391 reg = <0 0x20010000 0 0x1000>;
392
393 clocks = <&oscclk6a>;
394 clock-names = "apb_pclk";
395 port {
396 etb_in_port: endpoint {
397 slave-mode;
398 remote-endpoint = <&replicator_out_port0>;
399 };
400 };
401 };
402
403 tpiu@20030000 {
404 compatible = "arm,coresight-tpiu", "arm,primecell";
405 reg = <0 0x20030000 0 0x1000>;
406
407 clocks = <&oscclk6a>;
408 clock-names = "apb_pclk";
409 port {
410 tpiu_in_port: endpoint {
411 slave-mode;
412 remote-endpoint = <&replicator_out_port1>;
413 };
414 };
415 };
416
417 replicator {
418 /* non-configurable replicators don't show up on the
419 * AMBA bus. As such no need to add "arm,primecell".
420 */
421 compatible = "arm,coresight-replicator";
422
423 ports {
424 #address-cells = <1>;
425 #size-cells = <0>;
426
427 /* replicator output ports */
428 port@0 {
429 reg = <0>;
430 replicator_out_port0: endpoint {
431 remote-endpoint = <&etb_in_port>;
432 };
433 };
434
435 port@1 {
436 reg = <1>;
437 replicator_out_port1: endpoint {
438 remote-endpoint = <&tpiu_in_port>;
439 };
440 };
441
442 /* replicator input port */
443 port@2 {
444 reg = <0>;
445 replicator_in_port0: endpoint {
446 slave-mode;
447 remote-endpoint = <&funnel_out_port0>;
448 };
449 };
450 };
451 };
452
453 funnel@20040000 {
454 compatible = "arm,coresight-funnel", "arm,primecell";
455 reg = <0 0x20040000 0 0x1000>;
456
457 clocks = <&oscclk6a>;
458 clock-names = "apb_pclk";
459 ports {
460 #address-cells = <1>;
461 #size-cells = <0>;
462
463 /* funnel output port */
464 port@0 {
465 reg = <0>;
466 funnel_out_port0: endpoint {
467 remote-endpoint =
468 <&replicator_in_port0>;
469 };
470 };
471
472 /* funnel input ports */
473 port@1 {
474 reg = <0>;
475 funnel_in_port0: endpoint {
476 slave-mode;
477 remote-endpoint = <&ptm0_out_port>;
478 };
479 };
480
481 port@2 {
482 reg = <1>;
483 funnel_in_port1: endpoint {
484 slave-mode;
485 remote-endpoint = <&ptm1_out_port>;
486 };
487 };
488
489 port@3 {
490 reg = <2>;
491 funnel_in_port2: endpoint {
492 slave-mode;
493 remote-endpoint = <&etm0_out_port>;
494 };
495 };
496
497 /* Input port #3 is for ITM, not supported here */
498
499 port@4 {
500 reg = <4>;
501 funnel_in_port4: endpoint {
502 slave-mode;
503 remote-endpoint = <&etm1_out_port>;
504 };
505 };
506
507 port@5 {
508 reg = <5>;
509 funnel_in_port5: endpoint {
510 slave-mode;
511 remote-endpoint = <&etm2_out_port>;
512 };
513 };
514 };
515 };
516
517 ptm@2201c000 {
518 compatible = "arm,coresight-etm3x", "arm,primecell";
519 reg = <0 0x2201c000 0 0x1000>;
520
521 cpu = <&cpu0>;
522 clocks = <&oscclk6a>;
523 clock-names = "apb_pclk";
524 port {
525 ptm0_out_port: endpoint {
526 remote-endpoint = <&funnel_in_port0>;
527 };
528 };
529 };
530
531 ptm@2201d000 {
532 compatible = "arm,coresight-etm3x", "arm,primecell";
533 reg = <0 0x2201d000 0 0x1000>;
534
535 cpu = <&cpu1>;
536 clocks = <&oscclk6a>;
537 clock-names = "apb_pclk";
538 port {
539 ptm1_out_port: endpoint {
540 remote-endpoint = <&funnel_in_port1>;
541 };
542 };
543 };
544
545 etm@2203c000 {
546 compatible = "arm,coresight-etm3x", "arm,primecell";
547 reg = <0 0x2203c000 0 0x1000>;
548
549 cpu = <&cpu2>;
550 clocks = <&oscclk6a>;
551 clock-names = "apb_pclk";
552 port {
553 etm0_out_port: endpoint {
554 remote-endpoint = <&funnel_in_port2>;
555 };
556 };
557 };
558
559 etm@2203d000 {
560 compatible = "arm,coresight-etm3x", "arm,primecell";
561 reg = <0 0x2203d000 0 0x1000>;
562
563 cpu = <&cpu3>;
564 clocks = <&oscclk6a>;
565 clock-names = "apb_pclk";
566 port {
567 etm1_out_port: endpoint {
568 remote-endpoint = <&funnel_in_port4>;
569 };
570 };
571 };
572
573 etm@2203e000 {
574 compatible = "arm,coresight-etm3x", "arm,primecell";
575 reg = <0 0x2203e000 0 0x1000>;
576
577 cpu = <&cpu4>;
578 clocks = <&oscclk6a>;
579 clock-names = "apb_pclk";
580 port {
581 etm2_out_port: endpoint {
582 remote-endpoint = <&funnel_in_port5>;
583 };
584 };
585 };
586
587 smb@8000000 {
588 compatible = "simple-bus";
589
590 #address-cells = <2>;
591 #size-cells = <1>;
592 ranges = <0 0 0 0x08000000 0x04000000>,
593 <1 0 0 0x14000000 0x04000000>,
594 <2 0 0 0x18000000 0x04000000>,
595 <3 0 0 0x1c000000 0x04000000>,
596 <4 0 0 0x0c000000 0x04000000>,
597 <5 0 0 0x10000000 0x04000000>;
598
599 #interrupt-cells = <1>;
600 interrupt-map-mask = <0 0 63>;
601 interrupt-map = <0 0 0 &gic 0 0 4>,
602 <0 0 1 &gic 0 1 4>,
603 <0 0 2 &gic 0 2 4>,
604 <0 0 3 &gic 0 3 4>,
605 <0 0 4 &gic 0 4 4>,
606 <0 0 5 &gic 0 5 4>,
607 <0 0 6 &gic 0 6 4>,
608 <0 0 7 &gic 0 7 4>,
609 <0 0 8 &gic 0 8 4>,
610 <0 0 9 &gic 0 9 4>,
611 <0 0 10 &gic 0 10 4>,
612 <0 0 11 &gic 0 11 4>,
613 <0 0 12 &gic 0 12 4>,
614 <0 0 13 &gic 0 13 4>,
615 <0 0 14 &gic 0 14 4>,
616 <0 0 15 &gic 0 15 4>,
617 <0 0 16 &gic 0 16 4>,
618 <0 0 17 &gic 0 17 4>,
619 <0 0 18 &gic 0 18 4>,
620 <0 0 19 &gic 0 19 4>,
621 <0 0 20 &gic 0 20 4>,
622 <0 0 21 &gic 0 21 4>,
623 <0 0 22 &gic 0 22 4>,
624 <0 0 23 &gic 0 23 4>,
625 <0 0 24 &gic 0 24 4>,
626 <0 0 25 &gic 0 25 4>,
627 <0 0 26 &gic 0 26 4>,
628 <0 0 27 &gic 0 27 4>,
629 <0 0 28 &gic 0 28 4>,
630 <0 0 29 &gic 0 29 4>,
631 <0 0 30 &gic 0 30 4>,
632 <0 0 31 &gic 0 31 4>,
633 <0 0 32 &gic 0 32 4>,
634 <0 0 33 &gic 0 33 4>,
635 <0 0 34 &gic 0 34 4>,
636 <0 0 35 &gic 0 35 4>,
637 <0 0 36 &gic 0 36 4>,
638 <0 0 37 &gic 0 37 4>,
639 <0 0 38 &gic 0 38 4>,
640 <0 0 39 &gic 0 39 4>,
641 <0 0 40 &gic 0 40 4>,
642 <0 0 41 &gic 0 41 4>,
643 <0 0 42 &gic 0 42 4>;
644
645 /include/ "vexpress-v2m-rs1.dtsi"
646 };
647
648 site2: hsb@40000000 {
649 compatible = "simple-bus";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 ranges = <0 0 0x40000000 0x3fef0000>;
653 #interrupt-cells = <1>;
654 interrupt-map-mask = <0 3>;
655 interrupt-map = <0 0 &gic 0 36 4>,
656 <0 1 &gic 0 37 4>,
657 <0 2 &gic 0 38 4>,
658 <0 3 &gic 0 39 4>;
659 };
660};
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 cci-control-port = <&cci_control1>;
41 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
42 };
43
44 cpu1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a15";
47 reg = <1>;
48 cci-control-port = <&cci_control1>;
49 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
50 };
51
52 cpu2: cpu@2 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0x100>;
56 cci-control-port = <&cci_control2>;
57 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
58 };
59
60 cpu3: cpu@3 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0x101>;
64 cci-control-port = <&cci_control2>;
65 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
66 };
67
68 cpu4: cpu@4 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a7";
71 reg = <0x102>;
72 cci-control-port = <&cci_control2>;
73 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
74 };
75
76 idle-states {
77 CLUSTER_SLEEP_BIG: cluster-sleep-big {
78 compatible = "arm,idle-state";
79 local-timer-stop;
80 entry-latency-us = <1000>;
81 exit-latency-us = <700>;
82 min-residency-us = <2000>;
83 };
84
85 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
86 compatible = "arm,idle-state";
87 local-timer-stop;
88 entry-latency-us = <1000>;
89 exit-latency-us = <500>;
90 min-residency-us = <2500>;
91 };
92 };
93 };
94
95 memory@80000000 {
96 device_type = "memory";
97 reg = <0 0x80000000 0 0x40000000>;
98 };
99
100 wdt@2a490000 {
101 compatible = "arm,sp805", "arm,primecell";
102 reg = <0 0x2a490000 0 0x1000>;
103 interrupts = <0 98 4>;
104 clocks = <&oscclk6a>, <&oscclk6a>;
105 clock-names = "wdogclk", "apb_pclk";
106 };
107
108 hdlcd@2b000000 {
109 compatible = "arm,hdlcd";
110 reg = <0 0x2b000000 0 0x1000>;
111 interrupts = <0 85 4>;
112 clocks = <&oscclk5>;
113 clock-names = "pxlclk";
114 };
115
116 memory-controller@2b0a0000 {
117 compatible = "arm,pl341", "arm,primecell";
118 reg = <0 0x2b0a0000 0 0x1000>;
119 clocks = <&oscclk6a>;
120 clock-names = "apb_pclk";
121 };
122
123 gic: interrupt-controller@2c001000 {
124 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 #address-cells = <0>;
127 interrupt-controller;
128 reg = <0 0x2c001000 0 0x1000>,
129 <0 0x2c002000 0 0x1000>,
130 <0 0x2c004000 0 0x2000>,
131 <0 0x2c006000 0 0x2000>;
132 interrupts = <1 9 0xf04>;
133 };
134
135 cci@2c090000 {
136 compatible = "arm,cci-400";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 reg = <0 0x2c090000 0 0x1000>;
140 ranges = <0x0 0x0 0x2c090000 0x10000>;
141
142 cci_control1: slave-if@4000 {
143 compatible = "arm,cci-400-ctrl-if";
144 interface-type = "ace";
145 reg = <0x4000 0x1000>;
146 };
147
148 cci_control2: slave-if@5000 {
149 compatible = "arm,cci-400-ctrl-if";
150 interface-type = "ace";
151 reg = <0x5000 0x1000>;
152 };
153
154 pmu@9000 {
155 compatible = "arm,cci-400-pmu,r0";
156 reg = <0x9000 0x5000>;
157 interrupts = <0 105 4>,
158 <0 101 4>,
159 <0 102 4>,
160 <0 103 4>,
161 <0 104 4>;
162 };
163 };
164
165 memory-controller@7ffd0000 {
166 compatible = "arm,pl354", "arm,primecell";
167 reg = <0 0x7ffd0000 0 0x1000>;
168 interrupts = <0 86 4>,
169 <0 87 4>;
170 clocks = <&oscclk6a>;
171 clock-names = "apb_pclk";
172 };
173
174 dma@7ff00000 {
175 compatible = "arm,pl330", "arm,primecell";
176 reg = <0 0x7ff00000 0 0x1000>;
177 interrupts = <0 92 4>,
178 <0 88 4>,
179 <0 89 4>,
180 <0 90 4>,
181 <0 91 4>;
182 clocks = <&oscclk6a>;
183 clock-names = "apb_pclk";
184 };
185
186 scc@7fff0000 {
187 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
188 reg = <0 0x7fff0000 0 0x1000>;
189 interrupts = <0 95 4>;
190 };
191
192 timer {
193 compatible = "arm,armv7-timer";
194 interrupts = <1 13 0xf08>,
195 <1 14 0xf08>,
196 <1 11 0xf08>,
197 <1 10 0xf08>;
198 };
199
200 pmu_a15 {
201 compatible = "arm,cortex-a15-pmu";
202 interrupts = <0 68 4>,
203 <0 69 4>;
204 interrupt-affinity = <&cpu0>,
205 <&cpu1>;
206 };
207
208 pmu_a7 {
209 compatible = "arm,cortex-a7-pmu";
210 interrupts = <0 128 4>,
211 <0 129 4>,
212 <0 130 4>;
213 interrupt-affinity = <&cpu2>,
214 <&cpu3>,
215 <&cpu4>;
216 };
217
218 oscclk6a: oscclk6a {
219 /* Reference 24MHz clock */
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <24000000>;
223 clock-output-names = "oscclk6a";
224 };
225
226 dcc {
227 compatible = "arm,vexpress,config-bus";
228 arm,vexpress,config-bridge = <&v2m_sysreg>;
229
230 osc@0 {
231 /* A15 PLL 0 reference clock */
232 compatible = "arm,vexpress-osc";
233 arm,vexpress-sysreg,func = <1 0>;
234 freq-range = <17000000 50000000>;
235 #clock-cells = <0>;
236 clock-output-names = "oscclk0";
237 };
238
239 osc@1 {
240 /* A15 PLL 1 reference clock */
241 compatible = "arm,vexpress-osc";
242 arm,vexpress-sysreg,func = <1 1>;
243 freq-range = <17000000 50000000>;
244 #clock-cells = <0>;
245 clock-output-names = "oscclk1";
246 };
247
248 osc@2 {
249 /* A7 PLL 0 reference clock */
250 compatible = "arm,vexpress-osc";
251 arm,vexpress-sysreg,func = <1 2>;
252 freq-range = <17000000 50000000>;
253 #clock-cells = <0>;
254 clock-output-names = "oscclk2";
255 };
256
257 osc@3 {
258 /* A7 PLL 1 reference clock */
259 compatible = "arm,vexpress-osc";
260 arm,vexpress-sysreg,func = <1 3>;
261 freq-range = <17000000 50000000>;
262 #clock-cells = <0>;
263 clock-output-names = "oscclk3";
264 };
265
266 osc@4 {
267 /* External AXI master clock */
268 compatible = "arm,vexpress-osc";
269 arm,vexpress-sysreg,func = <1 4>;
270 freq-range = <20000000 40000000>;
271 #clock-cells = <0>;
272 clock-output-names = "oscclk4";
273 };
274
275 oscclk5: osc@5 {
276 /* HDLCD PLL reference clock */
277 compatible = "arm,vexpress-osc";
278 arm,vexpress-sysreg,func = <1 5>;
279 freq-range = <23750000 165000000>;
280 #clock-cells = <0>;
281 clock-output-names = "oscclk5";
282 };
283
284 smbclk: osc@6 {
285 /* Static memory controller clock */
286 compatible = "arm,vexpress-osc";
287 arm,vexpress-sysreg,func = <1 6>;
288 freq-range = <20000000 40000000>;
289 #clock-cells = <0>;
290 clock-output-names = "oscclk6";
291 };
292
293 osc@7 {
294 /* SYS PLL reference clock */
295 compatible = "arm,vexpress-osc";
296 arm,vexpress-sysreg,func = <1 7>;
297 freq-range = <17000000 50000000>;
298 #clock-cells = <0>;
299 clock-output-names = "oscclk7";
300 };
301
302 osc@8 {
303 /* DDR2 PLL reference clock */
304 compatible = "arm,vexpress-osc";
305 arm,vexpress-sysreg,func = <1 8>;
306 freq-range = <20000000 50000000>;
307 #clock-cells = <0>;
308 clock-output-names = "oscclk8";
309 };
310
311 volt@0 {
312 /* A15 CPU core voltage */
313 compatible = "arm,vexpress-volt";
314 arm,vexpress-sysreg,func = <2 0>;
315 regulator-name = "A15 Vcore";
316 regulator-min-microvolt = <800000>;
317 regulator-max-microvolt = <1050000>;
318 regulator-always-on;
319 label = "A15 Vcore";
320 };
321
322 volt@1 {
323 /* A7 CPU core voltage */
324 compatible = "arm,vexpress-volt";
325 arm,vexpress-sysreg,func = <2 1>;
326 regulator-name = "A7 Vcore";
327 regulator-min-microvolt = <800000>;
328 regulator-max-microvolt = <1050000>;
329 regulator-always-on;
330 label = "A7 Vcore";
331 };
332
333 amp@0 {
334 /* Total current for the two A15 cores */
335 compatible = "arm,vexpress-amp";
336 arm,vexpress-sysreg,func = <3 0>;
337 label = "A15 Icore";
338 };
339
340 amp@1 {
341 /* Total current for the three A7 cores */
342 compatible = "arm,vexpress-amp";
343 arm,vexpress-sysreg,func = <3 1>;
344 label = "A7 Icore";
345 };
346
347 temp@0 {
348 /* DCC internal temperature */
349 compatible = "arm,vexpress-temp";
350 arm,vexpress-sysreg,func = <4 0>;
351 label = "DCC";
352 };
353
354 power@0 {
355 /* Total power for the two A15 cores */
356 compatible = "arm,vexpress-power";
357 arm,vexpress-sysreg,func = <12 0>;
358 label = "A15 Pcore";
359 };
360
361 power@1 {
362 /* Total power for the three A7 cores */
363 compatible = "arm,vexpress-power";
364 arm,vexpress-sysreg,func = <12 1>;
365 label = "A7 Pcore";
366 };
367
368 energy@0 {
369 /* Total energy for the two A15 cores */
370 compatible = "arm,vexpress-energy";
371 arm,vexpress-sysreg,func = <13 0>, <13 1>;
372 label = "A15 Jcore";
373 };
374
375 energy@2 {
376 /* Total energy for the three A7 cores */
377 compatible = "arm,vexpress-energy";
378 arm,vexpress-sysreg,func = <13 2>, <13 3>;
379 label = "A7 Jcore";
380 };
381 };
382
383 etb@0,20010000 {
384 compatible = "arm,coresight-etb10", "arm,primecell";
385 reg = <0 0x20010000 0 0x1000>;
386
387 clocks = <&oscclk6a>;
388 clock-names = "apb_pclk";
389 port {
390 etb_in_port: endpoint@0 {
391 slave-mode;
392 remote-endpoint = <&replicator_out_port0>;
393 };
394 };
395 };
396
397 tpiu@0,20030000 {
398 compatible = "arm,coresight-tpiu", "arm,primecell";
399 reg = <0 0x20030000 0 0x1000>;
400
401 clocks = <&oscclk6a>;
402 clock-names = "apb_pclk";
403 port {
404 tpiu_in_port: endpoint@0 {
405 slave-mode;
406 remote-endpoint = <&replicator_out_port1>;
407 };
408 };
409 };
410
411 replicator {
412 /* non-configurable replicators don't show up on the
413 * AMBA bus. As such no need to add "arm,primecell".
414 */
415 compatible = "arm,coresight-replicator";
416
417 ports {
418 #address-cells = <1>;
419 #size-cells = <0>;
420
421 /* replicator output ports */
422 port@0 {
423 reg = <0>;
424 replicator_out_port0: endpoint {
425 remote-endpoint = <&etb_in_port>;
426 };
427 };
428
429 port@1 {
430 reg = <1>;
431 replicator_out_port1: endpoint {
432 remote-endpoint = <&tpiu_in_port>;
433 };
434 };
435
436 /* replicator input port */
437 port@2 {
438 reg = <0>;
439 replicator_in_port0: endpoint {
440 slave-mode;
441 remote-endpoint = <&funnel_out_port0>;
442 };
443 };
444 };
445 };
446
447 funnel@0,20040000 {
448 compatible = "arm,coresight-funnel", "arm,primecell";
449 reg = <0 0x20040000 0 0x1000>;
450
451 clocks = <&oscclk6a>;
452 clock-names = "apb_pclk";
453 ports {
454 #address-cells = <1>;
455 #size-cells = <0>;
456
457 /* funnel output port */
458 port@0 {
459 reg = <0>;
460 funnel_out_port0: endpoint {
461 remote-endpoint =
462 <&replicator_in_port0>;
463 };
464 };
465
466 /* funnel input ports */
467 port@1 {
468 reg = <0>;
469 funnel_in_port0: endpoint {
470 slave-mode;
471 remote-endpoint = <&ptm0_out_port>;
472 };
473 };
474
475 port@2 {
476 reg = <1>;
477 funnel_in_port1: endpoint {
478 slave-mode;
479 remote-endpoint = <&ptm1_out_port>;
480 };
481 };
482
483 port@3 {
484 reg = <2>;
485 funnel_in_port2: endpoint {
486 slave-mode;
487 remote-endpoint = <&etm0_out_port>;
488 };
489 };
490
491 /* Input port #3 is for ITM, not supported here */
492
493 port@4 {
494 reg = <4>;
495 funnel_in_port4: endpoint {
496 slave-mode;
497 remote-endpoint = <&etm1_out_port>;
498 };
499 };
500
501 port@5 {
502 reg = <5>;
503 funnel_in_port5: endpoint {
504 slave-mode;
505 remote-endpoint = <&etm2_out_port>;
506 };
507 };
508 };
509 };
510
511 ptm@0,2201c000 {
512 compatible = "arm,coresight-etm3x", "arm,primecell";
513 reg = <0 0x2201c000 0 0x1000>;
514
515 cpu = <&cpu0>;
516 clocks = <&oscclk6a>;
517 clock-names = "apb_pclk";
518 port {
519 ptm0_out_port: endpoint {
520 remote-endpoint = <&funnel_in_port0>;
521 };
522 };
523 };
524
525 ptm@0,2201d000 {
526 compatible = "arm,coresight-etm3x", "arm,primecell";
527 reg = <0 0x2201d000 0 0x1000>;
528
529 cpu = <&cpu1>;
530 clocks = <&oscclk6a>;
531 clock-names = "apb_pclk";
532 port {
533 ptm1_out_port: endpoint {
534 remote-endpoint = <&funnel_in_port1>;
535 };
536 };
537 };
538
539 etm@0,2203c000 {
540 compatible = "arm,coresight-etm3x", "arm,primecell";
541 reg = <0 0x2203c000 0 0x1000>;
542
543 cpu = <&cpu2>;
544 clocks = <&oscclk6a>;
545 clock-names = "apb_pclk";
546 port {
547 etm0_out_port: endpoint {
548 remote-endpoint = <&funnel_in_port2>;
549 };
550 };
551 };
552
553 etm@0,2203d000 {
554 compatible = "arm,coresight-etm3x", "arm,primecell";
555 reg = <0 0x2203d000 0 0x1000>;
556
557 cpu = <&cpu3>;
558 clocks = <&oscclk6a>;
559 clock-names = "apb_pclk";
560 port {
561 etm1_out_port: endpoint {
562 remote-endpoint = <&funnel_in_port4>;
563 };
564 };
565 };
566
567 etm@0,2203e000 {
568 compatible = "arm,coresight-etm3x", "arm,primecell";
569 reg = <0 0x2203e000 0 0x1000>;
570
571 cpu = <&cpu4>;
572 clocks = <&oscclk6a>;
573 clock-names = "apb_pclk";
574 port {
575 etm2_out_port: endpoint {
576 remote-endpoint = <&funnel_in_port5>;
577 };
578 };
579 };
580
581 smb {
582 compatible = "simple-bus";
583
584 #address-cells = <2>;
585 #size-cells = <1>;
586 ranges = <0 0 0 0x08000000 0x04000000>,
587 <1 0 0 0x14000000 0x04000000>,
588 <2 0 0 0x18000000 0x04000000>,
589 <3 0 0 0x1c000000 0x04000000>,
590 <4 0 0 0x0c000000 0x04000000>,
591 <5 0 0 0x10000000 0x04000000>;
592
593 #interrupt-cells = <1>;
594 interrupt-map-mask = <0 0 63>;
595 interrupt-map = <0 0 0 &gic 0 0 4>,
596 <0 0 1 &gic 0 1 4>,
597 <0 0 2 &gic 0 2 4>,
598 <0 0 3 &gic 0 3 4>,
599 <0 0 4 &gic 0 4 4>,
600 <0 0 5 &gic 0 5 4>,
601 <0 0 6 &gic 0 6 4>,
602 <0 0 7 &gic 0 7 4>,
603 <0 0 8 &gic 0 8 4>,
604 <0 0 9 &gic 0 9 4>,
605 <0 0 10 &gic 0 10 4>,
606 <0 0 11 &gic 0 11 4>,
607 <0 0 12 &gic 0 12 4>,
608 <0 0 13 &gic 0 13 4>,
609 <0 0 14 &gic 0 14 4>,
610 <0 0 15 &gic 0 15 4>,
611 <0 0 16 &gic 0 16 4>,
612 <0 0 17 &gic 0 17 4>,
613 <0 0 18 &gic 0 18 4>,
614 <0 0 19 &gic 0 19 4>,
615 <0 0 20 &gic 0 20 4>,
616 <0 0 21 &gic 0 21 4>,
617 <0 0 22 &gic 0 22 4>,
618 <0 0 23 &gic 0 23 4>,
619 <0 0 24 &gic 0 24 4>,
620 <0 0 25 &gic 0 25 4>,
621 <0 0 26 &gic 0 26 4>,
622 <0 0 27 &gic 0 27 4>,
623 <0 0 28 &gic 0 28 4>,
624 <0 0 29 &gic 0 29 4>,
625 <0 0 30 &gic 0 30 4>,
626 <0 0 31 &gic 0 31 4>,
627 <0 0 32 &gic 0 32 4>,
628 <0 0 33 &gic 0 33 4>,
629 <0 0 34 &gic 0 34 4>,
630 <0 0 35 &gic 0 35 4>,
631 <0 0 36 &gic 0 36 4>,
632 <0 0 37 &gic 0 37 4>,
633 <0 0 38 &gic 0 38 4>,
634 <0 0 39 &gic 0 39 4>,
635 <0 0 40 &gic 0 40 4>,
636 <0 0 41 &gic 0 41 4>,
637 <0 0 42 &gic 0 42 4>;
638
639 /include/ "vexpress-v2m-rs1.dtsi"
640 };
641};