1/*
  2 * Device Tree Source for UniPhier PH1-Pro5 SoC
  3 *
  4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  5 *
  6 * This file is dual-licensed: you can use it either under the terms
  7 * of the GPL or the X11 license, at your option. Note that this dual
  8 * licensing only applies to this file, and not this project as a
  9 * whole.
 10 *
 11 *  a) This file is free software; you can redistribute it and/or
 12 *     modify it under the terms of the GNU General Public License as
 13 *     published by the Free Software Foundation; either version 2 of the
 14 *     License, or (at your option) any later version.
 15 *
 16 *     This file is distributed in the hope that it will be useful,
 17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19 *     GNU General Public License for more details.
 20 *
 21 * Or, alternatively,
 22 *
 23 *  b) Permission is hereby granted, free of charge, to any person
 24 *     obtaining a copy of this software and associated documentation
 25 *     files (the "Software"), to deal in the Software without
 26 *     restriction, including without limitation the rights to use,
 27 *     copy, modify, merge, publish, distribute, sublicense, and/or
 28 *     sell copies of the Software, and to permit persons to whom the
 29 *     Software is furnished to do so, subject to the following
 30 *     conditions:
 31 *
 32 *     The above copyright notice and this permission notice shall be
 33 *     included in all copies or substantial portions of the Software.
 34 *
 35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 42 *     OTHER DEALINGS IN THE SOFTWARE.
 43 */
 44
 45/include/ "uniphier-common32.dtsi"
 46
 47/ {
 48	compatible = "socionext,ph1-pro5";
 49
 50	cpus {
 51		#address-cells = <1>;
 52		#size-cells = <0>;
 53		enable-method = "socionext,uniphier-smp";
 54
 55		cpu@0 {
 56			device_type = "cpu";
 57			compatible = "arm,cortex-a9";
 58			reg = <0>;
 59			next-level-cache = <&l2>;
 60		};
 61
 62		cpu@1 {
 63			device_type = "cpu";
 64			compatible = "arm,cortex-a9";
 65			reg = <1>;
 66			next-level-cache = <&l2>;
 67		};
 68	};
 69
 70	clocks {
 71		arm_timer_clk: arm_timer_clk {
 72			#clock-cells = <0>;
 73			compatible = "fixed-clock";
 74			clock-frequency = <50000000>;
 75		};
 76
 77		uart_clk: uart_clk {
 78			#clock-cells = <0>;
 79			compatible = "fixed-clock";
 80			clock-frequency = <73728000>;
 81		};
 82
 83		i2c_clk: i2c_clk {
 84			#clock-cells = <0>;
 85			compatible = "fixed-clock";
 86			clock-frequency = <50000000>;
 87		};
 88	};
 89};
 90
 91&soc {
 92	l2: l2-cache@500c0000 {
 93		compatible = "socionext,uniphier-system-cache";
 94		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
 95		interrupts = <0 190 4>, <0 191 4>;
 96		cache-unified;
 97		cache-size = <(2 * 1024 * 1024)>;
 98		cache-sets = <512>;
 99		cache-line-size = <128>;
100		cache-level = <2>;
101		next-level-cache = <&l3>;
102	};
103
104	l3: l3-cache@500c8000 {
105		compatible = "socionext,uniphier-system-cache";
106		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
107		interrupts = <0 174 4>, <0 175 4>;
108		cache-unified;
109		cache-size = <(2 * 1024 * 1024)>;
110		cache-sets = <512>;
111		cache-line-size = <256>;
112		cache-level = <3>;
113	};
114
115	i2c0: i2c@58780000 {
116		compatible = "socionext,uniphier-fi2c";
117		status = "disabled";
118		reg = <0x58780000 0x80>;
119		#address-cells = <1>;
120		#size-cells = <0>;
121		interrupts = <0 41 4>;
122		pinctrl-names = "default";
123		pinctrl-0 = <&pinctrl_i2c0>;
124		clocks = <&i2c_clk>;
125		clock-frequency = <100000>;
126	};
127
128	i2c1: i2c@58781000 {
129		compatible = "socionext,uniphier-fi2c";
130		status = "disabled";
131		reg = <0x58781000 0x80>;
132		#address-cells = <1>;
133		#size-cells = <0>;
134		interrupts = <0 42 4>;
135		pinctrl-names = "default";
136		pinctrl-0 = <&pinctrl_i2c1>;
137		clocks = <&i2c_clk>;
138		clock-frequency = <100000>;
139	};
140
141	i2c2: i2c@58782000 {
142		compatible = "socionext,uniphier-fi2c";
143		status = "disabled";
144		reg = <0x58782000 0x80>;
145		#address-cells = <1>;
146		#size-cells = <0>;
147		interrupts = <0 43 4>;
148		pinctrl-names = "default";
149		pinctrl-0 = <&pinctrl_i2c2>;
150		clocks = <&i2c_clk>;
151		clock-frequency = <100000>;
152	};
153
154	i2c3: i2c@58783000 {
155		compatible = "socionext,uniphier-fi2c";
156		status = "disabled";
157		reg = <0x58783000 0x80>;
158		#address-cells = <1>;
159		#size-cells = <0>;
160		interrupts = <0 44 4>;
161		pinctrl-names = "default";
162		pinctrl-0 = <&pinctrl_i2c3>;
163		clocks = <&i2c_clk>;
164		clock-frequency = <100000>;
165	};
166
167	/* i2c4 does not exist */
168
169	/* chip-internal connection for DMD */
170	i2c5: i2c@58785000 {
171		compatible = "socionext,uniphier-fi2c";
172		reg = <0x58785000 0x80>;
173		#address-cells = <1>;
174		#size-cells = <0>;
175		interrupts = <0 25 4>;
176		clocks = <&i2c_clk>;
177		clock-frequency = <400000>;
178	};
179
180	/* chip-internal connection for HDMI */
181	i2c6: i2c@58786000 {
182		compatible = "socionext,uniphier-fi2c";
183		reg = <0x58786000 0x80>;
184		#address-cells = <1>;
185		#size-cells = <0>;
186		interrupts = <0 26 4>;
187		clocks = <&i2c_clk>;
188		clock-frequency = <400000>;
189	};
190};
191
192&refclk {
193	clock-frequency = <20000000>;
194};
195
196&pinctrl {
197	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
198};