1/*
  2 * Device Tree Source commonly used by UniPhier ARM SoCs
  3 *
  4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  5 *
  6 * This file is dual-licensed: you can use it either under the terms
  7 * of the GPL or the X11 license, at your option. Note that this dual
  8 * licensing only applies to this file, and not this project as a
  9 * whole.
 10 *
 11 *  a) This file is free software; you can redistribute it and/or
 12 *     modify it under the terms of the GNU General Public License as
 13 *     published by the Free Software Foundation; either version 2 of the
 14 *     License, or (at your option) any later version.
 15 *
 16 *     This file is distributed in the hope that it will be useful,
 17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19 *     GNU General Public License for more details.
 20 *
 21 * Or, alternatively,
 22 *
 23 *  b) Permission is hereby granted, free of charge, to any person
 24 *     obtaining a copy of this software and associated documentation
 25 *     files (the "Software"), to deal in the Software without
 26 *     restriction, including without limitation the rights to use,
 27 *     copy, modify, merge, publish, distribute, sublicense, and/or
 28 *     sell copies of the Software, and to permit persons to whom the
 29 *     Software is furnished to do so, subject to the following
 30 *     conditions:
 31 *
 32 *     The above copyright notice and this permission notice shall be
 33 *     included in all copies or substantial portions of the Software.
 34 *
 35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 42 *     OTHER DEALINGS IN THE SOFTWARE.
 43 */
 44
 45/include/ "skeleton.dtsi"
 46
 47/ {
 48	clocks {
 49		refclk: ref {
 50			#clock-cells = <0>;
 51			compatible = "fixed-clock";
 52		};
 53	};
 54
 55	soc: soc {
 56		compatible = "simple-bus";
 57		#address-cells = <1>;
 58		#size-cells = <1>;
 59		ranges;
 60		interrupt-parent = <&intc>;
 61
 62		serial0: serial@54006800 {
 63			compatible = "socionext,uniphier-uart";
 64			status = "disabled";
 65			reg = <0x54006800 0x40>;
 66			interrupts = <0 33 4>;
 67			pinctrl-names = "default";
 68			pinctrl-0 = <&pinctrl_uart0>;
 69			clocks = <&uart_clk>;
 70		};
 71
 72		serial1: serial@54006900 {
 73			compatible = "socionext,uniphier-uart";
 74			status = "disabled";
 75			reg = <0x54006900 0x40>;
 76			interrupts = <0 35 4>;
 77			pinctrl-names = "default";
 78			pinctrl-0 = <&pinctrl_uart1>;
 79			clocks = <&uart_clk>;
 80		};
 81
 82		serial2: serial@54006a00 {
 83			compatible = "socionext,uniphier-uart";
 84			status = "disabled";
 85			reg = <0x54006a00 0x40>;
 86			interrupts = <0 37 4>;
 87			pinctrl-names = "default";
 88			pinctrl-0 = <&pinctrl_uart2>;
 89			clocks = <&uart_clk>;
 90		};
 91
 92		serial3: serial@54006b00 {
 93			compatible = "socionext,uniphier-uart";
 94			status = "disabled";
 95			reg = <0x54006b00 0x40>;
 96			interrupts = <0 177 4>;
 97			pinctrl-names = "default";
 98			pinctrl-0 = <&pinctrl_uart3>;
 99			clocks = <&uart_clk>;
100		};
101
102		system_bus: system-bus@58c00000 {
103			compatible = "socionext,uniphier-system-bus";
104			status = "disabled";
105			reg = <0x58c00000 0x400>;
106			#address-cells = <2>;
107			#size-cells = <1>;
108		};
109
110		smpctrl@59800000 {
111			compatible = "socionext,uniphier-smpctrl";
112			reg = <0x59801000 0x400>;
113		};
114
115		timer@60000200 {
116			compatible = "arm,cortex-a9-global-timer";
117			reg = <0x60000200 0x20>;
118			interrupts = <1 11 0x104>;
119			clocks = <&arm_timer_clk>;
120		};
121
122		timer@60000600 {
123			compatible = "arm,cortex-a9-twd-timer";
124			reg = <0x60000600 0x20>;
125			interrupts = <1 13 0x104>;
126			clocks = <&arm_timer_clk>;
127		};
128
129		intc: interrupt-controller@60001000 {
130			compatible = "arm,cortex-a9-gic";
131			reg = <0x60001000 0x1000>,
132			      <0x60000100 0x100>;
133			#interrupt-cells = <3>;
134			interrupt-controller;
135		};
136
137		pinctrl: pinctrl@5f801000 {
138			/* specify compatible in each SoC DTSI */
139			reg = <0x5f801000 0xe00>;
140		};
141	};
142};
143
144/include/ "uniphier-pinctrl.dtsi"