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1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/reset/altr,rst-mgr-a10.h>
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
28
29 cpu@0 {
30 compatible = "arm,cortex-a9";
31 device_type = "cpu";
32 reg = <0>;
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 device_type = "cpu";
38 reg = <1>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 intc: intc@ffffd000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 interrupt-controller;
47 reg = <0xffffd000 0x1000>,
48 <0xffffc100 0x100>;
49 };
50
51 soc {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "simple-bus";
55 device_type = "soc";
56 interrupt-parent = <&intc>;
57 ranges;
58
59 amba {
60 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 pdma: pdma@ffda1000 {
66 compatible = "arm,pl330", "arm,primecell";
67 reg = <0xffda1000 0x1000>;
68 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
69 <0 84 IRQ_TYPE_LEVEL_HIGH>,
70 <0 85 IRQ_TYPE_LEVEL_HIGH>,
71 <0 86 IRQ_TYPE_LEVEL_HIGH>,
72 <0 87 IRQ_TYPE_LEVEL_HIGH>,
73 <0 88 IRQ_TYPE_LEVEL_HIGH>,
74 <0 89 IRQ_TYPE_LEVEL_HIGH>,
75 <0 90 IRQ_TYPE_LEVEL_HIGH>,
76 <0 91 IRQ_TYPE_LEVEL_HIGH>;
77 #dma-cells = <1>;
78 #dma-channels = <8>;
79 #dma-requests = <32>;
80 clocks = <&l4_main_clk>;
81 clock-names = "apb_pclk";
82 };
83 };
84
85 base_fpga_region {
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
88
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
91 };
92
93 clkmgr@ffd04000 {
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
96
97 clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 };
110
111 f2s_free_clk: f2s_free_clk {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 };
115
116 osc1: osc1 {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 };
120
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
127 <&f2s_free_clk>;
128 reg = <0x40>;
129
130 main_mpu_base_clk: main_mpu_base_clk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
135 };
136
137 main_noc_base_clk: main_noc_base_clk {
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
142 };
143
144 main_emaca_clk: main_emaca_clk@68 {
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
148 reg = <0x68>;
149 };
150
151 main_emacb_clk: main_emacb_clk@6c {
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
155 reg = <0x6C>;
156 };
157
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
162 reg = <0x70>;
163 };
164
165 main_gpio_db_clk: main_gpio_db_clk@74 {
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
169 reg = <0x74>;
170 };
171
172 main_sdmmc_clk: main_sdmmc_clk@78 {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-a10-perip-clk"
175;
176 clocks = <&main_pll>;
177 reg = <0x78>;
178 };
179
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x7C>;
185 };
186
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x80>;
192 };
193
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x84>;
199 };
200
201 main_periph_ref_clk: main_periph_ref_clk@9c {
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
205 reg = <0x9C>;
206 };
207 };
208
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
216 reg = <0xC0>;
217
218 peri_mpu_base_clk: peri_mpu_base_clk {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
223 };
224
225 peri_noc_base_clk: peri_noc_base_clk {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
230 };
231
232 peri_emaca_clk: peri_emaca_clk@e8 {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0xE8>;
237 };
238
239 peri_emacb_clk: peri_emacb_clk@ec {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0xEC>;
244 };
245
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0xF0>;
251 };
252
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0xF4>;
258 };
259
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
264 reg = <0xF8>;
265 };
266
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
271 reg = <0xFC>;
272 };
273
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
278 reg = <0x100>;
279 };
280
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
282 #clock-cells = <0>;
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
285 reg = <0x104>;
286 };
287 };
288
289 mpu_free_clk: mpu_free_clk@60 {
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
294 <&f2s_free_clk>;
295 reg = <0x60>;
296 };
297
298 noc_free_clk: noc_free_clk@64 {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
303 <&f2s_free_clk>;
304 reg = <0x64>;
305 };
306
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
312 <&f2s_free_clk>;
313 reg = <0x104>;
314 };
315
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
321 <&f2s_free_clk>;
322 fixed-divider = <4>;
323 reg = <0xF8>;
324 };
325
326 l4_sys_free_clk: l4_sys_free_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
330 fixed-divider = <4>;
331 };
332
333 l4_main_clk: l4_main_clk {
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
338 clk-gate = <0x48 1>;
339 };
340
341 l4_mp_clk: l4_mp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
346 clk-gate = <0x48 2>;
347 };
348
349 l4_sp_clk: l4_sp_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
354 clk-gate = <0x48 3>;
355 };
356
357 mpu_periph_clk: mpu_periph_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
361 fixed-divider = <4>;
362 clk-gate = <0x48 0>;
363 };
364
365 sdmmc_clk: sdmmc_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
369 clk-gate = <0xC8 5>;
370 clk-phase = <0 135>;
371 };
372
373 qspi_clk: qspi_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
378 };
379
380 nand_clk: nand_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
385 };
386
387 spi_m_clk: spi_m_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_main_clk>;
391 clk-gate = <0xC8 9>;
392 };
393
394 usb_clk: usb_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&l4_mp_clk>;
398 clk-gate = <0xC8 8>;
399 };
400
401 s2f_usr1_clk: s2f_usr1_clk {
402 #clock-cells = <0>;
403 compatible = "altr,socfpga-a10-gate-clk";
404 clocks = <&peri_s2f_usr1_clk>;
405 clk-gate = <0xC8 6>;
406 };
407 };
408 };
409
410 socfpga_axi_setup: stmmac-axi-config {
411 snps,wr_osr_lmt = <0xf>;
412 snps,rd_osr_lmt = <0xf>;
413 snps,blen = <0 0 0 0 16 0 0>;
414 };
415
416 gmac0: ethernet@ff800000 {
417 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
418 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
419 reg = <0xff800000 0x2000>;
420 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-names = "macirq";
422 /* Filled in by bootloader */
423 mac-address = [00 00 00 00 00 00];
424 snps,multicast-filter-bins = <256>;
425 snps,perfect-filter-entries = <128>;
426 tx-fifo-depth = <4096>;
427 rx-fifo-depth = <16384>;
428 clocks = <&l4_mp_clk>;
429 clock-names = "stmmaceth";
430 resets = <&rst EMAC0_RESET>;
431 reset-names = "stmmaceth";
432 snps,axi-config = <&socfpga_axi_setup>;
433 status = "disabled";
434 };
435
436 gmac1: ethernet@ff802000 {
437 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
438 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
439 reg = <0xff802000 0x2000>;
440 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "macirq";
442 /* Filled in by bootloader */
443 mac-address = [00 00 00 00 00 00];
444 snps,multicast-filter-bins = <256>;
445 snps,perfect-filter-entries = <128>;
446 tx-fifo-depth = <4096>;
447 rx-fifo-depth = <16384>;
448 clocks = <&l4_mp_clk>;
449 clock-names = "stmmaceth";
450 resets = <&rst EMAC1_RESET>;
451 reset-names = "stmmaceth";
452 snps,axi-config = <&socfpga_axi_setup>;
453 status = "disabled";
454 };
455
456 gmac2: ethernet@ff804000 {
457 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
458 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
459 reg = <0xff804000 0x2000>;
460 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "macirq";
462 /* Filled in by bootloader */
463 mac-address = [00 00 00 00 00 00];
464 snps,multicast-filter-bins = <256>;
465 snps,perfect-filter-entries = <128>;
466 tx-fifo-depth = <4096>;
467 rx-fifo-depth = <16384>;
468 clocks = <&l4_mp_clk>;
469 clock-names = "stmmaceth";
470 snps,axi-config = <&socfpga_axi_setup>;
471 status = "disabled";
472 };
473
474 gpio0: gpio@ffc02900 {
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "snps,dw-apb-gpio";
478 reg = <0xffc02900 0x100>;
479 status = "disabled";
480
481 porta: gpio-controller@0 {
482 compatible = "snps,dw-apb-gpio-port";
483 gpio-controller;
484 #gpio-cells = <2>;
485 snps,nr-gpios = <29>;
486 reg = <0>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
490 };
491 };
492
493 gpio1: gpio@ffc02a00 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "snps,dw-apb-gpio";
497 reg = <0xffc02a00 0x100>;
498 status = "disabled";
499
500 portb: gpio-controller@0 {
501 compatible = "snps,dw-apb-gpio-port";
502 gpio-controller;
503 #gpio-cells = <2>;
504 snps,nr-gpios = <29>;
505 reg = <0>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
509 };
510 };
511
512 gpio2: gpio@ffc02b00 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "snps,dw-apb-gpio";
516 reg = <0xffc02b00 0x100>;
517 status = "disabled";
518
519 portc: gpio-controller@0 {
520 compatible = "snps,dw-apb-gpio-port";
521 gpio-controller;
522 #gpio-cells = <2>;
523 snps,nr-gpios = <27>;
524 reg = <0>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
528 };
529 };
530
531 fpga_mgr: fpga-mgr@ffd03000 {
532 compatible = "altr,socfpga-a10-fpga-mgr";
533 reg = <0xffd03000 0x100
534 0xffcfe400 0x20>;
535 clocks = <&l4_mp_clk>;
536 resets = <&rst FPGAMGR_RESET>;
537 reset-names = "fpgamgr";
538 };
539
540 i2c0: i2c@ffc02200 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "snps,designware-i2c";
544 reg = <0xffc02200 0x100>;
545 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&l4_sp_clk>;
547 status = "disabled";
548 };
549
550 i2c1: i2c@ffc02300 {
551 #address-cells = <1>;
552 #size-cells = <0>;
553 compatible = "snps,designware-i2c";
554 reg = <0xffc02300 0x100>;
555 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&l4_sp_clk>;
557 status = "disabled";
558 };
559
560 i2c2: i2c@ffc02400 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "snps,designware-i2c";
564 reg = <0xffc02400 0x100>;
565 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&l4_sp_clk>;
567 status = "disabled";
568 };
569
570 i2c3: i2c@ffc02500 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "snps,designware-i2c";
574 reg = <0xffc02500 0x100>;
575 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&l4_sp_clk>;
577 status = "disabled";
578 };
579
580 i2c4: i2c@ffc02600 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "snps,designware-i2c";
584 reg = <0xffc02600 0x100>;
585 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&l4_sp_clk>;
587 status = "disabled";
588 };
589
590 spi1: spi@ffda5000 {
591 compatible = "snps,dw-apb-ssi";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 reg = <0xffda5000 0x100>;
595 interrupts = <0 102 4>;
596 num-chipselect = <4>;
597 bus-num = <0>;
598 /*32bit_access;*/
599 tx-dma-channel = <&pdma 16>;
600 rx-dma-channel = <&pdma 17>;
601 clocks = <&spi_m_clk>;
602 status = "disabled";
603 };
604
605 sdr: sdr@ffc25000 {
606 compatible = "altr,sdr-ctl", "syscon";
607 reg = <0xffcfb100 0x80>;
608 };
609
610 L2: l2-cache@fffff000 {
611 compatible = "arm,pl310-cache";
612 reg = <0xfffff000 0x1000>;
613 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
614 cache-unified;
615 cache-level = <2>;
616 prefetch-data = <1>;
617 prefetch-instr = <1>;
618 arm,shared-override;
619 };
620
621 mmc: dwmmc0@ff808000 {
622 #address-cells = <1>;
623 #size-cells = <0>;
624 compatible = "altr,socfpga-dw-mshc";
625 reg = <0xff808000 0x1000>;
626 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
627 fifo-depth = <0x400>;
628 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
629 clock-names = "biu", "ciu";
630 status = "disabled";
631 };
632
633 nand: nand@ffb90000 {
634 #address-cells = <1>;
635 #size-cells = <1>;
636 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
637 reg = <0xffb90000 0x72000>,
638 <0xffb80000 0x10000>;
639 reg-names = "nand_data", "denali_reg";
640 interrupts = <0 99 4>;
641 dma-mask = <0xffffffff>;
642 clocks = <&nand_clk>;
643 status = "disabled";
644 };
645
646 ocram: sram@ffe00000 {
647 compatible = "mmio-sram";
648 reg = <0xffe00000 0x40000>;
649 };
650
651 eccmgr: eccmgr {
652 compatible = "altr,socfpga-a10-ecc-manager";
653 altr,sysmgr-syscon = <&sysmgr>;
654 #address-cells = <1>;
655 #size-cells = <1>;
656 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
657 <0 0 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-controller;
659 #interrupt-cells = <2>;
660 ranges;
661
662 sdramedac {
663 compatible = "altr,sdram-edac-a10";
664 altr,sdr-syscon = <&sdr>;
665 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
666 <49 IRQ_TYPE_LEVEL_HIGH>;
667 };
668
669 l2-ecc@ffd06010 {
670 compatible = "altr,socfpga-a10-l2-ecc";
671 reg = <0xffd06010 0x4>;
672 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
673 <32 IRQ_TYPE_LEVEL_HIGH>;
674 };
675
676 ocram-ecc@ff8c3000 {
677 compatible = "altr,socfpga-a10-ocram-ecc";
678 reg = <0xff8c3000 0x400>;
679 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
680 <33 IRQ_TYPE_LEVEL_HIGH>;
681 };
682
683 emac0-rx-ecc@ff8c0800 {
684 compatible = "altr,socfpga-eth-mac-ecc";
685 reg = <0xff8c0800 0x400>;
686 altr,ecc-parent = <&gmac0>;
687 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
688 <36 IRQ_TYPE_LEVEL_HIGH>;
689 };
690
691 emac0-tx-ecc@ff8c0c00 {
692 compatible = "altr,socfpga-eth-mac-ecc";
693 reg = <0xff8c0c00 0x400>;
694 altr,ecc-parent = <&gmac0>;
695 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
696 <37 IRQ_TYPE_LEVEL_HIGH>;
697 };
698
699 dma-ecc@ff8c8000 {
700 compatible = "altr,socfpga-dma-ecc";
701 reg = <0xff8c8000 0x400>;
702 altr,ecc-parent = <&pdma>;
703 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
704 <42 IRQ_TYPE_LEVEL_HIGH>;
705 };
706
707 usb0-ecc@ff8c8800 {
708 compatible = "altr,socfpga-usb-ecc";
709 reg = <0xff8c8800 0x400>;
710 altr,ecc-parent = <&usb0>;
711 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
712 <34 IRQ_TYPE_LEVEL_HIGH>;
713 };
714 };
715
716 qspi: spi@ff809000 {
717 compatible = "cdns,qspi-nor";
718 #address-cells = <1>;
719 #size-cells = <0>;
720 reg = <0xff809000 0x100>,
721 <0xffa00000 0x100000>;
722 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
723 cdns,fifo-depth = <128>;
724 cdns,fifo-width = <4>;
725 cdns,trigger-address = <0x00000000>;
726 clocks = <&qspi_clk>;
727 status = "disabled";
728 };
729
730 rst: rstmgr@ffd05000 {
731 #reset-cells = <1>;
732 compatible = "altr,rst-mgr";
733 reg = <0xffd05000 0x100>;
734 altr,modrst-offset = <0x20>;
735 };
736
737 scu: snoop-control-unit@ffffc000 {
738 compatible = "arm,cortex-a9-scu";
739 reg = <0xffffc000 0x100>;
740 };
741
742 sysmgr: sysmgr@ffd06000 {
743 compatible = "altr,sys-mgr", "syscon";
744 reg = <0xffd06000 0x300>;
745 cpu1-start-addr = <0xffd06230>;
746 };
747
748 /* Local timer */
749 timer@ffffc600 {
750 compatible = "arm,cortex-a9-twd-timer";
751 reg = <0xffffc600 0x100>;
752 interrupts = <1 13 0xf04>;
753 clocks = <&mpu_periph_clk>;
754 };
755
756 timer0: timer0@ffc02700 {
757 compatible = "snps,dw-apb-timer";
758 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
759 reg = <0xffc02700 0x100>;
760 clocks = <&l4_sp_clk>;
761 clock-names = "timer";
762 };
763
764 timer1: timer1@ffc02800 {
765 compatible = "snps,dw-apb-timer";
766 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0xffc02800 0x100>;
768 clocks = <&l4_sp_clk>;
769 clock-names = "timer";
770 };
771
772 timer2: timer2@ffd00000 {
773 compatible = "snps,dw-apb-timer";
774 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
775 reg = <0xffd00000 0x100>;
776 clocks = <&l4_sys_free_clk>;
777 clock-names = "timer";
778 };
779
780 timer3: timer3@ffd00100 {
781 compatible = "snps,dw-apb-timer";
782 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
783 reg = <0xffd01000 0x100>;
784 clocks = <&l4_sys_free_clk>;
785 clock-names = "timer";
786 };
787
788 uart0: serial0@ffc02000 {
789 compatible = "snps,dw-apb-uart";
790 reg = <0xffc02000 0x100>;
791 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
792 reg-shift = <2>;
793 reg-io-width = <4>;
794 clocks = <&l4_sp_clk>;
795 status = "disabled";
796 };
797
798 uart1: serial1@ffc02100 {
799 compatible = "snps,dw-apb-uart";
800 reg = <0xffc02100 0x100>;
801 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
802 reg-shift = <2>;
803 reg-io-width = <4>;
804 clocks = <&l4_sp_clk>;
805 status = "disabled";
806 };
807
808 usbphy0: usbphy {
809 #phy-cells = <0>;
810 compatible = "usb-nop-xceiv";
811 status = "okay";
812 };
813
814 usb0: usb@ffb00000 {
815 compatible = "snps,dwc2";
816 reg = <0xffb00000 0xffff>;
817 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&usb_clk>;
819 clock-names = "otg";
820 resets = <&rst USB0_RESET>;
821 reset-names = "dwc2";
822 phys = <&usbphy0>;
823 phy-names = "usb2-phy";
824 status = "disabled";
825 };
826
827 usb1: usb@ffb40000 {
828 compatible = "snps,dwc2";
829 reg = <0xffb40000 0xffff>;
830 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&usb_clk>;
832 clock-names = "otg";
833 resets = <&rst USB1_RESET>;
834 reset-names = "dwc2";
835 phys = <&usbphy0>;
836 phy-names = "usb2-phy";
837 status = "disabled";
838 };
839
840 watchdog0: watchdog@ffd00200 {
841 compatible = "snps,dw-wdt";
842 reg = <0xffd00200 0x100>;
843 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&l4_sys_free_clk>;
845 status = "disabled";
846 };
847
848 watchdog1: watchdog@ffd00300 {
849 compatible = "snps,dw-wdt";
850 reg = <0xffd00300 0x100>;
851 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&l4_sys_free_clk>;
853 status = "disabled";
854 };
855 };
856};
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/reset/altr,rst-mgr-a10.h>
20
21/ {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "altr,socfpga-a10-smp";
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 };
47 };
48
49 intc: intc@ffffd000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xffffd000 0x1000>,
54 <0xffffc100 0x100>;
55 };
56
57 soc {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 device_type = "soc";
62 interrupt-parent = <&intc>;
63 ranges;
64
65 amba {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 pdma: pdma@ffda1000 {
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
78 <0 87 IRQ_TYPE_LEVEL_HIGH>,
79 <0 88 IRQ_TYPE_LEVEL_HIGH>,
80 <0 89 IRQ_TYPE_LEVEL_HIGH>,
81 <0 90 IRQ_TYPE_LEVEL_HIGH>;
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
85 };
86 };
87
88 clkmgr@ffd04000 {
89 compatible = "altr,clk-mgr";
90 reg = <0xffd04000 0x1000>;
91
92 clocks {
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 };
100
101 cb_intosc_ls_clk: cb_intosc_ls_clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 f2s_free_clk: f2s_free_clk {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 };
110
111 osc1: osc1 {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 };
115
116 main_pll: main_pll {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 #clock-cells = <0>;
120 compatible = "altr,socfpga-a10-pll-clock";
121 clocks = <&osc1>, <&cb_intosc_ls_clk>,
122 <&f2s_free_clk>;
123 reg = <0x40>;
124
125 main_mpu_base_clk: main_mpu_base_clk {
126 #clock-cells = <0>;
127 compatible = "altr,socfpga-a10-perip-clk";
128 clocks = <&main_pll>;
129 div-reg = <0x140 0 11>;
130 };
131
132 main_noc_base_clk: main_noc_base_clk {
133 #clock-cells = <0>;
134 compatible = "altr,socfpga-a10-perip-clk";
135 clocks = <&main_pll>;
136 div-reg = <0x144 0 11>;
137 };
138
139 main_emaca_clk: main_emaca_clk {
140 #clock-cells = <0>;
141 compatible = "altr,socfpga-a10-perip-clk";
142 clocks = <&main_pll>;
143 reg = <0x68>;
144 };
145
146 main_emacb_clk: main_emacb_clk {
147 #clock-cells = <0>;
148 compatible = "altr,socfpga-a10-perip-clk";
149 clocks = <&main_pll>;
150 reg = <0x6C>;
151 };
152
153 main_emac_ptp_clk: main_emac_ptp_clk {
154 #clock-cells = <0>;
155 compatible = "altr,socfpga-a10-perip-clk";
156 clocks = <&main_pll>;
157 reg = <0x70>;
158 };
159
160 main_gpio_db_clk: main_gpio_db_clk {
161 #clock-cells = <0>;
162 compatible = "altr,socfpga-a10-perip-clk";
163 clocks = <&main_pll>;
164 reg = <0x74>;
165 };
166
167 main_sdmmc_clk: main_sdmmc_clk {
168 #clock-cells = <0>;
169 compatible = "altr,socfpga-a10-perip-clk"
170;
171 clocks = <&main_pll>;
172 reg = <0x78>;
173 };
174
175 main_s2f_usr0_clk: main_s2f_usr0_clk {
176 #clock-cells = <0>;
177 compatible = "altr,socfpga-a10-perip-clk";
178 clocks = <&main_pll>;
179 reg = <0x7C>;
180 };
181
182 main_s2f_usr1_clk: main_s2f_usr1_clk {
183 #clock-cells = <0>;
184 compatible = "altr,socfpga-a10-perip-clk";
185 clocks = <&main_pll>;
186 reg = <0x80>;
187 };
188
189 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
190 #clock-cells = <0>;
191 compatible = "altr,socfpga-a10-perip-clk";
192 clocks = <&main_pll>;
193 reg = <0x84>;
194 };
195
196 main_periph_ref_clk: main_periph_ref_clk {
197 #clock-cells = <0>;
198 compatible = "altr,socfpga-a10-perip-clk";
199 clocks = <&main_pll>;
200 reg = <0x9C>;
201 };
202 };
203
204 periph_pll: periph_pll {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 #clock-cells = <0>;
208 compatible = "altr,socfpga-a10-pll-clock";
209 clocks = <&osc1>, <&cb_intosc_ls_clk>,
210 <&f2s_free_clk>, <&main_periph_ref_clk>;
211 reg = <0xC0>;
212
213 peri_mpu_base_clk: peri_mpu_base_clk {
214 #clock-cells = <0>;
215 compatible = "altr,socfpga-a10-perip-clk";
216 clocks = <&periph_pll>;
217 div-reg = <0x140 16 11>;
218 };
219
220 peri_noc_base_clk: peri_noc_base_clk {
221 #clock-cells = <0>;
222 compatible = "altr,socfpga-a10-perip-clk";
223 clocks = <&periph_pll>;
224 div-reg = <0x144 16 11>;
225 };
226
227 peri_emaca_clk: peri_emaca_clk {
228 #clock-cells = <0>;
229 compatible = "altr,socfpga-a10-perip-clk";
230 clocks = <&periph_pll>;
231 reg = <0xE8>;
232 };
233
234 peri_emacb_clk: peri_emacb_clk {
235 #clock-cells = <0>;
236 compatible = "altr,socfpga-a10-perip-clk";
237 clocks = <&periph_pll>;
238 reg = <0xEC>;
239 };
240
241 peri_emac_ptp_clk: peri_emac_ptp_clk {
242 #clock-cells = <0>;
243 compatible = "altr,socfpga-a10-perip-clk";
244 clocks = <&periph_pll>;
245 reg = <0xF0>;
246 };
247
248 peri_gpio_db_clk: peri_gpio_db_clk {
249 #clock-cells = <0>;
250 compatible = "altr,socfpga-a10-perip-clk";
251 clocks = <&periph_pll>;
252 reg = <0xF4>;
253 };
254
255 peri_sdmmc_clk: peri_sdmmc_clk {
256 #clock-cells = <0>;
257 compatible = "altr,socfpga-a10-perip-clk";
258 clocks = <&periph_pll>;
259 reg = <0xF8>;
260 };
261
262 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
263 #clock-cells = <0>;
264 compatible = "altr,socfpga-a10-perip-clk";
265 clocks = <&periph_pll>;
266 reg = <0xFC>;
267 };
268
269 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
270 #clock-cells = <0>;
271 compatible = "altr,socfpga-a10-perip-clk";
272 clocks = <&periph_pll>;
273 reg = <0x100>;
274 };
275
276 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-a10-perip-clk";
279 clocks = <&periph_pll>;
280 reg = <0x104>;
281 };
282 };
283
284 mpu_free_clk: mpu_free_clk {
285 #clock-cells = <0>;
286 compatible = "altr,socfpga-a10-perip-clk";
287 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
288 <&osc1>, <&cb_intosc_hs_div2_clk>,
289 <&f2s_free_clk>;
290 reg = <0x60>;
291 };
292
293 noc_free_clk: noc_free_clk {
294 #clock-cells = <0>;
295 compatible = "altr,socfpga-a10-perip-clk";
296 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
297 <&osc1>, <&cb_intosc_hs_div2_clk>,
298 <&f2s_free_clk>;
299 reg = <0x64>;
300 };
301
302 s2f_user1_free_clk: s2f_user1_free_clk {
303 #clock-cells = <0>;
304 compatible = "altr,socfpga-a10-perip-clk";
305 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
306 <&osc1>, <&cb_intosc_hs_div2_clk>,
307 <&f2s_free_clk>;
308 reg = <0x104>;
309 };
310
311 sdmmc_free_clk: sdmmc_free_clk {
312 #clock-cells = <0>;
313 compatible = "altr,socfpga-a10-perip-clk";
314 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
315 <&osc1>, <&cb_intosc_hs_div2_clk>,
316 <&f2s_free_clk>;
317 fixed-divider = <4>;
318 reg = <0xF8>;
319 };
320
321 l4_sys_free_clk: l4_sys_free_clk {
322 #clock-cells = <0>;
323 compatible = "altr,socfpga-a10-perip-clk";
324 clocks = <&noc_free_clk>;
325 fixed-divider = <4>;
326 };
327
328 l4_main_clk: l4_main_clk {
329 #clock-cells = <0>;
330 compatible = "altr,socfpga-a10-gate-clk";
331 clocks = <&noc_free_clk>;
332 div-reg = <0xA8 0 2>;
333 clk-gate = <0x48 1>;
334 };
335
336 l4_mp_clk: l4_mp_clk {
337 #clock-cells = <0>;
338 compatible = "altr,socfpga-a10-gate-clk";
339 clocks = <&noc_free_clk>;
340 div-reg = <0xA8 8 2>;
341 clk-gate = <0x48 2>;
342 };
343
344 l4_sp_clk: l4_sp_clk {
345 #clock-cells = <0>;
346 compatible = "altr,socfpga-a10-gate-clk";
347 clocks = <&noc_free_clk>;
348 div-reg = <0xA8 16 2>;
349 clk-gate = <0x48 3>;
350 };
351
352 mpu_periph_clk: mpu_periph_clk {
353 #clock-cells = <0>;
354 compatible = "altr,socfpga-a10-gate-clk";
355 clocks = <&mpu_free_clk>;
356 fixed-divider = <4>;
357 clk-gate = <0x48 0>;
358 };
359
360 sdmmc_clk: sdmmc_clk {
361 #clock-cells = <0>;
362 compatible = "altr,socfpga-a10-gate-clk";
363 clocks = <&sdmmc_free_clk>;
364 clk-gate = <0xC8 5>;
365 };
366
367 qspi_clk: qspi_clk {
368 #clock-cells = <0>;
369 compatible = "altr,socfpga-a10-gate-clk";
370 clocks = <&l4_main_clk>;
371 clk-gate = <0xC8 11>;
372 };
373
374 nand_clk: nand_clk {
375 #clock-cells = <0>;
376 compatible = "altr,socfpga-a10-gate-clk";
377 clocks = <&l4_mp_clk>;
378 clk-gate = <0xC8 10>;
379 };
380
381 spi_m_clk: spi_m_clk {
382 #clock-cells = <0>;
383 compatible = "altr,socfpga-a10-gate-clk";
384 clocks = <&l4_main_clk>;
385 clk-gate = <0xC8 9>;
386 };
387
388 usb_clk: usb_clk {
389 #clock-cells = <0>;
390 compatible = "altr,socfpga-a10-gate-clk";
391 clocks = <&l4_mp_clk>;
392 clk-gate = <0xC8 8>;
393 };
394
395 s2f_usr1_clk: s2f_usr1_clk {
396 #clock-cells = <0>;
397 compatible = "altr,socfpga-a10-gate-clk";
398 clocks = <&peri_s2f_usr1_clk>;
399 clk-gate = <0xC8 6>;
400 };
401 };
402 };
403
404 gmac0: ethernet@ff800000 {
405 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
406 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
407 reg = <0xff800000 0x2000>;
408 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "macirq";
410 /* Filled in by bootloader */
411 mac-address = [00 00 00 00 00 00];
412 snps,multicast-filter-bins = <256>;
413 snps,perfect-filter-entries = <128>;
414 tx-fifo-depth = <4096>;
415 rx-fifo-depth = <16384>;
416 clocks = <&l4_mp_clk>;
417 clock-names = "stmmaceth";
418 resets = <&rst EMAC0_RESET>;
419 reset-names = "stmmaceth";
420 status = "disabled";
421 };
422
423 gmac1: ethernet@ff802000 {
424 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
425 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
426 reg = <0xff802000 0x2000>;
427 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "macirq";
429 /* Filled in by bootloader */
430 mac-address = [00 00 00 00 00 00];
431 snps,multicast-filter-bins = <256>;
432 snps,perfect-filter-entries = <128>;
433 tx-fifo-depth = <4096>;
434 rx-fifo-depth = <16384>;
435 clocks = <&l4_mp_clk>;
436 clock-names = "stmmaceth";
437 resets = <&rst EMAC1_RESET>;
438 reset-names = "stmmaceth";
439 status = "disabled";
440 };
441
442 gmac2: ethernet@ff804000 {
443 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
444 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
445 reg = <0xff804000 0x2000>;
446 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "macirq";
448 /* Filled in by bootloader */
449 mac-address = [00 00 00 00 00 00];
450 snps,multicast-filter-bins = <256>;
451 snps,perfect-filter-entries = <128>;
452 tx-fifo-depth = <4096>;
453 rx-fifo-depth = <16384>;
454 clocks = <&l4_mp_clk>;
455 clock-names = "stmmaceth";
456 status = "disabled";
457 };
458
459 gpio0: gpio@ffc02900 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 compatible = "snps,dw-apb-gpio";
463 reg = <0xffc02900 0x100>;
464 status = "disabled";
465
466 porta: gpio-controller@0 {
467 compatible = "snps,dw-apb-gpio-port";
468 gpio-controller;
469 #gpio-cells = <2>;
470 snps,nr-gpios = <29>;
471 reg = <0>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
475 };
476 };
477
478 gpio1: gpio@ffc02a00 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "snps,dw-apb-gpio";
482 reg = <0xffc02a00 0x100>;
483 status = "disabled";
484
485 portb: gpio-controller@0 {
486 compatible = "snps,dw-apb-gpio-port";
487 gpio-controller;
488 #gpio-cells = <2>;
489 snps,nr-gpios = <29>;
490 reg = <0>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
494 };
495 };
496
497 gpio2: gpio@ffc02b00 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "snps,dw-apb-gpio";
501 reg = <0xffc02b00 0x100>;
502 status = "disabled";
503
504 portc: gpio-controller@0 {
505 compatible = "snps,dw-apb-gpio-port";
506 gpio-controller;
507 #gpio-cells = <2>;
508 snps,nr-gpios = <27>;
509 reg = <0>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
512 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
513 };
514 };
515
516 i2c0: i2c@ffc02200 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "snps,designware-i2c";
520 reg = <0xffc02200 0x100>;
521 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&l4_sp_clk>;
523 status = "disabled";
524 };
525
526 i2c1: i2c@ffc02300 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 compatible = "snps,designware-i2c";
530 reg = <0xffc02300 0x100>;
531 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&l4_sp_clk>;
533 status = "disabled";
534 };
535
536 i2c2: i2c@ffc02400 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "snps,designware-i2c";
540 reg = <0xffc02400 0x100>;
541 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&l4_sp_clk>;
543 status = "disabled";
544 };
545
546 i2c3: i2c@ffc02500 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "snps,designware-i2c";
550 reg = <0xffc02500 0x100>;
551 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&l4_sp_clk>;
553 status = "disabled";
554 };
555
556 i2c4: i2c@ffc02600 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "snps,designware-i2c";
560 reg = <0xffc02600 0x100>;
561 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&l4_sp_clk>;
563 status = "disabled";
564 };
565
566 sdr: sdr@ffc25000 {
567 compatible = "syscon";
568 reg = <0xffcfb100 0x80>;
569 };
570
571 sdramedac {
572 compatible = "altr,sdram-edac-a10";
573 altr,sdr-syscon = <&sdr>;
574 interrupts = <0 2 4>, <0 0 4>;
575 };
576
577 L2: l2-cache@fffff000 {
578 compatible = "arm,pl310-cache";
579 reg = <0xfffff000 0x1000>;
580 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
581 cache-unified;
582 cache-level = <2>;
583 };
584
585 mmc: dwmmc0@ff808000 {
586 #address-cells = <1>;
587 #size-cells = <0>;
588 compatible = "altr,socfpga-dw-mshc";
589 reg = <0xff808000 0x1000>;
590 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
591 fifo-depth = <0x400>;
592 clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
593 clock-names = "biu", "ciu";
594 status = "disabled";
595 };
596
597 ocram: sram@ffe00000 {
598 compatible = "mmio-sram";
599 reg = <0xffe00000 0x40000>;
600 };
601
602 rst: rstmgr@ffd05000 {
603 #reset-cells = <1>;
604 compatible = "altr,rst-mgr";
605 reg = <0xffd05000 0x100>;
606 altr,modrst-offset = <0x20>;
607 };
608
609 scu: snoop-control-unit@ffffc000 {
610 compatible = "arm,cortex-a9-scu";
611 reg = <0xffffc000 0x100>;
612 };
613
614 sysmgr: sysmgr@ffd06000 {
615 compatible = "altr,sys-mgr", "syscon";
616 reg = <0xffd06000 0x300>;
617 cpu1-start-addr = <0xffd06230>;
618 };
619
620 /* Local timer */
621 timer@ffffc600 {
622 compatible = "arm,cortex-a9-twd-timer";
623 reg = <0xffffc600 0x100>;
624 interrupts = <1 13 0xf04>;
625 clocks = <&mpu_periph_clk>;
626 };
627
628 timer0: timer0@ffc02700 {
629 compatible = "snps,dw-apb-timer";
630 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
631 reg = <0xffc02700 0x100>;
632 clocks = <&l4_sp_clk>;
633 clock-names = "timer";
634 };
635
636 timer1: timer1@ffc02800 {
637 compatible = "snps,dw-apb-timer";
638 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
639 reg = <0xffc02800 0x100>;
640 clocks = <&l4_sp_clk>;
641 clock-names = "timer";
642 };
643
644 timer2: timer2@ffd00000 {
645 compatible = "snps,dw-apb-timer";
646 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
647 reg = <0xffd00000 0x100>;
648 clocks = <&l4_sys_free_clk>;
649 clock-names = "timer";
650 };
651
652 timer3: timer3@ffd00100 {
653 compatible = "snps,dw-apb-timer";
654 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
655 reg = <0xffd01000 0x100>;
656 clocks = <&l4_sys_free_clk>;
657 clock-names = "timer";
658 };
659
660 uart0: serial0@ffc02000 {
661 compatible = "snps,dw-apb-uart";
662 reg = <0xffc02000 0x100>;
663 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
664 reg-shift = <2>;
665 reg-io-width = <4>;
666 clocks = <&l4_sp_clk>;
667 status = "disabled";
668 };
669
670 uart1: serial1@ffc02100 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0xffc02100 0x100>;
673 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
674 reg-shift = <2>;
675 reg-io-width = <4>;
676 clocks = <&l4_sp_clk>;
677 status = "disabled";
678 };
679
680 usbphy0: usbphy@0 {
681 #phy-cells = <0>;
682 compatible = "usb-nop-xceiv";
683 status = "okay";
684 };
685
686 usb0: usb@ffb00000 {
687 compatible = "snps,dwc2";
688 reg = <0xffb00000 0xffff>;
689 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&usb_clk>;
691 clock-names = "otg";
692 phys = <&usbphy0>;
693 phy-names = "usb2-phy";
694 status = "disabled";
695 };
696
697 usb1: usb@ffb40000 {
698 compatible = "snps,dwc2";
699 reg = <0xffb40000 0xffff>;
700 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&usb_clk>;
702 clock-names = "otg";
703 phys = <&usbphy0>;
704 phy-names = "usb2-phy";
705 status = "disabled";
706 };
707
708 watchdog0: watchdog@ffd00200 {
709 compatible = "snps,dw-wdt";
710 reg = <0xffd00200 0x100>;
711 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&l4_sys_free_clk>;
713 status = "disabled";
714 };
715
716 watchdog1: watchdog@ffd00300 {
717 compatible = "snps,dw-wdt";
718 reg = <0xffd00300 0x100>;
719 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&l4_sys_free_clk>;
721 status = "disabled";
722 };
723 };
724};