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1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/dma/at91.h>
49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 serial3 = &usart0;
63 serial4 = &usart1;
64 serial5 = &uart0;
65 serial6 = &uart1;
66 gpio0 = &pioA;
67 gpio1 = &pioB;
68 gpio2 = &pioC;
69 gpio3 = &pioD;
70 gpio4 = &pioE;
71 pwm0 = &pwm0;
72 ssc0 = &ssc0;
73 ssc1 = &ssc1;
74 tcb0 = &tcb0;
75 tcb1 = &tcb1;
76 i2c0 = &i2c0;
77 i2c1 = &i2c1;
78 i2c2 = &i2c2;
79 };
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu@0 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a5";
87 reg = <0>;
88 next-level-cache = <&L2>;
89 };
90 };
91
92 memory {
93 reg = <0x20000000 0x20000000>;
94 };
95
96 clocks {
97 slow_xtal: slow_xtal {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <0>;
101 };
102
103 main_xtal: main_xtal {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 };
108
109 adc_op_clk: adc_op_clk{
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <1000000>;
113 };
114 };
115
116 ns_sram: sram@210000 {
117 compatible = "mmio-sram";
118 reg = <0x00210000 0x10000>;
119 };
120
121 ahb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126
127 nfc_sram: sram@100000 {
128 compatible = "mmio-sram";
129 no-memory-wc;
130 reg = <0x100000 0x2400>;
131 };
132
133 usb0: gadget@400000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "atmel,sama5d3-udc";
137 reg = <0x00400000 0x100000
138 0xfc02c000 0x4000>;
139 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
140 clocks = <&udphs_clk>, <&utmi>;
141 clock-names = "pclk", "hclk";
142 status = "disabled";
143
144 ep@0 {
145 reg = <0>;
146 atmel,fifo-size = <64>;
147 atmel,nb-banks = <1>;
148 };
149
150 ep@1 {
151 reg = <1>;
152 atmel,fifo-size = <1024>;
153 atmel,nb-banks = <3>;
154 atmel,can-dma;
155 atmel,can-isoc;
156 };
157
158 ep@2 {
159 reg = <2>;
160 atmel,fifo-size = <1024>;
161 atmel,nb-banks = <3>;
162 atmel,can-dma;
163 atmel,can-isoc;
164 };
165
166 ep@3 {
167 reg = <3>;
168 atmel,fifo-size = <1024>;
169 atmel,nb-banks = <2>;
170 atmel,can-dma;
171 atmel,can-isoc;
172 };
173
174 ep@4 {
175 reg = <4>;
176 atmel,fifo-size = <1024>;
177 atmel,nb-banks = <2>;
178 atmel,can-dma;
179 atmel,can-isoc;
180 };
181
182 ep@5 {
183 reg = <5>;
184 atmel,fifo-size = <1024>;
185 atmel,nb-banks = <2>;
186 atmel,can-dma;
187 atmel,can-isoc;
188 };
189
190 ep@6 {
191 reg = <6>;
192 atmel,fifo-size = <1024>;
193 atmel,nb-banks = <2>;
194 atmel,can-dma;
195 atmel,can-isoc;
196 };
197
198 ep@7 {
199 reg = <7>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-dma;
203 atmel,can-isoc;
204 };
205
206 ep@8 {
207 reg = <8>;
208 atmel,fifo-size = <1024>;
209 atmel,nb-banks = <2>;
210 atmel,can-isoc;
211 };
212
213 ep@9 {
214 reg = <9>;
215 atmel,fifo-size = <1024>;
216 atmel,nb-banks = <2>;
217 atmel,can-isoc;
218 };
219
220 ep@10 {
221 reg = <10>;
222 atmel,fifo-size = <1024>;
223 atmel,nb-banks = <2>;
224 atmel,can-isoc;
225 };
226
227 ep@11 {
228 reg = <11>;
229 atmel,fifo-size = <1024>;
230 atmel,nb-banks = <2>;
231 atmel,can-isoc;
232 };
233
234 ep@12 {
235 reg = <12>;
236 atmel,fifo-size = <1024>;
237 atmel,nb-banks = <2>;
238 atmel,can-isoc;
239 };
240
241 ep@13 {
242 reg = <13>;
243 atmel,fifo-size = <1024>;
244 atmel,nb-banks = <2>;
245 atmel,can-isoc;
246 };
247
248 ep@14 {
249 reg = <14>;
250 atmel,fifo-size = <1024>;
251 atmel,nb-banks = <2>;
252 atmel,can-isoc;
253 };
254
255 ep@15 {
256 reg = <15>;
257 atmel,fifo-size = <1024>;
258 atmel,nb-banks = <2>;
259 atmel,can-isoc;
260 };
261 };
262
263 usb1: ohci@500000 {
264 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
265 reg = <0x00500000 0x100000>;
266 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
267 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
268 clock-names = "ohci_clk", "hclk", "uhpck";
269 status = "disabled";
270 };
271
272 usb2: ehci@600000 {
273 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
274 reg = <0x00600000 0x100000>;
275 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
276 clocks = <&utmi>, <&uhphs_clk>;
277 clock-names = "usb_clk", "ehci_clk";
278 status = "disabled";
279 };
280
281 L2: cache-controller@a00000 {
282 compatible = "arm,pl310-cache";
283 reg = <0x00a00000 0x1000>;
284 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
285 cache-unified;
286 cache-level = <2>;
287 };
288
289 ebi: ebi@10000000 {
290 compatible = "atmel,sama5d3-ebi";
291 #address-cells = <2>;
292 #size-cells = <1>;
293 atmel,smc = <&hsmc>;
294 reg = <0x10000000 0x10000000
295 0x60000000 0x28000000>;
296 ranges = <0x0 0x0 0x10000000 0x10000000
297 0x1 0x0 0x60000000 0x10000000
298 0x2 0x0 0x70000000 0x10000000
299 0x3 0x0 0x80000000 0x8000000>;
300 clocks = <&mck>;
301 status = "disabled";
302
303 nand_controller: nand-controller {
304 compatible = "atmel,sama5d3-nand-controller";
305 atmel,nfc-sram = <&nfc_sram>;
306 atmel,nfc-io = <&nfc_io>;
307 ecc-engine = <&pmecc>;
308 #address-cells = <2>;
309 #size-cells = <1>;
310 ranges;
311 status = "disabled";
312 };
313 };
314
315 nfc_io: nfc-io@90000000 {
316 compatible = "atmel,sama5d3-nfc-io", "syscon";
317 reg = <0x90000000 0x8000000>;
318 };
319
320 apb {
321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges;
325
326 hlcdc: hlcdc@f0000000 {
327 compatible = "atmel,sama5d4-hlcdc";
328 reg = <0xf0000000 0x4000>;
329 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
330 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
331 clock-names = "periph_clk","sys_clk", "slow_clk";
332 status = "disabled";
333
334 hlcdc-display-controller {
335 compatible = "atmel,hlcdc-display-controller";
336 #address-cells = <1>;
337 #size-cells = <0>;
338
339 port@0 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0>;
343 };
344 };
345
346 hlcdc_pwm: hlcdc-pwm {
347 compatible = "atmel,hlcdc-pwm";
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_lcd_pwm>;
350 #pwm-cells = <3>;
351 };
352 };
353
354 dma1: dma-controller@f0004000 {
355 compatible = "atmel,sama5d4-dma";
356 reg = <0xf0004000 0x200>;
357 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
358 #dma-cells = <1>;
359 clocks = <&dma1_clk>;
360 clock-names = "dma_clk";
361 };
362
363 isi: isi@f0008000 {
364 compatible = "atmel,at91sam9g45-isi";
365 reg = <0xf0008000 0x4000>;
366 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_isi_data_0_7>;
369 clocks = <&isi_clk>;
370 clock-names = "isi_clk";
371 status = "disabled";
372 port {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 };
376 };
377
378 ramc0: ramc@f0010000 {
379 compatible = "atmel,sama5d3-ddramc";
380 reg = <0xf0010000 0x200>;
381 clocks = <&ddrck>, <&mpddr_clk>;
382 clock-names = "ddrck", "mpddr";
383 };
384
385 dma0: dma-controller@f0014000 {
386 compatible = "atmel,sama5d4-dma";
387 reg = <0xf0014000 0x200>;
388 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
389 #dma-cells = <1>;
390 clocks = <&dma0_clk>;
391 clock-names = "dma_clk";
392 };
393
394 pmc: pmc@f0018000 {
395 compatible = "atmel,sama5d3-pmc", "syscon";
396 reg = <0xf0018000 0x120>;
397 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
398 interrupt-controller;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 #interrupt-cells = <1>;
402
403 main_rc_osc: main_rc_osc {
404 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
405 #clock-cells = <0>;
406 interrupt-parent = <&pmc>;
407 interrupts = <AT91_PMC_MOSCRCS>;
408 clock-frequency = <12000000>;
409 clock-accuracy = <100000000>;
410 };
411
412 main_osc: main_osc {
413 compatible = "atmel,at91rm9200-clk-main-osc";
414 #clock-cells = <0>;
415 interrupt-parent = <&pmc>;
416 interrupts = <AT91_PMC_MOSCS>;
417 clocks = <&main_xtal>;
418 };
419
420 main: mainck {
421 compatible = "atmel,at91sam9x5-clk-main";
422 #clock-cells = <0>;
423 interrupt-parent = <&pmc>;
424 interrupts = <AT91_PMC_MOSCSELS>;
425 clocks = <&main_rc_osc &main_osc>;
426 };
427
428 plla: pllack {
429 compatible = "atmel,sama5d3-clk-pll";
430 #clock-cells = <0>;
431 interrupt-parent = <&pmc>;
432 interrupts = <AT91_PMC_LOCKA>;
433 clocks = <&main>;
434 reg = <0>;
435 atmel,clk-input-range = <12000000 12000000>;
436 #atmel,pll-clk-output-range-cells = <4>;
437 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
438 };
439
440 plladiv: plladivck {
441 compatible = "atmel,at91sam9x5-clk-plldiv";
442 #clock-cells = <0>;
443 clocks = <&plla>;
444 };
445
446 utmi: utmick {
447 compatible = "atmel,at91sam9x5-clk-utmi";
448 #clock-cells = <0>;
449 interrupt-parent = <&pmc>;
450 interrupts = <AT91_PMC_LOCKU>;
451 clocks = <&main>;
452 };
453
454 mck: masterck {
455 compatible = "atmel,at91sam9x5-clk-master";
456 #clock-cells = <0>;
457 interrupt-parent = <&pmc>;
458 interrupts = <AT91_PMC_MCKRDY>;
459 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
460 atmel,clk-output-range = <125000000 200000000>;
461 atmel,clk-divisors = <1 2 4 3>;
462 };
463
464 h32ck: h32mxck {
465 #clock-cells = <0>;
466 compatible = "atmel,sama5d4-clk-h32mx";
467 clocks = <&mck>;
468 };
469
470 usb: usbck {
471 compatible = "atmel,at91sam9x5-clk-usb";
472 #clock-cells = <0>;
473 clocks = <&plladiv>, <&utmi>;
474 };
475
476 prog: progck {
477 compatible = "atmel,at91sam9x5-clk-programmable";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupt-parent = <&pmc>;
481 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
482
483 prog0: prog0 {
484 #clock-cells = <0>;
485 reg = <0>;
486 interrupts = <AT91_PMC_PCKRDY(0)>;
487 };
488
489 prog1: prog1 {
490 #clock-cells = <0>;
491 reg = <1>;
492 interrupts = <AT91_PMC_PCKRDY(1)>;
493 };
494
495 prog2: prog2 {
496 #clock-cells = <0>;
497 reg = <2>;
498 interrupts = <AT91_PMC_PCKRDY(2)>;
499 };
500 };
501
502 smd: smdclk {
503 compatible = "atmel,at91sam9x5-clk-smd";
504 #clock-cells = <0>;
505 clocks = <&plladiv>, <&utmi>;
506 };
507
508 systemck {
509 compatible = "atmel,at91rm9200-clk-system";
510 #address-cells = <1>;
511 #size-cells = <0>;
512
513 ddrck: ddrck {
514 #clock-cells = <0>;
515 reg = <2>;
516 clocks = <&mck>;
517 };
518
519 lcdck: lcdck {
520 #clock-cells = <0>;
521 reg = <3>;
522 clocks = <&mck>;
523 };
524
525 smdck: smdck {
526 #clock-cells = <0>;
527 reg = <4>;
528 clocks = <&smd>;
529 };
530
531 uhpck: uhpck {
532 #clock-cells = <0>;
533 reg = <6>;
534 clocks = <&usb>;
535 };
536
537 udpck: udpck {
538 #clock-cells = <0>;
539 reg = <7>;
540 clocks = <&usb>;
541 };
542
543 pck0: pck0 {
544 #clock-cells = <0>;
545 reg = <8>;
546 clocks = <&prog0>;
547 };
548
549 pck1: pck1 {
550 #clock-cells = <0>;
551 reg = <9>;
552 clocks = <&prog1>;
553 };
554
555 pck2: pck2 {
556 #clock-cells = <0>;
557 reg = <10>;
558 clocks = <&prog2>;
559 };
560 };
561
562 periph32ck {
563 compatible = "atmel,at91sam9x5-clk-peripheral";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clocks = <&h32ck>;
567
568 pioD_clk: pioD_clk {
569 #clock-cells = <0>;
570 reg = <5>;
571 };
572
573 usart0_clk: usart0_clk {
574 #clock-cells = <0>;
575 reg = <6>;
576 };
577
578 usart1_clk: usart1_clk {
579 #clock-cells = <0>;
580 reg = <7>;
581 };
582
583 icm_clk: icm_clk {
584 #clock-cells = <0>;
585 reg = <9>;
586 };
587
588 aes_clk: aes_clk {
589 #clock-cells = <0>;
590 reg = <12>;
591 };
592
593 tdes_clk: tdes_clk {
594 #clock-cells = <0>;
595 reg = <14>;
596 };
597
598 sha_clk: sha_clk {
599 #clock-cells = <0>;
600 reg = <15>;
601 };
602
603 matrix1_clk: matrix1_clk {
604 #clock-cells = <0>;
605 reg = <17>;
606 };
607
608 hsmc_clk: hsmc_clk {
609 #clock-cells = <0>;
610 reg = <22>;
611 };
612
613 pioA_clk: pioA_clk {
614 #clock-cells = <0>;
615 reg = <23>;
616 };
617
618 pioB_clk: pioB_clk {
619 #clock-cells = <0>;
620 reg = <24>;
621 };
622
623 pioC_clk: pioC_clk {
624 #clock-cells = <0>;
625 reg = <25>;
626 };
627
628 pioE_clk: pioE_clk {
629 #clock-cells = <0>;
630 reg = <26>;
631 };
632
633 uart0_clk: uart0_clk {
634 #clock-cells = <0>;
635 reg = <27>;
636 };
637
638 uart1_clk: uart1_clk {
639 #clock-cells = <0>;
640 reg = <28>;
641 };
642
643 usart2_clk: usart2_clk {
644 #clock-cells = <0>;
645 reg = <29>;
646 };
647
648 usart3_clk: usart3_clk {
649 #clock-cells = <0>;
650 reg = <30>;
651 };
652
653 usart4_clk: usart4_clk {
654 #clock-cells = <0>;
655 reg = <31>;
656 };
657
658 twi0_clk: twi0_clk {
659 reg = <32>;
660 #clock-cells = <0>;
661 };
662
663 twi1_clk: twi1_clk {
664 #clock-cells = <0>;
665 reg = <33>;
666 };
667
668 twi2_clk: twi2_clk {
669 #clock-cells = <0>;
670 reg = <34>;
671 };
672
673 mci0_clk: mci0_clk {
674 #clock-cells = <0>;
675 reg = <35>;
676 };
677
678 mci1_clk: mci1_clk {
679 #clock-cells = <0>;
680 reg = <36>;
681 };
682
683 spi0_clk: spi0_clk {
684 #clock-cells = <0>;
685 reg = <37>;
686 };
687
688 spi1_clk: spi1_clk {
689 #clock-cells = <0>;
690 reg = <38>;
691 };
692
693 spi2_clk: spi2_clk {
694 #clock-cells = <0>;
695 reg = <39>;
696 };
697
698 tcb0_clk: tcb0_clk {
699 #clock-cells = <0>;
700 reg = <40>;
701 };
702
703 tcb1_clk: tcb1_clk {
704 #clock-cells = <0>;
705 reg = <41>;
706 };
707
708 tcb2_clk: tcb2_clk {
709 #clock-cells = <0>;
710 reg = <42>;
711 };
712
713 pwm_clk: pwm_clk {
714 #clock-cells = <0>;
715 reg = <43>;
716 };
717
718 adc_clk: adc_clk {
719 #clock-cells = <0>;
720 reg = <44>;
721 };
722
723 dbgu_clk: dbgu_clk {
724 #clock-cells = <0>;
725 reg = <45>;
726 };
727
728 uhphs_clk: uhphs_clk {
729 #clock-cells = <0>;
730 reg = <46>;
731 };
732
733 udphs_clk: udphs_clk {
734 #clock-cells = <0>;
735 reg = <47>;
736 };
737
738 ssc0_clk: ssc0_clk {
739 #clock-cells = <0>;
740 reg = <48>;
741 };
742
743 ssc1_clk: ssc1_clk {
744 #clock-cells = <0>;
745 reg = <49>;
746 };
747
748 trng_clk: trng_clk {
749 #clock-cells = <0>;
750 reg = <53>;
751 };
752
753 macb0_clk: macb0_clk {
754 #clock-cells = <0>;
755 reg = <54>;
756 };
757
758 macb1_clk: macb1_clk {
759 #clock-cells = <0>;
760 reg = <55>;
761 };
762
763 fuse_clk: fuse_clk {
764 #clock-cells = <0>;
765 reg = <57>;
766 };
767
768 securam_clk: securam_clk {
769 #clock-cells = <0>;
770 reg = <59>;
771 };
772
773 smd_clk: smd_clk {
774 #clock-cells = <0>;
775 reg = <61>;
776 };
777
778 twi3_clk: twi3_clk {
779 #clock-cells = <0>;
780 reg = <62>;
781 };
782
783 catb_clk: catb_clk {
784 #clock-cells = <0>;
785 reg = <63>;
786 };
787 };
788
789 periph64ck {
790 compatible = "atmel,at91sam9x5-clk-peripheral";
791 #address-cells = <1>;
792 #size-cells = <0>;
793 clocks = <&mck>;
794
795 dma0_clk: dma0_clk {
796 #clock-cells = <0>;
797 reg = <8>;
798 };
799
800 cpkcc_clk: cpkcc_clk {
801 #clock-cells = <0>;
802 reg = <10>;
803 };
804
805 aesb_clk: aesb_clk {
806 #clock-cells = <0>;
807 reg = <13>;
808 };
809
810 mpddr_clk: mpddr_clk {
811 #clock-cells = <0>;
812 reg = <16>;
813 };
814
815 matrix0_clk: matrix0_clk {
816 #clock-cells = <0>;
817 reg = <18>;
818 };
819
820 vdec_clk: vdec_clk {
821 #clock-cells = <0>;
822 reg = <19>;
823 };
824
825 dma1_clk: dma1_clk {
826 #clock-cells = <0>;
827 reg = <50>;
828 };
829
830 lcdc_clk: lcdc_clk {
831 #clock-cells = <0>;
832 reg = <51>;
833 };
834
835 isi_clk: isi_clk {
836 #clock-cells = <0>;
837 reg = <52>;
838 };
839 };
840 };
841
842 mmc0: mmc@f8000000 {
843 compatible = "atmel,hsmci";
844 reg = <0xf8000000 0x600>;
845 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
846 dmas = <&dma1
847 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
848 | AT91_XDMAC_DT_PERID(0))>;
849 dma-names = "rxtx";
850 pinctrl-names = "default";
851 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
852 status = "disabled";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 clocks = <&mci0_clk>;
856 clock-names = "mci_clk";
857 };
858
859 uart0: serial@f8004000 {
860 compatible = "atmel,at91sam9260-usart";
861 reg = <0xf8004000 0x100>;
862 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
863 dmas = <&dma0
864 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
865 | AT91_XDMAC_DT_PERID(22))>,
866 <&dma0
867 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
868 | AT91_XDMAC_DT_PERID(23))>;
869 dma-names = "tx", "rx";
870 pinctrl-names = "default";
871 pinctrl-0 = <&pinctrl_uart0>;
872 clocks = <&uart0_clk>;
873 clock-names = "usart";
874 status = "disabled";
875 };
876
877 ssc0: ssc@f8008000 {
878 compatible = "atmel,at91sam9g45-ssc";
879 reg = <0xf8008000 0x4000>;
880 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
883 dmas = <&dma1
884 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
885 | AT91_XDMAC_DT_PERID(26))>,
886 <&dma1
887 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
888 | AT91_XDMAC_DT_PERID(27))>;
889 dma-names = "tx", "rx";
890 clocks = <&ssc0_clk>;
891 clock-names = "pclk";
892 status = "disabled";
893 };
894
895 pwm0: pwm@f800c000 {
896 compatible = "atmel,sama5d3-pwm";
897 reg = <0xf800c000 0x300>;
898 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
899 #pwm-cells = <3>;
900 clocks = <&pwm_clk>;
901 status = "disabled";
902 };
903
904 spi0: spi@f8010000 {
905 #address-cells = <1>;
906 #size-cells = <0>;
907 compatible = "atmel,at91rm9200-spi";
908 reg = <0xf8010000 0x100>;
909 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
910 dmas = <&dma1
911 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
912 | AT91_XDMAC_DT_PERID(10))>,
913 <&dma1
914 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
915 | AT91_XDMAC_DT_PERID(11))>;
916 dma-names = "tx", "rx";
917 pinctrl-names = "default";
918 pinctrl-0 = <&pinctrl_spi0>;
919 clocks = <&spi0_clk>;
920 clock-names = "spi_clk";
921 status = "disabled";
922 };
923
924 i2c0: i2c@f8014000 {
925 compatible = "atmel,sama5d4-i2c";
926 reg = <0xf8014000 0x4000>;
927 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
928 dmas = <&dma1
929 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
930 | AT91_XDMAC_DT_PERID(2))>,
931 <&dma1
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
933 | AT91_XDMAC_DT_PERID(3))>;
934 dma-names = "tx", "rx";
935 pinctrl-names = "default";
936 pinctrl-0 = <&pinctrl_i2c0>;
937 #address-cells = <1>;
938 #size-cells = <0>;
939 clocks = <&twi0_clk>;
940 status = "disabled";
941 };
942
943 i2c1: i2c@f8018000 {
944 compatible = "atmel,sama5d4-i2c";
945 reg = <0xf8018000 0x4000>;
946 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
947 dmas = <&dma0
948 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
949 | AT91_XDMAC_DT_PERID(4))>,
950 <&dma0
951 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
952 | AT91_XDMAC_DT_PERID(5))>;
953 dma-names = "tx", "rx";
954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_i2c1>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 clocks = <&twi1_clk>;
959 status = "disabled";
960 };
961
962 tcb0: timer@f801c000 {
963 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
964 #address-cells = <1>;
965 #size-cells = <0>;
966 reg = <0xf801c000 0x100>;
967 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
968 clocks = <&tcb0_clk>, <&clk32k>;
969 clock-names = "t0_clk", "slow_clk";
970 };
971
972 macb0: ethernet@f8020000 {
973 compatible = "atmel,sama5d4-gem";
974 reg = <0xf8020000 0x100>;
975 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_macb0_rmii>;
978 #address-cells = <1>;
979 #size-cells = <0>;
980 clocks = <&macb0_clk>, <&macb0_clk>;
981 clock-names = "hclk", "pclk";
982 status = "disabled";
983 };
984
985 i2c2: i2c@f8024000 {
986 compatible = "atmel,sama5d4-i2c";
987 reg = <0xf8024000 0x4000>;
988 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
989 dmas = <&dma1
990 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
991 | AT91_XDMAC_DT_PERID(6))>,
992 <&dma1
993 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
994 | AT91_XDMAC_DT_PERID(7))>;
995 dma-names = "tx", "rx";
996 pinctrl-names = "default";
997 pinctrl-0 = <&pinctrl_i2c2>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1000 clocks = <&twi2_clk>;
1001 status = "disabled";
1002 };
1003
1004 sfr: sfr@f8028000 {
1005 compatible = "atmel,sama5d4-sfr", "syscon";
1006 reg = <0xf8028000 0x60>;
1007 };
1008
1009 usart0: serial@f802c000 {
1010 compatible = "atmel,at91sam9260-usart";
1011 reg = <0xf802c000 0x100>;
1012 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1013 dmas = <&dma0
1014 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1015 | AT91_XDMAC_DT_PERID(36))>,
1016 <&dma0
1017 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1018 | AT91_XDMAC_DT_PERID(37))>;
1019 dma-names = "tx", "rx";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1022 clocks = <&usart0_clk>;
1023 clock-names = "usart";
1024 status = "disabled";
1025 };
1026
1027 usart1: serial@f8030000 {
1028 compatible = "atmel,at91sam9260-usart";
1029 reg = <0xf8030000 0x100>;
1030 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1031 dmas = <&dma0
1032 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1033 | AT91_XDMAC_DT_PERID(38))>,
1034 <&dma0
1035 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1036 | AT91_XDMAC_DT_PERID(39))>;
1037 dma-names = "tx", "rx";
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1040 clocks = <&usart1_clk>;
1041 clock-names = "usart";
1042 status = "disabled";
1043 };
1044
1045 mmc1: mmc@fc000000 {
1046 compatible = "atmel,hsmci";
1047 reg = <0xfc000000 0x600>;
1048 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1049 dmas = <&dma1
1050 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1051 | AT91_XDMAC_DT_PERID(1))>;
1052 dma-names = "rxtx";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1055 status = "disabled";
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 clocks = <&mci1_clk>;
1059 clock-names = "mci_clk";
1060 };
1061
1062 uart1: serial@fc004000 {
1063 compatible = "atmel,at91sam9260-usart";
1064 reg = <0xfc004000 0x100>;
1065 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1066 dmas = <&dma0
1067 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1068 | AT91_XDMAC_DT_PERID(24))>,
1069 <&dma0
1070 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1071 | AT91_XDMAC_DT_PERID(25))>;
1072 dma-names = "tx", "rx";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&pinctrl_uart1>;
1075 clocks = <&uart1_clk>;
1076 clock-names = "usart";
1077 status = "disabled";
1078 };
1079
1080 usart2: serial@fc008000 {
1081 compatible = "atmel,at91sam9260-usart";
1082 reg = <0xfc008000 0x100>;
1083 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1084 dmas = <&dma1
1085 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1086 | AT91_XDMAC_DT_PERID(16))>,
1087 <&dma1
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1089 | AT91_XDMAC_DT_PERID(17))>;
1090 dma-names = "tx", "rx";
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1093 clocks = <&usart2_clk>;
1094 clock-names = "usart";
1095 status = "disabled";
1096 };
1097
1098 usart3: serial@fc00c000 {
1099 compatible = "atmel,at91sam9260-usart";
1100 reg = <0xfc00c000 0x100>;
1101 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1102 dmas = <&dma1
1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1104 | AT91_XDMAC_DT_PERID(18))>,
1105 <&dma1
1106 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1107 | AT91_XDMAC_DT_PERID(19))>;
1108 dma-names = "tx", "rx";
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&pinctrl_usart3>;
1111 clocks = <&usart3_clk>;
1112 clock-names = "usart";
1113 status = "disabled";
1114 };
1115
1116 usart4: serial@fc010000 {
1117 compatible = "atmel,at91sam9260-usart";
1118 reg = <0xfc010000 0x100>;
1119 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1120 dmas = <&dma1
1121 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1122 | AT91_XDMAC_DT_PERID(20))>,
1123 <&dma1
1124 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1125 | AT91_XDMAC_DT_PERID(21))>;
1126 dma-names = "tx", "rx";
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&pinctrl_usart4>;
1129 clocks = <&usart4_clk>;
1130 clock-names = "usart";
1131 status = "disabled";
1132 };
1133
1134 ssc1: ssc@fc014000 {
1135 compatible = "atmel,at91sam9g45-ssc";
1136 reg = <0xfc014000 0x4000>;
1137 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1140 dmas = <&dma1
1141 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1142 | AT91_XDMAC_DT_PERID(28))>,
1143 <&dma1
1144 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1145 | AT91_XDMAC_DT_PERID(29))>;
1146 dma-names = "tx", "rx";
1147 clocks = <&ssc1_clk>;
1148 clock-names = "pclk";
1149 status = "disabled";
1150 };
1151
1152 spi1: spi@fc018000 {
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 compatible = "atmel,at91rm9200-spi";
1156 reg = <0xfc018000 0x100>;
1157 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1158 dmas = <&dma1
1159 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1160 | AT91_XDMAC_DT_PERID(12))>,
1161 <&dma1
1162 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1163 | AT91_XDMAC_DT_PERID(13))>;
1164 dma-names = "tx", "rx";
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&pinctrl_spi1>;
1167 clocks = <&spi1_clk>;
1168 clock-names = "spi_clk";
1169 status = "disabled";
1170 };
1171
1172 spi2: spi@fc01c000 {
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175 compatible = "atmel,at91rm9200-spi";
1176 reg = <0xfc01c000 0x100>;
1177 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1178 dmas = <&dma0
1179 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1180 | AT91_XDMAC_DT_PERID(14))>,
1181 <&dma0
1182 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1183 | AT91_XDMAC_DT_PERID(15))>;
1184 dma-names = "tx", "rx";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&pinctrl_spi2>;
1187 clocks = <&spi2_clk>;
1188 clock-names = "spi_clk";
1189 status = "disabled";
1190 };
1191
1192 tcb1: timer@fc020000 {
1193 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196 reg = <0xfc020000 0x100>;
1197 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1198 clocks = <&tcb1_clk>, <&clk32k>;
1199 clock-names = "t0_clk", "slow_clk";
1200 };
1201
1202 tcb2: timer@fc024000 {
1203 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 reg = <0xfc024000 0x100>;
1207 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
1208 clocks = <&tcb2_clk>, <&clk32k>;
1209 clock-names = "t0_clk", "slow_clk";
1210 };
1211
1212 macb1: ethernet@fc028000 {
1213 compatible = "atmel,sama5d4-gem";
1214 reg = <0xfc028000 0x100>;
1215 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&pinctrl_macb1_rmii>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 clocks = <&macb1_clk>, <&macb1_clk>;
1221 clock-names = "hclk", "pclk";
1222 status = "disabled";
1223 };
1224
1225 trng@fc030000 {
1226 compatible = "atmel,at91sam9g45-trng";
1227 reg = <0xfc030000 0x100>;
1228 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&trng_clk>;
1230 };
1231
1232 adc0: adc@fc034000 {
1233 compatible = "atmel,at91sam9x5-adc";
1234 reg = <0xfc034000 0x100>;
1235 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1236 clocks = <&adc_clk>,
1237 <&adc_op_clk>;
1238 clock-names = "adc_clk", "adc_op_clk";
1239 atmel,adc-channels-used = <0x01f>;
1240 atmel,adc-startup-time = <40>;
1241 atmel,adc-use-external-triggers;
1242 atmel,adc-vref = <3000>;
1243 atmel,adc-res = <8 10>;
1244 atmel,adc-sample-hold-time = <11>;
1245 atmel,adc-res-names = "lowres", "highres";
1246 atmel,adc-ts-pressure-threshold = <10000>;
1247 status = "disabled";
1248
1249 trigger0 {
1250 trigger-name = "external-rising";
1251 trigger-value = <0x1>;
1252 trigger-external;
1253 };
1254 trigger1 {
1255 trigger-name = "external-falling";
1256 trigger-value = <0x2>;
1257 trigger-external;
1258 };
1259 trigger2 {
1260 trigger-name = "external-any";
1261 trigger-value = <0x3>;
1262 trigger-external;
1263 };
1264 trigger3 {
1265 trigger-name = "continuous";
1266 trigger-value = <0x6>;
1267 };
1268 };
1269
1270 aes@fc044000 {
1271 compatible = "atmel,at91sam9g46-aes";
1272 reg = <0xfc044000 0x100>;
1273 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1274 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1275 | AT91_XDMAC_DT_PERID(41))>,
1276 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1277 | AT91_XDMAC_DT_PERID(40))>;
1278 dma-names = "tx", "rx";
1279 clocks = <&aes_clk>;
1280 clock-names = "aes_clk";
1281 status = "okay";
1282 };
1283
1284 tdes@fc04c000 {
1285 compatible = "atmel,at91sam9g46-tdes";
1286 reg = <0xfc04c000 0x100>;
1287 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1288 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1289 | AT91_XDMAC_DT_PERID(42))>,
1290 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1291 | AT91_XDMAC_DT_PERID(43))>;
1292 dma-names = "tx", "rx";
1293 clocks = <&tdes_clk>;
1294 clock-names = "tdes_clk";
1295 status = "okay";
1296 };
1297
1298 sha@fc050000 {
1299 compatible = "atmel,at91sam9g46-sha";
1300 reg = <0xfc050000 0x100>;
1301 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1302 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1303 | AT91_XDMAC_DT_PERID(44))>;
1304 dma-names = "tx";
1305 clocks = <&sha_clk>;
1306 clock-names = "sha_clk";
1307 status = "okay";
1308 };
1309
1310 hsmc: smc@fc05c000 {
1311 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
1312 reg = <0xfc05c000 0x1000>;
1313 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
1314 clocks = <&hsmc_clk>;
1315 #address-cells = <1>;
1316 #size-cells = <1>;
1317 ranges;
1318
1319 pmecc: ecc-engine@ffffc070 {
1320 compatible = "atmel,sama5d4-pmecc";
1321 reg = <0xfc05c070 0x490>,
1322 <0xfc05c500 0x100>;
1323 };
1324 };
1325
1326 rstc@fc068600 {
1327 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1328 reg = <0xfc068600 0x10>;
1329 clocks = <&clk32k>;
1330 };
1331
1332 shdwc@fc068610 {
1333 compatible = "atmel,at91sam9x5-shdwc";
1334 reg = <0xfc068610 0x10>;
1335 clocks = <&clk32k>;
1336 };
1337
1338 pit: timer@fc068630 {
1339 compatible = "atmel,at91sam9260-pit";
1340 reg = <0xfc068630 0x10>;
1341 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1342 clocks = <&h32ck>;
1343 };
1344
1345 watchdog@fc068640 {
1346 compatible = "atmel,sama5d4-wdt";
1347 reg = <0xfc068640 0x10>;
1348 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1349 clocks = <&clk32k>;
1350 status = "disabled";
1351 };
1352
1353 clk32k: sckc@fc068650 {
1354 compatible = "atmel,sama5d4-sckc";
1355 reg = <0xfc068650 0x4>;
1356 #clock-cells = <0>;
1357 clocks = <&slow_xtal>;
1358 };
1359
1360 rtc@fc0686b0 {
1361 compatible = "atmel,at91rm9200-rtc";
1362 reg = <0xfc0686b0 0x30>;
1363 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1364 clocks = <&clk32k>;
1365 };
1366
1367 dbgu: serial@fc069000 {
1368 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1369 reg = <0xfc069000 0x200>;
1370 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&pinctrl_dbgu>;
1373 clocks = <&dbgu_clk>;
1374 clock-names = "usart";
1375 status = "disabled";
1376 };
1377
1378
1379 pinctrl@fc06a000 {
1380 #address-cells = <1>;
1381 #size-cells = <1>;
1382 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
1383 ranges = <0xfc068000 0xfc068000 0x100
1384 0xfc06a000 0xfc06a000 0x4000>;
1385 /* WARNING: revisit as pin spec has changed */
1386 atmel,mux-mask = <
1387 /* A B C */
1388 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1389 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1390 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1391 0x0003ff00 0x8002a800 0x00000000 /* pioD */
1392 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1393 >;
1394
1395 pioA: gpio@fc06a000 {
1396 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1397 reg = <0xfc06a000 0x100>;
1398 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1399 #gpio-cells = <2>;
1400 gpio-controller;
1401 interrupt-controller;
1402 #interrupt-cells = <2>;
1403 clocks = <&pioA_clk>;
1404 };
1405
1406 pioB: gpio@fc06b000 {
1407 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1408 reg = <0xfc06b000 0x100>;
1409 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1410 #gpio-cells = <2>;
1411 gpio-controller;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1414 clocks = <&pioB_clk>;
1415 };
1416
1417 pioC: gpio@fc06c000 {
1418 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1419 reg = <0xfc06c000 0x100>;
1420 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1421 #gpio-cells = <2>;
1422 gpio-controller;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1425 clocks = <&pioC_clk>;
1426 };
1427
1428 pioD: gpio@fc068000 {
1429 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1430 reg = <0xfc068000 0x100>;
1431 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1432 #gpio-cells = <2>;
1433 gpio-controller;
1434 interrupt-controller;
1435 #interrupt-cells = <2>;
1436 clocks = <&pioD_clk>;
1437 };
1438
1439 pioE: gpio@fc06d000 {
1440 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1441 reg = <0xfc06d000 0x100>;
1442 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1443 #gpio-cells = <2>;
1444 gpio-controller;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1447 clocks = <&pioE_clk>;
1448 };
1449
1450 /* pinctrl pin settings */
1451 adc0 {
1452 pinctrl_adc0_adtrg: adc0_adtrg {
1453 atmel,pins =
1454 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1455 };
1456 pinctrl_adc0_ad0: adc0_ad0 {
1457 atmel,pins =
1458 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1459 };
1460 pinctrl_adc0_ad1: adc0_ad1 {
1461 atmel,pins =
1462 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1463 };
1464 pinctrl_adc0_ad2: adc0_ad2 {
1465 atmel,pins =
1466 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1467 };
1468 pinctrl_adc0_ad3: adc0_ad3 {
1469 atmel,pins =
1470 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1471 };
1472 pinctrl_adc0_ad4: adc0_ad4 {
1473 atmel,pins =
1474 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1475 };
1476 };
1477
1478 dbgu {
1479 pinctrl_dbgu: dbgu-0 {
1480 atmel,pins =
1481 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
1482 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
1483 };
1484 };
1485
1486 ebi {
1487 pinctrl_ebi_addr: ebi-addr-0 {
1488 atmel,pins =
1489 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
1490 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
1491 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
1492 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
1493 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
1494 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1495 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1496 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1497 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1498 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1499 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1500 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1501 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
1502 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
1503 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
1504 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
1505 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
1506 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1507 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1508 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
1509 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
1510 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1511 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1512 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
1513 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
1514 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1515 };
1516
1517 pinctrl_ebi_nand_addr: ebi-addr-1 {
1518 atmel,pins =
1519 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1520 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1521 };
1522
1523 pinctrl_ebi_cs0: ebi-cs0-0 {
1524 atmel,pins =
1525 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1526 };
1527
1528 pinctrl_ebi_cs1: ebi-cs1-0 {
1529 atmel,pins =
1530 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1531 };
1532
1533 pinctrl_ebi_cs2: ebi-cs2-0 {
1534 atmel,pins =
1535 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1536 };
1537
1538 pinctrl_ebi_cs3: ebi-cs3-0 {
1539 atmel,pins =
1540 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1541 };
1542
1543 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
1544 atmel,pins =
1545 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1546 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1547 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1548 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1549 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1550 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1551 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1552 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1553 };
1554
1555 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
1556 atmel,pins =
1557 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
1558 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
1559 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
1560 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
1561 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
1562 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
1563 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
1564 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
1565 };
1566
1567 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
1568 atmel,pins =
1569 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1570 };
1571
1572 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
1573 atmel,pins =
1574 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1575 };
1576
1577 pinctrl_ebi_nwait: ebi-nwait-0 {
1578 atmel,pins =
1579 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1580 };
1581
1582 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
1583 atmel,pins =
1584 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1585 };
1586
1587 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1588 atmel,pins =
1589 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1590 };
1591 };
1592
1593 i2c0 {
1594 pinctrl_i2c0: i2c0-0 {
1595 atmel,pins =
1596 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1597 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1598 };
1599 };
1600
1601 i2c1 {
1602 pinctrl_i2c1: i2c1-0 {
1603 atmel,pins =
1604 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1605 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1606 };
1607 };
1608
1609 i2c2 {
1610 pinctrl_i2c2: i2c2-0 {
1611 atmel,pins =
1612 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1613 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1614 };
1615 };
1616
1617 isi {
1618 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1619 atmel,pins =
1620 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1621 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1622 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1623 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1624 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1625 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1626 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1627 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1628 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1629 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1630 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1631 };
1632 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1633 atmel,pins =
1634 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1635 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1636 };
1637 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1638 atmel,pins =
1639 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1640 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1641 };
1642 };
1643
1644 lcd {
1645 pinctrl_lcd_base: lcd-base-0 {
1646 atmel,pins =
1647 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1648 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1649 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1650 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1651 };
1652 pinctrl_lcd_pwm: lcd-pwm-0 {
1653 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1654 };
1655 pinctrl_lcd_rgb444: lcd-rgb-0 {
1656 atmel,pins =
1657 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1658 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1659 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1660 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1661 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1662 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1663 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1664 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1665 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1666 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1667 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1668 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1669 };
1670 pinctrl_lcd_rgb565: lcd-rgb-1 {
1671 atmel,pins =
1672 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1673 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1674 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1675 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1676 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1677 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1678 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1679 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1680 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1681 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1682 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1683 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1684 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1685 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1686 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1687 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1688 };
1689 pinctrl_lcd_rgb666: lcd-rgb-2 {
1690 atmel,pins =
1691 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1692 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1693 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1694 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1695 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1696 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1697 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1698 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1699 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1700 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1701 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1702 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1703 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1704 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1705 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1706 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1707 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1708 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1709 };
1710 pinctrl_lcd_rgb777: lcd-rgb-3 {
1711 atmel,pins =
1712 /* LCDDAT0 conflicts with TMS */
1713 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1714 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1715 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1716 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1717 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1718 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1719 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1720 /* LCDDAT8 conflicts with TCK */
1721 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1722 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1723 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1724 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1725 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1726 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1727 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1728 /* LCDDAT16 conflicts with NTRST */
1729 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1730 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1731 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1732 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1733 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1734 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1735 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1736 };
1737 pinctrl_lcd_rgb888: lcd-rgb-4 {
1738 atmel,pins =
1739 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1740 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1741 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1742 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1743 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1744 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1745 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1746 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1747 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1748 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1749 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1750 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1751 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1752 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1753 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1754 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1755 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1756 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1757 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1758 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1759 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1760 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1761 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1762 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1763 };
1764 };
1765
1766 macb0 {
1767 pinctrl_macb0_rmii: macb0_rmii-0 {
1768 atmel,pins =
1769 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1770 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1771 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1772 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1773 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1774 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1775 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1776 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1777 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1778 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1779 >;
1780 };
1781 };
1782
1783 macb1 {
1784 pinctrl_macb1_rmii: macb1_rmii-0 {
1785 atmel,pins =
1786 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1787 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1788 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1789 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1790 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1791 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1792 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1793 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1794 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1795 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1796 >;
1797 };
1798 };
1799
1800 mmc0 {
1801 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1802 atmel,pins =
1803 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1804 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1805 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1806 >;
1807 };
1808 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1809 atmel,pins =
1810 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1811 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1812 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1813 >;
1814 };
1815 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1816 atmel,pins =
1817 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1818 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1819 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1820 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1821 >;
1822 };
1823 };
1824
1825 mmc1 {
1826 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1827 atmel,pins =
1828 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1829 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1830 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1831 >;
1832 };
1833 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1834 atmel,pins =
1835 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1836 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1837 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1838 >;
1839 };
1840 };
1841
1842 nand0 {
1843 pinctrl_nand: nand-0 {
1844 atmel,pins =
1845 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1846 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1847
1848 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1849 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1850
1851 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1852 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1853 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1854 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1855 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1856 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1857 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1858 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1859 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1860 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1861 };
1862 };
1863
1864 spi0 {
1865 pinctrl_spi0: spi0-0 {
1866 atmel,pins =
1867 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1868 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1869 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1870 >;
1871 };
1872 };
1873
1874 ssc0 {
1875 pinctrl_ssc0_tx: ssc0_tx {
1876 atmel,pins =
1877 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1878 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1879 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1880 };
1881
1882 pinctrl_ssc0_rx: ssc0_rx {
1883 atmel,pins =
1884 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1885 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1886 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1887 };
1888 };
1889
1890 ssc1 {
1891 pinctrl_ssc1_tx: ssc1_tx {
1892 atmel,pins =
1893 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1894 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1895 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1896 };
1897
1898 pinctrl_ssc1_rx: ssc1_rx {
1899 atmel,pins =
1900 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1901 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1902 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1903 };
1904 };
1905
1906 spi1 {
1907 pinctrl_spi1: spi1-0 {
1908 atmel,pins =
1909 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1910 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1911 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1912 >;
1913 };
1914 };
1915
1916 spi2 {
1917 pinctrl_spi2: spi2-0 {
1918 atmel,pins =
1919 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1920 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1921 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1922 >;
1923 };
1924 };
1925
1926 uart0 {
1927 pinctrl_uart0: uart0-0 {
1928 atmel,pins =
1929 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1930 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1931 >;
1932 };
1933 };
1934
1935 uart1 {
1936 pinctrl_uart1: uart1-0 {
1937 atmel,pins =
1938 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
1939 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
1940 >;
1941 };
1942 };
1943
1944 usart0 {
1945 pinctrl_usart0: usart0-0 {
1946 atmel,pins =
1947 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1948 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1949 >;
1950 };
1951 pinctrl_usart0_rts: usart0_rts-0 {
1952 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1953 };
1954 pinctrl_usart0_cts: usart0_cts-0 {
1955 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1956 };
1957 };
1958
1959 usart1 {
1960 pinctrl_usart1: usart1-0 {
1961 atmel,pins =
1962 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1963 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1964 >;
1965 };
1966 pinctrl_usart1_rts: usart1_rts-0 {
1967 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1968 };
1969 pinctrl_usart1_cts: usart1_cts-0 {
1970 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1971 };
1972 };
1973
1974 usart2 {
1975 pinctrl_usart2: usart2-0 {
1976 atmel,pins =
1977 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1978 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
1979 >;
1980 };
1981 pinctrl_usart2_rts: usart2_rts-0 {
1982 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1983 };
1984 pinctrl_usart2_cts: usart2_cts-0 {
1985 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1986 };
1987 };
1988
1989 usart3 {
1990 pinctrl_usart3: usart3-0 {
1991 atmel,pins =
1992 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1993 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1994 >;
1995 };
1996 };
1997
1998 usart4 {
1999 pinctrl_usart4: usart4-0 {
2000 atmel,pins =
2001 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
2002 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
2003 >;
2004 };
2005 pinctrl_usart4_rts: usart4_rts-0 {
2006 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
2007 };
2008 pinctrl_usart4_cts: usart4_cts-0 {
2009 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
2010 };
2011 };
2012 };
2013
2014 aic: interrupt-controller@fc06e000 {
2015 #interrupt-cells = <3>;
2016 compatible = "atmel,sama5d4-aic";
2017 interrupt-controller;
2018 reg = <0xfc06e000 0x200>;
2019 atmel,external-irqs = <56>;
2020 };
2021 };
2022 };
2023};
1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/dma/at91.h>
49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 serial3 = &usart0;
63 serial4 = &usart1;
64 serial5 = &uart0;
65 serial6 = &uart1;
66 gpio0 = &pioA;
67 gpio1 = &pioB;
68 gpio2 = &pioC;
69 gpio3 = &pioD;
70 gpio4 = &pioE;
71 pwm0 = &pwm0;
72 ssc0 = &ssc0;
73 ssc1 = &ssc1;
74 tcb0 = &tcb0;
75 tcb1 = &tcb1;
76 i2c0 = &i2c0;
77 i2c1 = &i2c1;
78 i2c2 = &i2c2;
79 };
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu@0 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a5";
87 reg = <0>;
88 next-level-cache = <&L2>;
89 };
90 };
91
92 memory {
93 reg = <0x20000000 0x20000000>;
94 };
95
96 clocks {
97 slow_xtal: slow_xtal {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <0>;
101 };
102
103 main_xtal: main_xtal {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 };
108
109 adc_op_clk: adc_op_clk{
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <1000000>;
113 };
114 };
115
116 ns_sram: sram@00210000 {
117 compatible = "mmio-sram";
118 reg = <0x00210000 0x10000>;
119 };
120
121 ahb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126
127 usb0: gadget@00400000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "atmel,sama5d3-udc";
131 reg = <0x00400000 0x100000
132 0xfc02c000 0x4000>;
133 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&udphs_clk>, <&utmi>;
135 clock-names = "pclk", "hclk";
136 status = "disabled";
137
138 ep0 {
139 reg = <0>;
140 atmel,fifo-size = <64>;
141 atmel,nb-banks = <1>;
142 };
143
144 ep1 {
145 reg = <1>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <3>;
148 atmel,can-dma;
149 atmel,can-isoc;
150 };
151
152 ep2 {
153 reg = <2>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <3>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep3 {
161 reg = <3>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep4 {
169 reg = <4>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep5 {
177 reg = <5>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep6 {
185 reg = <6>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-dma;
189 atmel,can-isoc;
190 };
191
192 ep7 {
193 reg = <7>;
194 atmel,fifo-size = <1024>;
195 atmel,nb-banks = <2>;
196 atmel,can-dma;
197 atmel,can-isoc;
198 };
199
200 ep8 {
201 reg = <8>;
202 atmel,fifo-size = <1024>;
203 atmel,nb-banks = <2>;
204 atmel,can-isoc;
205 };
206
207 ep9 {
208 reg = <9>;
209 atmel,fifo-size = <1024>;
210 atmel,nb-banks = <2>;
211 atmel,can-isoc;
212 };
213
214 ep10 {
215 reg = <10>;
216 atmel,fifo-size = <1024>;
217 atmel,nb-banks = <2>;
218 atmel,can-isoc;
219 };
220
221 ep11 {
222 reg = <11>;
223 atmel,fifo-size = <1024>;
224 atmel,nb-banks = <2>;
225 atmel,can-isoc;
226 };
227
228 ep12 {
229 reg = <12>;
230 atmel,fifo-size = <1024>;
231 atmel,nb-banks = <2>;
232 atmel,can-isoc;
233 };
234
235 ep13 {
236 reg = <13>;
237 atmel,fifo-size = <1024>;
238 atmel,nb-banks = <2>;
239 atmel,can-isoc;
240 };
241
242 ep14 {
243 reg = <14>;
244 atmel,fifo-size = <1024>;
245 atmel,nb-banks = <2>;
246 atmel,can-isoc;
247 };
248
249 ep15 {
250 reg = <15>;
251 atmel,fifo-size = <1024>;
252 atmel,nb-banks = <2>;
253 atmel,can-isoc;
254 };
255 };
256
257 usb1: ohci@00500000 {
258 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
259 reg = <0x00500000 0x100000>;
260 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
261 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
262 clock-names = "ohci_clk", "hclk", "uhpck";
263 status = "disabled";
264 };
265
266 usb2: ehci@00600000 {
267 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
268 reg = <0x00600000 0x100000>;
269 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
270 clocks = <&utmi>, <&uhphs_clk>;
271 clock-names = "usb_clk", "ehci_clk";
272 status = "disabled";
273 };
274
275 L2: cache-controller@00a00000 {
276 compatible = "arm,pl310-cache";
277 reg = <0x00a00000 0x1000>;
278 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
279 cache-unified;
280 cache-level = <2>;
281 };
282
283 nand0: nand@80000000 {
284 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
285 #address-cells = <1>;
286 #size-cells = <1>;
287 ranges;
288 reg = < 0x80000000 0x08000000 /* EBI CS3 */
289 0xfc05c070 0x00000490 /* SMC PMECC regs */
290 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
291 >;
292 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
293 atmel,nand-addr-offset = <21>;
294 atmel,nand-cmd-offset = <22>;
295 atmel,nand-has-dma;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_nand>;
298 status = "disabled";
299
300 nfc@90000000 {
301 compatible = "atmel,sama5d3-nfc";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 reg = <
305 0x90000000 0x08000000 /* NFC Command Registers */
306 0xfc05c000 0x00000070 /* NFC HSMC regs */
307 0x00100000 0x00100000 /* NFC SRAM banks */
308 >;
309 clocks = <&hsmc_clk>;
310 atmel,write-by-sram;
311 };
312 };
313
314 apb {
315 compatible = "simple-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges;
319
320 hlcdc: hlcdc@f0000000 {
321 compatible = "atmel,sama5d4-hlcdc";
322 reg = <0xf0000000 0x4000>;
323 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
324 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
325 clock-names = "periph_clk","sys_clk", "slow_clk";
326 status = "disabled";
327
328 hlcdc-display-controller {
329 compatible = "atmel,hlcdc-display-controller";
330 #address-cells = <1>;
331 #size-cells = <0>;
332
333 port@0 {
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0>;
337 };
338 };
339
340 hlcdc_pwm: hlcdc-pwm {
341 compatible = "atmel,hlcdc-pwm";
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_lcd_pwm>;
344 #pwm-cells = <3>;
345 };
346 };
347
348 dma1: dma-controller@f0004000 {
349 compatible = "atmel,sama5d4-dma";
350 reg = <0xf0004000 0x200>;
351 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
352 #dma-cells = <1>;
353 clocks = <&dma1_clk>;
354 clock-names = "dma_clk";
355 };
356
357 isi: isi@f0008000 {
358 compatible = "atmel,at91sam9g45-isi";
359 reg = <0xf0008000 0x4000>;
360 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_isi_data_0_7>;
363 clocks = <&isi_clk>;
364 clock-names = "isi_clk";
365 status = "disabled";
366 port {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 };
370 };
371
372 ramc0: ramc@f0010000 {
373 compatible = "atmel,sama5d3-ddramc";
374 reg = <0xf0010000 0x200>;
375 clocks = <&ddrck>, <&mpddr_clk>;
376 clock-names = "ddrck", "mpddr";
377 };
378
379 dma0: dma-controller@f0014000 {
380 compatible = "atmel,sama5d4-dma";
381 reg = <0xf0014000 0x200>;
382 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
383 #dma-cells = <1>;
384 clocks = <&dma0_clk>;
385 clock-names = "dma_clk";
386 };
387
388 pmc: pmc@f0018000 {
389 compatible = "atmel,sama5d3-pmc", "syscon";
390 reg = <0xf0018000 0x120>;
391 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
392 interrupt-controller;
393 #address-cells = <1>;
394 #size-cells = <0>;
395 #interrupt-cells = <1>;
396
397 main_rc_osc: main_rc_osc {
398 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
399 #clock-cells = <0>;
400 interrupt-parent = <&pmc>;
401 interrupts = <AT91_PMC_MOSCRCS>;
402 clock-frequency = <12000000>;
403 clock-accuracy = <100000000>;
404 };
405
406 main_osc: main_osc {
407 compatible = "atmel,at91rm9200-clk-main-osc";
408 #clock-cells = <0>;
409 interrupt-parent = <&pmc>;
410 interrupts = <AT91_PMC_MOSCS>;
411 clocks = <&main_xtal>;
412 };
413
414 main: mainck {
415 compatible = "atmel,at91sam9x5-clk-main";
416 #clock-cells = <0>;
417 interrupt-parent = <&pmc>;
418 interrupts = <AT91_PMC_MOSCSELS>;
419 clocks = <&main_rc_osc &main_osc>;
420 };
421
422 plla: pllack {
423 compatible = "atmel,sama5d3-clk-pll";
424 #clock-cells = <0>;
425 interrupt-parent = <&pmc>;
426 interrupts = <AT91_PMC_LOCKA>;
427 clocks = <&main>;
428 reg = <0>;
429 atmel,clk-input-range = <12000000 12000000>;
430 #atmel,pll-clk-output-range-cells = <4>;
431 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
432 };
433
434 plladiv: plladivck {
435 compatible = "atmel,at91sam9x5-clk-plldiv";
436 #clock-cells = <0>;
437 clocks = <&plla>;
438 };
439
440 utmi: utmick {
441 compatible = "atmel,at91sam9x5-clk-utmi";
442 #clock-cells = <0>;
443 interrupt-parent = <&pmc>;
444 interrupts = <AT91_PMC_LOCKU>;
445 clocks = <&main>;
446 };
447
448 mck: masterck {
449 compatible = "atmel,at91sam9x5-clk-master";
450 #clock-cells = <0>;
451 interrupt-parent = <&pmc>;
452 interrupts = <AT91_PMC_MCKRDY>;
453 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
454 atmel,clk-output-range = <125000000 200000000>;
455 atmel,clk-divisors = <1 2 4 3>;
456 };
457
458 h32ck: h32mxck {
459 #clock-cells = <0>;
460 compatible = "atmel,sama5d4-clk-h32mx";
461 clocks = <&mck>;
462 };
463
464 usb: usbck {
465 compatible = "atmel,at91sam9x5-clk-usb";
466 #clock-cells = <0>;
467 clocks = <&plladiv>, <&utmi>;
468 };
469
470 prog: progck {
471 compatible = "atmel,at91sam9x5-clk-programmable";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 interrupt-parent = <&pmc>;
475 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
476
477 prog0: prog0 {
478 #clock-cells = <0>;
479 reg = <0>;
480 interrupts = <AT91_PMC_PCKRDY(0)>;
481 };
482
483 prog1: prog1 {
484 #clock-cells = <0>;
485 reg = <1>;
486 interrupts = <AT91_PMC_PCKRDY(1)>;
487 };
488
489 prog2: prog2 {
490 #clock-cells = <0>;
491 reg = <2>;
492 interrupts = <AT91_PMC_PCKRDY(2)>;
493 };
494 };
495
496 smd: smdclk {
497 compatible = "atmel,at91sam9x5-clk-smd";
498 #clock-cells = <0>;
499 clocks = <&plladiv>, <&utmi>;
500 };
501
502 systemck {
503 compatible = "atmel,at91rm9200-clk-system";
504 #address-cells = <1>;
505 #size-cells = <0>;
506
507 ddrck: ddrck {
508 #clock-cells = <0>;
509 reg = <2>;
510 clocks = <&mck>;
511 };
512
513 lcdck: lcdck {
514 #clock-cells = <0>;
515 reg = <3>;
516 clocks = <&mck>;
517 };
518
519 smdck: smdck {
520 #clock-cells = <0>;
521 reg = <4>;
522 clocks = <&smd>;
523 };
524
525 uhpck: uhpck {
526 #clock-cells = <0>;
527 reg = <6>;
528 clocks = <&usb>;
529 };
530
531 udpck: udpck {
532 #clock-cells = <0>;
533 reg = <7>;
534 clocks = <&usb>;
535 };
536
537 pck0: pck0 {
538 #clock-cells = <0>;
539 reg = <8>;
540 clocks = <&prog0>;
541 };
542
543 pck1: pck1 {
544 #clock-cells = <0>;
545 reg = <9>;
546 clocks = <&prog1>;
547 };
548
549 pck2: pck2 {
550 #clock-cells = <0>;
551 reg = <10>;
552 clocks = <&prog2>;
553 };
554 };
555
556 periph32ck {
557 compatible = "atmel,at91sam9x5-clk-peripheral";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 clocks = <&h32ck>;
561
562 pioD_clk: pioD_clk {
563 #clock-cells = <0>;
564 reg = <5>;
565 };
566
567 usart0_clk: usart0_clk {
568 #clock-cells = <0>;
569 reg = <6>;
570 };
571
572 usart1_clk: usart1_clk {
573 #clock-cells = <0>;
574 reg = <7>;
575 };
576
577 icm_clk: icm_clk {
578 #clock-cells = <0>;
579 reg = <9>;
580 };
581
582 aes_clk: aes_clk {
583 #clock-cells = <0>;
584 reg = <12>;
585 };
586
587 tdes_clk: tdes_clk {
588 #clock-cells = <0>;
589 reg = <14>;
590 };
591
592 sha_clk: sha_clk {
593 #clock-cells = <0>;
594 reg = <15>;
595 };
596
597 matrix1_clk: matrix1_clk {
598 #clock-cells = <0>;
599 reg = <17>;
600 };
601
602 hsmc_clk: hsmc_clk {
603 #clock-cells = <0>;
604 reg = <22>;
605 };
606
607 pioA_clk: pioA_clk {
608 #clock-cells = <0>;
609 reg = <23>;
610 };
611
612 pioB_clk: pioB_clk {
613 #clock-cells = <0>;
614 reg = <24>;
615 };
616
617 pioC_clk: pioC_clk {
618 #clock-cells = <0>;
619 reg = <25>;
620 };
621
622 pioE_clk: pioE_clk {
623 #clock-cells = <0>;
624 reg = <26>;
625 };
626
627 uart0_clk: uart0_clk {
628 #clock-cells = <0>;
629 reg = <27>;
630 };
631
632 uart1_clk: uart1_clk {
633 #clock-cells = <0>;
634 reg = <28>;
635 };
636
637 usart2_clk: usart2_clk {
638 #clock-cells = <0>;
639 reg = <29>;
640 };
641
642 usart3_clk: usart3_clk {
643 #clock-cells = <0>;
644 reg = <30>;
645 };
646
647 usart4_clk: usart4_clk {
648 #clock-cells = <0>;
649 reg = <31>;
650 };
651
652 twi0_clk: twi0_clk {
653 reg = <32>;
654 #clock-cells = <0>;
655 };
656
657 twi1_clk: twi1_clk {
658 #clock-cells = <0>;
659 reg = <33>;
660 };
661
662 twi2_clk: twi2_clk {
663 #clock-cells = <0>;
664 reg = <34>;
665 };
666
667 mci0_clk: mci0_clk {
668 #clock-cells = <0>;
669 reg = <35>;
670 };
671
672 mci1_clk: mci1_clk {
673 #clock-cells = <0>;
674 reg = <36>;
675 };
676
677 spi0_clk: spi0_clk {
678 #clock-cells = <0>;
679 reg = <37>;
680 };
681
682 spi1_clk: spi1_clk {
683 #clock-cells = <0>;
684 reg = <38>;
685 };
686
687 spi2_clk: spi2_clk {
688 #clock-cells = <0>;
689 reg = <39>;
690 };
691
692 tcb0_clk: tcb0_clk {
693 #clock-cells = <0>;
694 reg = <40>;
695 };
696
697 tcb1_clk: tcb1_clk {
698 #clock-cells = <0>;
699 reg = <41>;
700 };
701
702 tcb2_clk: tcb2_clk {
703 #clock-cells = <0>;
704 reg = <42>;
705 };
706
707 pwm_clk: pwm_clk {
708 #clock-cells = <0>;
709 reg = <43>;
710 };
711
712 adc_clk: adc_clk {
713 #clock-cells = <0>;
714 reg = <44>;
715 };
716
717 dbgu_clk: dbgu_clk {
718 #clock-cells = <0>;
719 reg = <45>;
720 };
721
722 uhphs_clk: uhphs_clk {
723 #clock-cells = <0>;
724 reg = <46>;
725 };
726
727 udphs_clk: udphs_clk {
728 #clock-cells = <0>;
729 reg = <47>;
730 };
731
732 ssc0_clk: ssc0_clk {
733 #clock-cells = <0>;
734 reg = <48>;
735 };
736
737 ssc1_clk: ssc1_clk {
738 #clock-cells = <0>;
739 reg = <49>;
740 };
741
742 trng_clk: trng_clk {
743 #clock-cells = <0>;
744 reg = <53>;
745 };
746
747 macb0_clk: macb0_clk {
748 #clock-cells = <0>;
749 reg = <54>;
750 };
751
752 macb1_clk: macb1_clk {
753 #clock-cells = <0>;
754 reg = <55>;
755 };
756
757 fuse_clk: fuse_clk {
758 #clock-cells = <0>;
759 reg = <57>;
760 };
761
762 securam_clk: securam_clk {
763 #clock-cells = <0>;
764 reg = <59>;
765 };
766
767 smd_clk: smd_clk {
768 #clock-cells = <0>;
769 reg = <61>;
770 };
771
772 twi3_clk: twi3_clk {
773 #clock-cells = <0>;
774 reg = <62>;
775 };
776
777 catb_clk: catb_clk {
778 #clock-cells = <0>;
779 reg = <63>;
780 };
781 };
782
783 periph64ck {
784 compatible = "atmel,at91sam9x5-clk-peripheral";
785 #address-cells = <1>;
786 #size-cells = <0>;
787 clocks = <&mck>;
788
789 dma0_clk: dma0_clk {
790 #clock-cells = <0>;
791 reg = <8>;
792 };
793
794 cpkcc_clk: cpkcc_clk {
795 #clock-cells = <0>;
796 reg = <10>;
797 };
798
799 aesb_clk: aesb_clk {
800 #clock-cells = <0>;
801 reg = <13>;
802 };
803
804 mpddr_clk: mpddr_clk {
805 #clock-cells = <0>;
806 reg = <16>;
807 };
808
809 matrix0_clk: matrix0_clk {
810 #clock-cells = <0>;
811 reg = <18>;
812 };
813
814 vdec_clk: vdec_clk {
815 #clock-cells = <0>;
816 reg = <19>;
817 };
818
819 dma1_clk: dma1_clk {
820 #clock-cells = <0>;
821 reg = <50>;
822 };
823
824 lcdc_clk: lcdc_clk {
825 #clock-cells = <0>;
826 reg = <51>;
827 };
828
829 isi_clk: isi_clk {
830 #clock-cells = <0>;
831 reg = <52>;
832 };
833 };
834 };
835
836 mmc0: mmc@f8000000 {
837 compatible = "atmel,hsmci";
838 reg = <0xf8000000 0x600>;
839 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
840 dmas = <&dma1
841 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
842 | AT91_XDMAC_DT_PERID(0))>;
843 dma-names = "rxtx";
844 pinctrl-names = "default";
845 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
846 status = "disabled";
847 #address-cells = <1>;
848 #size-cells = <0>;
849 clocks = <&mci0_clk>;
850 clock-names = "mci_clk";
851 };
852
853 uart0: serial@f8004000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xf8004000 0x100>;
856 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
857 dmas = <&dma1
858 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
859 | AT91_XDMAC_DT_PERID(22))>,
860 <&dma1
861 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
862 | AT91_XDMAC_DT_PERID(23))>;
863 dma-names = "tx", "rx";
864 pinctrl-names = "default";
865 pinctrl-0 = <&pinctrl_uart0>;
866 clocks = <&uart0_clk>;
867 clock-names = "usart";
868 status = "disabled";
869 };
870
871 ssc0: ssc@f8008000 {
872 compatible = "atmel,at91sam9g45-ssc";
873 reg = <0xf8008000 0x4000>;
874 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
877 dmas = <&dma1
878 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
879 | AT91_XDMAC_DT_PERID(26))>,
880 <&dma1
881 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
882 | AT91_XDMAC_DT_PERID(27))>;
883 dma-names = "tx", "rx";
884 clocks = <&ssc0_clk>;
885 clock-names = "pclk";
886 status = "disabled";
887 };
888
889 pwm0: pwm@f800c000 {
890 compatible = "atmel,sama5d3-pwm";
891 reg = <0xf800c000 0x300>;
892 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
893 #pwm-cells = <3>;
894 clocks = <&pwm_clk>;
895 status = "disabled";
896 };
897
898 spi0: spi@f8010000 {
899 #address-cells = <1>;
900 #size-cells = <0>;
901 compatible = "atmel,at91rm9200-spi";
902 reg = <0xf8010000 0x100>;
903 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
904 dmas = <&dma1
905 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
906 | AT91_XDMAC_DT_PERID(10))>,
907 <&dma1
908 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
909 | AT91_XDMAC_DT_PERID(11))>;
910 dma-names = "tx", "rx";
911 pinctrl-names = "default";
912 pinctrl-0 = <&pinctrl_spi0>;
913 clocks = <&spi0_clk>;
914 clock-names = "spi_clk";
915 status = "disabled";
916 };
917
918 i2c0: i2c@f8014000 {
919 compatible = "atmel,sama5d4-i2c";
920 reg = <0xf8014000 0x4000>;
921 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
922 dmas = <&dma1
923 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
924 | AT91_XDMAC_DT_PERID(2))>,
925 <&dma1
926 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
927 | AT91_XDMAC_DT_PERID(3))>;
928 dma-names = "tx", "rx";
929 pinctrl-names = "default";
930 pinctrl-0 = <&pinctrl_i2c0>;
931 #address-cells = <1>;
932 #size-cells = <0>;
933 clocks = <&twi0_clk>;
934 status = "disabled";
935 };
936
937 i2c1: i2c@f8018000 {
938 compatible = "atmel,sama5d4-i2c";
939 reg = <0xf8018000 0x4000>;
940 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
941 dmas = <&dma1
942 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
943 | AT91_XDMAC_DT_PERID(4))>,
944 <&dma1
945 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
946 | AT91_XDMAC_DT_PERID(5))>;
947 dma-names = "tx", "rx";
948 pinctrl-names = "default";
949 pinctrl-0 = <&pinctrl_i2c1>;
950 #address-cells = <1>;
951 #size-cells = <0>;
952 clocks = <&twi1_clk>;
953 status = "disabled";
954 };
955
956 tcb0: timer@f801c000 {
957 compatible = "atmel,at91sam9x5-tcb";
958 reg = <0xf801c000 0x100>;
959 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
960 clocks = <&tcb0_clk>, <&clk32k>;
961 clock-names = "t0_clk", "slow_clk";
962 };
963
964 macb0: ethernet@f8020000 {
965 compatible = "atmel,sama5d4-gem";
966 reg = <0xf8020000 0x100>;
967 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&pinctrl_macb0_rmii>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 clocks = <&macb0_clk>, <&macb0_clk>;
973 clock-names = "hclk", "pclk";
974 status = "disabled";
975 };
976
977 i2c2: i2c@f8024000 {
978 compatible = "atmel,sama5d4-i2c";
979 reg = <0xf8024000 0x4000>;
980 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
981 dmas = <&dma1
982 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
983 | AT91_XDMAC_DT_PERID(6))>,
984 <&dma1
985 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
986 | AT91_XDMAC_DT_PERID(7))>;
987 dma-names = "tx", "rx";
988 pinctrl-names = "default";
989 pinctrl-0 = <&pinctrl_i2c2>;
990 #address-cells = <1>;
991 #size-cells = <0>;
992 clocks = <&twi2_clk>;
993 status = "disabled";
994 };
995
996 sfr: sfr@f8028000 {
997 compatible = "atmel,sama5d4-sfr", "syscon";
998 reg = <0xf8028000 0x60>;
999 };
1000
1001 usart0: serial@f802c000 {
1002 compatible = "atmel,at91sam9260-usart";
1003 reg = <0xf802c000 0x100>;
1004 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1005 dmas = <&dma0
1006 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1007 | AT91_XDMAC_DT_PERID(36))>,
1008 <&dma0
1009 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1010 | AT91_XDMAC_DT_PERID(37))>;
1011 dma-names = "tx", "rx";
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1014 clocks = <&usart0_clk>;
1015 clock-names = "usart";
1016 status = "disabled";
1017 };
1018
1019 usart1: serial@f8030000 {
1020 compatible = "atmel,at91sam9260-usart";
1021 reg = <0xf8030000 0x100>;
1022 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1023 dmas = <&dma0
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1025 | AT91_XDMAC_DT_PERID(38))>,
1026 <&dma0
1027 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1028 | AT91_XDMAC_DT_PERID(39))>;
1029 dma-names = "tx", "rx";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1032 clocks = <&usart1_clk>;
1033 clock-names = "usart";
1034 status = "disabled";
1035 };
1036
1037 mmc1: mmc@fc000000 {
1038 compatible = "atmel,hsmci";
1039 reg = <0xfc000000 0x600>;
1040 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1041 dmas = <&dma1
1042 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1043 | AT91_XDMAC_DT_PERID(1))>;
1044 dma-names = "rxtx";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1047 status = "disabled";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 clocks = <&mci1_clk>;
1051 clock-names = "mci_clk";
1052 };
1053
1054 uart1: serial@fc004000 {
1055 compatible = "atmel,at91sam9260-usart";
1056 reg = <0xfc004000 0x100>;
1057 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1058 dmas = <&dma1
1059 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1060 | AT91_XDMAC_DT_PERID(24))>,
1061 <&dma1
1062 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1063 | AT91_XDMAC_DT_PERID(25))>;
1064 dma-names = "tx", "rx";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&pinctrl_uart1>;
1067 clocks = <&uart1_clk>;
1068 clock-names = "usart";
1069 status = "disabled";
1070 };
1071
1072 usart2: serial@fc008000 {
1073 compatible = "atmel,at91sam9260-usart";
1074 reg = <0xfc008000 0x100>;
1075 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1076 dmas = <&dma1
1077 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1078 | AT91_XDMAC_DT_PERID(16))>,
1079 <&dma1
1080 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1081 | AT91_XDMAC_DT_PERID(17))>;
1082 dma-names = "tx", "rx";
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1085 clocks = <&usart2_clk>;
1086 clock-names = "usart";
1087 status = "disabled";
1088 };
1089
1090 usart3: serial@fc00c000 {
1091 compatible = "atmel,at91sam9260-usart";
1092 reg = <0xfc00c000 0x100>;
1093 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1094 dmas = <&dma1
1095 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1096 | AT91_XDMAC_DT_PERID(18))>,
1097 <&dma1
1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1099 | AT91_XDMAC_DT_PERID(19))>;
1100 dma-names = "tx", "rx";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&pinctrl_usart3>;
1103 clocks = <&usart3_clk>;
1104 clock-names = "usart";
1105 status = "disabled";
1106 };
1107
1108 usart4: serial@fc010000 {
1109 compatible = "atmel,at91sam9260-usart";
1110 reg = <0xfc010000 0x100>;
1111 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1112 dmas = <&dma1
1113 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1114 | AT91_XDMAC_DT_PERID(20))>,
1115 <&dma1
1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1117 | AT91_XDMAC_DT_PERID(21))>;
1118 dma-names = "tx", "rx";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&pinctrl_usart4>;
1121 clocks = <&usart4_clk>;
1122 clock-names = "usart";
1123 status = "disabled";
1124 };
1125
1126 ssc1: ssc@fc014000 {
1127 compatible = "atmel,at91sam9g45-ssc";
1128 reg = <0xfc014000 0x4000>;
1129 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1132 dmas = <&dma1
1133 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1134 | AT91_XDMAC_DT_PERID(28))>,
1135 <&dma1
1136 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1137 | AT91_XDMAC_DT_PERID(29))>;
1138 dma-names = "tx", "rx";
1139 clocks = <&ssc1_clk>;
1140 clock-names = "pclk";
1141 status = "disabled";
1142 };
1143
1144 spi1: spi@fc018000 {
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 compatible = "atmel,at91rm9200-spi";
1148 reg = <0xfc018000 0x100>;
1149 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1150 dmas = <&dma1
1151 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1152 | AT91_XDMAC_DT_PERID(12))>,
1153 <&dma1
1154 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1155 | AT91_XDMAC_DT_PERID(13))>;
1156 dma-names = "tx", "rx";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&pinctrl_spi1>;
1159 clocks = <&spi1_clk>;
1160 clock-names = "spi_clk";
1161 status = "disabled";
1162 };
1163
1164 spi2: spi@fc01c000 {
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1167 compatible = "atmel,at91rm9200-spi";
1168 reg = <0xfc01c000 0x100>;
1169 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1170 dmas = <&dma1
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1172 | AT91_XDMAC_DT_PERID(14))>,
1173 <&dma1
1174 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1175 | AT91_XDMAC_DT_PERID(15))>;
1176 dma-names = "tx", "rx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&pinctrl_spi2>;
1179 clocks = <&spi2_clk>;
1180 clock-names = "spi_clk";
1181 status = "disabled";
1182 };
1183
1184 tcb1: timer@fc020000 {
1185 compatible = "atmel,at91sam9x5-tcb";
1186 reg = <0xfc020000 0x100>;
1187 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1188 clocks = <&tcb1_clk>, <&clk32k>;
1189 clock-names = "t0_clk", "slow_clk";
1190 };
1191
1192 macb1: ethernet@fc028000 {
1193 compatible = "atmel,sama5d4-gem";
1194 reg = <0xfc028000 0x100>;
1195 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&pinctrl_macb1_rmii>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 clocks = <&macb1_clk>, <&macb1_clk>;
1201 clock-names = "hclk", "pclk";
1202 status = "disabled";
1203 };
1204
1205 adc0: adc@fc034000 {
1206 compatible = "atmel,at91sam9x5-adc";
1207 reg = <0xfc034000 0x100>;
1208 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1209 clocks = <&adc_clk>,
1210 <&adc_op_clk>;
1211 clock-names = "adc_clk", "adc_op_clk";
1212 atmel,adc-channels-used = <0x01f>;
1213 atmel,adc-startup-time = <40>;
1214 atmel,adc-use-external-triggers;
1215 atmel,adc-vref = <3000>;
1216 atmel,adc-res = <8 10>;
1217 atmel,adc-sample-hold-time = <11>;
1218 atmel,adc-res-names = "lowres", "highres";
1219 atmel,adc-ts-pressure-threshold = <10000>;
1220 status = "disabled";
1221
1222 trigger@0 {
1223 trigger-name = "external-rising";
1224 trigger-value = <0x1>;
1225 trigger-external;
1226 };
1227 trigger@1 {
1228 trigger-name = "external-falling";
1229 trigger-value = <0x2>;
1230 trigger-external;
1231 };
1232 trigger@2 {
1233 trigger-name = "external-any";
1234 trigger-value = <0x3>;
1235 trigger-external;
1236 };
1237 trigger@3 {
1238 trigger-name = "continuous";
1239 trigger-value = <0x6>;
1240 };
1241 };
1242
1243 aes@fc044000 {
1244 compatible = "atmel,at91sam9g46-aes";
1245 reg = <0xfc044000 0x100>;
1246 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1247 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1248 | AT91_XDMAC_DT_PERID(41))>,
1249 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1250 | AT91_XDMAC_DT_PERID(40))>;
1251 dma-names = "tx", "rx";
1252 clocks = <&aes_clk>;
1253 clock-names = "aes_clk";
1254 status = "okay";
1255 };
1256
1257 tdes@fc04c000 {
1258 compatible = "atmel,at91sam9g46-tdes";
1259 reg = <0xfc04c000 0x100>;
1260 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1261 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1262 | AT91_XDMAC_DT_PERID(42))>,
1263 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1264 | AT91_XDMAC_DT_PERID(43))>;
1265 dma-names = "tx", "rx";
1266 clocks = <&tdes_clk>;
1267 clock-names = "tdes_clk";
1268 status = "okay";
1269 };
1270
1271 sha@fc050000 {
1272 compatible = "atmel,at91sam9g46-sha";
1273 reg = <0xfc050000 0x100>;
1274 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1275 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1276 | AT91_XDMAC_DT_PERID(44))>;
1277 dma-names = "tx";
1278 clocks = <&sha_clk>;
1279 clock-names = "sha_clk";
1280 status = "okay";
1281 };
1282
1283 rstc@fc068600 {
1284 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1285 reg = <0xfc068600 0x10>;
1286 clocks = <&clk32k>;
1287 };
1288
1289 shdwc@fc068610 {
1290 compatible = "atmel,at91sam9x5-shdwc";
1291 reg = <0xfc068610 0x10>;
1292 clocks = <&clk32k>;
1293 };
1294
1295 pit: timer@fc068630 {
1296 compatible = "atmel,at91sam9260-pit";
1297 reg = <0xfc068630 0x10>;
1298 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1299 clocks = <&h32ck>;
1300 };
1301
1302 watchdog@fc068640 {
1303 compatible = "atmel,sama5d4-wdt";
1304 reg = <0xfc068640 0x10>;
1305 clocks = <&clk32k>;
1306 status = "disabled";
1307 };
1308
1309 sckc@fc068650 {
1310 compatible = "atmel,at91sam9x5-sckc";
1311 reg = <0xfc068650 0x4>;
1312
1313 slow_rc_osc: slow_rc_osc {
1314 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1315 #clock-cells = <0>;
1316 clock-frequency = <32768>;
1317 clock-accuracy = <250000000>;
1318 atmel,startup-time-usec = <75>;
1319 };
1320
1321 slow_osc: slow_osc {
1322 compatible = "atmel,at91sam9x5-clk-slow-osc";
1323 #clock-cells = <0>;
1324 clocks = <&slow_xtal>;
1325 atmel,startup-time-usec = <1200000>;
1326 };
1327
1328 clk32k: slowck {
1329 compatible = "atmel,at91sam9x5-clk-slow";
1330 #clock-cells = <0>;
1331 clocks = <&slow_rc_osc &slow_osc>;
1332 };
1333 };
1334
1335 rtc@fc0686b0 {
1336 compatible = "atmel,at91rm9200-rtc";
1337 reg = <0xfc0686b0 0x30>;
1338 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1339 clocks = <&clk32k>;
1340 };
1341
1342 dbgu: serial@fc069000 {
1343 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1344 reg = <0xfc069000 0x200>;
1345 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&pinctrl_dbgu>;
1348 clocks = <&dbgu_clk>;
1349 clock-names = "usart";
1350 status = "disabled";
1351 };
1352
1353
1354 pinctrl@fc06a000 {
1355 #address-cells = <1>;
1356 #size-cells = <1>;
1357 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1358 ranges = <0xfc068000 0xfc068000 0x100
1359 0xfc06a000 0xfc06a000 0x4000>;
1360 /* WARNING: revisit as pin spec has changed */
1361 atmel,mux-mask = <
1362 /* A B C */
1363 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1364 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1365 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1366 0x0003ff00 0x8002a800 0x00000000 /* pioD */
1367 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1368 >;
1369
1370 pioA: gpio@fc06a000 {
1371 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1372 reg = <0xfc06a000 0x100>;
1373 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1374 #gpio-cells = <2>;
1375 gpio-controller;
1376 interrupt-controller;
1377 #interrupt-cells = <2>;
1378 clocks = <&pioA_clk>;
1379 };
1380
1381 pioB: gpio@fc06b000 {
1382 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1383 reg = <0xfc06b000 0x100>;
1384 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1385 #gpio-cells = <2>;
1386 gpio-controller;
1387 interrupt-controller;
1388 #interrupt-cells = <2>;
1389 clocks = <&pioB_clk>;
1390 };
1391
1392 pioC: gpio@fc06c000 {
1393 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1394 reg = <0xfc06c000 0x100>;
1395 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1396 #gpio-cells = <2>;
1397 gpio-controller;
1398 interrupt-controller;
1399 #interrupt-cells = <2>;
1400 clocks = <&pioC_clk>;
1401 };
1402
1403 pioD: gpio@fc068000 {
1404 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1405 reg = <0xfc068000 0x100>;
1406 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1407 #gpio-cells = <2>;
1408 gpio-controller;
1409 interrupt-controller;
1410 #interrupt-cells = <2>;
1411 clocks = <&pioD_clk>;
1412 };
1413
1414 pioE: gpio@fc06d000 {
1415 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1416 reg = <0xfc06d000 0x100>;
1417 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1418 #gpio-cells = <2>;
1419 gpio-controller;
1420 interrupt-controller;
1421 #interrupt-cells = <2>;
1422 clocks = <&pioE_clk>;
1423 };
1424
1425 /* pinctrl pin settings */
1426 adc0 {
1427 pinctrl_adc0_adtrg: adc0_adtrg {
1428 atmel,pins =
1429 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1430 };
1431 pinctrl_adc0_ad0: adc0_ad0 {
1432 atmel,pins =
1433 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1434 };
1435 pinctrl_adc0_ad1: adc0_ad1 {
1436 atmel,pins =
1437 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1438 };
1439 pinctrl_adc0_ad2: adc0_ad2 {
1440 atmel,pins =
1441 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1442 };
1443 pinctrl_adc0_ad3: adc0_ad3 {
1444 atmel,pins =
1445 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1446 };
1447 pinctrl_adc0_ad4: adc0_ad4 {
1448 atmel,pins =
1449 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1450 };
1451 };
1452
1453 dbgu {
1454 pinctrl_dbgu: dbgu-0 {
1455 atmel,pins =
1456 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1457 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1458 };
1459 };
1460
1461 i2c0 {
1462 pinctrl_i2c0: i2c0-0 {
1463 atmel,pins =
1464 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1465 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1466 };
1467 };
1468
1469 i2c1 {
1470 pinctrl_i2c1: i2c1-0 {
1471 atmel,pins =
1472 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1473 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1474 };
1475 };
1476
1477 i2c2 {
1478 pinctrl_i2c2: i2c2-0 {
1479 atmel,pins =
1480 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1481 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1482 };
1483 };
1484
1485 isi {
1486 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1487 atmel,pins =
1488 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1489 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1490 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1491 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1492 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1493 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1494 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1495 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1496 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1497 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1498 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1499 };
1500 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1501 atmel,pins =
1502 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1503 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1504 };
1505 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1506 atmel,pins =
1507 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1508 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1509 };
1510 };
1511
1512 lcd {
1513 pinctrl_lcd_base: lcd-base-0 {
1514 atmel,pins =
1515 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1516 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1517 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1518 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1519 };
1520 pinctrl_lcd_pwm: lcd-pwm-0 {
1521 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1522 };
1523 pinctrl_lcd_rgb444: lcd-rgb-0 {
1524 atmel,pins =
1525 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1526 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1527 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1528 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1529 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1530 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1531 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1532 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1533 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1534 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1535 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1536 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1537 };
1538 pinctrl_lcd_rgb565: lcd-rgb-1 {
1539 atmel,pins =
1540 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1541 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1542 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1543 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1544 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1545 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1546 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1547 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1548 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1549 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1550 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1551 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1552 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1553 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1554 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1555 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1556 };
1557 pinctrl_lcd_rgb666: lcd-rgb-2 {
1558 atmel,pins =
1559 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1560 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1561 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1562 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1563 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1564 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1565 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1566 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1567 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1568 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1569 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1570 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1571 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1572 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1573 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1574 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1575 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1576 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1577 };
1578 pinctrl_lcd_rgb777: lcd-rgb-3 {
1579 atmel,pins =
1580 /* LCDDAT0 conflicts with TMS */
1581 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1582 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1583 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1584 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1585 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1586 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1587 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1588 /* LCDDAT8 conflicts with TCK */
1589 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1590 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1591 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1592 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1593 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1594 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1595 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1596 /* LCDDAT16 conflicts with NTRST */
1597 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1598 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1599 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1600 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1601 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1602 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1603 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1604 };
1605 pinctrl_lcd_rgb888: lcd-rgb-4 {
1606 atmel,pins =
1607 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1608 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1609 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1610 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1611 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1612 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1613 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1614 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1615 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1616 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1617 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1618 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1619 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1620 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1621 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1622 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1623 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1624 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1625 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1626 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1627 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1628 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1629 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1630 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1631 };
1632 };
1633
1634 macb0 {
1635 pinctrl_macb0_rmii: macb0_rmii-0 {
1636 atmel,pins =
1637 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1638 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1639 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1640 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1641 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1642 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1643 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1644 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1645 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1646 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1647 >;
1648 };
1649 };
1650
1651 macb1 {
1652 pinctrl_macb1_rmii: macb1_rmii-0 {
1653 atmel,pins =
1654 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1655 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1656 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1657 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1658 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1659 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1660 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1661 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1662 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1663 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1664 >;
1665 };
1666 };
1667
1668 mmc0 {
1669 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1670 atmel,pins =
1671 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1672 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1673 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1674 >;
1675 };
1676 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1677 atmel,pins =
1678 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1679 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1680 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1681 >;
1682 };
1683 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1684 atmel,pins =
1685 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1686 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1687 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1688 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1689 >;
1690 };
1691 };
1692
1693 mmc1 {
1694 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1695 atmel,pins =
1696 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1697 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1698 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1699 >;
1700 };
1701 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1702 atmel,pins =
1703 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1704 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1705 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1706 >;
1707 };
1708 };
1709
1710 nand0 {
1711 pinctrl_nand: nand-0 {
1712 atmel,pins =
1713 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1714 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1715
1716 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1717 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1718
1719 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1720 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1721 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1722 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1723 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1724 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1725 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1726 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1727 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1728 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1729 };
1730 };
1731
1732 spi0 {
1733 pinctrl_spi0: spi0-0 {
1734 atmel,pins =
1735 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1736 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1737 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1738 >;
1739 };
1740 };
1741
1742 ssc0 {
1743 pinctrl_ssc0_tx: ssc0_tx {
1744 atmel,pins =
1745 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1746 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1747 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1748 };
1749
1750 pinctrl_ssc0_rx: ssc0_rx {
1751 atmel,pins =
1752 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1753 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1754 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1755 };
1756 };
1757
1758 ssc1 {
1759 pinctrl_ssc1_tx: ssc1_tx {
1760 atmel,pins =
1761 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1762 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1763 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1764 };
1765
1766 pinctrl_ssc1_rx: ssc1_rx {
1767 atmel,pins =
1768 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1769 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1770 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1771 };
1772 };
1773
1774 spi1 {
1775 pinctrl_spi1: spi1-0 {
1776 atmel,pins =
1777 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1778 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1779 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1780 >;
1781 };
1782 };
1783
1784 spi2 {
1785 pinctrl_spi2: spi2-0 {
1786 atmel,pins =
1787 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1788 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1789 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1790 >;
1791 };
1792 };
1793
1794 uart0 {
1795 pinctrl_uart0: uart0-0 {
1796 atmel,pins =
1797 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1798 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1799 >;
1800 };
1801 };
1802
1803 uart1 {
1804 pinctrl_uart1: uart1-0 {
1805 atmel,pins =
1806 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */
1807 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */
1808 >;
1809 };
1810 };
1811
1812 usart0 {
1813 pinctrl_usart0: usart0-0 {
1814 atmel,pins =
1815 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1816 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1817 >;
1818 };
1819 pinctrl_usart0_rts: usart0_rts-0 {
1820 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1821 };
1822 pinctrl_usart0_cts: usart0_cts-0 {
1823 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1824 };
1825 };
1826
1827 usart1 {
1828 pinctrl_usart1: usart1-0 {
1829 atmel,pins =
1830 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1831 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1832 >;
1833 };
1834 pinctrl_usart1_rts: usart1_rts-0 {
1835 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1836 };
1837 pinctrl_usart1_cts: usart1_cts-0 {
1838 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1839 };
1840 };
1841
1842 usart2 {
1843 pinctrl_usart2: usart2-0 {
1844 atmel,pins =
1845 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1846 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1847 >;
1848 };
1849 pinctrl_usart2_rts: usart2_rts-0 {
1850 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1851 };
1852 pinctrl_usart2_cts: usart2_cts-0 {
1853 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1854 };
1855 };
1856
1857 usart3 {
1858 pinctrl_usart3: usart3-0 {
1859 atmel,pins =
1860 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1861 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1862 >;
1863 };
1864 };
1865
1866 usart4 {
1867 pinctrl_usart4: usart4-0 {
1868 atmel,pins =
1869 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1870 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1871 >;
1872 };
1873 pinctrl_usart4_rts: usart4_rts-0 {
1874 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1875 };
1876 pinctrl_usart4_cts: usart4_cts-0 {
1877 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1878 };
1879 };
1880 };
1881
1882 aic: interrupt-controller@fc06e000 {
1883 #interrupt-cells = <3>;
1884 compatible = "atmel,sama5d4-aic";
1885 interrupt-controller;
1886 reg = <0xfc06e000 0x200>;
1887 atmel,external-irqs = <56>;
1888 };
1889 };
1890 };
1891};