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1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/power/r8a7790-sysc.h>
17
18/ {
19 compatible = "renesas,r8a7790";
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
32 spi0 = &qspi;
33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
41 };
42
43 /*
44 * The external audio clocks are configured as 0 Hz fixed frequency
45 * clocks by default.
46 * Boards that provide audio clocks should override them.
47 */
48 audio_clk_a: audio_clk_a {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 };
53 audio_clk_b: audio_clk_b {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <0>;
57 };
58 audio_clk_c: audio_clk_c {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 /* External CAN clock */
65 can_clk: can {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 /* This value must be overridden by the board. */
69 clock-frequency = <0>;
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 enable-method = "renesas,apmu";
76
77 cpu0: cpu@0 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a15";
80 reg = <0>;
81 clock-frequency = <1300000000>;
82 voltage-tolerance = <1>; /* 1% */
83 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
84 clock-latency = <300000>; /* 300 us */
85 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
86 next-level-cache = <&L2_CA15>;
87 capacity-dmips-mhz = <1024>;
88
89 /* kHz - uV - OPPs unknown yet */
90 operating-points = <1400000 1000000>,
91 <1225000 1000000>,
92 <1050000 1000000>,
93 < 875000 1000000>,
94 < 700000 1000000>,
95 < 350000 1000000>;
96 };
97
98 cpu1: cpu@1 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a15";
101 reg = <1>;
102 clock-frequency = <1300000000>;
103 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
104 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
105 next-level-cache = <&L2_CA15>;
106 capacity-dmips-mhz = <1024>;
107 };
108
109 cpu2: cpu@2 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a15";
112 reg = <2>;
113 clock-frequency = <1300000000>;
114 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
115 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
116 next-level-cache = <&L2_CA15>;
117 capacity-dmips-mhz = <1024>;
118 };
119
120 cpu3: cpu@3 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a15";
123 reg = <3>;
124 clock-frequency = <1300000000>;
125 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
126 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
127 next-level-cache = <&L2_CA15>;
128 capacity-dmips-mhz = <1024>;
129 };
130
131 cpu4: cpu@100 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a7";
134 reg = <0x100>;
135 clock-frequency = <780000000>;
136 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
137 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
138 next-level-cache = <&L2_CA7>;
139 capacity-dmips-mhz = <539>;
140 };
141
142 cpu5: cpu@101 {
143 device_type = "cpu";
144 compatible = "arm,cortex-a7";
145 reg = <0x101>;
146 clock-frequency = <780000000>;
147 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
148 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
149 next-level-cache = <&L2_CA7>;
150 capacity-dmips-mhz = <539>;
151 };
152
153 cpu6: cpu@102 {
154 device_type = "cpu";
155 compatible = "arm,cortex-a7";
156 reg = <0x102>;
157 clock-frequency = <780000000>;
158 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
159 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
160 next-level-cache = <&L2_CA7>;
161 capacity-dmips-mhz = <539>;
162 };
163
164 cpu7: cpu@103 {
165 device_type = "cpu";
166 compatible = "arm,cortex-a7";
167 reg = <0x103>;
168 clock-frequency = <780000000>;
169 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
170 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
171 next-level-cache = <&L2_CA7>;
172 capacity-dmips-mhz = <539>;
173 };
174
175 L2_CA15: cache-controller-0 {
176 compatible = "cache";
177 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
178 cache-unified;
179 cache-level = <2>;
180 };
181
182 L2_CA7: cache-controller-1 {
183 compatible = "cache";
184 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
185 cache-unified;
186 cache-level = <2>;
187 };
188 };
189
190 /* External root clock */
191 extal_clk: extal {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 /* This value must be overridden by the board. */
195 clock-frequency = <0>;
196 };
197
198 /* External PCIe clock - can be overridden by the board */
199 pcie_bus_clk: pcie_bus {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <0>;
203 };
204
205 /* External SCIF clock */
206 scif_clk: scif {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 /* This value must be overridden by the board. */
210 clock-frequency = <0>;
211 };
212
213 soc {
214 compatible = "simple-bus";
215 interrupt-parent = <&gic>;
216
217 #address-cells = <2>;
218 #size-cells = <2>;
219 ranges;
220
221 gpio0: gpio@e6050000 {
222 compatible = "renesas,gpio-r8a7790",
223 "renesas,rcar-gen2-gpio";
224 reg = <0 0xe6050000 0 0x50>;
225 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
226 #gpio-cells = <2>;
227 gpio-controller;
228 gpio-ranges = <&pfc 0 0 32>;
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 clocks = <&cpg CPG_MOD 912>;
232 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
233 resets = <&cpg 912>;
234 };
235
236 gpio1: gpio@e6051000 {
237 compatible = "renesas,gpio-r8a7790",
238 "renesas,rcar-gen2-gpio";
239 reg = <0 0xe6051000 0 0x50>;
240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
241 #gpio-cells = <2>;
242 gpio-controller;
243 gpio-ranges = <&pfc 0 32 30>;
244 #interrupt-cells = <2>;
245 interrupt-controller;
246 clocks = <&cpg CPG_MOD 911>;
247 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
248 resets = <&cpg 911>;
249 };
250
251 gpio2: gpio@e6052000 {
252 compatible = "renesas,gpio-r8a7790",
253 "renesas,rcar-gen2-gpio";
254 reg = <0 0xe6052000 0 0x50>;
255 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
256 #gpio-cells = <2>;
257 gpio-controller;
258 gpio-ranges = <&pfc 0 64 30>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 clocks = <&cpg CPG_MOD 910>;
262 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
263 resets = <&cpg 910>;
264 };
265
266 gpio3: gpio@e6053000 {
267 compatible = "renesas,gpio-r8a7790",
268 "renesas,rcar-gen2-gpio";
269 reg = <0 0xe6053000 0 0x50>;
270 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 gpio-ranges = <&pfc 0 96 32>;
274 #interrupt-cells = <2>;
275 interrupt-controller;
276 clocks = <&cpg CPG_MOD 909>;
277 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
278 resets = <&cpg 909>;
279 };
280
281 gpio4: gpio@e6054000 {
282 compatible = "renesas,gpio-r8a7790",
283 "renesas,rcar-gen2-gpio";
284 reg = <0 0xe6054000 0 0x50>;
285 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
286 #gpio-cells = <2>;
287 gpio-controller;
288 gpio-ranges = <&pfc 0 128 32>;
289 #interrupt-cells = <2>;
290 interrupt-controller;
291 clocks = <&cpg CPG_MOD 908>;
292 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
293 resets = <&cpg 908>;
294 };
295
296 gpio5: gpio@e6055000 {
297 compatible = "renesas,gpio-r8a7790",
298 "renesas,rcar-gen2-gpio";
299 reg = <0 0xe6055000 0 0x50>;
300 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
301 #gpio-cells = <2>;
302 gpio-controller;
303 gpio-ranges = <&pfc 0 160 32>;
304 #interrupt-cells = <2>;
305 interrupt-controller;
306 clocks = <&cpg CPG_MOD 907>;
307 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
308 resets = <&cpg 907>;
309 };
310
311 pfc: pin-controller@e6060000 {
312 compatible = "renesas,pfc-r8a7790";
313 reg = <0 0xe6060000 0 0x250>;
314 };
315
316 cpg: clock-controller@e6150000 {
317 compatible = "renesas,r8a7790-cpg-mssr";
318 reg = <0 0xe6150000 0 0x1000>;
319 clocks = <&extal_clk>, <&usb_extal_clk>;
320 clock-names = "extal", "usb_extal";
321 #clock-cells = <2>;
322 #power-domain-cells = <0>;
323 #reset-cells = <1>;
324 };
325
326 apmu@e6151000 {
327 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
328 reg = <0 0xe6151000 0 0x188>;
329 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
330 };
331
332 apmu@e6152000 {
333 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
334 reg = <0 0xe6152000 0 0x188>;
335 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
336 };
337
338 rst: reset-controller@e6160000 {
339 compatible = "renesas,r8a7790-rst";
340 reg = <0 0xe6160000 0 0x0100>;
341 };
342
343 sysc: system-controller@e6180000 {
344 compatible = "renesas,r8a7790-sysc";
345 reg = <0 0xe6180000 0 0x0200>;
346 #power-domain-cells = <1>;
347 };
348
349 irqc0: interrupt-controller@e61c0000 {
350 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
351 #interrupt-cells = <2>;
352 interrupt-controller;
353 reg = <0 0xe61c0000 0 0x200>;
354 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&cpg CPG_MOD 407>;
359 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
360 resets = <&cpg 407>;
361 };
362
363 thermal: thermal@e61f0000 {
364 compatible = "renesas,thermal-r8a7790",
365 "renesas,rcar-gen2-thermal",
366 "renesas,rcar-thermal";
367 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
368 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cpg CPG_MOD 522>;
370 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
371 resets = <&cpg 522>;
372 #thermal-sensor-cells = <0>;
373 };
374
375 ipmmu_sy0: mmu@e6280000 {
376 compatible = "renesas,ipmmu-r8a7790",
377 "renesas,ipmmu-vmsa";
378 reg = <0 0xe6280000 0 0x1000>;
379 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
381 #iommu-cells = <1>;
382 status = "disabled";
383 };
384
385 ipmmu_sy1: mmu@e6290000 {
386 compatible = "renesas,ipmmu-r8a7790",
387 "renesas,ipmmu-vmsa";
388 reg = <0 0xe6290000 0 0x1000>;
389 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
390 #iommu-cells = <1>;
391 status = "disabled";
392 };
393
394 ipmmu_ds: mmu@e6740000 {
395 compatible = "renesas,ipmmu-r8a7790",
396 "renesas,ipmmu-vmsa";
397 reg = <0 0xe6740000 0 0x1000>;
398 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
400 #iommu-cells = <1>;
401 status = "disabled";
402 };
403
404 ipmmu_mp: mmu@ec680000 {
405 compatible = "renesas,ipmmu-r8a7790",
406 "renesas,ipmmu-vmsa";
407 reg = <0 0xec680000 0 0x1000>;
408 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
409 #iommu-cells = <1>;
410 status = "disabled";
411 };
412
413 ipmmu_mx: mmu@fe951000 {
414 compatible = "renesas,ipmmu-r8a7790",
415 "renesas,ipmmu-vmsa";
416 reg = <0 0xfe951000 0 0x1000>;
417 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
419 #iommu-cells = <1>;
420 status = "disabled";
421 };
422
423 ipmmu_rt: mmu@ffc80000 {
424 compatible = "renesas,ipmmu-r8a7790",
425 "renesas,ipmmu-vmsa";
426 reg = <0 0xffc80000 0 0x1000>;
427 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
428 #iommu-cells = <1>;
429 status = "disabled";
430 };
431
432 icram0: sram@e63a0000 {
433 compatible = "mmio-sram";
434 reg = <0 0xe63a0000 0 0x12000>;
435 };
436
437 icram1: sram@e63c0000 {
438 compatible = "mmio-sram";
439 reg = <0 0xe63c0000 0 0x1000>;
440 #address-cells = <1>;
441 #size-cells = <1>;
442 ranges = <0 0 0xe63c0000 0x1000>;
443
444 smp-sram@0 {
445 compatible = "renesas,smp-sram";
446 reg = <0 0x10>;
447 };
448 };
449
450 i2c0: i2c@e6508000 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 compatible = "renesas,i2c-r8a7790",
454 "renesas,rcar-gen2-i2c";
455 reg = <0 0xe6508000 0 0x40>;
456 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cpg CPG_MOD 931>;
458 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
459 resets = <&cpg 931>;
460 i2c-scl-internal-delay-ns = <110>;
461 status = "disabled";
462 };
463
464 i2c1: i2c@e6518000 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 compatible = "renesas,i2c-r8a7790",
468 "renesas,rcar-gen2-i2c";
469 reg = <0 0xe6518000 0 0x40>;
470 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cpg CPG_MOD 930>;
472 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
473 resets = <&cpg 930>;
474 i2c-scl-internal-delay-ns = <6>;
475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790",
482 "renesas,rcar-gen2-i2c";
483 reg = <0 0xe6530000 0 0x40>;
484 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cpg CPG_MOD 929>;
486 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
487 resets = <&cpg 929>;
488 i2c-scl-internal-delay-ns = <6>;
489 status = "disabled";
490 };
491
492 i2c3: i2c@e6540000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,i2c-r8a7790",
496 "renesas,rcar-gen2-i2c";
497 reg = <0 0xe6540000 0 0x40>;
498 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&cpg CPG_MOD 928>;
500 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
501 resets = <&cpg 928>;
502 i2c-scl-internal-delay-ns = <110>;
503 status = "disabled";
504 };
505
506 iic0: i2c@e6500000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "renesas,iic-r8a7790",
510 "renesas,rcar-gen2-iic",
511 "renesas,rmobile-iic";
512 reg = <0 0xe6500000 0 0x425>;
513 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&cpg CPG_MOD 318>;
515 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
516 <&dmac1 0x61>, <&dmac1 0x62>;
517 dma-names = "tx", "rx", "tx", "rx";
518 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
519 resets = <&cpg 318>;
520 status = "disabled";
521 };
522
523 iic1: i2c@e6510000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "renesas,iic-r8a7790",
527 "renesas,rcar-gen2-iic",
528 "renesas,rmobile-iic";
529 reg = <0 0xe6510000 0 0x425>;
530 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cpg CPG_MOD 323>;
532 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
533 <&dmac1 0x65>, <&dmac1 0x66>;
534 dma-names = "tx", "rx", "tx", "rx";
535 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
536 resets = <&cpg 323>;
537 status = "disabled";
538 };
539
540 iic2: i2c@e6520000 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "renesas,iic-r8a7790",
544 "renesas,rcar-gen2-iic",
545 "renesas,rmobile-iic";
546 reg = <0 0xe6520000 0 0x425>;
547 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cpg CPG_MOD 300>;
549 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
550 <&dmac1 0x69>, <&dmac1 0x6a>;
551 dma-names = "tx", "rx", "tx", "rx";
552 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
553 resets = <&cpg 300>;
554 status = "disabled";
555 };
556
557 iic3: i2c@e60b0000 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "renesas,iic-r8a7790",
561 "renesas,rcar-gen2-iic",
562 "renesas,rmobile-iic";
563 reg = <0 0xe60b0000 0 0x425>;
564 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cpg CPG_MOD 926>;
566 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
567 <&dmac1 0x77>, <&dmac1 0x78>;
568 dma-names = "tx", "rx", "tx", "rx";
569 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
570 resets = <&cpg 926>;
571 status = "disabled";
572 };
573
574 hsusb: usb@e6590000 {
575 compatible = "renesas,usbhs-r8a7790",
576 "renesas,rcar-gen2-usbhs";
577 reg = <0 0xe6590000 0 0x100>;
578 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cpg CPG_MOD 704>;
580 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
581 <&usb_dmac1 0>, <&usb_dmac1 1>;
582 dma-names = "ch0", "ch1", "ch2", "ch3";
583 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
584 resets = <&cpg 704>;
585 renesas,buswait = <4>;
586 phys = <&usb0 1>;
587 phy-names = "usb";
588 status = "disabled";
589 };
590
591 usbphy: usb-phy@e6590100 {
592 compatible = "renesas,usb-phy-r8a7790",
593 "renesas,rcar-gen2-usb-phy";
594 reg = <0 0xe6590100 0 0x100>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clocks = <&cpg CPG_MOD 704>;
598 clock-names = "usbhs";
599 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
600 resets = <&cpg 704>;
601 status = "disabled";
602
603 usb0: usb-channel@0 {
604 reg = <0>;
605 #phy-cells = <1>;
606 };
607 usb2: usb-channel@2 {
608 reg = <2>;
609 #phy-cells = <1>;
610 };
611 };
612
613 usb_dmac0: dma-controller@e65a0000 {
614 compatible = "renesas,r8a7790-usb-dmac",
615 "renesas,usb-dmac";
616 reg = <0 0xe65a0000 0 0x100>;
617 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
618 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-names = "ch0", "ch1";
620 clocks = <&cpg CPG_MOD 330>;
621 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
622 resets = <&cpg 330>;
623 #dma-cells = <1>;
624 dma-channels = <2>;
625 };
626
627 usb_dmac1: dma-controller@e65b0000 {
628 compatible = "renesas,r8a7790-usb-dmac",
629 "renesas,usb-dmac";
630 reg = <0 0xe65b0000 0 0x100>;
631 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
632 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "ch0", "ch1";
634 clocks = <&cpg CPG_MOD 331>;
635 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
636 resets = <&cpg 331>;
637 #dma-cells = <1>;
638 dma-channels = <2>;
639 };
640
641 dmac0: dma-controller@e6700000 {
642 compatible = "renesas,dmac-r8a7790",
643 "renesas,rcar-dmac";
644 reg = <0 0xe6700000 0 0x20000>;
645 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
646 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
647 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
648 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
649 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
650 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
651 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
652 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
653 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
654 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
655 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
656 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
657 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
658 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
659 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
660 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
661 interrupt-names = "error",
662 "ch0", "ch1", "ch2", "ch3",
663 "ch4", "ch5", "ch6", "ch7",
664 "ch8", "ch9", "ch10", "ch11",
665 "ch12", "ch13", "ch14";
666 clocks = <&cpg CPG_MOD 219>;
667 clock-names = "fck";
668 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
669 resets = <&cpg 219>;
670 #dma-cells = <1>;
671 dma-channels = <15>;
672 };
673
674 dmac1: dma-controller@e6720000 {
675 compatible = "renesas,dmac-r8a7790",
676 "renesas,rcar-dmac";
677 reg = <0 0xe6720000 0 0x20000>;
678 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
679 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
680 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
681 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
682 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
683 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
684 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
685 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
686 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
687 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
688 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
689 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
690 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
691 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
692 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
693 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
694 interrupt-names = "error",
695 "ch0", "ch1", "ch2", "ch3",
696 "ch4", "ch5", "ch6", "ch7",
697 "ch8", "ch9", "ch10", "ch11",
698 "ch12", "ch13", "ch14";
699 clocks = <&cpg CPG_MOD 218>;
700 clock-names = "fck";
701 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
702 resets = <&cpg 218>;
703 #dma-cells = <1>;
704 dma-channels = <15>;
705 };
706
707 avb: ethernet@e6800000 {
708 compatible = "renesas,etheravb-r8a7790",
709 "renesas,etheravb-rcar-gen2";
710 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
711 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&cpg CPG_MOD 812>;
713 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
714 resets = <&cpg 812>;
715 #address-cells = <1>;
716 #size-cells = <0>;
717 status = "disabled";
718 };
719
720 qspi: spi@e6b10000 {
721 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
722 reg = <0 0xe6b10000 0 0x2c>;
723 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&cpg CPG_MOD 917>;
725 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
726 <&dmac1 0x17>, <&dmac1 0x18>;
727 dma-names = "tx", "rx", "tx", "rx";
728 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
729 resets = <&cpg 917>;
730 num-cs = <1>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
735
736 scifa0: serial@e6c40000 {
737 compatible = "renesas,scifa-r8a7790",
738 "renesas,rcar-gen2-scifa", "renesas,scifa";
739 reg = <0 0xe6c40000 0 64>;
740 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cpg CPG_MOD 204>;
742 clock-names = "fck";
743 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
744 <&dmac1 0x21>, <&dmac1 0x22>;
745 dma-names = "tx", "rx", "tx", "rx";
746 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
747 resets = <&cpg 204>;
748 status = "disabled";
749 };
750
751 scifa1: serial@e6c50000 {
752 compatible = "renesas,scifa-r8a7790",
753 "renesas,rcar-gen2-scifa", "renesas,scifa";
754 reg = <0 0xe6c50000 0 64>;
755 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&cpg CPG_MOD 203>;
757 clock-names = "fck";
758 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
759 <&dmac1 0x25>, <&dmac1 0x26>;
760 dma-names = "tx", "rx", "tx", "rx";
761 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
762 resets = <&cpg 203>;
763 status = "disabled";
764 };
765
766 scifa2: serial@e6c60000 {
767 compatible = "renesas,scifa-r8a7790",
768 "renesas,rcar-gen2-scifa", "renesas,scifa";
769 reg = <0 0xe6c60000 0 64>;
770 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cpg CPG_MOD 202>;
772 clock-names = "fck";
773 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
774 <&dmac1 0x27>, <&dmac1 0x28>;
775 dma-names = "tx", "rx", "tx", "rx";
776 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
777 resets = <&cpg 202>;
778 status = "disabled";
779 };
780
781 scifb0: serial@e6c20000 {
782 compatible = "renesas,scifb-r8a7790",
783 "renesas,rcar-gen2-scifb", "renesas,scifb";
784 reg = <0 0xe6c20000 0 0x100>;
785 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cpg CPG_MOD 206>;
787 clock-names = "fck";
788 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
789 <&dmac1 0x3d>, <&dmac1 0x3e>;
790 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
792 resets = <&cpg 206>;
793 status = "disabled";
794 };
795
796 scifb1: serial@e6c30000 {
797 compatible = "renesas,scifb-r8a7790",
798 "renesas,rcar-gen2-scifb", "renesas,scifb";
799 reg = <0 0xe6c30000 0 0x100>;
800 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cpg CPG_MOD 207>;
802 clock-names = "fck";
803 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
804 <&dmac1 0x19>, <&dmac1 0x1a>;
805 dma-names = "tx", "rx", "tx", "rx";
806 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
807 resets = <&cpg 207>;
808 status = "disabled";
809 };
810
811 scifb2: serial@e6ce0000 {
812 compatible = "renesas,scifb-r8a7790",
813 "renesas,rcar-gen2-scifb", "renesas,scifb";
814 reg = <0 0xe6ce0000 0 0x100>;
815 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&cpg CPG_MOD 216>;
817 clock-names = "fck";
818 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
819 <&dmac1 0x1d>, <&dmac1 0x1e>;
820 dma-names = "tx", "rx", "tx", "rx";
821 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
822 resets = <&cpg 216>;
823 status = "disabled";
824 };
825
826 scif0: serial@e6e60000 {
827 compatible = "renesas,scif-r8a7790",
828 "renesas,rcar-gen2-scif",
829 "renesas,scif";
830 reg = <0 0xe6e60000 0 64>;
831 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cpg CPG_MOD 721>,
833 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
834 clock-names = "fck", "brg_int", "scif_clk";
835 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
836 <&dmac1 0x29>, <&dmac1 0x2a>;
837 dma-names = "tx", "rx", "tx", "rx";
838 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
839 resets = <&cpg 721>;
840 status = "disabled";
841 };
842
843 scif1: serial@e6e68000 {
844 compatible = "renesas,scif-r8a7790",
845 "renesas,rcar-gen2-scif",
846 "renesas,scif";
847 reg = <0 0xe6e68000 0 64>;
848 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cpg CPG_MOD 720>,
850 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
853 <&dmac1 0x2d>, <&dmac1 0x2e>;
854 dma-names = "tx", "rx", "tx", "rx";
855 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
856 resets = <&cpg 720>;
857 status = "disabled";
858 };
859
860 scif2: serial@e6e56000 {
861 compatible = "renesas,scif-r8a7790",
862 "renesas,rcar-gen2-scif",
863 "renesas,scif";
864 reg = <0 0xe6e56000 0 64>;
865 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cpg CPG_MOD 310>,
867 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
868 clock-names = "fck", "brg_int", "scif_clk";
869 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
870 <&dmac1 0x2b>, <&dmac1 0x2c>;
871 dma-names = "tx", "rx", "tx", "rx";
872 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
873 resets = <&cpg 310>;
874 status = "disabled";
875 };
876
877 hscif0: serial@e62c0000 {
878 compatible = "renesas,hscif-r8a7790",
879 "renesas,rcar-gen2-hscif", "renesas,hscif";
880 reg = <0 0xe62c0000 0 96>;
881 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&cpg CPG_MOD 717>,
883 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
884 clock-names = "fck", "brg_int", "scif_clk";
885 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
886 <&dmac1 0x39>, <&dmac1 0x3a>;
887 dma-names = "tx", "rx", "tx", "rx";
888 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
889 resets = <&cpg 717>;
890 status = "disabled";
891 };
892
893 hscif1: serial@e62c8000 {
894 compatible = "renesas,hscif-r8a7790",
895 "renesas,rcar-gen2-hscif", "renesas,hscif";
896 reg = <0 0xe62c8000 0 96>;
897 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&cpg CPG_MOD 716>,
899 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
900 clock-names = "fck", "brg_int", "scif_clk";
901 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
902 <&dmac1 0x4d>, <&dmac1 0x4e>;
903 dma-names = "tx", "rx", "tx", "rx";
904 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
905 resets = <&cpg 716>;
906 status = "disabled";
907 };
908
909 msiof0: spi@e6e20000 {
910 compatible = "renesas,msiof-r8a7790",
911 "renesas,rcar-gen2-msiof";
912 reg = <0 0xe6e20000 0 0x0064>;
913 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&cpg CPG_MOD 0>;
915 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
916 <&dmac1 0x51>, <&dmac1 0x52>;
917 dma-names = "tx", "rx", "tx", "rx";
918 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
919 resets = <&cpg 0>;
920 #address-cells = <1>;
921 #size-cells = <0>;
922 status = "disabled";
923 };
924
925 msiof1: spi@e6e10000 {
926 compatible = "renesas,msiof-r8a7790",
927 "renesas,rcar-gen2-msiof";
928 reg = <0 0xe6e10000 0 0x0064>;
929 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&cpg CPG_MOD 208>;
931 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
932 <&dmac1 0x55>, <&dmac1 0x56>;
933 dma-names = "tx", "rx", "tx", "rx";
934 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
935 resets = <&cpg 208>;
936 #address-cells = <1>;
937 #size-cells = <0>;
938 status = "disabled";
939 };
940
941 msiof2: spi@e6e00000 {
942 compatible = "renesas,msiof-r8a7790",
943 "renesas,rcar-gen2-msiof";
944 reg = <0 0xe6e00000 0 0x0064>;
945 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&cpg CPG_MOD 205>;
947 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
948 <&dmac1 0x41>, <&dmac1 0x42>;
949 dma-names = "tx", "rx", "tx", "rx";
950 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
951 resets = <&cpg 205>;
952 #address-cells = <1>;
953 #size-cells = <0>;
954 status = "disabled";
955 };
956
957 msiof3: spi@e6c90000 {
958 compatible = "renesas,msiof-r8a7790",
959 "renesas,rcar-gen2-msiof";
960 reg = <0 0xe6c90000 0 0x0064>;
961 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&cpg CPG_MOD 215>;
963 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
964 <&dmac1 0x45>, <&dmac1 0x46>;
965 dma-names = "tx", "rx", "tx", "rx";
966 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
967 resets = <&cpg 215>;
968 #address-cells = <1>;
969 #size-cells = <0>;
970 status = "disabled";
971 };
972
973 can0: can@e6e80000 {
974 compatible = "renesas,can-r8a7790",
975 "renesas,rcar-gen2-can";
976 reg = <0 0xe6e80000 0 0x1000>;
977 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cpg CPG_MOD 916>,
979 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
980 clock-names = "clkp1", "clkp2", "can_clk";
981 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
982 resets = <&cpg 916>;
983 status = "disabled";
984 };
985
986 can1: can@e6e88000 {
987 compatible = "renesas,can-r8a7790",
988 "renesas,rcar-gen2-can";
989 reg = <0 0xe6e88000 0 0x1000>;
990 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&cpg CPG_MOD 915>,
992 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
993 clock-names = "clkp1", "clkp2", "can_clk";
994 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
995 resets = <&cpg 915>;
996 status = "disabled";
997 };
998
999 vin0: video@e6ef0000 {
1000 compatible = "renesas,vin-r8a7790",
1001 "renesas,rcar-gen2-vin";
1002 reg = <0 0xe6ef0000 0 0x1000>;
1003 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cpg CPG_MOD 811>;
1005 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1006 resets = <&cpg 811>;
1007 status = "disabled";
1008 };
1009
1010 vin1: video@e6ef1000 {
1011 compatible = "renesas,vin-r8a7790",
1012 "renesas,rcar-gen2-vin";
1013 reg = <0 0xe6ef1000 0 0x1000>;
1014 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MOD 810>;
1016 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1017 resets = <&cpg 810>;
1018 status = "disabled";
1019 };
1020
1021 vin2: video@e6ef2000 {
1022 compatible = "renesas,vin-r8a7790",
1023 "renesas,rcar-gen2-vin";
1024 reg = <0 0xe6ef2000 0 0x1000>;
1025 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cpg CPG_MOD 809>;
1027 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1028 resets = <&cpg 809>;
1029 status = "disabled";
1030 };
1031
1032 vin3: video@e6ef3000 {
1033 compatible = "renesas,vin-r8a7790",
1034 "renesas,rcar-gen2-vin";
1035 reg = <0 0xe6ef3000 0 0x1000>;
1036 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&cpg CPG_MOD 808>;
1038 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1039 resets = <&cpg 808>;
1040 status = "disabled";
1041 };
1042
1043 rcar_sound: sound@ec500000 {
1044 /*
1045 * #sound-dai-cells is required
1046 *
1047 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1048 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1049 */
1050 compatible = "renesas,rcar_sound-r8a7790",
1051 "renesas,rcar_sound-gen2";
1052 reg = <0 0xec500000 0 0x1000>, /* SCU */
1053 <0 0xec5a0000 0 0x100>, /* ADG */
1054 <0 0xec540000 0 0x1000>, /* SSIU */
1055 <0 0xec541000 0 0x280>, /* SSI */
1056 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1057 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1058
1059 clocks = <&cpg CPG_MOD 1005>,
1060 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1061 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1062 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1063 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1064 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1065 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1066 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1067 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1068 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1069 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1070 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1071 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1072 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1073 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1074 <&cpg CPG_CORE R8A7790_CLK_M2>;
1075 clock-names = "ssi-all",
1076 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1077 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1078 "ssi.1", "ssi.0",
1079 "src.9", "src.8", "src.7", "src.6",
1080 "src.5", "src.4", "src.3", "src.2",
1081 "src.1", "src.0",
1082 "ctu.0", "ctu.1",
1083 "mix.0", "mix.1",
1084 "dvc.0", "dvc.1",
1085 "clk_a", "clk_b", "clk_c", "clk_i";
1086 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1087 resets = <&cpg 1005>,
1088 <&cpg 1006>, <&cpg 1007>,
1089 <&cpg 1008>, <&cpg 1009>,
1090 <&cpg 1010>, <&cpg 1011>,
1091 <&cpg 1012>, <&cpg 1013>,
1092 <&cpg 1014>, <&cpg 1015>;
1093 reset-names = "ssi-all",
1094 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1095 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1096 "ssi.1", "ssi.0";
1097
1098 status = "disabled";
1099
1100 rcar_sound,dvc {
1101 dvc0: dvc-0 {
1102 dmas = <&audma1 0xbc>;
1103 dma-names = "tx";
1104 };
1105 dvc1: dvc-1 {
1106 dmas = <&audma1 0xbe>;
1107 dma-names = "tx";
1108 };
1109 };
1110
1111 rcar_sound,mix {
1112 mix0: mix-0 { };
1113 mix1: mix-1 { };
1114 };
1115
1116 rcar_sound,ctu {
1117 ctu00: ctu-0 { };
1118 ctu01: ctu-1 { };
1119 ctu02: ctu-2 { };
1120 ctu03: ctu-3 { };
1121 ctu10: ctu-4 { };
1122 ctu11: ctu-5 { };
1123 ctu12: ctu-6 { };
1124 ctu13: ctu-7 { };
1125 };
1126
1127 rcar_sound,src {
1128 src0: src-0 {
1129 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1130 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1131 dma-names = "rx", "tx";
1132 };
1133 src1: src-1 {
1134 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1135 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1136 dma-names = "rx", "tx";
1137 };
1138 src2: src-2 {
1139 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1141 dma-names = "rx", "tx";
1142 };
1143 src3: src-3 {
1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1145 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1146 dma-names = "rx", "tx";
1147 };
1148 src4: src-4 {
1149 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1150 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1151 dma-names = "rx", "tx";
1152 };
1153 src5: src-5 {
1154 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1155 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1156 dma-names = "rx", "tx";
1157 };
1158 src6: src-6 {
1159 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1160 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1161 dma-names = "rx", "tx";
1162 };
1163 src7: src-7 {
1164 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1165 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1166 dma-names = "rx", "tx";
1167 };
1168 src8: src-8 {
1169 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1170 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1171 dma-names = "rx", "tx";
1172 };
1173 src9: src-9 {
1174 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1175 dmas = <&audma0 0x97>, <&audma1 0xba>;
1176 dma-names = "rx", "tx";
1177 };
1178 };
1179
1180 rcar_sound,ssi {
1181 ssi0: ssi-0 {
1182 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1183 dmas = <&audma0 0x01>, <&audma1 0x02>,
1184 <&audma0 0x15>, <&audma1 0x16>;
1185 dma-names = "rx", "tx", "rxu", "txu";
1186 };
1187 ssi1: ssi-1 {
1188 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1189 dmas = <&audma0 0x03>, <&audma1 0x04>,
1190 <&audma0 0x49>, <&audma1 0x4a>;
1191 dma-names = "rx", "tx", "rxu", "txu";
1192 };
1193 ssi2: ssi-2 {
1194 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1195 dmas = <&audma0 0x05>, <&audma1 0x06>,
1196 <&audma0 0x63>, <&audma1 0x64>;
1197 dma-names = "rx", "tx", "rxu", "txu";
1198 };
1199 ssi3: ssi-3 {
1200 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1201 dmas = <&audma0 0x07>, <&audma1 0x08>,
1202 <&audma0 0x6f>, <&audma1 0x70>;
1203 dma-names = "rx", "tx", "rxu", "txu";
1204 };
1205 ssi4: ssi-4 {
1206 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1207 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1208 <&audma0 0x71>, <&audma1 0x72>;
1209 dma-names = "rx", "tx", "rxu", "txu";
1210 };
1211 ssi5: ssi-5 {
1212 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1213 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1214 <&audma0 0x73>, <&audma1 0x74>;
1215 dma-names = "rx", "tx", "rxu", "txu";
1216 };
1217 ssi6: ssi-6 {
1218 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1219 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1220 <&audma0 0x75>, <&audma1 0x76>;
1221 dma-names = "rx", "tx", "rxu", "txu";
1222 };
1223 ssi7: ssi-7 {
1224 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1225 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1226 <&audma0 0x79>, <&audma1 0x7a>;
1227 dma-names = "rx", "tx", "rxu", "txu";
1228 };
1229 ssi8: ssi-8 {
1230 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1231 dmas = <&audma0 0x11>, <&audma1 0x12>,
1232 <&audma0 0x7b>, <&audma1 0x7c>;
1233 dma-names = "rx", "tx", "rxu", "txu";
1234 };
1235 ssi9: ssi-9 {
1236 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1237 dmas = <&audma0 0x13>, <&audma1 0x14>,
1238 <&audma0 0x7d>, <&audma1 0x7e>;
1239 dma-names = "rx", "tx", "rxu", "txu";
1240 };
1241 };
1242 };
1243
1244 audma0: dma-controller@ec700000 {
1245 compatible = "renesas,dmac-r8a7790",
1246 "renesas,rcar-dmac";
1247 reg = <0 0xec700000 0 0x10000>;
1248 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1249 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1250 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1251 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1252 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1253 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1254 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1255 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1256 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1257 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1258 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1259 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1260 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1261 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1262 interrupt-names = "error",
1263 "ch0", "ch1", "ch2", "ch3",
1264 "ch4", "ch5", "ch6", "ch7",
1265 "ch8", "ch9", "ch10", "ch11",
1266 "ch12";
1267 clocks = <&cpg CPG_MOD 502>;
1268 clock-names = "fck";
1269 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1270 resets = <&cpg 502>;
1271 #dma-cells = <1>;
1272 dma-channels = <13>;
1273 };
1274
1275 audma1: dma-controller@ec720000 {
1276 compatible = "renesas,dmac-r8a7790",
1277 "renesas,rcar-dmac";
1278 reg = <0 0xec720000 0 0x10000>;
1279 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1280 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1281 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1282 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
1283 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1284 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1285 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1286 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1287 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1288 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1289 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1290 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1291 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1292 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1293 interrupt-names = "error",
1294 "ch0", "ch1", "ch2", "ch3",
1295 "ch4", "ch5", "ch6", "ch7",
1296 "ch8", "ch9", "ch10", "ch11",
1297 "ch12";
1298 clocks = <&cpg CPG_MOD 501>;
1299 clock-names = "fck";
1300 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1301 resets = <&cpg 501>;
1302 #dma-cells = <1>;
1303 dma-channels = <13>;
1304 };
1305
1306 xhci: usb@ee000000 {
1307 compatible = "renesas,xhci-r8a7790",
1308 "renesas,rcar-gen2-xhci";
1309 reg = <0 0xee000000 0 0xc00>;
1310 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&cpg CPG_MOD 328>;
1312 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1313 resets = <&cpg 328>;
1314 phys = <&usb2 1>;
1315 phy-names = "usb";
1316 status = "disabled";
1317 };
1318
1319 pci0: pci@ee090000 {
1320 compatible = "renesas,pci-r8a7790",
1321 "renesas,pci-rcar-gen2";
1322 device_type = "pci";
1323 reg = <0 0xee090000 0 0xc00>,
1324 <0 0xee080000 0 0x1100>;
1325 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&cpg CPG_MOD 703>;
1327 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1328 resets = <&cpg 703>;
1329 status = "disabled";
1330
1331 bus-range = <0 0>;
1332 #address-cells = <3>;
1333 #size-cells = <2>;
1334 #interrupt-cells = <1>;
1335 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1336 interrupt-map-mask = <0xff00 0 0 0x7>;
1337 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1338 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1339 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1340
1341 usb@1,0 {
1342 reg = <0x800 0 0 0 0>;
1343 phys = <&usb0 0>;
1344 phy-names = "usb";
1345 };
1346
1347 usb@2,0 {
1348 reg = <0x1000 0 0 0 0>;
1349 phys = <&usb0 0>;
1350 phy-names = "usb";
1351 };
1352 };
1353
1354 pci1: pci@ee0b0000 {
1355 compatible = "renesas,pci-r8a7790",
1356 "renesas,pci-rcar-gen2";
1357 device_type = "pci";
1358 reg = <0 0xee0b0000 0 0xc00>,
1359 <0 0xee0a0000 0 0x1100>;
1360 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1361 clocks = <&cpg CPG_MOD 703>;
1362 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1363 resets = <&cpg 703>;
1364 status = "disabled";
1365
1366 bus-range = <1 1>;
1367 #address-cells = <3>;
1368 #size-cells = <2>;
1369 #interrupt-cells = <1>;
1370 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1371 interrupt-map-mask = <0xff00 0 0 0x7>;
1372 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1373 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1374 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1375 };
1376
1377 pci2: pci@ee0d0000 {
1378 compatible = "renesas,pci-r8a7790",
1379 "renesas,pci-rcar-gen2";
1380 device_type = "pci";
1381 clocks = <&cpg CPG_MOD 703>;
1382 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1383 resets = <&cpg 703>;
1384 reg = <0 0xee0d0000 0 0xc00>,
1385 <0 0xee0c0000 0 0x1100>;
1386 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1387 status = "disabled";
1388
1389 bus-range = <2 2>;
1390 #address-cells = <3>;
1391 #size-cells = <2>;
1392 #interrupt-cells = <1>;
1393 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1394 interrupt-map-mask = <0xff00 0 0 0x7>;
1395 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1396 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1397 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1398
1399 usb@1,0 {
1400 reg = <0x20800 0 0 0 0>;
1401 phys = <&usb2 0>;
1402 phy-names = "usb";
1403 };
1404
1405 usb@2,0 {
1406 reg = <0x21000 0 0 0 0>;
1407 phys = <&usb2 0>;
1408 phy-names = "usb";
1409 };
1410 };
1411
1412 sdhi0: sd@ee100000 {
1413 compatible = "renesas,sdhi-r8a7790",
1414 "renesas,rcar-gen2-sdhi";
1415 reg = <0 0xee100000 0 0x328>;
1416 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1417 clocks = <&cpg CPG_MOD 314>;
1418 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1419 <&dmac1 0xcd>, <&dmac1 0xce>;
1420 dma-names = "tx", "rx", "tx", "rx";
1421 max-frequency = <195000000>;
1422 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1423 resets = <&cpg 314>;
1424 status = "disabled";
1425 };
1426
1427 sdhi1: sd@ee120000 {
1428 compatible = "renesas,sdhi-r8a7790",
1429 "renesas,rcar-gen2-sdhi";
1430 reg = <0 0xee120000 0 0x328>;
1431 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1432 clocks = <&cpg CPG_MOD 313>;
1433 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
1434 <&dmac1 0xc9>, <&dmac1 0xca>;
1435 dma-names = "tx", "rx", "tx", "rx";
1436 max-frequency = <195000000>;
1437 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1438 resets = <&cpg 313>;
1439 status = "disabled";
1440 };
1441
1442 sdhi2: sd@ee140000 {
1443 compatible = "renesas,sdhi-r8a7790",
1444 "renesas,rcar-gen2-sdhi";
1445 reg = <0 0xee140000 0 0x100>;
1446 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&cpg CPG_MOD 312>;
1448 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1449 <&dmac1 0xc1>, <&dmac1 0xc2>;
1450 dma-names = "tx", "rx", "tx", "rx";
1451 max-frequency = <97500000>;
1452 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1453 resets = <&cpg 312>;
1454 status = "disabled";
1455 };
1456
1457 sdhi3: sd@ee160000 {
1458 compatible = "renesas,sdhi-r8a7790",
1459 "renesas,rcar-gen2-sdhi";
1460 reg = <0 0xee160000 0 0x100>;
1461 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1462 clocks = <&cpg CPG_MOD 311>;
1463 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1464 <&dmac1 0xd3>, <&dmac1 0xd4>;
1465 dma-names = "tx", "rx", "tx", "rx";
1466 max-frequency = <97500000>;
1467 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1468 resets = <&cpg 311>;
1469 status = "disabled";
1470 };
1471
1472 mmcif0: mmc@ee200000 {
1473 compatible = "renesas,mmcif-r8a7790",
1474 "renesas,sh-mmcif";
1475 reg = <0 0xee200000 0 0x80>;
1476 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1477 clocks = <&cpg CPG_MOD 315>;
1478 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1479 <&dmac1 0xd1>, <&dmac1 0xd2>;
1480 dma-names = "tx", "rx", "tx", "rx";
1481 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1482 resets = <&cpg 315>;
1483 reg-io-width = <4>;
1484 status = "disabled";
1485 max-frequency = <97500000>;
1486 };
1487
1488 mmcif1: mmc@ee220000 {
1489 compatible = "renesas,mmcif-r8a7790",
1490 "renesas,sh-mmcif";
1491 reg = <0 0xee220000 0 0x80>;
1492 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&cpg CPG_MOD 305>;
1494 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
1495 <&dmac1 0xe1>, <&dmac1 0xe2>;
1496 dma-names = "tx", "rx", "tx", "rx";
1497 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1498 resets = <&cpg 305>;
1499 reg-io-width = <4>;
1500 status = "disabled";
1501 max-frequency = <97500000>;
1502 };
1503
1504 sata0: sata@ee300000 {
1505 compatible = "renesas,sata-r8a7790",
1506 "renesas,rcar-gen2-sata";
1507 reg = <0 0xee300000 0 0x2000>;
1508 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1509 clocks = <&cpg CPG_MOD 815>;
1510 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1511 resets = <&cpg 815>;
1512 status = "disabled";
1513 };
1514
1515 sata1: sata@ee500000 {
1516 compatible = "renesas,sata-r8a7790",
1517 "renesas,rcar-gen2-sata";
1518 reg = <0 0xee500000 0 0x2000>;
1519 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1520 clocks = <&cpg CPG_MOD 814>;
1521 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1522 resets = <&cpg 814>;
1523 status = "disabled";
1524 };
1525
1526 ether: ethernet@ee700000 {
1527 compatible = "renesas,ether-r8a7790",
1528 "renesas,rcar-gen2-ether";
1529 reg = <0 0xee700000 0 0x400>;
1530 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1531 clocks = <&cpg CPG_MOD 813>;
1532 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1533 resets = <&cpg 813>;
1534 phy-mode = "rmii";
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537 status = "disabled";
1538 };
1539
1540 gic: interrupt-controller@f1001000 {
1541 compatible = "arm,gic-400";
1542 #interrupt-cells = <3>;
1543 #address-cells = <0>;
1544 interrupt-controller;
1545 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1546 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1547 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1548 clocks = <&cpg CPG_MOD 408>;
1549 clock-names = "clk";
1550 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1551 resets = <&cpg 408>;
1552 };
1553
1554 pciec: pcie@fe000000 {
1555 compatible = "renesas,pcie-r8a7790",
1556 "renesas,pcie-rcar-gen2";
1557 reg = <0 0xfe000000 0 0x80000>;
1558 #address-cells = <3>;
1559 #size-cells = <2>;
1560 bus-range = <0x00 0xff>;
1561 device_type = "pci";
1562 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1563 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1564 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1565 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1566 /* Map all possible DDR as inbound ranges */
1567 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1568 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1569 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1572 #interrupt-cells = <1>;
1573 interrupt-map-mask = <0 0 0 0>;
1574 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1575 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1576 clock-names = "pcie", "pcie_bus";
1577 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1578 resets = <&cpg 319>;
1579 status = "disabled";
1580 };
1581
1582 vsp@fe920000 {
1583 compatible = "renesas,vsp1";
1584 reg = <0 0xfe920000 0 0x8000>;
1585 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&cpg CPG_MOD 130>;
1587 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1588 resets = <&cpg 130>;
1589 };
1590
1591 vsp@fe928000 {
1592 compatible = "renesas,vsp1";
1593 reg = <0 0xfe928000 0 0x8000>;
1594 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&cpg CPG_MOD 131>;
1596 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1597 resets = <&cpg 131>;
1598 };
1599
1600 vsp@fe930000 {
1601 compatible = "renesas,vsp1";
1602 reg = <0 0xfe930000 0 0x8000>;
1603 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1604 clocks = <&cpg CPG_MOD 128>;
1605 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1606 resets = <&cpg 128>;
1607 };
1608
1609 vsp@fe938000 {
1610 compatible = "renesas,vsp1";
1611 reg = <0 0xfe938000 0 0x8000>;
1612 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1613 clocks = <&cpg CPG_MOD 127>;
1614 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1615 resets = <&cpg 127>;
1616 };
1617
1618 jpu: jpeg-codec@fe980000 {
1619 compatible = "renesas,jpu-r8a7790",
1620 "renesas,rcar-gen2-jpu";
1621 reg = <0 0xfe980000 0 0x10300>;
1622 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MOD 106>;
1624 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1625 resets = <&cpg 106>;
1626 };
1627
1628 du: display@feb00000 {
1629 compatible = "renesas,du-r8a7790";
1630 reg = <0 0xfeb00000 0 0x70000>;
1631 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1634 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
1635 <&cpg CPG_MOD 722>;
1636 clock-names = "du.0", "du.1", "du.2";
1637 status = "disabled";
1638
1639 ports {
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642
1643 port@0 {
1644 reg = <0>;
1645 du_out_rgb: endpoint {
1646 };
1647 };
1648 port@1 {
1649 reg = <1>;
1650 du_out_lvds0: endpoint {
1651 remote-endpoint = <&lvds0_in>;
1652 };
1653 };
1654 port@2 {
1655 reg = <2>;
1656 du_out_lvds1: endpoint {
1657 remote-endpoint = <&lvds1_in>;
1658 };
1659 };
1660 };
1661 };
1662
1663 lvds0: lvds@feb90000 {
1664 compatible = "renesas,r8a7790-lvds";
1665 reg = <0 0xfeb90000 0 0x1c>;
1666 clocks = <&cpg CPG_MOD 726>;
1667 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1668 resets = <&cpg 726>;
1669 status = "disabled";
1670
1671 ports {
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1674
1675 port@0 {
1676 reg = <0>;
1677 lvds0_in: endpoint {
1678 remote-endpoint = <&du_out_lvds0>;
1679 };
1680 };
1681 port@1 {
1682 reg = <1>;
1683 lvds0_out: endpoint {
1684 };
1685 };
1686 };
1687 };
1688
1689 lvds1: lvds@feb94000 {
1690 compatible = "renesas,r8a7790-lvds";
1691 reg = <0 0xfeb94000 0 0x1c>;
1692 clocks = <&cpg CPG_MOD 725>;
1693 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1694 resets = <&cpg 725>;
1695 status = "disabled";
1696
1697 ports {
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1700
1701 port@0 {
1702 reg = <0>;
1703 lvds1_in: endpoint {
1704 remote-endpoint = <&du_out_lvds1>;
1705 };
1706 };
1707 port@1 {
1708 reg = <1>;
1709 lvds1_out: endpoint {
1710 };
1711 };
1712 };
1713 };
1714
1715 prr: chipid@ff000044 {
1716 compatible = "renesas,prr";
1717 reg = <0 0xff000044 0 4>;
1718 };
1719
1720 cmt0: timer@ffca0000 {
1721 compatible = "renesas,r8a7790-cmt0",
1722 "renesas,rcar-gen2-cmt0";
1723 reg = <0 0xffca0000 0 0x1004>;
1724 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MOD 124>;
1727 clock-names = "fck";
1728 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1729 resets = <&cpg 124>;
1730
1731 status = "disabled";
1732 };
1733
1734 cmt1: timer@e6130000 {
1735 compatible = "renesas,r8a7790-cmt1",
1736 "renesas,rcar-gen2-cmt1";
1737 reg = <0 0xe6130000 0 0x1004>;
1738 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MOD 329>;
1747 clock-names = "fck";
1748 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1749 resets = <&cpg 329>;
1750
1751 status = "disabled";
1752 };
1753 };
1754
1755 thermal-zones {
1756 cpu_thermal: cpu-thermal {
1757 polling-delay-passive = <0>;
1758 polling-delay = <0>;
1759
1760 thermal-sensors = <&thermal>;
1761
1762 trips {
1763 cpu-crit {
1764 temperature = <95000>;
1765 hysteresis = <0>;
1766 type = "critical";
1767 };
1768 };
1769 cooling-maps {
1770 };
1771 };
1772 };
1773
1774 timer {
1775 compatible = "arm,armv7-timer";
1776 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1777 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1778 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1779 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1780 };
1781
1782 /* External USB clock - can be overridden by the board */
1783 usb_extal_clk: usb_extal {
1784 compatible = "fixed-clock";
1785 #clock-cells = <0>;
1786 clock-frequency = <48000000>;
1787 };
1788};
1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <dt-bindings/clock/r8a7790-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
32 spi0 = &qspi;
33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55 next-level-cache = <&L2_CA15>;
56
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
59 <1225000 1000000>,
60 <1050000 1000000>,
61 < 875000 1000000>,
62 < 700000 1000000>,
63 < 350000 1000000>;
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <1>;
70 clock-frequency = <1300000000>;
71 next-level-cache = <&L2_CA15>;
72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <2>;
78 clock-frequency = <1300000000>;
79 next-level-cache = <&L2_CA15>;
80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <3>;
86 clock-frequency = <1300000000>;
87 next-level-cache = <&L2_CA15>;
88 };
89
90 cpu4: cpu@4 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <780000000>;
95 next-level-cache = <&L2_CA7>;
96 };
97
98 cpu5: cpu@5 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <780000000>;
103 next-level-cache = <&L2_CA7>;
104 };
105
106 cpu6: cpu@6 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <780000000>;
111 next-level-cache = <&L2_CA7>;
112 };
113
114 cpu7: cpu@7 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <780000000>;
119 next-level-cache = <&L2_CA7>;
120 };
121 };
122
123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
126 polling-delay = <0>;
127
128 thermal-sensors = <&thermal>;
129
130 trips {
131 cpu-crit {
132 temperature = <115000>;
133 hysteresis = <0>;
134 type = "critical";
135 };
136 };
137 cooling-maps {
138 };
139 };
140 };
141
142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
150 cache-unified;
151 cache-level = <2>;
152 };
153
154 gic: interrupt-controller@f1001000 {
155 compatible = "arm,gic-400";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164 };
165
166 gpio0: gpio@e6050000 {
167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
168 reg = <0 0xe6050000 0 0x50>;
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
176 power-domains = <&cpg_clocks>;
177 };
178
179 gpio1: gpio@e6051000 {
180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
181 reg = <0 0xe6051000 0 0x50>;
182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 32 30>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
189 power-domains = <&cpg_clocks>;
190 };
191
192 gpio2: gpio@e6052000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6052000 0 0x50>;
195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 64 30>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
202 power-domains = <&cpg_clocks>;
203 };
204
205 gpio3: gpio@e6053000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6053000 0 0x50>;
208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
215 power-domains = <&cpg_clocks>;
216 };
217
218 gpio4: gpio@e6054000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6054000 0 0x50>;
221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
228 power-domains = <&cpg_clocks>;
229 };
230
231 gpio5: gpio@e6055000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6055000 0 0x50>;
234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
241 power-domains = <&cpg_clocks>;
242 };
243
244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
251 power-domains = <&cpg_clocks>;
252 #thermal-sensor-cells = <0>;
253 };
254
255 timer {
256 compatible = "arm,armv7-timer";
257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
261 };
262
263 cmt0: timer@ffca0000 {
264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
265 reg = <0 0xffca0000 0 0x1004>;
266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck";
270 power-domains = <&cpg_clocks>;
271
272 renesas,channels-mask = <0x60>;
273
274 status = "disabled";
275 };
276
277 cmt1: timer@e6130000 {
278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
279 reg = <0 0xe6130000 0 0x1004>;
280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck";
290 power-domains = <&cpg_clocks>;
291
292 renesas,channels-mask = <0xff>;
293
294 status = "disabled";
295 };
296
297 irqc0: interrupt-controller@e61c0000 {
298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 reg = <0 0xe61c0000 0 0x200>;
302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
307 power-domains = <&cpg_clocks>;
308 };
309
310 dmac0: dma-controller@e6700000 {
311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
312 reg = <0 0xe6700000 0 0x20000>;
313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck";
336 power-domains = <&cpg_clocks>;
337 #dma-cells = <1>;
338 dma-channels = <15>;
339 };
340
341 dmac1: dma-controller@e6720000 {
342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
343 reg = <0 0xe6720000 0 0x20000>;
344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck";
367 power-domains = <&cpg_clocks>;
368 #dma-cells = <1>;
369 dma-channels = <15>;
370 };
371
372 audma0: dma-controller@ec700000 {
373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
374 reg = <0 0xec700000 0 0x10000>;
375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
393 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck";
396 power-domains = <&cpg_clocks>;
397 #dma-cells = <1>;
398 dma-channels = <13>;
399 };
400
401 audma1: dma-controller@ec720000 {
402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
403 reg = <0 0xec720000 0 0x10000>;
404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
422 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck";
425 power-domains = <&cpg_clocks>;
426 #dma-cells = <1>;
427 dma-channels = <13>;
428 };
429
430 usb_dmac0: dma-controller@e65a0000 {
431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
432 reg = <0 0xe65a0000 0 0x100>;
433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
437 power-domains = <&cpg_clocks>;
438 #dma-cells = <1>;
439 dma-channels = <2>;
440 };
441
442 usb_dmac1: dma-controller@e65b0000 {
443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
444 reg = <0 0xe65b0000 0 0x100>;
445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
449 power-domains = <&cpg_clocks>;
450 #dma-cells = <1>;
451 dma-channels = <2>;
452 };
453
454 i2c0: i2c@e6508000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
461 power-domains = <&cpg_clocks>;
462 i2c-scl-internal-delay-ns = <110>;
463 status = "disabled";
464 };
465
466 i2c1: i2c@e6518000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
473 power-domains = <&cpg_clocks>;
474 i2c-scl-internal-delay-ns = <6>;
475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
485 power-domains = <&cpg_clocks>;
486 i2c-scl-internal-delay-ns = <6>;
487 status = "disabled";
488 };
489
490 i2c3: i2c@e6540000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
497 power-domains = <&cpg_clocks>;
498 i2c-scl-internal-delay-ns = <110>;
499 status = "disabled";
500 };
501
502 iic0: i2c@e6500000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>;
512 status = "disabled";
513 };
514
515 iic1: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
524 power-domains = <&cpg_clocks>;
525 status = "disabled";
526 };
527
528 iic2: i2c@e6520000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
537 power-domains = <&cpg_clocks>;
538 status = "disabled";
539 };
540
541 iic3: i2c@e60b0000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
550 power-domains = <&cpg_clocks>;
551 status = "disabled";
552 };
553
554 mmcif0: mmc@ee200000 {
555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
556 reg = <0 0xee200000 0 0x80>;
557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
561 power-domains = <&cpg_clocks>;
562 reg-io-width = <4>;
563 status = "disabled";
564 max-frequency = <97500000>;
565 };
566
567 mmcif1: mmc@ee220000 {
568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
569 reg = <0 0xee220000 0 0x80>;
570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>;
575 reg-io-width = <4>;
576 status = "disabled";
577 max-frequency = <97500000>;
578 };
579
580 pfc: pfc@e6060000 {
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
583 };
584
585 sdhi0: sd@ee100000 {
586 compatible = "renesas,sdhi-r8a7790";
587 reg = <0 0xee100000 0 0x328>;
588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>;
593 status = "disabled";
594 };
595
596 sdhi1: sd@ee120000 {
597 compatible = "renesas,sdhi-r8a7790";
598 reg = <0 0xee120000 0 0x328>;
599 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx";
603 power-domains = <&cpg_clocks>;
604 status = "disabled";
605 };
606
607 sdhi2: sd@ee140000 {
608 compatible = "renesas,sdhi-r8a7790";
609 reg = <0 0xee140000 0 0x100>;
610 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx";
614 power-domains = <&cpg_clocks>;
615 status = "disabled";
616 };
617
618 sdhi3: sd@ee160000 {
619 compatible = "renesas,sdhi-r8a7790";
620 reg = <0 0xee160000 0 0x100>;
621 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx";
625 power-domains = <&cpg_clocks>;
626 status = "disabled";
627 };
628
629 scifa0: serial@e6c40000 {
630 compatible = "renesas,scifa-r8a7790",
631 "renesas,rcar-gen2-scifa", "renesas,scifa";
632 reg = <0 0xe6c40000 0 64>;
633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
635 clock-names = "fck";
636 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
637 dma-names = "tx", "rx";
638 power-domains = <&cpg_clocks>;
639 status = "disabled";
640 };
641
642 scifa1: serial@e6c50000 {
643 compatible = "renesas,scifa-r8a7790",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
645 reg = <0 0xe6c50000 0 64>;
646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
648 clock-names = "fck";
649 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
652 status = "disabled";
653 };
654
655 scifa2: serial@e6c60000 {
656 compatible = "renesas,scifa-r8a7790",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
658 reg = <0 0xe6c60000 0 64>;
659 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
661 clock-names = "fck";
662 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
663 dma-names = "tx", "rx";
664 power-domains = <&cpg_clocks>;
665 status = "disabled";
666 };
667
668 scifb0: serial@e6c20000 {
669 compatible = "renesas,scifb-r8a7790",
670 "renesas,rcar-gen2-scifb", "renesas,scifb";
671 reg = <0 0xe6c20000 0 64>;
672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
674 clock-names = "fck";
675 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
676 dma-names = "tx", "rx";
677 power-domains = <&cpg_clocks>;
678 status = "disabled";
679 };
680
681 scifb1: serial@e6c30000 {
682 compatible = "renesas,scifb-r8a7790",
683 "renesas,rcar-gen2-scifb", "renesas,scifb";
684 reg = <0 0xe6c30000 0 64>;
685 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
687 clock-names = "fck";
688 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
689 dma-names = "tx", "rx";
690 power-domains = <&cpg_clocks>;
691 status = "disabled";
692 };
693
694 scifb2: serial@e6ce0000 {
695 compatible = "renesas,scifb-r8a7790",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
697 reg = <0 0xe6ce0000 0 64>;
698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
700 clock-names = "fck";
701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
702 dma-names = "tx", "rx";
703 power-domains = <&cpg_clocks>;
704 status = "disabled";
705 };
706
707 scif0: serial@e6e60000 {
708 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
709 "renesas,scif";
710 reg = <0 0xe6e60000 0 64>;
711 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
713 <&scif_clk>;
714 clock-names = "fck", "brg_int", "scif_clk";
715 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
716 dma-names = "tx", "rx";
717 power-domains = <&cpg_clocks>;
718 status = "disabled";
719 };
720
721 scif1: serial@e6e68000 {
722 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
723 "renesas,scif";
724 reg = <0 0xe6e68000 0 64>;
725 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
727 <&scif_clk>;
728 clock-names = "fck", "brg_int", "scif_clk";
729 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
730 dma-names = "tx", "rx";
731 power-domains = <&cpg_clocks>;
732 status = "disabled";
733 };
734
735 hscif0: serial@e62c0000 {
736 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif";
738 reg = <0 0xe62c0000 0 96>;
739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
744 dma-names = "tx", "rx";
745 power-domains = <&cpg_clocks>;
746 status = "disabled";
747 };
748
749 hscif1: serial@e62c8000 {
750 compatible = "renesas,hscif-r8a7790",
751 "renesas,rcar-gen2-hscif", "renesas,hscif";
752 reg = <0 0xe62c8000 0 96>;
753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
755 <&scif_clk>;
756 clock-names = "fck", "brg_int", "scif_clk";
757 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
758 dma-names = "tx", "rx";
759 power-domains = <&cpg_clocks>;
760 status = "disabled";
761 };
762
763 ether: ethernet@ee700000 {
764 compatible = "renesas,ether-r8a7790";
765 reg = <0 0xee700000 0 0x400>;
766 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
768 power-domains = <&cpg_clocks>;
769 phy-mode = "rmii";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 status = "disabled";
773 };
774
775 avb: ethernet@e6800000 {
776 compatible = "renesas,etheravb-r8a7790",
777 "renesas,etheravb-rcar-gen2";
778 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
779 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
781 power-domains = <&cpg_clocks>;
782 #address-cells = <1>;
783 #size-cells = <0>;
784 status = "disabled";
785 };
786
787 sata0: sata@ee300000 {
788 compatible = "renesas,sata-r8a7790";
789 reg = <0 0xee300000 0 0x2000>;
790 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
792 power-domains = <&cpg_clocks>;
793 status = "disabled";
794 };
795
796 sata1: sata@ee500000 {
797 compatible = "renesas,sata-r8a7790";
798 reg = <0 0xee500000 0 0x2000>;
799 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
801 power-domains = <&cpg_clocks>;
802 status = "disabled";
803 };
804
805 hsusb: usb@e6590000 {
806 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
807 reg = <0 0xe6590000 0 0x100>;
808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
810 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
811 <&usb_dmac1 0>, <&usb_dmac1 1>;
812 dma-names = "ch0", "ch1", "ch2", "ch3";
813 power-domains = <&cpg_clocks>;
814 renesas,buswait = <4>;
815 phys = <&usb0 1>;
816 phy-names = "usb";
817 status = "disabled";
818 };
819
820 usbphy: usb-phy@e6590100 {
821 compatible = "renesas,usb-phy-r8a7790";
822 reg = <0 0xe6590100 0 0x100>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
826 clock-names = "usbhs";
827 power-domains = <&cpg_clocks>;
828 status = "disabled";
829
830 usb0: usb-channel@0 {
831 reg = <0>;
832 #phy-cells = <1>;
833 };
834 usb2: usb-channel@2 {
835 reg = <2>;
836 #phy-cells = <1>;
837 };
838 };
839
840 vin0: video@e6ef0000 {
841 compatible = "renesas,vin-r8a7790";
842 reg = <0 0xe6ef0000 0 0x1000>;
843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
845 power-domains = <&cpg_clocks>;
846 status = "disabled";
847 };
848
849 vin1: video@e6ef1000 {
850 compatible = "renesas,vin-r8a7790";
851 reg = <0 0xe6ef1000 0 0x1000>;
852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
854 power-domains = <&cpg_clocks>;
855 status = "disabled";
856 };
857
858 vin2: video@e6ef2000 {
859 compatible = "renesas,vin-r8a7790";
860 reg = <0 0xe6ef2000 0 0x1000>;
861 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
863 power-domains = <&cpg_clocks>;
864 status = "disabled";
865 };
866
867 vin3: video@e6ef3000 {
868 compatible = "renesas,vin-r8a7790";
869 reg = <0 0xe6ef3000 0 0x1000>;
870 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
872 power-domains = <&cpg_clocks>;
873 status = "disabled";
874 };
875
876 vsp1@fe920000 {
877 compatible = "renesas,vsp1";
878 reg = <0 0xfe920000 0 0x8000>;
879 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
881 power-domains = <&cpg_clocks>;
882
883 renesas,has-sru;
884 renesas,#rpf = <5>;
885 renesas,#uds = <1>;
886 renesas,#wpf = <4>;
887 };
888
889 vsp1@fe928000 {
890 compatible = "renesas,vsp1";
891 reg = <0 0xfe928000 0 0x8000>;
892 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
894 power-domains = <&cpg_clocks>;
895
896 renesas,has-lut;
897 renesas,has-sru;
898 renesas,#rpf = <5>;
899 renesas,#uds = <3>;
900 renesas,#wpf = <4>;
901 };
902
903 vsp1@fe930000 {
904 compatible = "renesas,vsp1";
905 reg = <0 0xfe930000 0 0x8000>;
906 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
908 power-domains = <&cpg_clocks>;
909
910 renesas,has-lif;
911 renesas,has-lut;
912 renesas,#rpf = <4>;
913 renesas,#uds = <1>;
914 renesas,#wpf = <4>;
915 };
916
917 vsp1@fe938000 {
918 compatible = "renesas,vsp1";
919 reg = <0 0xfe938000 0 0x8000>;
920 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
922 power-domains = <&cpg_clocks>;
923
924 renesas,has-lif;
925 renesas,has-lut;
926 renesas,#rpf = <4>;
927 renesas,#uds = <1>;
928 renesas,#wpf = <4>;
929 };
930
931 du: display@feb00000 {
932 compatible = "renesas,du-r8a7790";
933 reg = <0 0xfeb00000 0 0x70000>,
934 <0 0xfeb90000 0 0x1c>,
935 <0 0xfeb94000 0 0x1c>;
936 reg-names = "du", "lvds.0", "lvds.1";
937 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
941 <&mstp7_clks R8A7790_CLK_DU1>,
942 <&mstp7_clks R8A7790_CLK_DU2>,
943 <&mstp7_clks R8A7790_CLK_LVDS0>,
944 <&mstp7_clks R8A7790_CLK_LVDS1>;
945 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
946 status = "disabled";
947
948 ports {
949 #address-cells = <1>;
950 #size-cells = <0>;
951
952 port@0 {
953 reg = <0>;
954 du_out_rgb: endpoint {
955 };
956 };
957 port@1 {
958 reg = <1>;
959 du_out_lvds0: endpoint {
960 };
961 };
962 port@2 {
963 reg = <2>;
964 du_out_lvds1: endpoint {
965 };
966 };
967 };
968 };
969
970 can0: can@e6e80000 {
971 compatible = "renesas,can-r8a7790";
972 reg = <0 0xe6e80000 0 0x1000>;
973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
975 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
976 clock-names = "clkp1", "clkp2", "can_clk";
977 power-domains = <&cpg_clocks>;
978 status = "disabled";
979 };
980
981 can1: can@e6e88000 {
982 compatible = "renesas,can-r8a7790";
983 reg = <0 0xe6e88000 0 0x1000>;
984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
986 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
987 clock-names = "clkp1", "clkp2", "can_clk";
988 power-domains = <&cpg_clocks>;
989 status = "disabled";
990 };
991
992 jpu: jpeg-codec@fe980000 {
993 compatible = "renesas,jpu-r8a7790";
994 reg = <0 0xfe980000 0 0x10300>;
995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
997 power-domains = <&cpg_clocks>;
998 };
999
1000 clocks {
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 ranges;
1004
1005 /* External root clock */
1006 extal_clk: extal_clk {
1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 /* This value must be overriden by the board. */
1010 clock-frequency = <0>;
1011 clock-output-names = "extal";
1012 };
1013
1014 /* External PCIe clock - can be overridden by the board */
1015 pcie_bus_clk: pcie_bus_clk {
1016 compatible = "fixed-clock";
1017 #clock-cells = <0>;
1018 clock-frequency = <100000000>;
1019 clock-output-names = "pcie_bus";
1020 status = "disabled";
1021 };
1022
1023 /*
1024 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1025 * default. Boards that provide audio clocks should override them.
1026 */
1027 audio_clk_a: audio_clk_a {
1028 compatible = "fixed-clock";
1029 #clock-cells = <0>;
1030 clock-frequency = <0>;
1031 clock-output-names = "audio_clk_a";
1032 };
1033 audio_clk_b: audio_clk_b {
1034 compatible = "fixed-clock";
1035 #clock-cells = <0>;
1036 clock-frequency = <0>;
1037 clock-output-names = "audio_clk_b";
1038 };
1039 audio_clk_c: audio_clk_c {
1040 compatible = "fixed-clock";
1041 #clock-cells = <0>;
1042 clock-frequency = <0>;
1043 clock-output-names = "audio_clk_c";
1044 };
1045
1046 /* External SCIF clock */
1047 scif_clk: scif {
1048 compatible = "fixed-clock";
1049 #clock-cells = <0>;
1050 /* This value must be overridden by the board. */
1051 clock-frequency = <0>;
1052 status = "disabled";
1053 };
1054
1055 /* External USB clock - can be overridden by the board */
1056 usb_extal_clk: usb_extal_clk {
1057 compatible = "fixed-clock";
1058 #clock-cells = <0>;
1059 clock-frequency = <48000000>;
1060 clock-output-names = "usb_extal";
1061 };
1062
1063 /* External CAN clock */
1064 can_clk: can_clk {
1065 compatible = "fixed-clock";
1066 #clock-cells = <0>;
1067 /* This value must be overridden by the board. */
1068 clock-frequency = <0>;
1069 clock-output-names = "can_clk";
1070 status = "disabled";
1071 };
1072
1073 /* Special CPG clocks */
1074 cpg_clocks: cpg_clocks@e6150000 {
1075 compatible = "renesas,r8a7790-cpg-clocks",
1076 "renesas,rcar-gen2-cpg-clocks";
1077 reg = <0 0xe6150000 0 0x1000>;
1078 clocks = <&extal_clk &usb_extal_clk>;
1079 #clock-cells = <1>;
1080 clock-output-names = "main", "pll0", "pll1", "pll3",
1081 "lb", "qspi", "sdh", "sd0", "sd1",
1082 "z", "rcan", "adsp";
1083 #power-domain-cells = <0>;
1084 };
1085
1086 /* Variable factor clocks */
1087 sd2_clk: sd2_clk@e6150078 {
1088 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1089 reg = <0 0xe6150078 0 4>;
1090 clocks = <&pll1_div2_clk>;
1091 #clock-cells = <0>;
1092 clock-output-names = "sd2";
1093 };
1094 sd3_clk: sd3_clk@e615026c {
1095 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1096 reg = <0 0xe615026c 0 4>;
1097 clocks = <&pll1_div2_clk>;
1098 #clock-cells = <0>;
1099 clock-output-names = "sd3";
1100 };
1101 mmc0_clk: mmc0_clk@e6150240 {
1102 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1103 reg = <0 0xe6150240 0 4>;
1104 clocks = <&pll1_div2_clk>;
1105 #clock-cells = <0>;
1106 clock-output-names = "mmc0";
1107 };
1108 mmc1_clk: mmc1_clk@e6150244 {
1109 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1110 reg = <0 0xe6150244 0 4>;
1111 clocks = <&pll1_div2_clk>;
1112 #clock-cells = <0>;
1113 clock-output-names = "mmc1";
1114 };
1115 ssp_clk: ssp_clk@e6150248 {
1116 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1117 reg = <0 0xe6150248 0 4>;
1118 clocks = <&pll1_div2_clk>;
1119 #clock-cells = <0>;
1120 clock-output-names = "ssp";
1121 };
1122 ssprs_clk: ssprs_clk@e615024c {
1123 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1124 reg = <0 0xe615024c 0 4>;
1125 clocks = <&pll1_div2_clk>;
1126 #clock-cells = <0>;
1127 clock-output-names = "ssprs";
1128 };
1129
1130 /* Fixed factor clocks */
1131 pll1_div2_clk: pll1_div2_clk {
1132 compatible = "fixed-factor-clock";
1133 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1134 #clock-cells = <0>;
1135 clock-div = <2>;
1136 clock-mult = <1>;
1137 clock-output-names = "pll1_div2";
1138 };
1139 z2_clk: z2_clk {
1140 compatible = "fixed-factor-clock";
1141 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1142 #clock-cells = <0>;
1143 clock-div = <2>;
1144 clock-mult = <1>;
1145 clock-output-names = "z2";
1146 };
1147 zg_clk: zg_clk {
1148 compatible = "fixed-factor-clock";
1149 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1150 #clock-cells = <0>;
1151 clock-div = <3>;
1152 clock-mult = <1>;
1153 clock-output-names = "zg";
1154 };
1155 zx_clk: zx_clk {
1156 compatible = "fixed-factor-clock";
1157 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1158 #clock-cells = <0>;
1159 clock-div = <3>;
1160 clock-mult = <1>;
1161 clock-output-names = "zx";
1162 };
1163 zs_clk: zs_clk {
1164 compatible = "fixed-factor-clock";
1165 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1166 #clock-cells = <0>;
1167 clock-div = <6>;
1168 clock-mult = <1>;
1169 clock-output-names = "zs";
1170 };
1171 hp_clk: hp_clk {
1172 compatible = "fixed-factor-clock";
1173 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1174 #clock-cells = <0>;
1175 clock-div = <12>;
1176 clock-mult = <1>;
1177 clock-output-names = "hp";
1178 };
1179 i_clk: i_clk {
1180 compatible = "fixed-factor-clock";
1181 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182 #clock-cells = <0>;
1183 clock-div = <2>;
1184 clock-mult = <1>;
1185 clock-output-names = "i";
1186 };
1187 b_clk: b_clk {
1188 compatible = "fixed-factor-clock";
1189 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1190 #clock-cells = <0>;
1191 clock-div = <12>;
1192 clock-mult = <1>;
1193 clock-output-names = "b";
1194 };
1195 p_clk: p_clk {
1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198 #clock-cells = <0>;
1199 clock-div = <24>;
1200 clock-mult = <1>;
1201 clock-output-names = "p";
1202 };
1203 cl_clk: cl_clk {
1204 compatible = "fixed-factor-clock";
1205 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1206 #clock-cells = <0>;
1207 clock-div = <48>;
1208 clock-mult = <1>;
1209 clock-output-names = "cl";
1210 };
1211 m2_clk: m2_clk {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1214 #clock-cells = <0>;
1215 clock-div = <8>;
1216 clock-mult = <1>;
1217 clock-output-names = "m2";
1218 };
1219 imp_clk: imp_clk {
1220 compatible = "fixed-factor-clock";
1221 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1222 #clock-cells = <0>;
1223 clock-div = <4>;
1224 clock-mult = <1>;
1225 clock-output-names = "imp";
1226 };
1227 rclk_clk: rclk_clk {
1228 compatible = "fixed-factor-clock";
1229 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1230 #clock-cells = <0>;
1231 clock-div = <(48 * 1024)>;
1232 clock-mult = <1>;
1233 clock-output-names = "rclk";
1234 };
1235 oscclk_clk: oscclk_clk {
1236 compatible = "fixed-factor-clock";
1237 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1238 #clock-cells = <0>;
1239 clock-div = <(12 * 1024)>;
1240 clock-mult = <1>;
1241 clock-output-names = "oscclk";
1242 };
1243 zb3_clk: zb3_clk {
1244 compatible = "fixed-factor-clock";
1245 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1246 #clock-cells = <0>;
1247 clock-div = <4>;
1248 clock-mult = <1>;
1249 clock-output-names = "zb3";
1250 };
1251 zb3d2_clk: zb3d2_clk {
1252 compatible = "fixed-factor-clock";
1253 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1254 #clock-cells = <0>;
1255 clock-div = <8>;
1256 clock-mult = <1>;
1257 clock-output-names = "zb3d2";
1258 };
1259 ddr_clk: ddr_clk {
1260 compatible = "fixed-factor-clock";
1261 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1262 #clock-cells = <0>;
1263 clock-div = <8>;
1264 clock-mult = <1>;
1265 clock-output-names = "ddr";
1266 };
1267 mp_clk: mp_clk {
1268 compatible = "fixed-factor-clock";
1269 clocks = <&pll1_div2_clk>;
1270 #clock-cells = <0>;
1271 clock-div = <15>;
1272 clock-mult = <1>;
1273 clock-output-names = "mp";
1274 };
1275 cp_clk: cp_clk {
1276 compatible = "fixed-factor-clock";
1277 clocks = <&extal_clk>;
1278 #clock-cells = <0>;
1279 clock-div = <2>;
1280 clock-mult = <1>;
1281 clock-output-names = "cp";
1282 };
1283
1284 /* Gate clocks */
1285 mstp0_clks: mstp0_clks@e6150130 {
1286 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1287 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1288 clocks = <&mp_clk>;
1289 #clock-cells = <1>;
1290 clock-indices = <R8A7790_CLK_MSIOF0>;
1291 clock-output-names = "msiof0";
1292 };
1293 mstp1_clks: mstp1_clks@e6150134 {
1294 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1295 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1296 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1297 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1298 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1299 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1300 #clock-cells = <1>;
1301 clock-indices = <
1302 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1303 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1304 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1305 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1306 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1307 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1308 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1309 >;
1310 clock-output-names =
1311 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1312 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1313 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1314 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1315 };
1316 mstp2_clks: mstp2_clks@e6150138 {
1317 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1318 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1319 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1320 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1321 <&zs_clk>;
1322 #clock-cells = <1>;
1323 clock-indices = <
1324 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1325 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1326 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1327 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1328 >;
1329 clock-output-names =
1330 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1331 "scifb1", "msiof1", "msiof3", "scifb2",
1332 "sys-dmac1", "sys-dmac0";
1333 };
1334 mstp3_clks: mstp3_clks@e615013c {
1335 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1336 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1337 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1338 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1339 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1340 <&hp_clk>, <&hp_clk>;
1341 #clock-cells = <1>;
1342 clock-indices = <
1343 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1344 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1345 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1346 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1347 >;
1348 clock-output-names =
1349 "iic2", "tpu0", "mmcif1", "sdhi3",
1350 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1351 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1352 "usbdmac0", "usbdmac1";
1353 };
1354 mstp4_clks: mstp4_clks@e6150140 {
1355 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1356 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1357 clocks = <&cp_clk>;
1358 #clock-cells = <1>;
1359 clock-indices = <R8A7790_CLK_IRQC>;
1360 clock-output-names = "irqc";
1361 };
1362 mstp5_clks: mstp5_clks@e6150144 {
1363 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1364 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1365 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1366 <&extal_clk>, <&p_clk>;
1367 #clock-cells = <1>;
1368 clock-indices = <
1369 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1370 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1371 R8A7790_CLK_PWM
1372 >;
1373 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1374 "thermal", "pwm";
1375 };
1376 mstp7_clks: mstp7_clks@e615014c {
1377 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1378 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1379 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1380 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1381 <&zx_clk>;
1382 #clock-cells = <1>;
1383 clock-indices = <
1384 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1385 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1386 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1387 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1388 >;
1389 clock-output-names =
1390 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1391 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1392 };
1393 mstp8_clks: mstp8_clks@e6150990 {
1394 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1395 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1396 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1397 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1398 <&zs_clk>;
1399 #clock-cells = <1>;
1400 clock-indices = <
1401 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1402 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1403 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1404 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1405 >;
1406 clock-output-names =
1407 "mlb", "vin3", "vin2", "vin1", "vin0",
1408 "etheravb", "ether", "sata1", "sata0";
1409 };
1410 mstp9_clks: mstp9_clks@e6150994 {
1411 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1412 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1413 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1414 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1415 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1416 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1417 #clock-cells = <1>;
1418 clock-indices = <
1419 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1420 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1421 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1422 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1423 >;
1424 clock-output-names =
1425 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1426 "rcan1", "rcan0", "qspi_mod", "iic3",
1427 "i2c3", "i2c2", "i2c1", "i2c0";
1428 };
1429 mstp10_clks: mstp10_clks@e6150998 {
1430 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1431 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1432 clocks = <&p_clk>,
1433 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1434 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1435 <&p_clk>,
1436 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1437 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1438 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1439 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1440 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1441 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1442 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1443
1444 #clock-cells = <1>;
1445 clock-indices = <
1446 R8A7790_CLK_SSI_ALL
1447 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1448 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1449 R8A7790_CLK_SCU_ALL
1450 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1451 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1452 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1453 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1454 >;
1455 clock-output-names =
1456 "ssi-all",
1457 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1458 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1459 "scu-all",
1460 "scu-dvc1", "scu-dvc0",
1461 "scu-ctu1-mix1", "scu-ctu0-mix0",
1462 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1463 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1464 };
1465 };
1466
1467 qspi: spi@e6b10000 {
1468 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1469 reg = <0 0xe6b10000 0 0x2c>;
1470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1472 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1473 dma-names = "tx", "rx";
1474 power-domains = <&cpg_clocks>;
1475 num-cs = <1>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 status = "disabled";
1479 };
1480
1481 msiof0: spi@e6e20000 {
1482 compatible = "renesas,msiof-r8a7790";
1483 reg = <0 0xe6e20000 0 0x0064>;
1484 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1486 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&cpg_clocks>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 status = "disabled";
1492 };
1493
1494 msiof1: spi@e6e10000 {
1495 compatible = "renesas,msiof-r8a7790";
1496 reg = <0 0xe6e10000 0 0x0064>;
1497 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1499 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1500 dma-names = "tx", "rx";
1501 power-domains = <&cpg_clocks>;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504 status = "disabled";
1505 };
1506
1507 msiof2: spi@e6e00000 {
1508 compatible = "renesas,msiof-r8a7790";
1509 reg = <0 0xe6e00000 0 0x0064>;
1510 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1512 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1513 dma-names = "tx", "rx";
1514 power-domains = <&cpg_clocks>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 status = "disabled";
1518 };
1519
1520 msiof3: spi@e6c90000 {
1521 compatible = "renesas,msiof-r8a7790";
1522 reg = <0 0xe6c90000 0 0x0064>;
1523 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1525 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1526 dma-names = "tx", "rx";
1527 power-domains = <&cpg_clocks>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 xhci: usb@ee000000 {
1534 compatible = "renesas,xhci-r8a7790";
1535 reg = <0 0xee000000 0 0xc00>;
1536 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1538 power-domains = <&cpg_clocks>;
1539 phys = <&usb2 1>;
1540 phy-names = "usb";
1541 status = "disabled";
1542 };
1543
1544 pci0: pci@ee090000 {
1545 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1546 device_type = "pci";
1547 reg = <0 0xee090000 0 0xc00>,
1548 <0 0xee080000 0 0x1100>;
1549 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1551 power-domains = <&cpg_clocks>;
1552 status = "disabled";
1553
1554 bus-range = <0 0>;
1555 #address-cells = <3>;
1556 #size-cells = <2>;
1557 #interrupt-cells = <1>;
1558 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1559 interrupt-map-mask = <0xff00 0 0 0x7>;
1560 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1561 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1562 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1563
1564 usb@0,1 {
1565 reg = <0x800 0 0 0 0>;
1566 device_type = "pci";
1567 phys = <&usb0 0>;
1568 phy-names = "usb";
1569 };
1570
1571 usb@0,2 {
1572 reg = <0x1000 0 0 0 0>;
1573 device_type = "pci";
1574 phys = <&usb0 0>;
1575 phy-names = "usb";
1576 };
1577 };
1578
1579 pci1: pci@ee0b0000 {
1580 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1581 device_type = "pci";
1582 reg = <0 0xee0b0000 0 0xc00>,
1583 <0 0xee0a0000 0 0x1100>;
1584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1586 power-domains = <&cpg_clocks>;
1587 status = "disabled";
1588
1589 bus-range = <1 1>;
1590 #address-cells = <3>;
1591 #size-cells = <2>;
1592 #interrupt-cells = <1>;
1593 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1594 interrupt-map-mask = <0xff00 0 0 0x7>;
1595 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1596 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1597 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1598 };
1599
1600 pci2: pci@ee0d0000 {
1601 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1602 device_type = "pci";
1603 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1604 power-domains = <&cpg_clocks>;
1605 reg = <0 0xee0d0000 0 0xc00>,
1606 <0 0xee0c0000 0 0x1100>;
1607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1608 status = "disabled";
1609
1610 bus-range = <2 2>;
1611 #address-cells = <3>;
1612 #size-cells = <2>;
1613 #interrupt-cells = <1>;
1614 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1615 interrupt-map-mask = <0xff00 0 0 0x7>;
1616 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1617 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1618 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1619
1620 usb@0,1 {
1621 reg = <0x800 0 0 0 0>;
1622 device_type = "pci";
1623 phys = <&usb2 0>;
1624 phy-names = "usb";
1625 };
1626
1627 usb@0,2 {
1628 reg = <0x1000 0 0 0 0>;
1629 device_type = "pci";
1630 phys = <&usb2 0>;
1631 phy-names = "usb";
1632 };
1633 };
1634
1635 pciec: pcie@fe000000 {
1636 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1637 reg = <0 0xfe000000 0 0x80000>;
1638 #address-cells = <3>;
1639 #size-cells = <2>;
1640 bus-range = <0x00 0xff>;
1641 device_type = "pci";
1642 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1643 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1644 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1645 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1646 /* Map all possible DDR as inbound ranges */
1647 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1648 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1649 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1652 #interrupt-cells = <1>;
1653 interrupt-map-mask = <0 0 0 0>;
1654 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1656 clock-names = "pcie", "pcie_bus";
1657 power-domains = <&cpg_clocks>;
1658 status = "disabled";
1659 };
1660
1661 rcar_sound: sound@ec500000 {
1662 /*
1663 * #sound-dai-cells is required
1664 *
1665 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1666 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1667 */
1668 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1669 reg = <0 0xec500000 0 0x1000>, /* SCU */
1670 <0 0xec5a0000 0 0x100>, /* ADG */
1671 <0 0xec540000 0 0x1000>, /* SSIU */
1672 <0 0xec541000 0 0x280>, /* SSI */
1673 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1674 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1675
1676 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1677 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1678 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1679 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1680 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1681 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1682 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1683 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1684 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1685 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1686 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1687 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1688 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1689 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1690 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1691 clock-names = "ssi-all",
1692 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1693 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1694 "src.9", "src.8", "src.7", "src.6", "src.5",
1695 "src.4", "src.3", "src.2", "src.1", "src.0",
1696 "ctu.0", "ctu.1",
1697 "mix.0", "mix.1",
1698 "dvc.0", "dvc.1",
1699 "clk_a", "clk_b", "clk_c", "clk_i";
1700 power-domains = <&cpg_clocks>;
1701
1702 status = "disabled";
1703
1704 rcar_sound,dvc {
1705 dvc0: dvc@0 {
1706 dmas = <&audma0 0xbc>;
1707 dma-names = "tx";
1708 };
1709 dvc1: dvc@1 {
1710 dmas = <&audma0 0xbe>;
1711 dma-names = "tx";
1712 };
1713 };
1714
1715 rcar_sound,mix {
1716 mix0: mix@0 { };
1717 mix1: mix@1 { };
1718 };
1719
1720 rcar_sound,ctu {
1721 ctu00: ctu@0 { };
1722 ctu01: ctu@1 { };
1723 ctu02: ctu@2 { };
1724 ctu03: ctu@3 { };
1725 ctu10: ctu@4 { };
1726 ctu11: ctu@5 { };
1727 ctu12: ctu@6 { };
1728 ctu13: ctu@7 { };
1729 };
1730
1731 rcar_sound,src {
1732 src0: src@0 {
1733 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1735 dma-names = "rx", "tx";
1736 };
1737 src1: src@1 {
1738 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1740 dma-names = "rx", "tx";
1741 };
1742 src2: src@2 {
1743 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1744 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1745 dma-names = "rx", "tx";
1746 };
1747 src3: src@3 {
1748 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1749 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1750 dma-names = "rx", "tx";
1751 };
1752 src4: src@4 {
1753 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1754 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1755 dma-names = "rx", "tx";
1756 };
1757 src5: src@5 {
1758 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1760 dma-names = "rx", "tx";
1761 };
1762 src6: src@6 {
1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1765 dma-names = "rx", "tx";
1766 };
1767 src7: src@7 {
1768 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1770 dma-names = "rx", "tx";
1771 };
1772 src8: src@8 {
1773 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1775 dma-names = "rx", "tx";
1776 };
1777 src9: src@9 {
1778 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x97>, <&audma1 0xba>;
1780 dma-names = "rx", "tx";
1781 };
1782 };
1783
1784 rcar_sound,ssi {
1785 ssi0: ssi@0 {
1786 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1788 dma-names = "rx", "tx", "rxu", "txu";
1789 };
1790 ssi1: ssi@1 {
1791 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1793 dma-names = "rx", "tx", "rxu", "txu";
1794 };
1795 ssi2: ssi@2 {
1796 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1798 dma-names = "rx", "tx", "rxu", "txu";
1799 };
1800 ssi3: ssi@3 {
1801 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1803 dma-names = "rx", "tx", "rxu", "txu";
1804 };
1805 ssi4: ssi@4 {
1806 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1808 dma-names = "rx", "tx", "rxu", "txu";
1809 };
1810 ssi5: ssi@5 {
1811 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1813 dma-names = "rx", "tx", "rxu", "txu";
1814 };
1815 ssi6: ssi@6 {
1816 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1818 dma-names = "rx", "tx", "rxu", "txu";
1819 };
1820 ssi7: ssi@7 {
1821 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1823 dma-names = "rx", "tx", "rxu", "txu";
1824 };
1825 ssi8: ssi@8 {
1826 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1828 dma-names = "rx", "tx", "rxu", "txu";
1829 };
1830 ssi9: ssi@9 {
1831 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1833 dma-names = "rx", "tx", "rxu", "txu";
1834 };
1835 };
1836 };
1837
1838 ipmmu_sy0: mmu@e6280000 {
1839 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1840 reg = <0 0xe6280000 0 0x1000>;
1841 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1843 #iommu-cells = <1>;
1844 status = "disabled";
1845 };
1846
1847 ipmmu_sy1: mmu@e6290000 {
1848 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1849 reg = <0 0xe6290000 0 0x1000>;
1850 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1851 #iommu-cells = <1>;
1852 status = "disabled";
1853 };
1854
1855 ipmmu_ds: mmu@e6740000 {
1856 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1857 reg = <0 0xe6740000 0 0x1000>;
1858 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1860 #iommu-cells = <1>;
1861 status = "disabled";
1862 };
1863
1864 ipmmu_mp: mmu@ec680000 {
1865 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1866 reg = <0 0xec680000 0 0x1000>;
1867 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1868 #iommu-cells = <1>;
1869 status = "disabled";
1870 };
1871
1872 ipmmu_mx: mmu@fe951000 {
1873 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1874 reg = <0 0xfe951000 0 0x1000>;
1875 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1877 #iommu-cells = <1>;
1878 status = "disabled";
1879 };
1880
1881 ipmmu_rt: mmu@ffc80000 {
1882 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1883 reg = <0 0xffc80000 0 0x1000>;
1884 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1885 #iommu-cells = <1>;
1886 status = "disabled";
1887 };
1888};