Loading...
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8974.h>
6#include <dt-bindings/clock/qcom,rpmcc.h>
7#include <dt-bindings/reset/qcom,gcc-msm8974.h>
8#include <dt-bindings/gpio/gpio.h>
9#include "skeleton.dtsi"
10
11/ {
12 model = "Qualcomm MSM8974";
13 compatible = "qcom,msm8974";
14 interrupt-parent = <&intc>;
15
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 ranges;
20
21 mpss@8000000 {
22 reg = <0x08000000 0x5100000>;
23 no-map;
24 };
25
26 mba@d100000 {
27 reg = <0x0d100000 0x100000>;
28 no-map;
29 };
30
31 reserved@d200000 {
32 reg = <0x0d200000 0xa00000>;
33 no-map;
34 };
35
36 adsp_region: adsp@dc00000 {
37 reg = <0x0dc00000 0x1900000>;
38 no-map;
39 };
40
41 venus@f500000 {
42 reg = <0x0f500000 0x500000>;
43 no-map;
44 };
45
46 smem_region: smem@fa00000 {
47 reg = <0xfa00000 0x200000>;
48 no-map;
49 };
50
51 tz@fc00000 {
52 reg = <0x0fc00000 0x160000>;
53 no-map;
54 };
55
56 rfsa@fd60000 {
57 reg = <0x0fd60000 0x20000>;
58 no-map;
59 };
60
61 rmtfs@fd80000 {
62 reg = <0x0fd80000 0x180000>;
63 no-map;
64 };
65 };
66
67 cpus {
68 #address-cells = <1>;
69 #size-cells = <0>;
70 interrupts = <1 9 0xf04>;
71
72 CPU0: cpu@0 {
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v2";
75 device_type = "cpu";
76 reg = <0>;
77 next-level-cache = <&L2>;
78 qcom,acc = <&acc0>;
79 qcom,saw = <&saw0>;
80 cpu-idle-states = <&CPU_SPC>;
81 };
82
83 CPU1: cpu@1 {
84 compatible = "qcom,krait";
85 enable-method = "qcom,kpss-acc-v2";
86 device_type = "cpu";
87 reg = <1>;
88 next-level-cache = <&L2>;
89 qcom,acc = <&acc1>;
90 qcom,saw = <&saw1>;
91 cpu-idle-states = <&CPU_SPC>;
92 };
93
94 CPU2: cpu@2 {
95 compatible = "qcom,krait";
96 enable-method = "qcom,kpss-acc-v2";
97 device_type = "cpu";
98 reg = <2>;
99 next-level-cache = <&L2>;
100 qcom,acc = <&acc2>;
101 qcom,saw = <&saw2>;
102 cpu-idle-states = <&CPU_SPC>;
103 };
104
105 CPU3: cpu@3 {
106 compatible = "qcom,krait";
107 enable-method = "qcom,kpss-acc-v2";
108 device_type = "cpu";
109 reg = <3>;
110 next-level-cache = <&L2>;
111 qcom,acc = <&acc3>;
112 qcom,saw = <&saw3>;
113 cpu-idle-states = <&CPU_SPC>;
114 };
115
116 L2: l2-cache {
117 compatible = "cache";
118 cache-level = <2>;
119 qcom,saw = <&saw_l2>;
120 };
121
122 idle-states {
123 CPU_SPC: spc {
124 compatible = "qcom,idle-state-spc",
125 "arm,idle-state";
126 entry-latency-us = <150>;
127 exit-latency-us = <200>;
128 min-residency-us = <2000>;
129 };
130 };
131 };
132
133 thermal-zones {
134 cpu-thermal0 {
135 polling-delay-passive = <250>;
136 polling-delay = <1000>;
137
138 thermal-sensors = <&tsens 5>;
139
140 trips {
141 cpu_alert0: trip0 {
142 temperature = <75000>;
143 hysteresis = <2000>;
144 type = "passive";
145 };
146 cpu_crit0: trip1 {
147 temperature = <110000>;
148 hysteresis = <2000>;
149 type = "critical";
150 };
151 };
152 };
153
154 cpu-thermal1 {
155 polling-delay-passive = <250>;
156 polling-delay = <1000>;
157
158 thermal-sensors = <&tsens 6>;
159
160 trips {
161 cpu_alert1: trip0 {
162 temperature = <75000>;
163 hysteresis = <2000>;
164 type = "passive";
165 };
166 cpu_crit1: trip1 {
167 temperature = <110000>;
168 hysteresis = <2000>;
169 type = "critical";
170 };
171 };
172 };
173
174 cpu-thermal2 {
175 polling-delay-passive = <250>;
176 polling-delay = <1000>;
177
178 thermal-sensors = <&tsens 7>;
179
180 trips {
181 cpu_alert2: trip0 {
182 temperature = <75000>;
183 hysteresis = <2000>;
184 type = "passive";
185 };
186 cpu_crit2: trip1 {
187 temperature = <110000>;
188 hysteresis = <2000>;
189 type = "critical";
190 };
191 };
192 };
193
194 cpu-thermal3 {
195 polling-delay-passive = <250>;
196 polling-delay = <1000>;
197
198 thermal-sensors = <&tsens 8>;
199
200 trips {
201 cpu_alert3: trip0 {
202 temperature = <75000>;
203 hysteresis = <2000>;
204 type = "passive";
205 };
206 cpu_crit3: trip1 {
207 temperature = <110000>;
208 hysteresis = <2000>;
209 type = "critical";
210 };
211 };
212 };
213 };
214
215 cpu-pmu {
216 compatible = "qcom,krait-pmu";
217 interrupts = <1 7 0xf04>;
218 };
219
220 clocks {
221 xo_board: xo_board {
222 compatible = "fixed-clock";
223 #clock-cells = <0>;
224 clock-frequency = <19200000>;
225 };
226
227 sleep_clk: sleep_clk {
228 compatible = "fixed-clock";
229 #clock-cells = <0>;
230 clock-frequency = <32768>;
231 };
232 };
233
234 timer {
235 compatible = "arm,armv7-timer";
236 interrupts = <1 2 0xf08>,
237 <1 3 0xf08>,
238 <1 4 0xf08>,
239 <1 1 0xf08>;
240 clock-frequency = <19200000>;
241 };
242
243 adsp-pil {
244 compatible = "qcom,msm8974-adsp-pil";
245
246 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
247 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
249 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
250 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
251 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
252
253 cx-supply = <&pm8841_s2>;
254
255 clocks = <&xo_board>;
256 clock-names = "xo";
257
258 memory-region = <&adsp_region>;
259
260 qcom,smem-states = <&adsp_smp2p_out 0>;
261 qcom,smem-state-names = "stop";
262 };
263
264 smem {
265 compatible = "qcom,smem";
266
267 memory-region = <&smem_region>;
268 qcom,rpm-msg-ram = <&rpm_msg_ram>;
269
270 hwlocks = <&tcsr_mutex 3>;
271 };
272
273 smp2p-adsp {
274 compatible = "qcom,smp2p";
275 qcom,smem = <443>, <429>;
276
277 interrupt-parent = <&intc>;
278 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
279
280 qcom,ipc = <&apcs 8 10>;
281
282 qcom,local-pid = <0>;
283 qcom,remote-pid = <2>;
284
285 adsp_smp2p_out: master-kernel {
286 qcom,entry-name = "master-kernel";
287 #qcom,smem-state-cells = <1>;
288 };
289
290 adsp_smp2p_in: slave-kernel {
291 qcom,entry-name = "slave-kernel";
292
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 };
296 };
297
298 smp2p-modem {
299 compatible = "qcom,smp2p";
300 qcom,smem = <435>, <428>;
301
302 interrupt-parent = <&intc>;
303 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
304
305 qcom,ipc = <&apcs 8 14>;
306
307 qcom,local-pid = <0>;
308 qcom,remote-pid = <1>;
309
310 modem_smp2p_out: master-kernel {
311 qcom,entry-name = "master-kernel";
312 #qcom,smem-state-cells = <1>;
313 };
314
315 modem_smp2p_in: slave-kernel {
316 qcom,entry-name = "slave-kernel";
317
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321 };
322
323 smp2p-wcnss {
324 compatible = "qcom,smp2p";
325 qcom,smem = <451>, <431>;
326
327 interrupt-parent = <&intc>;
328 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
329
330 qcom,ipc = <&apcs 8 18>;
331
332 qcom,local-pid = <0>;
333 qcom,remote-pid = <4>;
334
335 wcnss_smp2p_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337
338 #qcom,smem-state-cells = <1>;
339 };
340
341 wcnss_smp2p_in: slave-kernel {
342 qcom,entry-name = "slave-kernel";
343
344 interrupt-controller;
345 #interrupt-cells = <2>;
346 };
347 };
348
349 smsm {
350 compatible = "qcom,smsm";
351
352 #address-cells = <1>;
353 #size-cells = <0>;
354
355 qcom,ipc-1 = <&apcs 8 13>;
356 qcom,ipc-2 = <&apcs 8 9>;
357 qcom,ipc-3 = <&apcs 8 19>;
358
359 apps_smsm: apps@0 {
360 reg = <0>;
361
362 #qcom,smem-state-cells = <1>;
363 };
364
365 modem_smsm: modem@1 {
366 reg = <1>;
367 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
368
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 };
372
373 adsp_smsm: adsp@2 {
374 reg = <2>;
375 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
376
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 };
380
381 wcnss_smsm: wcnss@7 {
382 reg = <7>;
383 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
384
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 };
388 };
389
390 firmware {
391 scm {
392 compatible = "qcom,scm";
393 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
394 clock-names = "core", "bus", "iface";
395 };
396 };
397
398 soc: soc {
399 #address-cells = <1>;
400 #size-cells = <1>;
401 ranges;
402 compatible = "simple-bus";
403
404 intc: interrupt-controller@f9000000 {
405 compatible = "qcom,msm-qgic2";
406 interrupt-controller;
407 #interrupt-cells = <3>;
408 reg = <0xf9000000 0x1000>,
409 <0xf9002000 0x1000>;
410 };
411
412 apcs: syscon@f9011000 {
413 compatible = "syscon";
414 reg = <0xf9011000 0x1000>;
415 };
416
417 qfprom: qfprom@fc4bc000 {
418 #address-cells = <1>;
419 #size-cells = <1>;
420 compatible = "qcom,qfprom";
421 reg = <0xfc4bc000 0x1000>;
422 tsens_calib: calib@d0 {
423 reg = <0xd0 0x18>;
424 };
425 tsens_backup: backup@440 {
426 reg = <0x440 0x10>;
427 };
428 };
429
430 tsens: thermal-sensor@fc4a8000 {
431 compatible = "qcom,msm8974-tsens";
432 reg = <0xfc4a8000 0x2000>;
433 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
434 nvmem-cell-names = "calib", "calib_backup";
435 #thermal-sensor-cells = <1>;
436 };
437
438 timer@f9020000 {
439 #address-cells = <1>;
440 #size-cells = <1>;
441 ranges;
442 compatible = "arm,armv7-timer-mem";
443 reg = <0xf9020000 0x1000>;
444 clock-frequency = <19200000>;
445
446 frame@f9021000 {
447 frame-number = <0>;
448 interrupts = <0 8 0x4>,
449 <0 7 0x4>;
450 reg = <0xf9021000 0x1000>,
451 <0xf9022000 0x1000>;
452 };
453
454 frame@f9023000 {
455 frame-number = <1>;
456 interrupts = <0 9 0x4>;
457 reg = <0xf9023000 0x1000>;
458 status = "disabled";
459 };
460
461 frame@f9024000 {
462 frame-number = <2>;
463 interrupts = <0 10 0x4>;
464 reg = <0xf9024000 0x1000>;
465 status = "disabled";
466 };
467
468 frame@f9025000 {
469 frame-number = <3>;
470 interrupts = <0 11 0x4>;
471 reg = <0xf9025000 0x1000>;
472 status = "disabled";
473 };
474
475 frame@f9026000 {
476 frame-number = <4>;
477 interrupts = <0 12 0x4>;
478 reg = <0xf9026000 0x1000>;
479 status = "disabled";
480 };
481
482 frame@f9027000 {
483 frame-number = <5>;
484 interrupts = <0 13 0x4>;
485 reg = <0xf9027000 0x1000>;
486 status = "disabled";
487 };
488
489 frame@f9028000 {
490 frame-number = <6>;
491 interrupts = <0 14 0x4>;
492 reg = <0xf9028000 0x1000>;
493 status = "disabled";
494 };
495 };
496
497 saw0: power-controller@f9089000 {
498 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
499 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
500 };
501
502 saw1: power-controller@f9099000 {
503 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
504 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
505 };
506
507 saw2: power-controller@f90a9000 {
508 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
509 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
510 };
511
512 saw3: power-controller@f90b9000 {
513 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
514 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
515 };
516
517 saw_l2: power-controller@f9012000 {
518 compatible = "qcom,saw2";
519 reg = <0xf9012000 0x1000>;
520 regulator;
521 };
522
523 acc0: clock-controller@f9088000 {
524 compatible = "qcom,kpss-acc-v2";
525 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
526 };
527
528 acc1: clock-controller@f9098000 {
529 compatible = "qcom,kpss-acc-v2";
530 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
531 };
532
533 acc2: clock-controller@f90a8000 {
534 compatible = "qcom,kpss-acc-v2";
535 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
536 };
537
538 acc3: clock-controller@f90b8000 {
539 compatible = "qcom,kpss-acc-v2";
540 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
541 };
542
543 restart@fc4ab000 {
544 compatible = "qcom,pshold";
545 reg = <0xfc4ab000 0x4>;
546 };
547
548 gcc: clock-controller@fc400000 {
549 compatible = "qcom,gcc-msm8974";
550 #clock-cells = <1>;
551 #reset-cells = <1>;
552 #power-domain-cells = <1>;
553 reg = <0xfc400000 0x4000>;
554 };
555
556 tcsr: syscon@fd4a0000 {
557 compatible = "syscon";
558 reg = <0xfd4a0000 0x10000>;
559 };
560
561 tcsr_mutex_block: syscon@fd484000 {
562 compatible = "syscon";
563 reg = <0xfd484000 0x2000>;
564 };
565
566 mmcc: clock-controller@fd8c0000 {
567 compatible = "qcom,mmcc-msm8974";
568 #clock-cells = <1>;
569 #reset-cells = <1>;
570 #power-domain-cells = <1>;
571 reg = <0xfd8c0000 0x6000>;
572 };
573
574 tcsr_mutex: tcsr-mutex {
575 compatible = "qcom,tcsr-mutex";
576 syscon = <&tcsr_mutex_block 0 0x80>;
577
578 #hwlock-cells = <1>;
579 };
580
581 rpm_msg_ram: memory@fc428000 {
582 compatible = "qcom,rpm-msg-ram";
583 reg = <0xfc428000 0x4000>;
584 };
585
586 blsp1_uart1: serial@f991d000 {
587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
588 reg = <0xf991d000 0x1000>;
589 interrupts = <0 107 0x0>;
590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
591 clock-names = "core", "iface";
592 status = "disabled";
593 };
594
595 blsp1_uart2: serial@f991e000 {
596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597 reg = <0xf991e000 0x1000>;
598 interrupts = <0 108 0x0>;
599 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface";
601 status = "disabled";
602 };
603
604 sdhci@f9824900 {
605 compatible = "qcom,sdhci-msm-v4";
606 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
607 reg-names = "hc_mem", "core_mem";
608 interrupts = <0 123 0>, <0 138 0>;
609 interrupt-names = "hc_irq", "pwr_irq";
610 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
611 <&gcc GCC_SDCC1_AHB_CLK>,
612 <&xo_board>;
613 clock-names = "core", "iface", "xo";
614 status = "disabled";
615 };
616
617 sdhci@f9864900 {
618 compatible = "qcom,sdhci-msm-v4";
619 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
620 reg-names = "hc_mem", "core_mem";
621 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
622 <GIC_SPI 224 IRQ_TYPE_NONE>;
623 interrupt-names = "hc_irq", "pwr_irq";
624 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
625 <&gcc GCC_SDCC3_AHB_CLK>,
626 <&xo_board>;
627 clock-names = "core", "iface", "xo";
628 status = "disabled";
629 };
630
631 sdhci@f98a4900 {
632 compatible = "qcom,sdhci-msm-v4";
633 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
634 reg-names = "hc_mem", "core_mem";
635 interrupts = <0 125 0>, <0 221 0>;
636 interrupt-names = "hc_irq", "pwr_irq";
637 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
638 <&gcc GCC_SDCC2_AHB_CLK>,
639 <&xo_board>;
640 clock-names = "core", "iface", "xo";
641 status = "disabled";
642 };
643
644 otg: usb@f9a55000 {
645 compatible = "qcom,ci-hdrc";
646 reg = <0xf9a55000 0x200>,
647 <0xf9a55200 0x200>;
648 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
650 <&gcc GCC_USB_HS_SYSTEM_CLK>;
651 clock-names = "iface", "core";
652 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
653 assigned-clock-rates = <75000000>;
654 resets = <&gcc GCC_USB_HS_BCR>;
655 reset-names = "core";
656 phy_type = "ulpi";
657 dr_mode = "otg";
658 ahb-burst-config = <0>;
659 phy-names = "usb-phy";
660 status = "disabled";
661 #reset-cells = <1>;
662
663 ulpi {
664 usb_hs1_phy: phy@a {
665 compatible = "qcom,usb-hs-phy-msm8974",
666 "qcom,usb-hs-phy";
667 #phy-cells = <0>;
668 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
669 clock-names = "ref", "sleep";
670 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
671 reset-names = "phy", "por";
672 status = "disabled";
673 };
674
675 usb_hs2_phy: phy@b {
676 compatible = "qcom,usb-hs-phy-msm8974",
677 "qcom,usb-hs-phy";
678 #phy-cells = <0>;
679 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
680 clock-names = "ref", "sleep";
681 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
682 reset-names = "phy", "por";
683 status = "disabled";
684 };
685 };
686 };
687
688 rng@f9bff000 {
689 compatible = "qcom,prng";
690 reg = <0xf9bff000 0x200>;
691 clocks = <&gcc GCC_PRNG_AHB_CLK>;
692 clock-names = "core";
693 };
694
695 msmgpio: pinctrl@fd510000 {
696 compatible = "qcom,msm8974-pinctrl";
697 reg = <0xfd510000 0x4000>;
698 gpio-controller;
699 #gpio-cells = <2>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 interrupts = <0 208 0>;
703 };
704
705 i2c@f9924000 {
706 status = "disabled";
707 compatible = "qcom,i2c-qup-v2.1.1";
708 reg = <0xf9924000 0x1000>;
709 interrupts = <0 96 IRQ_TYPE_NONE>;
710 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
711 clock-names = "core", "iface";
712 #address-cells = <1>;
713 #size-cells = <0>;
714 };
715
716 blsp_i2c8: i2c@f9964000 {
717 status = "disabled";
718 compatible = "qcom,i2c-qup-v2.1.1";
719 reg = <0xf9964000 0x1000>;
720 interrupts = <0 102 IRQ_TYPE_NONE>;
721 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
722 clock-names = "core", "iface";
723 #address-cells = <1>;
724 #size-cells = <0>;
725 };
726
727 blsp_i2c11: i2c@f9967000 {
728 status = "disabled";
729 compatible = "qcom,i2c-qup-v2.1.1";
730 reg = <0xf9967000 0x1000>;
731 interrupts = <0 105 IRQ_TYPE_NONE>;
732 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
733 clock-names = "core", "iface";
734 #address-cells = <1>;
735 #size-cells = <0>;
736 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
737 dma-names = "tx", "rx";
738 };
739
740 spmi_bus: spmi@fc4cf000 {
741 compatible = "qcom,spmi-pmic-arb";
742 reg-names = "core", "intr", "cnfg";
743 reg = <0xfc4cf000 0x1000>,
744 <0xfc4cb000 0x1000>,
745 <0xfc4ca000 0x1000>;
746 interrupt-names = "periph_irq";
747 interrupts = <0 190 0>;
748 qcom,ee = <0>;
749 qcom,channel = <0>;
750 #address-cells = <2>;
751 #size-cells = <0>;
752 interrupt-controller;
753 #interrupt-cells = <4>;
754 };
755
756 blsp2_dma: dma-controller@f9944000 {
757 compatible = "qcom,bam-v1.4.0";
758 reg = <0xf9944000 0x19000>;
759 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
761 clock-names = "bam_clk";
762 #dma-cells = <1>;
763 qcom,ee = <0>;
764 };
765
766 etr@fc322000 {
767 compatible = "arm,coresight-tmc", "arm,primecell";
768 reg = <0xfc322000 0x1000>;
769
770 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
771 clock-names = "apb_pclk", "atclk";
772
773 port {
774 etr_in: endpoint {
775 slave-mode;
776 remote-endpoint = <&replicator_out0>;
777 };
778 };
779 };
780
781 tpiu@fc318000 {
782 compatible = "arm,coresight-tpiu", "arm,primecell";
783 reg = <0xfc318000 0x1000>;
784
785 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
786 clock-names = "apb_pclk", "atclk";
787
788 port {
789 tpiu_in: endpoint {
790 slave-mode;
791 remote-endpoint = <&replicator_out1>;
792 };
793 };
794 };
795
796 replicator@fc31c000 {
797 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
798 reg = <0xfc31c000 0x1000>;
799
800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
801 clock-names = "apb_pclk", "atclk";
802
803 ports {
804 #address-cells = <1>;
805 #size-cells = <0>;
806
807 port@0 {
808 reg = <0>;
809 replicator_out0: endpoint {
810 remote-endpoint = <&etr_in>;
811 };
812 };
813 port@1 {
814 reg = <1>;
815 replicator_out1: endpoint {
816 remote-endpoint = <&tpiu_in>;
817 };
818 };
819 port@2 {
820 reg = <0>;
821 replicator_in: endpoint {
822 slave-mode;
823 remote-endpoint = <&etf_out>;
824 };
825 };
826 };
827 };
828
829 etf@fc307000 {
830 compatible = "arm,coresight-tmc", "arm,primecell";
831 reg = <0xfc307000 0x1000>;
832
833 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
834 clock-names = "apb_pclk", "atclk";
835
836 ports {
837 #address-cells = <1>;
838 #size-cells = <0>;
839
840 port@0 {
841 reg = <0>;
842 etf_out: endpoint {
843 remote-endpoint = <&replicator_in>;
844 };
845 };
846 port@1 {
847 reg = <0>;
848 etf_in: endpoint {
849 slave-mode;
850 remote-endpoint = <&merger_out>;
851 };
852 };
853 };
854 };
855
856 funnel@fc31b000 {
857 compatible = "arm,coresight-funnel", "arm,primecell";
858 reg = <0xfc31b000 0x1000>;
859
860 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
861 clock-names = "apb_pclk", "atclk";
862
863 ports {
864 #address-cells = <1>;
865 #size-cells = <0>;
866
867 /*
868 * Not described input ports:
869 * 0 - connected trought funnel to Audio, Modem and
870 * Resource and Power Manager CPU's
871 * 2...7 - not-connected
872 */
873 port@1 {
874 reg = <1>;
875 merger_in1: endpoint {
876 slave-mode;
877 remote-endpoint = <&funnel1_out>;
878 };
879 };
880 port@8 {
881 reg = <0>;
882 merger_out: endpoint {
883 remote-endpoint = <&etf_in>;
884 };
885 };
886 };
887 };
888
889 funnel@fc31a000 {
890 compatible = "arm,coresight-funnel", "arm,primecell";
891 reg = <0xfc31a000 0x1000>;
892
893 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
894 clock-names = "apb_pclk", "atclk";
895
896 ports {
897 #address-cells = <1>;
898 #size-cells = <0>;
899
900 /*
901 * Not described input ports:
902 * 0 - not-connected
903 * 1 - connected trought funnel to Multimedia CPU
904 * 2 - connected to Wireless CPU
905 * 3 - not-connected
906 * 4 - not-connected
907 * 6 - not-connected
908 * 7 - connected to STM
909 */
910 port@5 {
911 reg = <5>;
912 funnel1_in5: endpoint {
913 slave-mode;
914 remote-endpoint = <&kpss_out>;
915 };
916 };
917 port@8 {
918 reg = <0>;
919 funnel1_out: endpoint {
920 remote-endpoint = <&merger_in1>;
921 };
922 };
923 };
924 };
925
926 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
927 compatible = "arm,coresight-funnel", "arm,primecell";
928 reg = <0xfc345000 0x1000>;
929
930 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
931 clock-names = "apb_pclk", "atclk";
932
933 ports {
934 #address-cells = <1>;
935 #size-cells = <0>;
936
937 port@0 {
938 reg = <0>;
939 kpss_in0: endpoint {
940 slave-mode;
941 remote-endpoint = <&etm0_out>;
942 };
943 };
944 port@1 {
945 reg = <1>;
946 kpss_in1: endpoint {
947 slave-mode;
948 remote-endpoint = <&etm1_out>;
949 };
950 };
951 port@2 {
952 reg = <2>;
953 kpss_in2: endpoint {
954 slave-mode;
955 remote-endpoint = <&etm2_out>;
956 };
957 };
958 port@3 {
959 reg = <3>;
960 kpss_in3: endpoint {
961 slave-mode;
962 remote-endpoint = <&etm3_out>;
963 };
964 };
965 port@8 {
966 reg = <0>;
967 kpss_out: endpoint {
968 remote-endpoint = <&funnel1_in5>;
969 };
970 };
971 };
972 };
973
974 etm@fc33c000 {
975 compatible = "arm,coresight-etm4x", "arm,primecell";
976 reg = <0xfc33c000 0x1000>;
977
978 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
979 clock-names = "apb_pclk", "atclk";
980
981 cpu = <&CPU0>;
982
983 port {
984 etm0_out: endpoint {
985 remote-endpoint = <&kpss_in0>;
986 };
987 };
988 };
989
990 etm@fc33d000 {
991 compatible = "arm,coresight-etm4x", "arm,primecell";
992 reg = <0xfc33d000 0x1000>;
993
994 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
995 clock-names = "apb_pclk", "atclk";
996
997 cpu = <&CPU1>;
998
999 port {
1000 etm1_out: endpoint {
1001 remote-endpoint = <&kpss_in1>;
1002 };
1003 };
1004 };
1005
1006 etm@fc33e000 {
1007 compatible = "arm,coresight-etm4x", "arm,primecell";
1008 reg = <0xfc33e000 0x1000>;
1009
1010 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1011 clock-names = "apb_pclk", "atclk";
1012
1013 cpu = <&CPU2>;
1014
1015 port {
1016 etm2_out: endpoint {
1017 remote-endpoint = <&kpss_in2>;
1018 };
1019 };
1020 };
1021
1022 etm@fc33f000 {
1023 compatible = "arm,coresight-etm4x", "arm,primecell";
1024 reg = <0xfc33f000 0x1000>;
1025
1026 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1027 clock-names = "apb_pclk", "atclk";
1028
1029 cpu = <&CPU3>;
1030
1031 port {
1032 etm3_out: endpoint {
1033 remote-endpoint = <&kpss_in3>;
1034 };
1035 };
1036 };
1037 };
1038
1039 smd {
1040 compatible = "qcom,smd";
1041
1042 adsp {
1043 interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
1044
1045 qcom,ipc = <&apcs 8 8>;
1046 qcom,smd-edge = <1>;
1047 };
1048
1049 modem {
1050 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1051
1052 qcom,ipc = <&apcs 8 12>;
1053 qcom,smd-edge = <0>;
1054 };
1055
1056 rpm {
1057 interrupts = <0 168 1>;
1058 qcom,ipc = <&apcs 8 0>;
1059 qcom,smd-edge = <15>;
1060
1061 rpm_requests {
1062 compatible = "qcom,rpm-msm8974";
1063 qcom,smd-channels = "rpm_requests";
1064
1065 rpmcc: clock-controller {
1066 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1067 #clock-cells = <1>;
1068 };
1069
1070 pm8841-regulators {
1071 compatible = "qcom,rpm-pm8841-regulators";
1072
1073 pm8841_s1: s1 {};
1074 pm8841_s2: s2 {};
1075 pm8841_s3: s3 {};
1076 pm8841_s4: s4 {};
1077 pm8841_s5: s5 {};
1078 pm8841_s6: s6 {};
1079 pm8841_s7: s7 {};
1080 pm8841_s8: s8 {};
1081 };
1082
1083 pm8941-regulators {
1084 compatible = "qcom,rpm-pm8941-regulators";
1085
1086 pm8941_s1: s1 {};
1087 pm8941_s2: s2 {};
1088 pm8941_s3: s3 {};
1089
1090 pm8941_l1: l1 {};
1091 pm8941_l2: l2 {};
1092 pm8941_l3: l3 {};
1093 pm8941_l4: l4 {};
1094 pm8941_l5: l5 {};
1095 pm8941_l6: l6 {};
1096 pm8941_l7: l7 {};
1097 pm8941_l8: l8 {};
1098 pm8941_l9: l9 {};
1099 pm8941_l10: l10 {};
1100 pm8941_l11: l11 {};
1101 pm8941_l12: l12 {};
1102 pm8941_l13: l13 {};
1103 pm8941_l14: l14 {};
1104 pm8941_l15: l15 {};
1105 pm8941_l16: l16 {};
1106 pm8941_l17: l17 {};
1107 pm8941_l18: l18 {};
1108 pm8941_l19: l19 {};
1109 pm8941_l20: l20 {};
1110 pm8941_l21: l21 {};
1111 pm8941_l22: l22 {};
1112 pm8941_l23: l23 {};
1113 pm8941_l24: l24 {};
1114
1115 pm8941_lvs1: lvs1 {};
1116 pm8941_lvs2: lvs2 {};
1117 pm8941_lvs3: lvs3 {};
1118 };
1119 };
1120 };
1121 };
1122
1123 vreg_boost: vreg-boost {
1124 compatible = "regulator-fixed";
1125
1126 regulator-name = "vreg-boost";
1127 regulator-min-microvolt = <3150000>;
1128 regulator-max-microvolt = <3150000>;
1129
1130 regulator-always-on;
1131 regulator-boot-on;
1132
1133 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1134 enable-active-high;
1135
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&boost_bypass_n_pin>;
1138 };
1139 vreg_vph_pwr: vreg-vph-pwr {
1140 compatible = "regulator-fixed";
1141 regulator-name = "vph-pwr";
1142
1143 regulator-min-microvolt = <3600000>;
1144 regulator-max-microvolt = <3600000>;
1145
1146 regulator-always-on;
1147 };
1148};
1/dts-v1/;
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/clock/qcom,gcc-msm8974.h>
5#include "skeleton.dtsi"
6
7/ {
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
11
12 reserved-memory {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges;
16
17 mpss@08000000 {
18 reg = <0x08000000 0x5100000>;
19 no-map;
20 };
21
22 mba@00d100000 {
23 reg = <0x0d100000 0x100000>;
24 no-map;
25 };
26
27 reserved@0d200000 {
28 reg = <0x0d200000 0xa00000>;
29 no-map;
30 };
31
32 adsp@0dc00000 {
33 reg = <0x0dc00000 0x1900000>;
34 no-map;
35 };
36
37 venus@0f500000 {
38 reg = <0x0f500000 0x500000>;
39 no-map;
40 };
41
42 smem_region: smem@fa00000 {
43 reg = <0xfa00000 0x200000>;
44 no-map;
45 };
46
47 tz@0fc00000 {
48 reg = <0x0fc00000 0x160000>;
49 no-map;
50 };
51
52 efs@0fd600000 {
53 reg = <0x0fd60000 0x1a0000>;
54 no-map;
55 };
56
57 unused@0ff00000 {
58 reg = <0x0ff00000 0x10100000>;
59 no-map;
60 };
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 interrupts = <1 9 0xf04>;
67
68 cpu@0 {
69 compatible = "qcom,krait";
70 enable-method = "qcom,kpss-acc-v2";
71 device_type = "cpu";
72 reg = <0>;
73 next-level-cache = <&L2>;
74 qcom,acc = <&acc0>;
75 qcom,saw = <&saw0>;
76 cpu-idle-states = <&CPU_SPC>;
77 };
78
79 cpu@1 {
80 compatible = "qcom,krait";
81 enable-method = "qcom,kpss-acc-v2";
82 device_type = "cpu";
83 reg = <1>;
84 next-level-cache = <&L2>;
85 qcom,acc = <&acc1>;
86 qcom,saw = <&saw1>;
87 cpu-idle-states = <&CPU_SPC>;
88 };
89
90 cpu@2 {
91 compatible = "qcom,krait";
92 enable-method = "qcom,kpss-acc-v2";
93 device_type = "cpu";
94 reg = <2>;
95 next-level-cache = <&L2>;
96 qcom,acc = <&acc2>;
97 qcom,saw = <&saw2>;
98 cpu-idle-states = <&CPU_SPC>;
99 };
100
101 cpu@3 {
102 compatible = "qcom,krait";
103 enable-method = "qcom,kpss-acc-v2";
104 device_type = "cpu";
105 reg = <3>;
106 next-level-cache = <&L2>;
107 qcom,acc = <&acc3>;
108 qcom,saw = <&saw3>;
109 cpu-idle-states = <&CPU_SPC>;
110 };
111
112 L2: l2-cache {
113 compatible = "cache";
114 cache-level = <2>;
115 qcom,saw = <&saw_l2>;
116 };
117
118 idle-states {
119 CPU_SPC: spc {
120 compatible = "qcom,idle-state-spc",
121 "arm,idle-state";
122 entry-latency-us = <150>;
123 exit-latency-us = <200>;
124 min-residency-us = <2000>;
125 };
126 };
127 };
128
129 cpu-pmu {
130 compatible = "qcom,krait-pmu";
131 interrupts = <1 7 0xf04>;
132 };
133
134 clocks {
135 xo_board {
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <19200000>;
139 };
140
141 sleep_clk {
142 compatible = "fixed-clock";
143 #clock-cells = <0>;
144 clock-frequency = <32768>;
145 };
146 };
147
148 timer {
149 compatible = "arm,armv7-timer";
150 interrupts = <1 2 0xf08>,
151 <1 3 0xf08>,
152 <1 4 0xf08>,
153 <1 1 0xf08>;
154 clock-frequency = <19200000>;
155 };
156
157 smem {
158 compatible = "qcom,smem";
159
160 memory-region = <&smem_region>;
161 qcom,rpm-msg-ram = <&rpm_msg_ram>;
162
163 hwlocks = <&tcsr_mutex 3>;
164 };
165
166 smp2p-wcnss {
167 compatible = "qcom,smp2p";
168 qcom,smem = <451>, <431>;
169
170 interrupt-parent = <&intc>;
171 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
172
173 qcom,ipc = <&apcs 8 18>;
174
175 qcom,local-pid = <0>;
176 qcom,remote-pid = <4>;
177
178 wcnss_smp2p_out: master-kernel {
179 qcom,entry-name = "master-kernel";
180
181 #qcom,state-cells = <1>;
182 };
183
184 wcnss_smp2p_in: slave-kernel {
185 qcom,entry-name = "slave-kernel";
186
187 interrupt-controller;
188 #interrupt-cells = <2>;
189 };
190 };
191
192 smsm {
193 compatible = "qcom,smsm";
194
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 qcom,ipc-1 = <&apcs 8 13>;
199 qcom,ipc-2 = <&apcs 8 9>;
200 qcom,ipc-3 = <&apcs 8 19>;
201
202 apps_smsm: apps@0 {
203 reg = <0>;
204
205 #qcom,state-cells = <1>;
206 };
207
208 modem_smsm: modem@1 {
209 reg = <1>;
210 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
211
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 adsp_smsm: adsp@2 {
217 reg = <2>;
218 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
219
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 };
223
224 wcnss_smsm: wcnss@7 {
225 reg = <7>;
226 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
227
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231 };
232
233 soc: soc {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 ranges;
237 compatible = "simple-bus";
238
239 intc: interrupt-controller@f9000000 {
240 compatible = "qcom,msm-qgic2";
241 interrupt-controller;
242 #interrupt-cells = <3>;
243 reg = <0xf9000000 0x1000>,
244 <0xf9002000 0x1000>;
245 };
246
247 apcs: syscon@f9011000 {
248 compatible = "syscon";
249 reg = <0xf9011000 0x1000>;
250 };
251
252 timer@f9020000 {
253 #address-cells = <1>;
254 #size-cells = <1>;
255 ranges;
256 compatible = "arm,armv7-timer-mem";
257 reg = <0xf9020000 0x1000>;
258 clock-frequency = <19200000>;
259
260 frame@f9021000 {
261 frame-number = <0>;
262 interrupts = <0 8 0x4>,
263 <0 7 0x4>;
264 reg = <0xf9021000 0x1000>,
265 <0xf9022000 0x1000>;
266 };
267
268 frame@f9023000 {
269 frame-number = <1>;
270 interrupts = <0 9 0x4>;
271 reg = <0xf9023000 0x1000>;
272 status = "disabled";
273 };
274
275 frame@f9024000 {
276 frame-number = <2>;
277 interrupts = <0 10 0x4>;
278 reg = <0xf9024000 0x1000>;
279 status = "disabled";
280 };
281
282 frame@f9025000 {
283 frame-number = <3>;
284 interrupts = <0 11 0x4>;
285 reg = <0xf9025000 0x1000>;
286 status = "disabled";
287 };
288
289 frame@f9026000 {
290 frame-number = <4>;
291 interrupts = <0 12 0x4>;
292 reg = <0xf9026000 0x1000>;
293 status = "disabled";
294 };
295
296 frame@f9027000 {
297 frame-number = <5>;
298 interrupts = <0 13 0x4>;
299 reg = <0xf9027000 0x1000>;
300 status = "disabled";
301 };
302
303 frame@f9028000 {
304 frame-number = <6>;
305 interrupts = <0 14 0x4>;
306 reg = <0xf9028000 0x1000>;
307 status = "disabled";
308 };
309 };
310
311 saw0: power-controller@f9089000 {
312 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
313 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
314 };
315
316 saw1: power-controller@f9099000 {
317 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
318 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
319 };
320
321 saw2: power-controller@f90a9000 {
322 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
323 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
324 };
325
326 saw3: power-controller@f90b9000 {
327 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
328 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
329 };
330
331 saw_l2: power-controller@f9012000 {
332 compatible = "qcom,saw2";
333 reg = <0xf9012000 0x1000>;
334 regulator;
335 };
336
337 acc0: clock-controller@f9088000 {
338 compatible = "qcom,kpss-acc-v2";
339 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
340 };
341
342 acc1: clock-controller@f9098000 {
343 compatible = "qcom,kpss-acc-v2";
344 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
345 };
346
347 acc2: clock-controller@f90a8000 {
348 compatible = "qcom,kpss-acc-v2";
349 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
350 };
351
352 acc3: clock-controller@f90b8000 {
353 compatible = "qcom,kpss-acc-v2";
354 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
355 };
356
357 restart@fc4ab000 {
358 compatible = "qcom,pshold";
359 reg = <0xfc4ab000 0x4>;
360 };
361
362 gcc: clock-controller@fc400000 {
363 compatible = "qcom,gcc-msm8974";
364 #clock-cells = <1>;
365 #reset-cells = <1>;
366 #power-domain-cells = <1>;
367 reg = <0xfc400000 0x4000>;
368 };
369
370 tcsr_mutex_block: syscon@fd484000 {
371 compatible = "syscon";
372 reg = <0xfd484000 0x2000>;
373 };
374
375 mmcc: clock-controller@fd8c0000 {
376 compatible = "qcom,mmcc-msm8974";
377 #clock-cells = <1>;
378 #reset-cells = <1>;
379 #power-domain-cells = <1>;
380 reg = <0xfd8c0000 0x6000>;
381 };
382
383 tcsr_mutex: tcsr-mutex {
384 compatible = "qcom,tcsr-mutex";
385 syscon = <&tcsr_mutex_block 0 0x80>;
386
387 #hwlock-cells = <1>;
388 };
389
390 rpm_msg_ram: memory@fc428000 {
391 compatible = "qcom,rpm-msg-ram";
392 reg = <0xfc428000 0x4000>;
393 };
394
395 blsp1_uart2: serial@f991e000 {
396 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
397 reg = <0xf991e000 0x1000>;
398 interrupts = <0 108 0x0>;
399 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", "iface";
401 status = "disabled";
402 };
403
404 sdhci@f9824900 {
405 compatible = "qcom,sdhci-msm-v4";
406 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
407 reg-names = "hc_mem", "core_mem";
408 interrupts = <0 123 0>, <0 138 0>;
409 interrupt-names = "hc_irq", "pwr_irq";
410 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
411 clock-names = "core", "iface";
412 status = "disabled";
413 };
414
415 sdhci@f98a4900 {
416 compatible = "qcom,sdhci-msm-v4";
417 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
418 reg-names = "hc_mem", "core_mem";
419 interrupts = <0 125 0>, <0 221 0>;
420 interrupt-names = "hc_irq", "pwr_irq";
421 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
422 clock-names = "core", "iface";
423 status = "disabled";
424 };
425
426 rng@f9bff000 {
427 compatible = "qcom,prng";
428 reg = <0xf9bff000 0x200>;
429 clocks = <&gcc GCC_PRNG_AHB_CLK>;
430 clock-names = "core";
431 };
432
433 msmgpio: pinctrl@fd510000 {
434 compatible = "qcom,msm8974-pinctrl";
435 reg = <0xfd510000 0x4000>;
436 gpio-controller;
437 #gpio-cells = <2>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 interrupts = <0 208 0>;
441 };
442
443 blsp_i2c8: i2c@f9964000 {
444 status = "disabled";
445 compatible = "qcom,i2c-qup-v2.1.1";
446 reg = <0xf9964000 0x1000>;
447 interrupts = <0 102 IRQ_TYPE_NONE>;
448 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
449 clock-names = "core", "iface";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 };
453
454 blsp_i2c11: i2c@f9967000 {
455 status = "disabled";
456 compatible = "qcom,i2c-qup-v2.1.1";
457 reg = <0xf9967000 0x1000>;
458 interrupts = <0 105 IRQ_TYPE_NONE>;
459 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
460 clock-names = "core", "iface";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 };
464
465 spmi_bus: spmi@fc4cf000 {
466 compatible = "qcom,spmi-pmic-arb";
467 reg-names = "core", "intr", "cnfg";
468 reg = <0xfc4cf000 0x1000>,
469 <0xfc4cb000 0x1000>,
470 <0xfc4ca000 0x1000>;
471 interrupt-names = "periph_irq";
472 interrupts = <0 190 0>;
473 qcom,ee = <0>;
474 qcom,channel = <0>;
475 #address-cells = <2>;
476 #size-cells = <0>;
477 interrupt-controller;
478 #interrupt-cells = <4>;
479 };
480 };
481
482 smd {
483 compatible = "qcom,smd";
484
485 rpm {
486 interrupts = <0 168 1>;
487 qcom,ipc = <&apcs 8 0>;
488 qcom,smd-edge = <15>;
489
490 rpm_requests {
491 compatible = "qcom,rpm-msm8974";
492 qcom,smd-channels = "rpm_requests";
493
494 pm8841-regulators {
495 compatible = "qcom,rpm-pm8841-regulators";
496
497 pm8841_s1: s1 {};
498 pm8841_s2: s2 {};
499 pm8841_s3: s3 {};
500 pm8841_s4: s4 {};
501 pm8841_s5: s5 {};
502 pm8841_s6: s6 {};
503 pm8841_s7: s7 {};
504 pm8841_s8: s8 {};
505 };
506
507 pm8941-regulators {
508 compatible = "qcom,rpm-pm8941-regulators";
509
510 pm8941_s1: s1 {};
511 pm8941_s2: s2 {};
512 pm8941_s3: s3 {};
513 pm8941_5v: s4 {};
514
515 pm8941_l1: l1 {};
516 pm8941_l2: l2 {};
517 pm8941_l3: l3 {};
518 pm8941_l4: l4 {};
519 pm8941_l5: l5 {};
520 pm8941_l6: l6 {};
521 pm8941_l7: l7 {};
522 pm8941_l8: l8 {};
523 pm8941_l9: l9 {};
524 pm8941_l10: l10 {};
525 pm8941_l11: l11 {};
526 pm8941_l12: l12 {};
527 pm8941_l13: l13 {};
528 pm8941_l14: l14 {};
529 pm8941_l15: l15 {};
530 pm8941_l16: l16 {};
531 pm8941_l17: l17 {};
532 pm8941_l18: l18 {};
533 pm8941_l19: l19 {};
534 pm8941_l20: l20 {};
535 pm8941_l21: l21 {};
536 pm8941_l22: l22 {};
537 pm8941_l23: l23 {};
538 pm8941_l24: l24 {};
539
540 pm8941_lvs1: lvs1 {};
541 pm8941_lvs2: lvs2 {};
542 pm8941_lvs3: lvs3 {};
543
544 pm8941_5vs1: 5vs1 {};
545 pm8941_5vs2: 5vs2 {};
546 };
547 };
548 };
549 };
550};