1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Marvell RD88F6181 A Board descrition
 4 *
 5 * Andrew Lunn <andrew@lunn.ch>
 6 *
 
 
 
 
 7 * This file contains the definitions for the board with the A0 or
 8 * higher stepping of the SoC. The ethernet switch does not have a
 9 * "wan" port.
10 */
11
12/dts-v1/;
13#include "kirkwood-rd88f6281.dtsi"
14
15/ {
16	model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
17	compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
18
 
 
 
 
 
19};
20
21&mdio {
22	status = "okay";
23
24	ethphy1: ethernet-phy@11 {
25		 reg = <11>;
26	};
27};
28
29&switch {
30	reg = <10>;
31};
32
33&eth1 {
34	status = "okay";
35
36	ethernet1-port@0 {
37		 phy-handle = <&ethphy1>;
38	};
39};

 
 1/*
 2 * Marvell RD88F6181 A Board descrition
 3 *
 4 * Andrew Lunn <andrew@lunn.ch>
 5 *
 6 * This file is licensed under the terms of the GNU General Public
 7 * License version 2.  This program is licensed "as is" without any
 8 * warranty of any kind, whether express or implied.
 9 *
10 * This file contains the definitions for the board with the A0 or
11 * higher stepping of the SoC. The ethernet switch does not have a
12 * "wan" port.
13 */
14
15/dts-v1/;
16#include "kirkwood-rd88f6281.dtsi"
17
18/ {
19	model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
20	compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
21
22	dsa@0 {
23		switch@0 {
24			reg = <10 0>;	 /* MDIO address 10, switch 0 in tree */
25		};
26	};
27};
28
29&mdio {
30	status = "okay";
31
32	ethphy1: ethernet-phy@11 {
33		 reg = <11>;
34	};
 
 
 
 
35};
36
37&eth1 {
38	status = "okay";
39
40	ethernet1-port@0 {
41		 phy-handle = <&ethphy1>;
42	};
43};