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1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "imx50-pinfunc.h"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clock/imx5-clock.h>
17
18/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 /*
22 * The decompressor and also some bootloaders rely on a
23 * pre-existing /chosen node to be available to insert the
24 * command line and merge other ATAGS info.
25 * Also for U-Boot there must be a pre-existing /memory node.
26 */
27 chosen {};
28 memory { device_type = "memory"; };
29
30 aliases {
31 ethernet0 = &fec;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a8";
51 reg = <0x0>;
52 };
53 };
54
55 tzic: tz-interrupt-controller@fffc000 {
56 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x0fffc000 0x4000>;
60 };
61
62 clocks {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 ckil {
67 compatible = "fsl,imx-ckil", "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <32768>;
70 };
71
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <22579200>;
76 };
77
78 ckih2 {
79 compatible = "fsl,imx-ckih2", "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <24000000>;
88 };
89 };
90
91 soc {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "simple-bus";
95 interrupt-parent = <&tzic>;
96 ranges;
97
98 aips@50000000 { /* AIPS1 */
99 compatible = "fsl,aips-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x50000000 0x10000000>;
103 ranges;
104
105 spba@50000000 {
106 compatible = "fsl,spba-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x50000000 0x40000>;
110 ranges;
111
112 esdhc1: esdhc@50004000 {
113 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
114 reg = <0x50004000 0x4000>;
115 interrupts = <1>;
116 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
117 <&clks IMX5_CLK_DUMMY>,
118 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
119 clock-names = "ipg", "ahb", "per";
120 bus-width = <4>;
121 status = "disabled";
122 };
123
124 esdhc2: esdhc@50008000 {
125 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
126 reg = <0x50008000 0x4000>;
127 interrupts = <2>;
128 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
129 <&clks IMX5_CLK_DUMMY>,
130 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
131 clock-names = "ipg", "ahb", "per";
132 bus-width = <4>;
133 status = "disabled";
134 };
135
136 uart3: serial@5000c000 {
137 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
138 reg = <0x5000c000 0x4000>;
139 interrupts = <33>;
140 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
141 <&clks IMX5_CLK_UART3_PER_GATE>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
145
146 ecspi1: ecspi@50010000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
150 reg = <0x50010000 0x4000>;
151 interrupts = <36>;
152 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
153 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157
158 ssi2: ssi@50014000 {
159 #sound-dai-cells = <0>;
160 compatible = "fsl,imx50-ssi",
161 "fsl,imx51-ssi",
162 "fsl,imx21-ssi";
163 reg = <0x50014000 0x4000>;
164 interrupts = <30>;
165 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
166 dmas = <&sdma 24 1 0>,
167 <&sdma 25 1 0>;
168 dma-names = "rx", "tx";
169 fsl,fifo-depth = <15>;
170 status = "disabled";
171 };
172
173 esdhc3: esdhc@50020000 {
174 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
175 reg = <0x50020000 0x4000>;
176 interrupts = <3>;
177 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
180 clock-names = "ipg", "ahb", "per";
181 bus-width = <4>;
182 status = "disabled";
183 };
184
185 esdhc4: esdhc@50024000 {
186 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
187 reg = <0x50024000 0x4000>;
188 interrupts = <4>;
189 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
190 <&clks IMX5_CLK_DUMMY>,
191 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
192 clock-names = "ipg", "ahb", "per";
193 bus-width = <4>;
194 status = "disabled";
195 };
196 };
197
198 usbotg: usb@53f80000 {
199 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
200 reg = <0x53f80000 0x0200>;
201 interrupts = <18>;
202 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
203 status = "disabled";
204 };
205
206 usbh1: usb@53f80200 {
207 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
208 reg = <0x53f80200 0x0200>;
209 interrupts = <14>;
210 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
211 dr_mode = "host";
212 status = "disabled";
213 };
214
215 usbh2: usb@53f80400 {
216 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
217 reg = <0x53f80400 0x0200>;
218 interrupts = <16>;
219 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
220 dr_mode = "host";
221 status = "disabled";
222 };
223
224 usbh3: usb@53f80600 {
225 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
226 reg = <0x53f80600 0x0200>;
227 interrupts = <17>;
228 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
229 dr_mode = "host";
230 status = "disabled";
231 };
232
233 gpio1: gpio@53f84000 {
234 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
235 reg = <0x53f84000 0x4000>;
236 interrupts = <50 51>;
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 gpio-ranges = <&iomuxc 0 151 28>;
242 };
243
244 gpio2: gpio@53f88000 {
245 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
246 reg = <0x53f88000 0x4000>;
247 interrupts = <52 53>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
253 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
254 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
255 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
256 };
257
258 gpio3: gpio@53f8c000 {
259 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
260 reg = <0x53f8c000 0x4000>;
261 interrupts = <54 55>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 108 32>;
267 };
268
269 gpio4: gpio@53f90000 {
270 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
271 reg = <0x53f90000 0x4000>;
272 interrupts = <56 57>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
278 <&iomuxc 20 140 11>;
279 };
280
281 wdog1: wdog@53f98000 {
282 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
283 reg = <0x53f98000 0x4000>;
284 interrupts = <58>;
285 clocks = <&clks IMX5_CLK_DUMMY>;
286 };
287
288 gpt: timer@53fa0000 {
289 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
290 reg = <0x53fa0000 0x4000>;
291 interrupts = <39>;
292 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
293 <&clks IMX5_CLK_GPT_HF_GATE>;
294 clock-names = "ipg", "per";
295 };
296
297 iomuxc: iomuxc@53fa8000 {
298 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
299 reg = <0x53fa8000 0x4000>;
300 };
301
302 gpr: iomuxc-gpr@53fa8000 {
303 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
304 reg = <0x53fa8000 0xc>;
305 };
306
307 pwm1: pwm@53fb4000 {
308 #pwm-cells = <2>;
309 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
310 reg = <0x53fb4000 0x4000>;
311 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
312 <&clks IMX5_CLK_PWM1_HF_GATE>;
313 clock-names = "ipg", "per";
314 interrupts = <61>;
315 };
316
317 pwm2: pwm@53fb8000 {
318 #pwm-cells = <2>;
319 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
320 reg = <0x53fb8000 0x4000>;
321 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
322 <&clks IMX5_CLK_PWM2_HF_GATE>;
323 clock-names = "ipg", "per";
324 interrupts = <94>;
325 };
326
327 uart1: serial@53fbc000 {
328 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
329 reg = <0x53fbc000 0x4000>;
330 interrupts = <31>;
331 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
332 <&clks IMX5_CLK_UART1_PER_GATE>;
333 clock-names = "ipg", "per";
334 status = "disabled";
335 };
336
337 uart2: serial@53fc0000 {
338 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
339 reg = <0x53fc0000 0x4000>;
340 interrupts = <32>;
341 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
342 <&clks IMX5_CLK_UART2_PER_GATE>;
343 clock-names = "ipg", "per";
344 status = "disabled";
345 };
346
347 src: src@53fd0000 {
348 compatible = "fsl,imx50-src", "fsl,imx51-src";
349 reg = <0x53fd0000 0x4000>;
350 #reset-cells = <1>;
351 };
352
353 clks: ccm@53fd4000{
354 compatible = "fsl,imx50-ccm";
355 reg = <0x53fd4000 0x4000>;
356 interrupts = <0 71 0x04 0 72 0x04>;
357 #clock-cells = <1>;
358 };
359
360 gpio5: gpio@53fdc000 {
361 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
362 reg = <0x53fdc000 0x4000>;
363 interrupts = <103 104>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
369 };
370
371 gpio6: gpio@53fe0000 {
372 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
373 reg = <0x53fe0000 0x4000>;
374 interrupts = <105 106>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
380 };
381
382 i2c3: i2c@53fec000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
386 reg = <0x53fec000 0x4000>;
387 interrupts = <64>;
388 clocks = <&clks IMX5_CLK_I2C3_GATE>;
389 status = "disabled";
390 };
391
392 uart4: serial@53ff0000 {
393 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
394 reg = <0x53ff0000 0x4000>;
395 interrupts = <13>;
396 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
397 <&clks IMX5_CLK_UART4_PER_GATE>;
398 clock-names = "ipg", "per";
399 status = "disabled";
400 };
401 };
402
403 aips@60000000 { /* AIPS2 */
404 compatible = "fsl,aips-bus", "simple-bus";
405 #address-cells = <1>;
406 #size-cells = <1>;
407 reg = <0x60000000 0x10000000>;
408 ranges;
409
410 uart5: serial@63f90000 {
411 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
412 reg = <0x63f90000 0x4000>;
413 interrupts = <86>;
414 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
415 <&clks IMX5_CLK_UART5_PER_GATE>;
416 clock-names = "ipg", "per";
417 status = "disabled";
418 };
419
420 owire: owire@63fa4000 {
421 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
422 reg = <0x63fa4000 0x4000>;
423 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
424 status = "disabled";
425 };
426
427 ecspi2: ecspi@63fac000 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
431 reg = <0x63fac000 0x4000>;
432 interrupts = <37>;
433 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
434 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
435 clock-names = "ipg", "per";
436 status = "disabled";
437 };
438
439 sdma: sdma@63fb0000 {
440 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
441 reg = <0x63fb0000 0x4000>;
442 interrupts = <6>;
443 clocks = <&clks IMX5_CLK_SDMA_GATE>,
444 <&clks IMX5_CLK_SDMA_GATE>;
445 clock-names = "ipg", "ahb";
446 #dma-cells = <3>;
447 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
448 };
449
450 cspi: cspi@63fc0000 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
454 reg = <0x63fc0000 0x4000>;
455 interrupts = <38>;
456 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
457 <&clks IMX5_CLK_CSPI_IPG_GATE>;
458 clock-names = "ipg", "per";
459 status = "disabled";
460 };
461
462 i2c2: i2c@63fc4000 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
466 reg = <0x63fc4000 0x4000>;
467 interrupts = <63>;
468 clocks = <&clks IMX5_CLK_I2C2_GATE>;
469 status = "disabled";
470 };
471
472 i2c1: i2c@63fc8000 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
476 reg = <0x63fc8000 0x4000>;
477 interrupts = <62>;
478 clocks = <&clks IMX5_CLK_I2C1_GATE>;
479 status = "disabled";
480 };
481
482 ssi1: ssi@63fcc000 {
483 #sound-dai-cells = <0>;
484 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
485 "fsl,imx21-ssi";
486 reg = <0x63fcc000 0x4000>;
487 interrupts = <29>;
488 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
489 dmas = <&sdma 28 0 0>,
490 <&sdma 29 0 0>;
491 dma-names = "rx", "tx";
492 fsl,fifo-depth = <15>;
493 status = "disabled";
494 };
495
496 audmux: audmux@63fd0000 {
497 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
498 reg = <0x63fd0000 0x4000>;
499 status = "disabled";
500 };
501
502 fec: ethernet@63fec000 {
503 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
504 reg = <0x63fec000 0x4000>;
505 interrupts = <87>;
506 clocks = <&clks IMX5_CLK_FEC_GATE>,
507 <&clks IMX5_CLK_FEC_GATE>,
508 <&clks IMX5_CLK_FEC_GATE>;
509 clock-names = "ipg", "ahb", "ptp";
510 status = "disabled";
511 };
512 };
513 };
514};
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "skeleton.dtsi"
15#include "imx50-pinfunc.h"
16#include <dt-bindings/clock/imx5-clock.h>
17
18/ {
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37 cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a8";
40 reg = <0x0>;
41 };
42 };
43
44 tzic: tz-interrupt-controller@0fffc000 {
45 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 reg = <0x0fffc000 0x4000>;
49 };
50
51 clocks {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 ckil {
56 compatible = "fsl,imx-ckil", "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <32768>;
59 };
60
61 ckih1 {
62 compatible = "fsl,imx-ckih1", "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <22579200>;
65 };
66
67 ckih2 {
68 compatible = "fsl,imx-ckih2", "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <0>;
71 };
72
73 osc {
74 compatible = "fsl,imx-osc", "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <24000000>;
77 };
78 };
79
80 soc {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
85 ranges;
86
87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x50000000 0x10000000>;
92 ranges;
93
94 spba@50000000 {
95 compatible = "fsl,spba-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x50000000 0x40000>;
99 ranges;
100
101 esdhc1: esdhc@50004000 {
102 compatible = "fsl,imx50-esdhc";
103 reg = <0x50004000 0x4000>;
104 interrupts = <1>;
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
108 clock-names = "ipg", "ahb", "per";
109 bus-width = <4>;
110 status = "disabled";
111 };
112
113 esdhc2: esdhc@50008000 {
114 compatible = "fsl,imx50-esdhc";
115 reg = <0x50008000 0x4000>;
116 interrupts = <2>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
120 clock-names = "ipg", "ahb", "per";
121 bus-width = <4>;
122 status = "disabled";
123 };
124
125 uart3: serial@5000c000 {
126 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
127 reg = <0x5000c000 0x4000>;
128 interrupts = <33>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
131 clock-names = "ipg", "per";
132 status = "disabled";
133 };
134
135 ecspi1: ecspi@50010000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
139 reg = <0x50010000 0x4000>;
140 interrupts = <36>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
143 clock-names = "ipg", "per";
144 status = "disabled";
145 };
146
147 ssi2: ssi@50014000 {
148 #sound-dai-cells = <0>;
149 compatible = "fsl,imx50-ssi",
150 "fsl,imx51-ssi",
151 "fsl,imx21-ssi";
152 reg = <0x50014000 0x4000>;
153 interrupts = <30>;
154 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
155 dmas = <&sdma 24 1 0>,
156 <&sdma 25 1 0>;
157 dma-names = "rx", "tx";
158 fsl,fifo-depth = <15>;
159 status = "disabled";
160 };
161
162 esdhc3: esdhc@50020000 {
163 compatible = "fsl,imx50-esdhc";
164 reg = <0x50020000 0x4000>;
165 interrupts = <3>;
166 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
169 clock-names = "ipg", "ahb", "per";
170 bus-width = <4>;
171 status = "disabled";
172 };
173
174 esdhc4: esdhc@50024000 {
175 compatible = "fsl,imx50-esdhc";
176 reg = <0x50024000 0x4000>;
177 interrupts = <4>;
178 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
179 <&clks IMX5_CLK_DUMMY>,
180 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
181 clock-names = "ipg", "ahb", "per";
182 bus-width = <4>;
183 status = "disabled";
184 };
185 };
186
187 usbotg: usb@53f80000 {
188 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
189 reg = <0x53f80000 0x0200>;
190 interrupts = <18>;
191 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
192 status = "disabled";
193 };
194
195 usbh1: usb@53f80200 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80200 0x0200>;
198 interrupts = <14>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
200 dr_mode = "host";
201 status = "disabled";
202 };
203
204 usbh2: usb@53f80400 {
205 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
206 reg = <0x53f80400 0x0200>;
207 interrupts = <16>;
208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
209 dr_mode = "host";
210 status = "disabled";
211 };
212
213 usbh3: usb@53f80600 {
214 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
215 reg = <0x53f80600 0x0200>;
216 interrupts = <17>;
217 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
218 dr_mode = "host";
219 status = "disabled";
220 };
221
222 gpio1: gpio@53f84000 {
223 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
224 reg = <0x53f84000 0x4000>;
225 interrupts = <50 51>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 gpio2: gpio@53f88000 {
233 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
234 reg = <0x53f88000 0x4000>;
235 interrupts = <52 53>;
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241
242 gpio3: gpio@53f8c000 {
243 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
244 reg = <0x53f8c000 0x4000>;
245 interrupts = <54 55>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
250 };
251
252 gpio4: gpio@53f90000 {
253 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
254 reg = <0x53f90000 0x4000>;
255 interrupts = <56 57>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 };
261
262 wdog1: wdog@53f98000 {
263 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
264 reg = <0x53f98000 0x4000>;
265 interrupts = <58>;
266 clocks = <&clks IMX5_CLK_DUMMY>;
267 };
268
269 gpt: timer@53fa0000 {
270 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
271 reg = <0x53fa0000 0x4000>;
272 interrupts = <39>;
273 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
274 <&clks IMX5_CLK_GPT_HF_GATE>;
275 clock-names = "ipg", "per";
276 };
277
278 iomuxc: iomuxc@53fa8000 {
279 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
280 reg = <0x53fa8000 0x4000>;
281 };
282
283 gpr: iomuxc-gpr@53fa8000 {
284 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
285 reg = <0x53fa8000 0xc>;
286 };
287
288 pwm1: pwm@53fb4000 {
289 #pwm-cells = <2>;
290 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
291 reg = <0x53fb4000 0x4000>;
292 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
293 <&clks IMX5_CLK_PWM1_HF_GATE>;
294 clock-names = "ipg", "per";
295 interrupts = <61>;
296 };
297
298 pwm2: pwm@53fb8000 {
299 #pwm-cells = <2>;
300 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
301 reg = <0x53fb8000 0x4000>;
302 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
303 <&clks IMX5_CLK_PWM2_HF_GATE>;
304 clock-names = "ipg", "per";
305 interrupts = <94>;
306 };
307
308 uart1: serial@53fbc000 {
309 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
310 reg = <0x53fbc000 0x4000>;
311 interrupts = <31>;
312 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
313 <&clks IMX5_CLK_UART1_PER_GATE>;
314 clock-names = "ipg", "per";
315 status = "disabled";
316 };
317
318 uart2: serial@53fc0000 {
319 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
320 reg = <0x53fc0000 0x4000>;
321 interrupts = <32>;
322 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
323 <&clks IMX5_CLK_UART2_PER_GATE>;
324 clock-names = "ipg", "per";
325 status = "disabled";
326 };
327
328 src: src@53fd0000 {
329 compatible = "fsl,imx50-src", "fsl,imx51-src";
330 reg = <0x53fd0000 0x4000>;
331 #reset-cells = <1>;
332 };
333
334 clks: ccm@53fd4000{
335 compatible = "fsl,imx50-ccm";
336 reg = <0x53fd4000 0x4000>;
337 interrupts = <0 71 0x04 0 72 0x04>;
338 #clock-cells = <1>;
339 };
340
341 gpio5: gpio@53fdc000 {
342 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
343 reg = <0x53fdc000 0x4000>;
344 interrupts = <103 104>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 };
350
351 gpio6: gpio@53fe0000 {
352 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
353 reg = <0x53fe0000 0x4000>;
354 interrupts = <105 106>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 };
360
361 i2c3: i2c@53fec000 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
365 reg = <0x53fec000 0x4000>;
366 interrupts = <64>;
367 clocks = <&clks IMX5_CLK_I2C3_GATE>;
368 status = "disabled";
369 };
370
371 uart4: serial@53ff0000 {
372 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
373 reg = <0x53ff0000 0x4000>;
374 interrupts = <13>;
375 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
376 <&clks IMX5_CLK_UART4_PER_GATE>;
377 clock-names = "ipg", "per";
378 status = "disabled";
379 };
380 };
381
382 aips@60000000 { /* AIPS2 */
383 compatible = "fsl,aips-bus", "simple-bus";
384 #address-cells = <1>;
385 #size-cells = <1>;
386 reg = <0x60000000 0x10000000>;
387 ranges;
388
389 uart5: serial@63f90000 {
390 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
391 reg = <0x63f90000 0x4000>;
392 interrupts = <86>;
393 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
394 <&clks IMX5_CLK_UART5_PER_GATE>;
395 clock-names = "ipg", "per";
396 status = "disabled";
397 };
398
399 owire: owire@63fa4000 {
400 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
401 reg = <0x63fa4000 0x4000>;
402 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
403 status = "disabled";
404 };
405
406 ecspi2: ecspi@63fac000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
410 reg = <0x63fac000 0x4000>;
411 interrupts = <37>;
412 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
413 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
414 clock-names = "ipg", "per";
415 status = "disabled";
416 };
417
418 sdma: sdma@63fb0000 {
419 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
420 reg = <0x63fb0000 0x4000>;
421 interrupts = <6>;
422 clocks = <&clks IMX5_CLK_SDMA_GATE>,
423 <&clks IMX5_CLK_SDMA_GATE>;
424 clock-names = "ipg", "ahb";
425 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
426 };
427
428 cspi: cspi@63fc0000 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
432 reg = <0x63fc0000 0x4000>;
433 interrupts = <38>;
434 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
435 <&clks IMX5_CLK_CSPI_IPG_GATE>;
436 clock-names = "ipg", "per";
437 status = "disabled";
438 };
439
440 i2c2: i2c@63fc4000 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
444 reg = <0x63fc4000 0x4000>;
445 interrupts = <63>;
446 clocks = <&clks IMX5_CLK_I2C2_GATE>;
447 status = "disabled";
448 };
449
450 i2c1: i2c@63fc8000 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
454 reg = <0x63fc8000 0x4000>;
455 interrupts = <62>;
456 clocks = <&clks IMX5_CLK_I2C1_GATE>;
457 status = "disabled";
458 };
459
460 ssi1: ssi@63fcc000 {
461 #sound-dai-cells = <0>;
462 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
463 "fsl,imx21-ssi";
464 reg = <0x63fcc000 0x4000>;
465 interrupts = <29>;
466 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
467 dmas = <&sdma 28 0 0>,
468 <&sdma 29 0 0>;
469 dma-names = "rx", "tx";
470 fsl,fifo-depth = <15>;
471 status = "disabled";
472 };
473
474 audmux: audmux@63fd0000 {
475 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
476 reg = <0x63fd0000 0x4000>;
477 status = "disabled";
478 };
479
480 fec: ethernet@63fec000 {
481 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
482 reg = <0x63fec000 0x4000>;
483 interrupts = <87>;
484 clocks = <&clks IMX5_CLK_FEC_GATE>,
485 <&clks IMX5_CLK_FEC_GATE>,
486 <&clks IMX5_CLK_FEC_GATE>;
487 clock-names = "ipg", "ahb", "ptp";
488 status = "disabled";
489 };
490 };
491 };
492};