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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4-cpu-thermal.dtsi"
18#include "exynos-syscon-restart.dtsi"
19#include <dt-bindings/clock/exynos3250.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21#include <dt-bindings/interrupt-controller/irq.h>
22
23/ {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 mshc0 = &mshc_0;
33 mshc1 = &mshc_1;
34 mshc2 = &mshc_2;
35 spi0 = &spi_0;
36 spi1 = &spi_1;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 serial0 = &serial_0;
46 serial1 = &serial_1;
47 serial2 = &serial_2;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0>;
58 clock-frequency = <1000000000>;
59 clocks = <&cmu CLK_ARM_CLK>;
60 clock-names = "cpu";
61 #cooling-cells = <2>;
62
63 operating-points = <
64 1000000 1150000
65 900000 1112500
66 800000 1075000
67 700000 1037500
68 600000 1000000
69 500000 962500
70 400000 925000
71 300000 887500
72 200000 850000
73 100000 850000
74 >;
75 };
76
77 cpu1: cpu@1 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <1>;
81 clock-frequency = <1000000000>;
82 };
83 };
84
85 soc: soc {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90
91 fixed-rate-clocks {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 xusbxti: clock@0 {
96 compatible = "fixed-clock";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0>;
100 clock-frequency = <0>;
101 #clock-cells = <0>;
102 clock-output-names = "xusbxti";
103 };
104
105 xxti: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 clock-frequency = <0>;
109 #clock-cells = <0>;
110 clock-output-names = "xxti";
111 };
112
113 xtcxo: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
118 clock-output-names = "xtcxo";
119 };
120 };
121
122 sysram@2020000 {
123 compatible = "mmio-sram";
124 reg = <0x02020000 0x40000>;
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0 0x02020000 0x40000>;
128
129 smp-sysram@0 {
130 compatible = "samsung,exynos4210-sysram";
131 reg = <0x0 0x1000>;
132 };
133
134 smp-sysram@3f000 {
135 compatible = "samsung,exynos4210-sysram-ns";
136 reg = <0x3f000 0x1000>;
137 };
138 };
139
140 chipid@10000000 {
141 compatible = "samsung,exynos4210-chipid";
142 reg = <0x10000000 0x100>;
143 };
144
145 sys_reg: syscon@10010000 {
146 compatible = "samsung,exynos3-sysreg", "syscon";
147 reg = <0x10010000 0x400>;
148 };
149
150 pmu_system_controller: system-controller@10020000 {
151 compatible = "samsung,exynos3250-pmu", "syscon";
152 reg = <0x10020000 0x4000>;
153 interrupt-controller;
154 #interrupt-cells = <3>;
155 interrupt-parent = <&gic>;
156 };
157
158 mipi_phy: video-phy {
159 compatible = "samsung,s5pv210-mipi-video-phy";
160 #phy-cells = <1>;
161 syscon = <&pmu_system_controller>;
162 };
163
164 pd_cam: power-domain@10023c00 {
165 compatible = "samsung,exynos4210-pd";
166 reg = <0x10023C00 0x20>;
167 #power-domain-cells = <0>;
168 label = "CAM";
169 };
170
171 pd_mfc: power-domain@10023c40 {
172 compatible = "samsung,exynos4210-pd";
173 reg = <0x10023C40 0x20>;
174 #power-domain-cells = <0>;
175 label = "MFC";
176 };
177
178 pd_g3d: power-domain@10023c60 {
179 compatible = "samsung,exynos4210-pd";
180 reg = <0x10023C60 0x20>;
181 #power-domain-cells = <0>;
182 label = "G3D";
183 };
184
185 pd_lcd0: power-domain@10023c80 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10023C80 0x20>;
188 #power-domain-cells = <0>;
189 label = "LCD0";
190 };
191
192 pd_isp: power-domain@10023ca0 {
193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10023CA0 0x20>;
195 #power-domain-cells = <0>;
196 label = "ISP";
197 };
198
199 cmu: clock-controller@10030000 {
200 compatible = "samsung,exynos3250-cmu";
201 reg = <0x10030000 0x20000>;
202 #clock-cells = <1>;
203 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
204 <&cmu CLK_MOUT_ACLK_266_SUB>;
205 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
206 <&cmu CLK_FIN_PLL>;
207 };
208
209 cmu_dmc: clock-controller@105c0000 {
210 compatible = "samsung,exynos3250-cmu-dmc";
211 reg = <0x105C0000 0x2000>;
212 #clock-cells = <1>;
213 };
214
215 rtc: rtc@10070000 {
216 compatible = "samsung,s3c6410-rtc";
217 reg = <0x10070000 0x100>;
218 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-parent = <&pmu_system_controller>;
221 status = "disabled";
222 };
223
224 tmu: tmu@100c0000 {
225 compatible = "samsung,exynos3250-tmu";
226 reg = <0x100C0000 0x100>;
227 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cmu CLK_TMU_APBIF>;
229 clock-names = "tmu_apbif";
230 #include "exynos4412-tmu-sensor-conf.dtsi"
231 status = "disabled";
232 };
233
234 gic: interrupt-controller@10481000 {
235 compatible = "arm,cortex-a15-gic";
236 #interrupt-cells = <3>;
237 interrupt-controller;
238 reg = <0x10481000 0x1000>,
239 <0x10482000 0x2000>,
240 <0x10484000 0x2000>,
241 <0x10486000 0x2000>;
242 interrupts = <GIC_PPI 9
243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
244 };
245
246 mct@10050000 {
247 compatible = "samsung,exynos4210-mct";
248 reg = <0x10050000 0x800>;
249 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
258 clock-names = "fin_pll", "mct";
259 };
260
261 pinctrl_1: pinctrl@11000000 {
262 compatible = "samsung,exynos3250-pinctrl";
263 reg = <0x11000000 0x1000>;
264 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
265
266 wakeup-interrupt-controller {
267 compatible = "samsung,exynos4210-wakeup-eint";
268 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
269 };
270 };
271
272 pinctrl_0: pinctrl@11400000 {
273 compatible = "samsung,exynos3250-pinctrl";
274 reg = <0x11400000 0x1000>;
275 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
276 };
277
278 jpeg: codec@11830000 {
279 compatible = "samsung,exynos3250-jpeg";
280 reg = <0x11830000 0x1000>;
281 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
283 clock-names = "jpeg", "sclk";
284 power-domains = <&pd_cam>;
285 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
286 assigned-clock-rates = <0>, <150000000>;
287 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
288 iommus = <&sysmmu_jpeg>;
289 status = "disabled";
290 };
291
292 sysmmu_jpeg: sysmmu@11a60000 {
293 compatible = "samsung,exynos-sysmmu";
294 reg = <0x11a60000 0x1000>;
295 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
297 clock-names = "sysmmu", "master";
298 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
299 power-domains = <&pd_cam>;
300 #iommu-cells = <0>;
301 };
302
303 fimd: fimd@11c00000 {
304 compatible = "samsung,exynos3250-fimd";
305 reg = <0x11c00000 0x30000>;
306 interrupt-names = "fifo", "vsync", "lcd_sys";
307 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
311 clock-names = "sclk_fimd", "fimd";
312 power-domains = <&pd_lcd0>;
313 iommus = <&sysmmu_fimd0>;
314 samsung,sysreg = <&sys_reg>;
315 status = "disabled";
316 };
317
318 dsi_0: dsi@11c80000 {
319 compatible = "samsung,exynos3250-mipi-dsi";
320 reg = <0x11C80000 0x10000>;
321 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
322 samsung,phy-type = <0>;
323 power-domains = <&pd_lcd0>;
324 phys = <&mipi_phy 1>;
325 phy-names = "dsim";
326 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
327 clock-names = "bus_clk", "pll_clk";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 status = "disabled";
331 };
332
333 sysmmu_fimd0: sysmmu@11e20000 {
334 compatible = "samsung,exynos-sysmmu";
335 reg = <0x11e20000 0x1000>;
336 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "sysmmu", "master";
339 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
340 power-domains = <&pd_lcd0>;
341 #iommu-cells = <0>;
342 };
343
344 hsotg: hsotg@12480000 {
345 compatible = "snps,dwc2";
346 reg = <0x12480000 0x20000>;
347 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cmu CLK_USBOTG>;
349 clock-names = "otg";
350 phys = <&exynos_usbphy 0>;
351 phy-names = "usb2-phy";
352 status = "disabled";
353 };
354
355 mshc_0: mshc@12510000 {
356 compatible = "samsung,exynos5420-dw-mshc";
357 reg = <0x12510000 0x1000>;
358 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
360 clock-names = "biu", "ciu";
361 fifo-depth = <0x80>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 status = "disabled";
365 };
366
367 mshc_1: mshc@12520000 {
368 compatible = "samsung,exynos5420-dw-mshc";
369 reg = <0x12520000 0x1000>;
370 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
372 clock-names = "biu", "ciu";
373 fifo-depth = <0x80>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 mshc_2: mshc@12530000 {
380 compatible = "samsung,exynos5250-dw-mshc";
381 reg = <0x12530000 0x1000>;
382 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
384 clock-names = "biu", "ciu";
385 fifo-depth = <0x80>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 exynos_usbphy: exynos-usbphy@125b0000 {
392 compatible = "samsung,exynos3250-usb2-phy";
393 reg = <0x125B0000 0x100>;
394 samsung,pmureg-phandle = <&pmu_system_controller>;
395 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
396 clock-names = "phy", "ref";
397 #phy-cells = <1>;
398 status = "disabled";
399 };
400
401 amba {
402 compatible = "simple-bus";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges;
406
407 pdma0: pdma@12680000 {
408 compatible = "arm,pl330", "arm,primecell";
409 reg = <0x12680000 0x1000>;
410 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&cmu CLK_PDMA0>;
412 clock-names = "apb_pclk";
413 #dma-cells = <1>;
414 #dma-channels = <8>;
415 #dma-requests = <32>;
416 };
417
418 pdma1: pdma@12690000 {
419 compatible = "arm,pl330", "arm,primecell";
420 reg = <0x12690000 0x1000>;
421 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cmu CLK_PDMA1>;
423 clock-names = "apb_pclk";
424 #dma-cells = <1>;
425 #dma-channels = <8>;
426 #dma-requests = <32>;
427 };
428 };
429
430 adc: adc@126c0000 {
431 compatible = "samsung,exynos3250-adc",
432 "samsung,exynos-adc-v2";
433 reg = <0x126C0000 0x100>;
434 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
435 clock-names = "adc", "sclk";
436 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
437 #io-channel-cells = <1>;
438 io-channel-ranges;
439 samsung,syscon-phandle = <&pmu_system_controller>;
440 status = "disabled";
441 };
442
443 mfc: codec@13400000 {
444 compatible = "samsung,mfc-v7";
445 reg = <0x13400000 0x10000>;
446 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
447 clock-names = "mfc", "sclk_mfc";
448 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
449 power-domains = <&pd_mfc>;
450 iommus = <&sysmmu_mfc>;
451 };
452
453 sysmmu_mfc: sysmmu@13620000 {
454 compatible = "samsung,exynos-sysmmu";
455 reg = <0x13620000 0x1000>;
456 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
458 clock-names = "sysmmu", "master";
459 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
460 power-domains = <&pd_mfc>;
461 #iommu-cells = <0>;
462 };
463
464 serial_0: serial@13800000 {
465 compatible = "samsung,exynos4210-uart";
466 reg = <0x13800000 0x100>;
467 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
469 clock-names = "uart", "clk_uart_baud0";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart0_data &uart0_fctl>;
472 status = "disabled";
473 };
474
475 serial_1: serial@13810000 {
476 compatible = "samsung,exynos4210-uart";
477 reg = <0x13810000 0x100>;
478 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
480 clock-names = "uart", "clk_uart_baud0";
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart1_data>;
483 status = "disabled";
484 };
485
486 serial_2: serial@13820000 {
487 compatible = "samsung,exynos4210-uart";
488 reg = <0x13820000 0x100>;
489 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
491 clock-names = "uart", "clk_uart_baud0";
492 pinctrl-names = "default";
493 pinctrl-0 = <&uart2_data>;
494 status = "disabled";
495 };
496
497 i2c_0: i2c@13860000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "samsung,s3c2440-i2c";
501 reg = <0x13860000 0x100>;
502 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cmu CLK_I2C0>;
504 clock-names = "i2c";
505 pinctrl-names = "default";
506 pinctrl-0 = <&i2c0_bus>;
507 status = "disabled";
508 };
509
510 i2c_1: i2c@13870000 {
511 #address-cells = <1>;
512 #size-cells = <0>;
513 compatible = "samsung,s3c2440-i2c";
514 reg = <0x13870000 0x100>;
515 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cmu CLK_I2C1>;
517 clock-names = "i2c";
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c1_bus>;
520 status = "disabled";
521 };
522
523 i2c_2: i2c@13880000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "samsung,s3c2440-i2c";
527 reg = <0x13880000 0x100>;
528 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cmu CLK_I2C2>;
530 clock-names = "i2c";
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c2_bus>;
533 status = "disabled";
534 };
535
536 i2c_3: i2c@13890000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "samsung,s3c2440-i2c";
540 reg = <0x13890000 0x100>;
541 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cmu CLK_I2C3>;
543 clock-names = "i2c";
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c3_bus>;
546 status = "disabled";
547 };
548
549 i2c_4: i2c@138a0000 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "samsung,s3c2440-i2c";
553 reg = <0x138A0000 0x100>;
554 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cmu CLK_I2C4>;
556 clock-names = "i2c";
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c4_bus>;
559 status = "disabled";
560 };
561
562 i2c_5: i2c@138b0000 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "samsung,s3c2440-i2c";
566 reg = <0x138B0000 0x100>;
567 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cmu CLK_I2C5>;
569 clock-names = "i2c";
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c5_bus>;
572 status = "disabled";
573 };
574
575 i2c_6: i2c@138c0000 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 compatible = "samsung,s3c2440-i2c";
579 reg = <0x138C0000 0x100>;
580 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cmu CLK_I2C6>;
582 clock-names = "i2c";
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c6_bus>;
585 status = "disabled";
586 };
587
588 i2c_7: i2c@138d0000 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "samsung,s3c2440-i2c";
592 reg = <0x138D0000 0x100>;
593 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cmu CLK_I2C7>;
595 clock-names = "i2c";
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c7_bus>;
598 status = "disabled";
599 };
600
601 spi_0: spi@13920000 {
602 compatible = "samsung,exynos4210-spi";
603 reg = <0x13920000 0x100>;
604 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
605 dmas = <&pdma0 7>, <&pdma0 6>;
606 dma-names = "tx", "rx";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
610 clock-names = "spi", "spi_busclk0";
611 samsung,spi-src-clk = <0>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&spi0_bus>;
614 status = "disabled";
615 };
616
617 spi_1: spi@13930000 {
618 compatible = "samsung,exynos4210-spi";
619 reg = <0x13930000 0x100>;
620 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
621 dmas = <&pdma1 7>, <&pdma1 6>;
622 dma-names = "tx", "rx";
623 #address-cells = <1>;
624 #size-cells = <0>;
625 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
626 clock-names = "spi", "spi_busclk0";
627 samsung,spi-src-clk = <0>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&spi1_bus>;
630 status = "disabled";
631 };
632
633 i2s2: i2s@13970000 {
634 compatible = "samsung,s3c6410-i2s";
635 reg = <0x13970000 0x100>;
636 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
638 clock-names = "iis", "i2s_opclk0";
639 dmas = <&pdma0 14>, <&pdma0 13>;
640 dma-names = "tx", "rx";
641 pinctrl-0 = <&i2s2_bus>;
642 pinctrl-names = "default";
643 status = "disabled";
644 };
645
646 pwm: pwm@139d0000 {
647 compatible = "samsung,exynos4210-pwm";
648 reg = <0x139D0000 0x1000>;
649 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
654 #pwm-cells = <3>;
655 status = "disabled";
656 };
657
658 pmu {
659 compatible = "arm,cortex-a7-pmu";
660 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
662 };
663
664 ppmu_dmc0: ppmu_dmc0@106a0000 {
665 compatible = "samsung,exynos-ppmu";
666 reg = <0x106a0000 0x2000>;
667 status = "disabled";
668 };
669
670 ppmu_dmc1: ppmu_dmc1@106b0000 {
671 compatible = "samsung,exynos-ppmu";
672 reg = <0x106b0000 0x2000>;
673 status = "disabled";
674 };
675
676 ppmu_cpu: ppmu_cpu@106c0000 {
677 compatible = "samsung,exynos-ppmu";
678 reg = <0x106c0000 0x2000>;
679 status = "disabled";
680 };
681
682 ppmu_rightbus: ppmu_rightbus@112a0000 {
683 compatible = "samsung,exynos-ppmu";
684 reg = <0x112a0000 0x2000>;
685 clocks = <&cmu CLK_PPMURIGHT>;
686 clock-names = "ppmu";
687 status = "disabled";
688 };
689
690 ppmu_leftbus: ppmu_leftbus0@116a0000 {
691 compatible = "samsung,exynos-ppmu";
692 reg = <0x116a0000 0x2000>;
693 clocks = <&cmu CLK_PPMULEFT>;
694 clock-names = "ppmu";
695 status = "disabled";
696 };
697
698 ppmu_camif: ppmu_camif@11ac0000 {
699 compatible = "samsung,exynos-ppmu";
700 reg = <0x11ac0000 0x2000>;
701 clocks = <&cmu CLK_PPMUCAMIF>;
702 clock-names = "ppmu";
703 status = "disabled";
704 };
705
706 ppmu_lcd0: ppmu_lcd0@11e40000 {
707 compatible = "samsung,exynos-ppmu";
708 reg = <0x11e40000 0x2000>;
709 clocks = <&cmu CLK_PPMULCD0>;
710 clock-names = "ppmu";
711 status = "disabled";
712 };
713
714 ppmu_fsys: ppmu_fsys@12630000 {
715 compatible = "samsung,exynos-ppmu";
716 reg = <0x12630000 0x2000>;
717 clocks = <&cmu CLK_PPMUFILE>;
718 clock-names = "ppmu";
719 status = "disabled";
720 };
721
722 ppmu_g3d: ppmu_g3d@13220000 {
723 compatible = "samsung,exynos-ppmu";
724 reg = <0x13220000 0x2000>;
725 clocks = <&cmu CLK_PPMUG3D>;
726 clock-names = "ppmu";
727 status = "disabled";
728 };
729
730 ppmu_mfc: ppmu_mfc@13660000 {
731 compatible = "samsung,exynos-ppmu";
732 reg = <0x13660000 0x2000>;
733 clocks = <&cmu CLK_PPMUMFC_L>;
734 clock-names = "ppmu";
735 status = "disabled";
736 };
737
738 bus_dmc: bus_dmc {
739 compatible = "samsung,exynos-bus";
740 clocks = <&cmu_dmc CLK_DIV_DMC>;
741 clock-names = "bus";
742 operating-points-v2 = <&bus_dmc_opp_table>;
743 status = "disabled";
744 };
745
746 bus_dmc_opp_table: opp_table1 {
747 compatible = "operating-points-v2";
748 opp-shared;
749
750 opp-50000000 {
751 opp-hz = /bits/ 64 <50000000>;
752 opp-microvolt = <800000>;
753 };
754 opp-100000000 {
755 opp-hz = /bits/ 64 <100000000>;
756 opp-microvolt = <800000>;
757 };
758 opp-134000000 {
759 opp-hz = /bits/ 64 <134000000>;
760 opp-microvolt = <800000>;
761 };
762 opp-200000000 {
763 opp-hz = /bits/ 64 <200000000>;
764 opp-microvolt = <825000>;
765 };
766 opp-400000000 {
767 opp-hz = /bits/ 64 <400000000>;
768 opp-microvolt = <875000>;
769 };
770 };
771
772 bus_leftbus: bus_leftbus {
773 compatible = "samsung,exynos-bus";
774 clocks = <&cmu CLK_DIV_GDL>;
775 clock-names = "bus";
776 operating-points-v2 = <&bus_leftbus_opp_table>;
777 status = "disabled";
778 };
779
780 bus_rightbus: bus_rightbus {
781 compatible = "samsung,exynos-bus";
782 clocks = <&cmu CLK_DIV_GDR>;
783 clock-names = "bus";
784 operating-points-v2 = <&bus_leftbus_opp_table>;
785 status = "disabled";
786 };
787
788 bus_lcd0: bus_lcd0 {
789 compatible = "samsung,exynos-bus";
790 clocks = <&cmu CLK_DIV_ACLK_160>;
791 clock-names = "bus";
792 operating-points-v2 = <&bus_leftbus_opp_table>;
793 status = "disabled";
794 };
795
796 bus_fsys: bus_fsys {
797 compatible = "samsung,exynos-bus";
798 clocks = <&cmu CLK_DIV_ACLK_200>;
799 clock-names = "bus";
800 operating-points-v2 = <&bus_leftbus_opp_table>;
801 status = "disabled";
802 };
803
804 bus_mcuisp: bus_mcuisp {
805 compatible = "samsung,exynos-bus";
806 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
807 clock-names = "bus";
808 operating-points-v2 = <&bus_mcuisp_opp_table>;
809 status = "disabled";
810 };
811
812 bus_isp: bus_isp {
813 compatible = "samsung,exynos-bus";
814 clocks = <&cmu CLK_DIV_ACLK_266>;
815 clock-names = "bus";
816 operating-points-v2 = <&bus_isp_opp_table>;
817 status = "disabled";
818 };
819
820 bus_peril: bus_peril {
821 compatible = "samsung,exynos-bus";
822 clocks = <&cmu CLK_DIV_ACLK_100>;
823 clock-names = "bus";
824 operating-points-v2 = <&bus_peril_opp_table>;
825 status = "disabled";
826 };
827
828 bus_mfc: bus_mfc {
829 compatible = "samsung,exynos-bus";
830 clocks = <&cmu CLK_SCLK_MFC>;
831 clock-names = "bus";
832 operating-points-v2 = <&bus_leftbus_opp_table>;
833 status = "disabled";
834 };
835
836 bus_leftbus_opp_table: opp_table2 {
837 compatible = "operating-points-v2";
838 opp-shared;
839
840 opp-50000000 {
841 opp-hz = /bits/ 64 <50000000>;
842 opp-microvolt = <900000>;
843 };
844 opp-80000000 {
845 opp-hz = /bits/ 64 <80000000>;
846 opp-microvolt = <900000>;
847 };
848 opp-100000000 {
849 opp-hz = /bits/ 64 <100000000>;
850 opp-microvolt = <1000000>;
851 };
852 opp-134000000 {
853 opp-hz = /bits/ 64 <134000000>;
854 opp-microvolt = <1000000>;
855 };
856 opp-200000000 {
857 opp-hz = /bits/ 64 <200000000>;
858 opp-microvolt = <1000000>;
859 };
860 };
861
862 bus_mcuisp_opp_table: opp_table3 {
863 compatible = "operating-points-v2";
864 opp-shared;
865
866 opp-50000000 {
867 opp-hz = /bits/ 64 <50000000>;
868 };
869 opp-80000000 {
870 opp-hz = /bits/ 64 <80000000>;
871 };
872 opp-100000000 {
873 opp-hz = /bits/ 64 <100000000>;
874 };
875 opp-200000000 {
876 opp-hz = /bits/ 64 <200000000>;
877 };
878 opp-400000000 {
879 opp-hz = /bits/ 64 <400000000>;
880 };
881 };
882
883 bus_isp_opp_table: opp_table4 {
884 compatible = "operating-points-v2";
885 opp-shared;
886
887 opp-50000000 {
888 opp-hz = /bits/ 64 <50000000>;
889 };
890 opp-80000000 {
891 opp-hz = /bits/ 64 <80000000>;
892 };
893 opp-100000000 {
894 opp-hz = /bits/ 64 <100000000>;
895 };
896 opp-200000000 {
897 opp-hz = /bits/ 64 <200000000>;
898 };
899 opp-300000000 {
900 opp-hz = /bits/ 64 <300000000>;
901 };
902 };
903
904 bus_peril_opp_table: opp_table5 {
905 compatible = "operating-points-v2";
906 opp-shared;
907
908 opp-50000000 {
909 opp-hz = /bits/ 64 <50000000>;
910 };
911 opp-80000000 {
912 opp-hz = /bits/ 64 <80000000>;
913 };
914 opp-100000000 {
915 opp-hz = /bits/ 64 <100000000>;
916 };
917 };
918 };
919};
920
921#include "exynos3250-pinctrl.dtsi"
1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
21#include "exynos4-cpu-thermal.dtsi"
22#include "exynos-syscon-restart.dtsi"
23#include <dt-bindings/clock/exynos3250.h>
24
25/ {
26 compatible = "samsung,exynos3250";
27 interrupt-parent = <&gic>;
28
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 mshc0 = &mshc_0;
33 mshc1 = &mshc_1;
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 serial0 = &serial_0;
45 serial1 = &serial_1;
46 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0>;
56 clock-frequency = <1000000000>;
57 clocks = <&cmu CLK_ARM_CLK>;
58 clock-names = "cpu";
59 #cooling-cells = <2>;
60
61 operating-points = <
62 1000000 1150000
63 900000 1112500
64 800000 1075000
65 700000 1037500
66 600000 1000000
67 500000 962500
68 400000 925000
69 300000 887500
70 200000 850000
71 100000 850000
72 >;
73 };
74
75 cpu1: cpu@1 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a7";
78 reg = <1>;
79 clock-frequency = <1000000000>;
80 };
81 };
82
83 soc: soc {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88
89 fixed-rate-clocks {
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 xusbxti: clock@0 {
94 compatible = "fixed-clock";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <0>;
98 clock-frequency = <0>;
99 #clock-cells = <0>;
100 clock-output-names = "xusbxti";
101 };
102
103 xxti: clock@1 {
104 compatible = "fixed-clock";
105 reg = <1>;
106 clock-frequency = <0>;
107 #clock-cells = <0>;
108 clock-output-names = "xxti";
109 };
110
111 xtcxo: clock@2 {
112 compatible = "fixed-clock";
113 reg = <2>;
114 clock-frequency = <0>;
115 #clock-cells = <0>;
116 clock-output-names = "xtcxo";
117 };
118 };
119
120 sysram@02020000 {
121 compatible = "mmio-sram";
122 reg = <0x02020000 0x40000>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x02020000 0x40000>;
126
127 smp-sysram@0 {
128 compatible = "samsung,exynos4210-sysram";
129 reg = <0x0 0x1000>;
130 };
131
132 smp-sysram@3f000 {
133 compatible = "samsung,exynos4210-sysram-ns";
134 reg = <0x3f000 0x1000>;
135 };
136 };
137
138 chipid@10000000 {
139 compatible = "samsung,exynos4210-chipid";
140 reg = <0x10000000 0x100>;
141 };
142
143 sys_reg: syscon@10010000 {
144 compatible = "samsung,exynos3-sysreg", "syscon";
145 reg = <0x10010000 0x400>;
146 };
147
148 pmu_system_controller: system-controller@10020000 {
149 compatible = "samsung,exynos3250-pmu", "syscon";
150 reg = <0x10020000 0x4000>;
151 interrupt-controller;
152 #interrupt-cells = <3>;
153 interrupt-parent = <&gic>;
154 };
155
156 mipi_phy: video-phy@10020710 {
157 compatible = "samsung,s5pv210-mipi-video-phy";
158 #phy-cells = <1>;
159 syscon = <&pmu_system_controller>;
160 };
161
162 pd_cam: cam-power-domain@10023C00 {
163 compatible = "samsung,exynos4210-pd";
164 reg = <0x10023C00 0x20>;
165 #power-domain-cells = <0>;
166 };
167
168 pd_mfc: mfc-power-domain@10023C40 {
169 compatible = "samsung,exynos4210-pd";
170 reg = <0x10023C40 0x20>;
171 #power-domain-cells = <0>;
172 };
173
174 pd_g3d: g3d-power-domain@10023C60 {
175 compatible = "samsung,exynos4210-pd";
176 reg = <0x10023C60 0x20>;
177 #power-domain-cells = <0>;
178 };
179
180 pd_lcd0: lcd0-power-domain@10023C80 {
181 compatible = "samsung,exynos4210-pd";
182 reg = <0x10023C80 0x20>;
183 #power-domain-cells = <0>;
184 };
185
186 pd_isp: isp-power-domain@10023CA0 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023CA0 0x20>;
189 #power-domain-cells = <0>;
190 };
191
192 cmu: clock-controller@10030000 {
193 compatible = "samsung,exynos3250-cmu";
194 reg = <0x10030000 0x20000>;
195 #clock-cells = <1>;
196 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
197 <&cmu CLK_MOUT_ACLK_266_SUB>;
198 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
199 <&cmu CLK_FIN_PLL>;
200 };
201
202 cmu_dmc: clock-controller@105C0000 {
203 compatible = "samsung,exynos3250-cmu-dmc";
204 reg = <0x105C0000 0x2000>;
205 #clock-cells = <1>;
206 };
207
208 rtc: rtc@10070000 {
209 compatible = "samsung,s3c6410-rtc";
210 reg = <0x10070000 0x100>;
211 interrupts = <0 73 0>, <0 74 0>;
212 interrupt-parent = <&pmu_system_controller>;
213 status = "disabled";
214 };
215
216 tmu: tmu@100C0000 {
217 compatible = "samsung,exynos3250-tmu";
218 reg = <0x100C0000 0x100>;
219 interrupts = <0 216 0>;
220 clocks = <&cmu CLK_TMU_APBIF>;
221 clock-names = "tmu_apbif";
222 #include "exynos4412-tmu-sensor-conf.dtsi"
223 status = "disabled";
224 };
225
226 gic: interrupt-controller@10481000 {
227 compatible = "arm,cortex-a15-gic";
228 #interrupt-cells = <3>;
229 interrupt-controller;
230 reg = <0x10481000 0x1000>,
231 <0x10482000 0x1000>,
232 <0x10484000 0x2000>,
233 <0x10486000 0x2000>;
234 interrupts = <1 9 0xf04>;
235 };
236
237 mct@10050000 {
238 compatible = "samsung,exynos4210-mct";
239 reg = <0x10050000 0x800>;
240 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
241 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
242 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
243 clock-names = "fin_pll", "mct";
244 };
245
246 pinctrl_1: pinctrl@11000000 {
247 compatible = "samsung,exynos3250-pinctrl";
248 reg = <0x11000000 0x1000>;
249 interrupts = <0 225 0>;
250
251 wakeup-interrupt-controller {
252 compatible = "samsung,exynos4210-wakeup-eint";
253 interrupts = <0 48 0>;
254 };
255 };
256
257 pinctrl_0: pinctrl@11400000 {
258 compatible = "samsung,exynos3250-pinctrl";
259 reg = <0x11400000 0x1000>;
260 interrupts = <0 240 0>;
261 };
262
263 jpeg: codec@11830000 {
264 compatible = "samsung,exynos3250-jpeg";
265 reg = <0x11830000 0x1000>;
266 interrupts = <0 171 0>;
267 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
268 clock-names = "jpeg", "sclk";
269 power-domains = <&pd_cam>;
270 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
271 assigned-clock-rates = <0>, <150000000>;
272 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
273 iommus = <&sysmmu_jpeg>;
274 status = "disabled";
275 };
276
277 sysmmu_jpeg: sysmmu@11A60000 {
278 compatible = "samsung,exynos-sysmmu";
279 reg = <0x11a60000 0x1000>;
280 interrupts = <0 156 0>, <0 161 0>;
281 clock-names = "sysmmu", "master";
282 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
283 power-domains = <&pd_cam>;
284 #iommu-cells = <0>;
285 };
286
287 fimd: fimd@11c00000 {
288 compatible = "samsung,exynos3250-fimd";
289 reg = <0x11c00000 0x30000>;
290 interrupt-names = "fifo", "vsync", "lcd_sys";
291 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
292 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
293 clock-names = "sclk_fimd", "fimd";
294 power-domains = <&pd_lcd0>;
295 iommus = <&sysmmu_fimd0>;
296 samsung,sysreg = <&sys_reg>;
297 status = "disabled";
298 };
299
300 dsi_0: dsi@11C80000 {
301 compatible = "samsung,exynos3250-mipi-dsi";
302 reg = <0x11C80000 0x10000>;
303 interrupts = <0 83 0>;
304 samsung,phy-type = <0>;
305 power-domains = <&pd_lcd0>;
306 phys = <&mipi_phy 1>;
307 phy-names = "dsim";
308 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
309 clock-names = "bus_clk", "pll_clk";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 sysmmu_fimd0: sysmmu@11E20000 {
316 compatible = "samsung,exynos-sysmmu";
317 reg = <0x11e20000 0x1000>;
318 interrupts = <0 80 0>, <0 81 0>;
319 clock-names = "sysmmu", "master";
320 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
321 power-domains = <&pd_lcd0>;
322 #iommu-cells = <0>;
323 };
324
325 hsotg: hsotg@12480000 {
326 compatible = "snps,dwc2";
327 reg = <0x12480000 0x20000>;
328 interrupts = <0 141 0>;
329 clocks = <&cmu CLK_USBOTG>;
330 clock-names = "otg";
331 phys = <&exynos_usbphy 0>;
332 phy-names = "usb2-phy";
333 status = "disabled";
334 };
335
336 mshc_0: mshc@12510000 {
337 compatible = "samsung,exynos5420-dw-mshc";
338 reg = <0x12510000 0x1000>;
339 interrupts = <0 142 0>;
340 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
341 clock-names = "biu", "ciu";
342 fifo-depth = <0x80>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 mshc_1: mshc@12520000 {
349 compatible = "samsung,exynos5420-dw-mshc";
350 reg = <0x12520000 0x1000>;
351 interrupts = <0 143 0>;
352 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
353 clock-names = "biu", "ciu";
354 fifo-depth = <0x80>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 status = "disabled";
358 };
359
360 exynos_usbphy: exynos-usbphy@125B0000 {
361 compatible = "samsung,exynos3250-usb2-phy";
362 reg = <0x125B0000 0x100>;
363 samsung,pmureg-phandle = <&pmu_system_controller>;
364 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
365 clock-names = "phy", "ref";
366 #phy-cells = <1>;
367 status = "disabled";
368 };
369
370 amba {
371 compatible = "simple-bus";
372 #address-cells = <1>;
373 #size-cells = <1>;
374 ranges;
375
376 pdma0: pdma@12680000 {
377 compatible = "arm,pl330", "arm,primecell";
378 reg = <0x12680000 0x1000>;
379 interrupts = <0 138 0>;
380 clocks = <&cmu CLK_PDMA0>;
381 clock-names = "apb_pclk";
382 #dma-cells = <1>;
383 #dma-channels = <8>;
384 #dma-requests = <32>;
385 };
386
387 pdma1: pdma@12690000 {
388 compatible = "arm,pl330", "arm,primecell";
389 reg = <0x12690000 0x1000>;
390 interrupts = <0 139 0>;
391 clocks = <&cmu CLK_PDMA1>;
392 clock-names = "apb_pclk";
393 #dma-cells = <1>;
394 #dma-channels = <8>;
395 #dma-requests = <32>;
396 };
397 };
398
399 adc: adc@126C0000 {
400 compatible = "samsung,exynos3250-adc",
401 "samsung,exynos-adc-v2";
402 reg = <0x126C0000 0x100>;
403 interrupts = <0 137 0>;
404 clock-names = "adc", "sclk";
405 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
406 #io-channel-cells = <1>;
407 io-channel-ranges;
408 samsung,syscon-phandle = <&pmu_system_controller>;
409 status = "disabled";
410 };
411
412 mfc: codec@13400000 {
413 compatible = "samsung,mfc-v7";
414 reg = <0x13400000 0x10000>;
415 interrupts = <0 102 0>;
416 clock-names = "mfc", "sclk_mfc";
417 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
418 power-domains = <&pd_mfc>;
419 iommus = <&sysmmu_mfc>;
420 status = "disabled";
421 };
422
423 sysmmu_mfc: sysmmu@13620000 {
424 compatible = "samsung,exynos-sysmmu";
425 reg = <0x13620000 0x1000>;
426 interrupts = <0 96 0>, <0 98 0>;
427 clock-names = "sysmmu", "master";
428 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
429 power-domains = <&pd_mfc>;
430 #iommu-cells = <0>;
431 };
432
433 serial_0: serial@13800000 {
434 compatible = "samsung,exynos4210-uart";
435 reg = <0x13800000 0x100>;
436 interrupts = <0 109 0>;
437 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
438 clock-names = "uart", "clk_uart_baud0";
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart0_data &uart0_fctl>;
441 status = "disabled";
442 };
443
444 serial_1: serial@13810000 {
445 compatible = "samsung,exynos4210-uart";
446 reg = <0x13810000 0x100>;
447 interrupts = <0 110 0>;
448 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
449 clock-names = "uart", "clk_uart_baud0";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart1_data>;
452 status = "disabled";
453 };
454
455 i2c_0: i2c@13860000 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 compatible = "samsung,s3c2440-i2c";
459 reg = <0x13860000 0x100>;
460 interrupts = <0 113 0>;
461 clocks = <&cmu CLK_I2C0>;
462 clock-names = "i2c";
463 pinctrl-names = "default";
464 pinctrl-0 = <&i2c0_bus>;
465 status = "disabled";
466 };
467
468 i2c_1: i2c@13870000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "samsung,s3c2440-i2c";
472 reg = <0x13870000 0x100>;
473 interrupts = <0 114 0>;
474 clocks = <&cmu CLK_I2C1>;
475 clock-names = "i2c";
476 pinctrl-names = "default";
477 pinctrl-0 = <&i2c1_bus>;
478 status = "disabled";
479 };
480
481 i2c_2: i2c@13880000 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 compatible = "samsung,s3c2440-i2c";
485 reg = <0x13880000 0x100>;
486 interrupts = <0 115 0>;
487 clocks = <&cmu CLK_I2C2>;
488 clock-names = "i2c";
489 pinctrl-names = "default";
490 pinctrl-0 = <&i2c2_bus>;
491 status = "disabled";
492 };
493
494 i2c_3: i2c@13890000 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "samsung,s3c2440-i2c";
498 reg = <0x13890000 0x100>;
499 interrupts = <0 116 0>;
500 clocks = <&cmu CLK_I2C3>;
501 clock-names = "i2c";
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2c3_bus>;
504 status = "disabled";
505 };
506
507 i2c_4: i2c@138A0000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "samsung,s3c2440-i2c";
511 reg = <0x138A0000 0x100>;
512 interrupts = <0 117 0>;
513 clocks = <&cmu CLK_I2C4>;
514 clock-names = "i2c";
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c4_bus>;
517 status = "disabled";
518 };
519
520 i2c_5: i2c@138B0000 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 compatible = "samsung,s3c2440-i2c";
524 reg = <0x138B0000 0x100>;
525 interrupts = <0 118 0>;
526 clocks = <&cmu CLK_I2C5>;
527 clock-names = "i2c";
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c5_bus>;
530 status = "disabled";
531 };
532
533 i2c_6: i2c@138C0000 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "samsung,s3c2440-i2c";
537 reg = <0x138C0000 0x100>;
538 interrupts = <0 119 0>;
539 clocks = <&cmu CLK_I2C6>;
540 clock-names = "i2c";
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c6_bus>;
543 status = "disabled";
544 };
545
546 i2c_7: i2c@138D0000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "samsung,s3c2440-i2c";
550 reg = <0x138D0000 0x100>;
551 interrupts = <0 120 0>;
552 clocks = <&cmu CLK_I2C7>;
553 clock-names = "i2c";
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c7_bus>;
556 status = "disabled";
557 };
558
559 spi_0: spi@13920000 {
560 compatible = "samsung,exynos4210-spi";
561 reg = <0x13920000 0x100>;
562 interrupts = <0 121 0>;
563 dmas = <&pdma0 7>, <&pdma0 6>;
564 dma-names = "tx", "rx";
565 #address-cells = <1>;
566 #size-cells = <0>;
567 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
568 clock-names = "spi", "spi_busclk0";
569 samsung,spi-src-clk = <0>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&spi0_bus>;
572 status = "disabled";
573 };
574
575 spi_1: spi@13930000 {
576 compatible = "samsung,exynos4210-spi";
577 reg = <0x13930000 0x100>;
578 interrupts = <0 122 0>;
579 dmas = <&pdma1 7>, <&pdma1 6>;
580 dma-names = "tx", "rx";
581 #address-cells = <1>;
582 #size-cells = <0>;
583 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
584 clock-names = "spi", "spi_busclk0";
585 samsung,spi-src-clk = <0>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&spi1_bus>;
588 status = "disabled";
589 };
590
591 i2s2: i2s@13970000 {
592 compatible = "samsung,s3c6410-i2s";
593 reg = <0x13970000 0x100>;
594 interrupts = <0 126 0>;
595 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
596 clock-names = "iis", "i2s_opclk0";
597 dmas = <&pdma0 14>, <&pdma0 13>;
598 dma-names = "tx", "rx";
599 pinctrl-0 = <&i2s2_bus>;
600 pinctrl-names = "default";
601 status = "disabled";
602 };
603
604 pwm: pwm@139D0000 {
605 compatible = "samsung,exynos4210-pwm";
606 reg = <0x139D0000 0x1000>;
607 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
608 <0 107 0>, <0 108 0>;
609 #pwm-cells = <3>;
610 status = "disabled";
611 };
612
613 pmu {
614 compatible = "arm,cortex-a7-pmu";
615 interrupts = <0 18 0>, <0 19 0>;
616 };
617
618 ppmu_dmc0: ppmu_dmc0@106a0000 {
619 compatible = "samsung,exynos-ppmu";
620 reg = <0x106a0000 0x2000>;
621 status = "disabled";
622 };
623
624 ppmu_dmc1: ppmu_dmc1@106b0000 {
625 compatible = "samsung,exynos-ppmu";
626 reg = <0x106b0000 0x2000>;
627 status = "disabled";
628 };
629
630 ppmu_cpu: ppmu_cpu@106c0000 {
631 compatible = "samsung,exynos-ppmu";
632 reg = <0x106c0000 0x2000>;
633 status = "disabled";
634 };
635
636 ppmu_rightbus: ppmu_rightbus@112a0000 {
637 compatible = "samsung,exynos-ppmu";
638 reg = <0x112a0000 0x2000>;
639 clocks = <&cmu CLK_PPMURIGHT>;
640 clock-names = "ppmu";
641 status = "disabled";
642 };
643
644 ppmu_leftbus: ppmu_leftbus0@116a0000 {
645 compatible = "samsung,exynos-ppmu";
646 reg = <0x116a0000 0x2000>;
647 clocks = <&cmu CLK_PPMULEFT>;
648 clock-names = "ppmu";
649 status = "disabled";
650 };
651
652 ppmu_camif: ppmu_camif@11ac0000 {
653 compatible = "samsung,exynos-ppmu";
654 reg = <0x11ac0000 0x2000>;
655 clocks = <&cmu CLK_PPMUCAMIF>;
656 clock-names = "ppmu";
657 status = "disabled";
658 };
659
660 ppmu_lcd0: ppmu_lcd0@11e40000 {
661 compatible = "samsung,exynos-ppmu";
662 reg = <0x11e40000 0x2000>;
663 clocks = <&cmu CLK_PPMULCD0>;
664 clock-names = "ppmu";
665 status = "disabled";
666 };
667
668 ppmu_fsys: ppmu_fsys@12630000 {
669 compatible = "samsung,exynos-ppmu";
670 reg = <0x12630000 0x2000>;
671 clocks = <&cmu CLK_PPMUFILE>;
672 clock-names = "ppmu";
673 status = "disabled";
674 };
675
676 ppmu_g3d: ppmu_g3d@13220000 {
677 compatible = "samsung,exynos-ppmu";
678 reg = <0x13220000 0x2000>;
679 clocks = <&cmu CLK_PPMUG3D>;
680 clock-names = "ppmu";
681 status = "disabled";
682 };
683
684 ppmu_mfc: ppmu_mfc@13660000 {
685 compatible = "samsung,exynos-ppmu";
686 reg = <0x13660000 0x2000>;
687 clocks = <&cmu CLK_PPMUMFC_L>;
688 clock-names = "ppmu";
689 status = "disabled";
690 };
691 };
692};
693
694#include "exynos3250-pinctrl.dtsi"