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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 *
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
14 */
15
16#include "armada-370-xp.dtsi"
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 serial2 = &uart2;
27 serial3 = &uart3;
28 };
29
30 soc {
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
32
33 bootrom {
34 compatible = "marvell,bootrom";
35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
36 };
37
38 internal-regs {
39 sdramc@1400 {
40 compatible = "marvell,armada-xp-sdram-controller";
41 reg = <0x1400 0x500>;
42 };
43
44 L2: l2-cache@8000 {
45 compatible = "marvell,aurora-system-cache";
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
48 cache-level = <2>;
49 cache-unified;
50 wt-override;
51 };
52
53 uart2: serial@12200 {
54 compatible = "snps,dw-apb-uart";
55 pinctrl-0 = <&uart2_pins>;
56 pinctrl-names = "default";
57 reg = <0x12200 0x100>;
58 reg-shift = <2>;
59 interrupts = <43>;
60 reg-io-width = <1>;
61 clocks = <&coreclk 0>;
62 status = "disabled";
63 };
64
65 uart3: serial@12300 {
66 compatible = "snps,dw-apb-uart";
67 pinctrl-0 = <&uart3_pins>;
68 pinctrl-names = "default";
69 reg = <0x12300 0x100>;
70 reg-shift = <2>;
71 interrupts = <44>;
72 reg-io-width = <1>;
73 clocks = <&coreclk 0>;
74 status = "disabled";
75 };
76
77 systemc: system-controller@18200 {
78 compatible = "marvell,armada-370-xp-system-controller";
79 reg = <0x18200 0x500>;
80 };
81
82 gateclk: clock-gating-control@18220 {
83 compatible = "marvell,armada-xp-gating-clock";
84 reg = <0x18220 0x4>;
85 clocks = <&coreclk 0>;
86 #clock-cells = <1>;
87 };
88
89 coreclk: mvebu-sar@18230 {
90 compatible = "marvell,armada-xp-core-clock";
91 reg = <0x18230 0x08>;
92 #clock-cells = <1>;
93 };
94
95 thermal: thermal@182b0 {
96 compatible = "marvell,armadaxp-thermal";
97 reg = <0x182b0 0x4
98 0x184d0 0x4>;
99 status = "okay";
100 };
101
102 cpuclk: clock-complex@18700 {
103 #clock-cells = <1>;
104 compatible = "marvell,armada-xp-cpu-clock";
105 reg = <0x18700 0x24>, <0x1c054 0x10>;
106 clocks = <&coreclk 1>;
107 };
108
109 cpu-config@21000 {
110 compatible = "marvell,armada-xp-cpu-config";
111 reg = <0x21000 0x8>;
112 };
113
114 eth2: ethernet@30000 {
115 compatible = "marvell,armada-xp-neta";
116 reg = <0x30000 0x4000>;
117 interrupts = <12>;
118 clocks = <&gateclk 2>;
119 status = "disabled";
120 };
121
122 usb2: usb@52000 {
123 compatible = "marvell,orion-ehci";
124 reg = <0x52000 0x500>;
125 interrupts = <47>;
126 clocks = <&gateclk 20>;
127 status = "disabled";
128 };
129
130 xor1: xor@60900 {
131 compatible = "marvell,orion-xor";
132 reg = <0x60900 0x100
133 0x60b00 0x100>;
134 clocks = <&gateclk 22>;
135 status = "okay";
136
137 xor10 {
138 interrupts = <51>;
139 dmacap,memcpy;
140 dmacap,xor;
141 };
142 xor11 {
143 interrupts = <52>;
144 dmacap,memcpy;
145 dmacap,xor;
146 dmacap,memset;
147 };
148 };
149
150 ethernet@70000 {
151 compatible = "marvell,armada-xp-neta";
152 };
153
154 ethernet@74000 {
155 compatible = "marvell,armada-xp-neta";
156 };
157
158 cesa: crypto@90000 {
159 compatible = "marvell,armada-xp-crypto";
160 reg = <0x90000 0x10000>;
161 reg-names = "regs";
162 interrupts = <48>, <49>;
163 clocks = <&gateclk 23>, <&gateclk 23>;
164 clock-names = "cesa0", "cesa1";
165 marvell,crypto-srams = <&crypto_sram0>,
166 <&crypto_sram1>;
167 marvell,crypto-sram-size = <0x800>;
168 };
169
170 bm: bm@c0000 {
171 compatible = "marvell,armada-380-neta-bm";
172 reg = <0xc0000 0xac>;
173 clocks = <&gateclk 13>;
174 internal-mem = <&bm_bppi>;
175 status = "disabled";
176 };
177
178 xor0: xor@f0900 {
179 compatible = "marvell,orion-xor";
180 reg = <0xF0900 0x100
181 0xF0B00 0x100>;
182 clocks = <&gateclk 28>;
183 status = "okay";
184
185 xor00 {
186 interrupts = <94>;
187 dmacap,memcpy;
188 dmacap,xor;
189 };
190 xor01 {
191 interrupts = <95>;
192 dmacap,memcpy;
193 dmacap,xor;
194 dmacap,memset;
195 };
196 };
197 };
198
199 crypto_sram0: sa-sram0 {
200 compatible = "mmio-sram";
201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
202 clocks = <&gateclk 23>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
206 };
207
208 crypto_sram1: sa-sram1 {
209 compatible = "mmio-sram";
210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
211 clocks = <&gateclk 23>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
215 };
216
217 bm_bppi: bm-bppi {
218 compatible = "mmio-sram";
219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 clocks = <&gateclk 13>;
224 no-memory-wc;
225 status = "disabled";
226 };
227 };
228
229 clocks {
230 /* 25 MHz reference crystal */
231 refclk: oscillator {
232 compatible = "fixed-clock";
233 #clock-cells = <0>;
234 clock-frequency = <25000000>;
235 };
236 };
237};
238
239&i2c0 {
240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
241 reg = <0x11000 0x100>;
242};
243
244&i2c1 {
245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x100>;
247};
248
249&mpic {
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
251};
252
253&timer {
254 compatible = "marvell,armada-xp-timer";
255 clocks = <&coreclk 2>, <&refclk>;
256 clock-names = "nbclk", "fixed";
257};
258
259&watchdog {
260 compatible = "marvell,armada-xp-wdt";
261 clocks = <&coreclk 2>, <&refclk>;
262 clock-names = "nbclk", "fixed";
263};
264
265&cpurst {
266 reg = <0x20800 0x20>;
267};
268
269&usb0 {
270 clocks = <&gateclk 18>;
271};
272
273&usb1 {
274 clocks = <&gateclk 19>;
275};
276
277&pinctrl {
278 ge0_gmii_pins: ge0-gmii-pins {
279 marvell,pins =
280 "mpp0", "mpp1", "mpp2", "mpp3",
281 "mpp4", "mpp5", "mpp6", "mpp7",
282 "mpp8", "mpp9", "mpp10", "mpp11",
283 "mpp12", "mpp13", "mpp14", "mpp15",
284 "mpp16", "mpp17", "mpp18", "mpp19",
285 "mpp20", "mpp21", "mpp22", "mpp23";
286 marvell,function = "ge0";
287 };
288
289 ge0_rgmii_pins: ge0-rgmii-pins {
290 marvell,pins =
291 "mpp0", "mpp1", "mpp2", "mpp3",
292 "mpp4", "mpp5", "mpp6", "mpp7",
293 "mpp8", "mpp9", "mpp10", "mpp11";
294 marvell,function = "ge0";
295 };
296
297 ge1_rgmii_pins: ge1-rgmii-pins {
298 marvell,pins =
299 "mpp12", "mpp13", "mpp14", "mpp15",
300 "mpp16", "mpp17", "mpp18", "mpp19",
301 "mpp20", "mpp21", "mpp22", "mpp23";
302 marvell,function = "ge1";
303 };
304
305 sdio_pins: sdio-pins {
306 marvell,pins = "mpp30", "mpp31", "mpp32",
307 "mpp33", "mpp34", "mpp35";
308 marvell,function = "sd0";
309 };
310
311 spi0_pins: spi0-pins {
312 marvell,pins = "mpp36", "mpp37",
313 "mpp38", "mpp39";
314 marvell,function = "spi0";
315 };
316
317 spi1_pins: spi1-pins {
318 marvell,pins = "mpp13", "mpp14",
319 "mpp16", "mpp17";
320 marvell,function = "spi1";
321 };
322
323 uart2_pins: uart2-pins {
324 marvell,pins = "mpp42", "mpp43";
325 marvell,function = "uart2";
326 };
327
328 uart3_pins: uart3-pins {
329 marvell,pins = "mpp44", "mpp45";
330 marvell,function = "uart3";
331 };
332};
333
334&spi0 {
335 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
336 pinctrl-0 = <&spi0_pins>;
337 pinctrl-names = "default";
338};
339
340&spi1 {
341 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
342 pinctrl-0 = <&spi1_pins>;
343 pinctrl-names = "default";
344};
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Contains definitions specific to the Armada XP SoC that are not
50 * common to all Armada SoCs.
51 */
52
53#include "armada-370-xp.dtsi"
54
55/ {
56 model = "Marvell Armada XP family SoC";
57 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58
59 aliases {
60 serial2 = &uart2;
61 serial3 = &uart3;
62 };
63
64 soc {
65 compatible = "marvell,armadaxp-mbus", "simple-bus";
66
67 bootrom {
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
70 };
71
72 internal-regs {
73 sdramc@1400 {
74 compatible = "marvell,armada-xp-sdram-controller";
75 reg = <0x1400 0x500>;
76 };
77
78 L2: l2-cache {
79 compatible = "marvell,aurora-system-cache";
80 reg = <0x08000 0x1000>;
81 cache-id-part = <0x100>;
82 cache-level = <2>;
83 cache-unified;
84 wt-override;
85 };
86
87 spi0: spi@10600 {
88 compatible = "marvell,armada-xp-spi",
89 "marvell,orion-spi";
90 pinctrl-0 = <&spi0_pins>;
91 pinctrl-names = "default";
92 };
93
94 spi1: spi@10680 {
95 compatible = "marvell,armada-xp-spi",
96 "marvell,orion-spi";
97 };
98
99
100 i2c0: i2c@11000 {
101 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
102 reg = <0x11000 0x100>;
103 };
104
105 i2c1: i2c@11100 {
106 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
107 reg = <0x11100 0x100>;
108 };
109
110 uart2: serial@12200 {
111 compatible = "snps,dw-apb-uart";
112 pinctrl-0 = <&uart2_pins>;
113 pinctrl-names = "default";
114 reg = <0x12200 0x100>;
115 reg-shift = <2>;
116 interrupts = <43>;
117 reg-io-width = <1>;
118 clocks = <&coreclk 0>;
119 status = "disabled";
120 };
121
122 uart3: serial@12300 {
123 compatible = "snps,dw-apb-uart";
124 pinctrl-0 = <&uart3_pins>;
125 pinctrl-names = "default";
126 reg = <0x12300 0x100>;
127 reg-shift = <2>;
128 interrupts = <44>;
129 reg-io-width = <1>;
130 clocks = <&coreclk 0>;
131 status = "disabled";
132 };
133
134 system-controller@18200 {
135 compatible = "marvell,armada-370-xp-system-controller";
136 reg = <0x18200 0x500>;
137 };
138
139 gateclk: clock-gating-control@18220 {
140 compatible = "marvell,armada-xp-gating-clock";
141 reg = <0x18220 0x4>;
142 clocks = <&coreclk 0>;
143 #clock-cells = <1>;
144 };
145
146 coreclk: mvebu-sar@18230 {
147 compatible = "marvell,armada-xp-core-clock";
148 reg = <0x18230 0x08>;
149 #clock-cells = <1>;
150 };
151
152 thermal@182b0 {
153 compatible = "marvell,armadaxp-thermal";
154 reg = <0x182b0 0x4
155 0x184d0 0x4>;
156 status = "okay";
157 };
158
159 cpuclk: clock-complex@18700 {
160 #clock-cells = <1>;
161 compatible = "marvell,armada-xp-cpu-clock";
162 reg = <0x18700 0x24>, <0x1c054 0x10>;
163 clocks = <&coreclk 1>;
164 };
165
166 interrupt-controller@20a00 {
167 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
168 };
169
170 timer@20300 {
171 compatible = "marvell,armada-xp-timer";
172 clocks = <&coreclk 2>, <&refclk>;
173 clock-names = "nbclk", "fixed";
174 };
175
176 watchdog@20300 {
177 compatible = "marvell,armada-xp-wdt";
178 clocks = <&coreclk 2>, <&refclk>;
179 clock-names = "nbclk", "fixed";
180 };
181
182 cpurst@20800 {
183 compatible = "marvell,armada-370-cpu-reset";
184 reg = <0x20800 0x20>;
185 };
186
187 cpu-config@21000 {
188 compatible = "marvell,armada-xp-cpu-config";
189 reg = <0x21000 0x8>;
190 };
191
192 eth2: ethernet@30000 {
193 compatible = "marvell,armada-xp-neta";
194 reg = <0x30000 0x4000>;
195 interrupts = <12>;
196 clocks = <&gateclk 2>;
197 status = "disabled";
198 };
199
200 usb@50000 {
201 clocks = <&gateclk 18>;
202 };
203
204 usb@51000 {
205 clocks = <&gateclk 19>;
206 };
207
208 usb@52000 {
209 compatible = "marvell,orion-ehci";
210 reg = <0x52000 0x500>;
211 interrupts = <47>;
212 clocks = <&gateclk 20>;
213 status = "disabled";
214 };
215
216 xor@60900 {
217 compatible = "marvell,orion-xor";
218 reg = <0x60900 0x100
219 0x60b00 0x100>;
220 clocks = <&gateclk 22>;
221 status = "okay";
222
223 xor10 {
224 interrupts = <51>;
225 dmacap,memcpy;
226 dmacap,xor;
227 };
228 xor11 {
229 interrupts = <52>;
230 dmacap,memcpy;
231 dmacap,xor;
232 dmacap,memset;
233 };
234 };
235
236 ethernet@70000 {
237 compatible = "marvell,armada-xp-neta";
238 };
239
240 ethernet@74000 {
241 compatible = "marvell,armada-xp-neta";
242 };
243
244 crypto@90000 {
245 compatible = "marvell,armada-xp-crypto";
246 reg = <0x90000 0x10000>;
247 reg-names = "regs";
248 interrupts = <48>, <49>;
249 clocks = <&gateclk 23>, <&gateclk 23>;
250 clock-names = "cesa0", "cesa1";
251 marvell,crypto-srams = <&crypto_sram0>,
252 <&crypto_sram1>;
253 marvell,crypto-sram-size = <0x800>;
254 };
255
256 bm: bm@c0000 {
257 compatible = "marvell,armada-380-neta-bm";
258 reg = <0xc0000 0xac>;
259 clocks = <&gateclk 13>;
260 internal-mem = <&bm_bppi>;
261 status = "disabled";
262 };
263
264 xor@f0900 {
265 compatible = "marvell,orion-xor";
266 reg = <0xF0900 0x100
267 0xF0B00 0x100>;
268 clocks = <&gateclk 28>;
269 status = "okay";
270
271 xor00 {
272 interrupts = <94>;
273 dmacap,memcpy;
274 dmacap,xor;
275 };
276 xor01 {
277 interrupts = <95>;
278 dmacap,memcpy;
279 dmacap,xor;
280 dmacap,memset;
281 };
282 };
283 };
284
285 crypto_sram0: sa-sram0 {
286 compatible = "mmio-sram";
287 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
288 clocks = <&gateclk 23>;
289 #address-cells = <1>;
290 #size-cells = <1>;
291 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
292 };
293
294 crypto_sram1: sa-sram1 {
295 compatible = "mmio-sram";
296 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
297 clocks = <&gateclk 23>;
298 #address-cells = <1>;
299 #size-cells = <1>;
300 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
301 };
302
303 bm_bppi: bm-bppi {
304 compatible = "mmio-sram";
305 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
306 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
307 #address-cells = <1>;
308 #size-cells = <1>;
309 clocks = <&gateclk 13>;
310 no-memory-wc;
311 status = "disabled";
312 };
313 };
314
315 clocks {
316 /* 25 MHz reference crystal */
317 refclk: oscillator {
318 compatible = "fixed-clock";
319 #clock-cells = <0>;
320 clock-frequency = <25000000>;
321 };
322 };
323};
324
325&pinctrl {
326 ge0_gmii_pins: ge0-gmii-pins {
327 marvell,pins =
328 "mpp0", "mpp1", "mpp2", "mpp3",
329 "mpp4", "mpp5", "mpp6", "mpp7",
330 "mpp8", "mpp9", "mpp10", "mpp11",
331 "mpp12", "mpp13", "mpp14", "mpp15",
332 "mpp16", "mpp17", "mpp18", "mpp19",
333 "mpp20", "mpp21", "mpp22", "mpp23";
334 marvell,function = "ge0";
335 };
336
337 ge0_rgmii_pins: ge0-rgmii-pins {
338 marvell,pins =
339 "mpp0", "mpp1", "mpp2", "mpp3",
340 "mpp4", "mpp5", "mpp6", "mpp7",
341 "mpp8", "mpp9", "mpp10", "mpp11";
342 marvell,function = "ge0";
343 };
344
345 ge1_rgmii_pins: ge1-rgmii-pins {
346 marvell,pins =
347 "mpp12", "mpp13", "mpp14", "mpp15",
348 "mpp16", "mpp17", "mpp18", "mpp19",
349 "mpp20", "mpp21", "mpp22", "mpp23";
350 marvell,function = "ge1";
351 };
352
353 sdio_pins: sdio-pins {
354 marvell,pins = "mpp30", "mpp31", "mpp32",
355 "mpp33", "mpp34", "mpp35";
356 marvell,function = "sd0";
357 };
358
359 spi0_pins: spi0-pins {
360 marvell,pins = "mpp36", "mpp37",
361 "mpp38", "mpp39";
362 marvell,function = "spi0";
363 };
364
365 uart2_pins: uart2-pins {
366 marvell,pins = "mpp42", "mpp43";
367 marvell,function = "uart2";
368 };
369
370 uart3_pins: uart3-pins {
371 marvell,pins = "mpp44", "mpp45";
372 marvell,function = "uart3";
373 };
374};