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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * Contains definitions specific to the Armada XP MV78230 SoC that are not
10 * common to all Armada XP SoCs.
11 */
12
13#include "armada-xp.dtsi"
14
15/ {
16 model = "Marvell Armada XP MV78230 SoC";
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "marvell,sheeva-v7";
32 reg = <0>;
33 clocks = <&cpuclk 0>;
34 clock-latency = <1000000>;
35 };
36
37 cpu@1 {
38 device_type = "cpu";
39 compatible = "marvell,sheeva-v7";
40 reg = <1>;
41 clocks = <&cpuclk 1>;
42 clock-latency = <1000000>;
43 };
44 };
45
46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x1 only.
51 */
52 pciec: pcie@82000000 {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 msi-parent = <&mpic>;
61 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
79
80 pcie1: pcie@1,0 {
81 device_type = "pci";
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 reg = <0x0800 0 0 0 0>;
84 #address-cells = <3>;
85 #size-cells = <2>;
86 #interrupt-cells = <1>;
87 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
88 0x81000000 0 0 0x81000000 0x1 0 1 0>;
89 bus-range = <0x00 0xff>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &mpic 58>;
92 marvell,pcie-port = <0>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
95 status = "disabled";
96 };
97
98 pcie2: pcie@2,0 {
99 device_type = "pci";
100 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
101 reg = <0x1000 0 0 0 0>;
102 #address-cells = <3>;
103 #size-cells = <2>;
104 #interrupt-cells = <1>;
105 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
106 0x81000000 0 0 0x81000000 0x2 0 1 0>;
107 bus-range = <0x00 0xff>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &mpic 59>;
110 marvell,pcie-port = <0>;
111 marvell,pcie-lane = <1>;
112 clocks = <&gateclk 6>;
113 status = "disabled";
114 };
115
116 pcie3: pcie@3,0 {
117 device_type = "pci";
118 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
119 reg = <0x1800 0 0 0 0>;
120 #address-cells = <3>;
121 #size-cells = <2>;
122 #interrupt-cells = <1>;
123 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
124 0x81000000 0 0 0x81000000 0x3 0 1 0>;
125 bus-range = <0x00 0xff>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 60>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <2>;
130 clocks = <&gateclk 7>;
131 status = "disabled";
132 };
133
134 pcie4: pcie@4,0 {
135 device_type = "pci";
136 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
137 reg = <0x2000 0 0 0 0>;
138 #address-cells = <3>;
139 #size-cells = <2>;
140 #interrupt-cells = <1>;
141 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
142 0x81000000 0 0 0x81000000 0x4 0 1 0>;
143 bus-range = <0x00 0xff>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
149 status = "disabled";
150 };
151
152 pcie5: pcie@5,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
155 reg = <0x2800 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
160 0x81000000 0 0 0x81000000 0x5 0 1 0>;
161 bus-range = <0x00 0xff>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 62>;
164 marvell,pcie-port = <1>;
165 marvell,pcie-lane = <0>;
166 clocks = <&gateclk 9>;
167 status = "disabled";
168 };
169 };
170
171 internal-regs {
172 gpio0: gpio@18100 {
173 compatible = "marvell,armada-370-gpio",
174 "marvell,orion-gpio";
175 reg = <0x18100 0x40>, <0x181c0 0x08>;
176 reg-names = "gpio", "pwm";
177 ngpios = <32>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 #pwm-cells = <2>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupts = <82>, <83>, <84>, <85>;
184 clocks = <&coreclk 0>;
185 };
186
187 gpio1: gpio@18140 {
188 compatible = "marvell,armada-370-gpio",
189 "marvell,orion-gpio";
190 reg = <0x18140 0x40>, <0x181c8 0x08>;
191 reg-names = "gpio", "pwm";
192 ngpios = <17>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 #pwm-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 interrupts = <87>, <88>, <89>;
199 clocks = <&coreclk 0>;
200 };
201 };
202 };
203};
204
205&pinctrl {
206 compatible = "marvell,mv78230-pinctrl";
207};
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 *
46 * Contains definitions specific to the Armada XP MV78230 SoC that are not
47 * common to all Armada XP SoCs.
48 */
49
50#include "armada-xp.dtsi"
51
52/ {
53 model = "Marvell Armada XP MV78230 SoC";
54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
55
56 aliases {
57 gpio0 = &gpio0;
58 gpio1 = &gpio1;
59 };
60
61 cpus {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 enable-method = "marvell,armada-xp-smp";
65
66 cpu@0 {
67 device_type = "cpu";
68 compatible = "marvell,sheeva-v7";
69 reg = <0>;
70 clocks = <&cpuclk 0>;
71 clock-latency = <1000000>;
72 };
73
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "marvell,sheeva-v7";
77 reg = <1>;
78 clocks = <&cpuclk 1>;
79 clock-latency = <1000000>;
80 };
81 };
82
83 soc {
84 /*
85 * MV78230 has 2 PCIe units Gen2.0: One unit can be
86 * configured as x4 or quad x1 lanes. One unit is
87 * x1 only.
88 */
89 pcie-controller {
90 compatible = "marvell,armada-xp-pcie";
91 status = "disabled";
92 device_type = "pci";
93
94 #address-cells = <3>;
95 #size-cells = <2>;
96
97 msi-parent = <&mpic>;
98 bus-range = <0x00 0xff>;
99
100 ranges =
101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
105 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
106 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
107 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
108 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
109 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
110 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
111 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
112 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
113 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
114 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
115 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
116
117 pcie@1,0 {
118 device_type = "pci";
119 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
120 reg = <0x0800 0 0 0 0>;
121 #address-cells = <3>;
122 #size-cells = <2>;
123 #interrupt-cells = <1>;
124 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
125 0x81000000 0 0 0x81000000 0x1 0 1 0>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 58>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
130 clocks = <&gateclk 5>;
131 status = "disabled";
132 };
133
134 pcie@2,0 {
135 device_type = "pci";
136 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
137 reg = <0x1000 0 0 0 0>;
138 #address-cells = <3>;
139 #size-cells = <2>;
140 #interrupt-cells = <1>;
141 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
142 0x81000000 0 0 0x81000000 0x2 0 1 0>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 59>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <1>;
147 clocks = <&gateclk 6>;
148 status = "disabled";
149 };
150
151 pcie@3,0 {
152 device_type = "pci";
153 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
154 reg = <0x1800 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
158 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
159 0x81000000 0 0 0x81000000 0x3 0 1 0>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 60>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <2>;
164 clocks = <&gateclk 7>;
165 status = "disabled";
166 };
167
168 pcie@4,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
171 reg = <0x2000 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
176 0x81000000 0 0 0x81000000 0x4 0 1 0>;
177 interrupt-map-mask = <0 0 0 0>;
178 interrupt-map = <0 0 0 0 &mpic 61>;
179 marvell,pcie-port = <0>;
180 marvell,pcie-lane = <3>;
181 clocks = <&gateclk 8>;
182 status = "disabled";
183 };
184
185 pcie@5,0 {
186 device_type = "pci";
187 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
188 reg = <0x2800 0 0 0 0>;
189 #address-cells = <3>;
190 #size-cells = <2>;
191 #interrupt-cells = <1>;
192 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
193 0x81000000 0 0 0x81000000 0x5 0 1 0>;
194 interrupt-map-mask = <0 0 0 0>;
195 interrupt-map = <0 0 0 0 &mpic 62>;
196 marvell,pcie-port = <1>;
197 marvell,pcie-lane = <0>;
198 clocks = <&gateclk 9>;
199 status = "disabled";
200 };
201 };
202
203 internal-regs {
204 gpio0: gpio@18100 {
205 compatible = "marvell,orion-gpio";
206 reg = <0x18100 0x40>;
207 ngpios = <32>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 interrupts = <82>, <83>, <84>, <85>;
213 };
214
215 gpio1: gpio@18140 {
216 compatible = "marvell,orion-gpio";
217 reg = <0x18140 0x40>;
218 ngpios = <17>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 interrupts = <87>, <88>, <89>;
224 };
225 };
226 };
227};
228
229&pinctrl {
230 compatible = "marvell,mv78230-pinctrl";
231};