1/*
  2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 */
  8
  9/*
 10 * Device Tree for ARC HS Development Kit
 11 */
 12/dts-v1/;
 13
 14#include <dt-bindings/net/ti-dp83867.h>
 15#include <dt-bindings/reset/snps,hsdk-reset.h>
 16
 17/ {
 18	model = "snps,hsdk";
 19	compatible = "snps,hsdk";
 20
 21	#address-cells = <1>;
 22	#size-cells = <1>;
 23
 24	chosen {
 25		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
 26	};
 27
 28	cpus {
 29		#address-cells = <1>;
 30		#size-cells = <0>;
 31
 32		cpu@0 {
 33			device_type = "cpu";
 34			compatible = "snps,archs38";
 35			reg = <0>;
 36			clocks = <&core_clk>;
 37		};
 38
 39		cpu@1 {
 40			device_type = "cpu";
 41			compatible = "snps,archs38";
 42			reg = <1>;
 43			clocks = <&core_clk>;
 44		};
 45
 46		cpu@2 {
 47			device_type = "cpu";
 48			compatible = "snps,archs38";
 49			reg = <2>;
 50			clocks = <&core_clk>;
 51		};
 52
 53		cpu@3 {
 54			device_type = "cpu";
 55			compatible = "snps,archs38";
 56			reg = <3>;
 57			clocks = <&core_clk>;
 58		};
 59	};
 60
 61	input_clk: input-clk {
 62		#clock-cells = <0>;
 63		compatible = "fixed-clock";
 64		clock-frequency = <33333333>;
 65	};
 66
 67	cpu_intc: cpu-interrupt-controller {
 68		compatible = "snps,archs-intc";
 69		interrupt-controller;
 70		#interrupt-cells = <1>;
 71	};
 72
 73	idu_intc: idu-interrupt-controller {
 74		compatible = "snps,archs-idu-intc";
 75		interrupt-controller;
 76		#interrupt-cells = <1>;
 77		interrupt-parent = <&cpu_intc>;
 78	};
 79
 80	arcpct: pct {
 81		compatible = "snps,archs-pct";
 82	};
 83
 84	/* TIMER0 with interrupt for clockevent */
 85	timer {
 86		compatible = "snps,arc-timer";
 87		interrupts = <16>;
 88		interrupt-parent = <&cpu_intc>;
 89		clocks = <&core_clk>;
 90	};
 91
 92	/* 64-bit Global Free Running Counter */
 93	gfrc {
 94		compatible = "snps,archs-timer-gfrc";
 95		clocks = <&core_clk>;
 96	};
 97
 98	soc {
 99		compatible = "simple-bus";
100		#address-cells = <1>;
101		#size-cells = <1>;
102		interrupt-parent = <&idu_intc>;
103
104		ranges = <0x00000000 0xf0000000 0x10000000>;
105
106		cgu_rst: reset-controller@8a0 {
107			compatible = "snps,hsdk-reset";
108			#reset-cells = <1>;
109			reg = <0x8A0 0x4>, <0xFF0 0x4>;
110		};
111
112		core_clk: core-clk@0 {
113			compatible = "snps,hsdk-core-pll-clock";
114			reg = <0x00 0x10>, <0x14B8 0x4>;
115			#clock-cells = <0>;
116			clocks = <&input_clk>;
117
118			/*
119			 * Set initial core pll output frequency to 1GHz.
120			 * It will be applied at the core pll driver probing
121			 * on early boot.
122			 */
123			assigned-clocks = <&core_clk>;
124			assigned-clock-rates = <1000000000>;
125		};
126
127		serial: serial@5000 {
128			compatible = "snps,dw-apb-uart";
129			reg = <0x5000 0x100>;
130			clock-frequency = <33330000>;
131			interrupts = <6>;
132			baud = <115200>;
133			reg-shift = <2>;
134			reg-io-width = <4>;
135		};
136
137		gmacclk: gmacclk {
138			compatible = "fixed-clock";
139			clock-frequency = <400000000>;
140			#clock-cells = <0>;
141		};
142
143		mmcclk_ciu: mmcclk-ciu {
144			compatible = "fixed-clock";
145			/*
146			 * DW sdio controller has external ciu clock divider
147			 * controlled via register in SDIO IP. Due to its
148			 * unexpected default value (it should divide by 1
149			 * but it divides by 8) SDIO IP uses wrong clock and
150			 * works unstable (see STAR 9001204800)
151			 * We switched to the minimum possible value of the
152			 * divisor (div-by-2) in HSDK platform code.
153			 * So add temporary fix and change clock frequency
154			 * to 50000000 Hz until we fix dw sdio driver itself.
155			 */
156			clock-frequency = <50000000>;
157			#clock-cells = <0>;
158		};
159
160		mmcclk_biu: mmcclk-biu {
161			compatible = "fixed-clock";
162			clock-frequency = <400000000>;
163			#clock-cells = <0>;
164		};
165
166		ethernet@8000 {
167			#interrupt-cells = <1>;
168			compatible = "snps,dwmac";
169			reg = <0x8000 0x2000>;
170			interrupts = <10>;
171			interrupt-names = "macirq";
172			phy-mode = "rgmii";
173			snps,pbl = <32>;
174			clocks = <&gmacclk>;
175			clock-names = "stmmaceth";
176			phy-handle = <&phy0>;
177			resets = <&cgu_rst HSDK_ETH_RESET>;
178			reset-names = "stmmaceth";
179
180			mdio {
181				#address-cells = <1>;
182				#size-cells = <0>;
183				compatible = "snps,dwmac-mdio";
184				phy0: ethernet-phy@0 {
185					reg = <0>;
186					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
187					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
188					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
189				};
190			};
191		};
192
193		ohci@60000 {
194			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
195			reg = <0x60000 0x100>;
196			interrupts = <15>;
197		};
198
199		ehci@40000 {
200			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
201			reg = <0x40000 0x100>;
202			interrupts = <15>;
203		};
204
205		mmc@a000 {
206			compatible = "altr,socfpga-dw-mshc";
207			reg = <0xa000 0x400>;
208			num-slots = <1>;
209			fifo-depth = <16>;
210			card-detect-delay = <200>;
211			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
212			clock-names = "biu", "ciu";
213			interrupts = <12>;
214			bus-width = <4>;
215		};
216	};
217
218	memory@80000000 {
219		#address-cells = <1>;
220		#size-cells = <1>;
221		device_type = "memory";
222		reg = <0x80000000 0x40000000>;  /* 1 GiB */
223	};
224};