1/* Renesas Ethernet AVB device driver
   2 *
   3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
   4 * Copyright (C) 2015 Renesas Solutions Corp.
   5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
   6 *
   7 * Based on the SuperH Ethernet driver
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms and conditions of the GNU General Public License version 2,
  11 * as published by the Free Software Foundation.
  12 */
  13
  14#include <linux/cache.h>
  15#include <linux/clk.h>
  16#include <linux/delay.h>
  17#include <linux/dma-mapping.h>
  18#include <linux/err.h>
  19#include <linux/etherdevice.h>
  20#include <linux/ethtool.h>
  21#include <linux/if_vlan.h>
  22#include <linux/kernel.h>
  23#include <linux/list.h>
  24#include <linux/module.h>
  25#include <linux/net_tstamp.h>
  26#include <linux/of.h>
  27#include <linux/of_device.h>
  28#include <linux/of_irq.h>
  29#include <linux/of_mdio.h>
  30#include <linux/of_net.h>
  31#include <linux/pm_runtime.h>
  32#include <linux/slab.h>
  33#include <linux/spinlock.h>
  34#include <linux/sys_soc.h>
  35
  36#include <asm/div64.h>
  37
  38#include "ravb.h"
  39
  40#define RAVB_DEF_MSG_ENABLE \
  41		(NETIF_MSG_LINK	  | \
  42		 NETIF_MSG_TIMER  | \
  43		 NETIF_MSG_RX_ERR | \
  44		 NETIF_MSG_TX_ERR)
  45
  46static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
  47	"ch0", /* RAVB_BE */
  48	"ch1", /* RAVB_NC */
  49};
  50
  51static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
  52	"ch18", /* RAVB_BE */
  53	"ch19", /* RAVB_NC */
  54};
  55
  56void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
  57		 u32 set)
  58{
  59	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
  60}
  61
  62int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
  63{
  64	int i;
  65
  66	for (i = 0; i < 10000; i++) {
  67		if ((ravb_read(ndev, reg) & mask) == value)
  68			return 0;
  69		udelay(10);
  70	}
  71	return -ETIMEDOUT;
  72}
  73
  74static int ravb_config(struct net_device *ndev)
  75{
  76	int error;
  77
  78	/* Set config mode */
  79	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
  80	/* Check if the operating mode is changed to the config mode */
  81	error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
  82	if (error)
  83		netdev_err(ndev, "failed to switch device to config mode\n");
  84
  85	return error;
  86}
  87
  88static void ravb_set_duplex(struct net_device *ndev)
  89{
  90	struct ravb_private *priv = netdev_priv(ndev);
  91
  92	ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
  93}
  94
  95static void ravb_set_rate(struct net_device *ndev)
  96{
  97	struct ravb_private *priv = netdev_priv(ndev);
  98
  99	switch (priv->speed) {
 100	case 100:		/* 100BASE */
 101		ravb_write(ndev, GECMR_SPEED_100, GECMR);
 102		break;
 103	case 1000:		/* 1000BASE */
 104		ravb_write(ndev, GECMR_SPEED_1000, GECMR);
 105		break;
 106	}
 107}
 108
 109static void ravb_set_buffer_align(struct sk_buff *skb)
 110{
 111	u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
 112
 113	if (reserve)
 114		skb_reserve(skb, RAVB_ALIGN - reserve);
 115}
 116
 117/* Get MAC address from the MAC address registers
 118 *
 119 * Ethernet AVB device doesn't have ROM for MAC address.
 120 * This function gets the MAC address that was used by a bootloader.
 121 */
 122static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
 123{
 124	if (mac) {
 125		ether_addr_copy(ndev->dev_addr, mac);
 126	} else {
 127		u32 mahr = ravb_read(ndev, MAHR);
 128		u32 malr = ravb_read(ndev, MALR);
 129
 130		ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 131		ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 132		ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 133		ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
 134		ndev->dev_addr[4] = (malr >>  8) & 0xFF;
 135		ndev->dev_addr[5] = (malr >>  0) & 0xFF;
 136	}
 137}
 138
 139static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
 140{
 141	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
 142						 mdiobb);
 143
 144	ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
 145}
 146
 147/* MDC pin control */
 148static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
 149{
 150	ravb_mdio_ctrl(ctrl, PIR_MDC, level);
 151}
 152
 153/* Data I/O pin control */
 154static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
 155{
 156	ravb_mdio_ctrl(ctrl, PIR_MMD, output);
 157}
 158
 159/* Set data bit */
 160static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
 161{
 162	ravb_mdio_ctrl(ctrl, PIR_MDO, value);
 163}
 164
 165/* Get data bit */
 166static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
 167{
 168	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
 169						 mdiobb);
 170
 171	return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
 172}
 173
 174/* MDIO bus control struct */
 175static struct mdiobb_ops bb_ops = {
 176	.owner = THIS_MODULE,
 177	.set_mdc = ravb_set_mdc,
 178	.set_mdio_dir = ravb_set_mdio_dir,
 179	.set_mdio_data = ravb_set_mdio_data,
 180	.get_mdio_data = ravb_get_mdio_data,
 181};
 182
 183/* Free TX skb function for AVB-IP */
 184static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
 185{
 186	struct ravb_private *priv = netdev_priv(ndev);
 187	struct net_device_stats *stats = &priv->stats[q];
 188	struct ravb_tx_desc *desc;
 189	int free_num = 0;
 190	int entry;
 191	u32 size;
 192
 193	for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
 194		bool txed;
 195
 196		entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
 197					     NUM_TX_DESC);
 198		desc = &priv->tx_ring[q][entry];
 199		txed = desc->die_dt == DT_FEMPTY;
 200		if (free_txed_only && !txed)
 201			break;
 202		/* Descriptor type must be checked before all other reads */
 203		dma_rmb();
 204		size = le16_to_cpu(desc->ds_tagl) & TX_DS;
 205		/* Free the original skb. */
 206		if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
 207			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
 208					 size, DMA_TO_DEVICE);
 209			/* Last packet descriptor? */
 210			if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
 211				entry /= NUM_TX_DESC;
 212				dev_kfree_skb_any(priv->tx_skb[q][entry]);
 213				priv->tx_skb[q][entry] = NULL;
 214				if (txed)
 215					stats->tx_packets++;
 216			}
 217			free_num++;
 218		}
 219		if (txed)
 220			stats->tx_bytes += size;
 221		desc->die_dt = DT_EEMPTY;
 222	}
 223	return free_num;
 224}
 225
 226/* Free skb's and DMA buffers for Ethernet AVB */
 227static void ravb_ring_free(struct net_device *ndev, int q)
 228{
 229	struct ravb_private *priv = netdev_priv(ndev);
 230	int ring_size;
 231	int i;
 232
 233	if (priv->rx_ring[q]) {
 234		for (i = 0; i < priv->num_rx_ring[q]; i++) {
 235			struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
 
 
 
 
 236
 237			if (!dma_mapping_error(ndev->dev.parent,
 238					       le32_to_cpu(desc->dptr)))
 239				dma_unmap_single(ndev->dev.parent,
 240						 le32_to_cpu(desc->dptr),
 241						 priv->rx_buf_sz,
 242						 DMA_FROM_DEVICE);
 243		}
 
 
 
 
 
 
 244		ring_size = sizeof(struct ravb_ex_rx_desc) *
 245			    (priv->num_rx_ring[q] + 1);
 246		dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
 247				  priv->rx_desc_dma[q]);
 248		priv->rx_ring[q] = NULL;
 249	}
 250
 251	if (priv->tx_ring[q]) {
 252		ravb_tx_free(ndev, q, false);
 253
 254		ring_size = sizeof(struct ravb_tx_desc) *
 255			    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
 256		dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
 257				  priv->tx_desc_dma[q]);
 258		priv->tx_ring[q] = NULL;
 259	}
 260
 261	/* Free RX skb ringbuffer */
 262	if (priv->rx_skb[q]) {
 263		for (i = 0; i < priv->num_rx_ring[q]; i++)
 264			dev_kfree_skb(priv->rx_skb[q][i]);
 265	}
 266	kfree(priv->rx_skb[q]);
 267	priv->rx_skb[q] = NULL;
 268
 269	/* Free aligned TX buffers */
 270	kfree(priv->tx_align[q]);
 271	priv->tx_align[q] = NULL;
 272
 273	/* Free TX skb ringbuffer.
 274	 * SKBs are freed by ravb_tx_free() call above.
 275	 */
 276	kfree(priv->tx_skb[q]);
 277	priv->tx_skb[q] = NULL;
 278}
 279
 280/* Format skb and descriptor buffer for Ethernet AVB */
 281static void ravb_ring_format(struct net_device *ndev, int q)
 282{
 283	struct ravb_private *priv = netdev_priv(ndev);
 284	struct ravb_ex_rx_desc *rx_desc;
 285	struct ravb_tx_desc *tx_desc;
 286	struct ravb_desc *desc;
 287	int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
 288	int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
 289			   NUM_TX_DESC;
 290	dma_addr_t dma_addr;
 291	int i;
 292
 293	priv->cur_rx[q] = 0;
 294	priv->cur_tx[q] = 0;
 295	priv->dirty_rx[q] = 0;
 296	priv->dirty_tx[q] = 0;
 297
 298	memset(priv->rx_ring[q], 0, rx_ring_size);
 299	/* Build RX ring buffer */
 300	for (i = 0; i < priv->num_rx_ring[q]; i++) {
 301		/* RX descriptor */
 302		rx_desc = &priv->rx_ring[q][i];
 303		rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
 
 304		dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
 305					  priv->rx_buf_sz,
 306					  DMA_FROM_DEVICE);
 307		/* We just set the data size to 0 for a failed mapping which
 308		 * should prevent DMA from happening...
 309		 */
 310		if (dma_mapping_error(ndev->dev.parent, dma_addr))
 311			rx_desc->ds_cc = cpu_to_le16(0);
 312		rx_desc->dptr = cpu_to_le32(dma_addr);
 313		rx_desc->die_dt = DT_FEMPTY;
 314	}
 315	rx_desc = &priv->rx_ring[q][i];
 316	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
 317	rx_desc->die_dt = DT_LINKFIX; /* type */
 318
 319	memset(priv->tx_ring[q], 0, tx_ring_size);
 320	/* Build TX ring buffer */
 321	for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
 322	     i++, tx_desc++) {
 323		tx_desc->die_dt = DT_EEMPTY;
 324		tx_desc++;
 325		tx_desc->die_dt = DT_EEMPTY;
 326	}
 327	tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
 328	tx_desc->die_dt = DT_LINKFIX; /* type */
 329
 330	/* RX descriptor base address for best effort */
 331	desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
 332	desc->die_dt = DT_LINKFIX; /* type */
 333	desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
 334
 335	/* TX descriptor base address for best effort */
 336	desc = &priv->desc_bat[q];
 337	desc->die_dt = DT_LINKFIX; /* type */
 338	desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
 339}
 340
 341/* Init skb and descriptor buffer for Ethernet AVB */
 342static int ravb_ring_init(struct net_device *ndev, int q)
 343{
 344	struct ravb_private *priv = netdev_priv(ndev);
 345	struct sk_buff *skb;
 346	int ring_size;
 347	int i;
 348
 349	priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
 350		ETH_HLEN + VLAN_HLEN;
 351
 352	/* Allocate RX and TX skb rings */
 353	priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
 354				  sizeof(*priv->rx_skb[q]), GFP_KERNEL);
 355	priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
 356				  sizeof(*priv->tx_skb[q]), GFP_KERNEL);
 357	if (!priv->rx_skb[q] || !priv->tx_skb[q])
 358		goto error;
 359
 360	for (i = 0; i < priv->num_rx_ring[q]; i++) {
 361		skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1);
 362		if (!skb)
 363			goto error;
 364		ravb_set_buffer_align(skb);
 365		priv->rx_skb[q][i] = skb;
 366	}
 367
 368	/* Allocate rings for the aligned buffers */
 369	priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
 370				    DPTR_ALIGN - 1, GFP_KERNEL);
 371	if (!priv->tx_align[q])
 372		goto error;
 373
 374	/* Allocate all RX descriptors. */
 375	ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
 376	priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
 377					      &priv->rx_desc_dma[q],
 378					      GFP_KERNEL);
 379	if (!priv->rx_ring[q])
 380		goto error;
 381
 382	priv->dirty_rx[q] = 0;
 383
 384	/* Allocate all TX descriptors. */
 385	ring_size = sizeof(struct ravb_tx_desc) *
 386		    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
 387	priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
 388					      &priv->tx_desc_dma[q],
 389					      GFP_KERNEL);
 390	if (!priv->tx_ring[q])
 391		goto error;
 392
 393	return 0;
 394
 395error:
 396	ravb_ring_free(ndev, q);
 397
 398	return -ENOMEM;
 399}
 400
 401/* E-MAC init function */
 402static void ravb_emac_init(struct net_device *ndev)
 403{
 404	struct ravb_private *priv = netdev_priv(ndev);
 405
 406	/* Receive frame limit set register */
 407	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
 408
 409	/* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
 410	ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
 411		   (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
 412		   ECMR_TE | ECMR_RE, ECMR);
 413
 414	ravb_set_rate(ndev);
 415
 416	/* Set MAC address */
 417	ravb_write(ndev,
 418		   (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 419		   (ndev->dev_addr[2] << 8)  | (ndev->dev_addr[3]), MAHR);
 420	ravb_write(ndev,
 421		   (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);
 422
 
 
 423	/* E-MAC status register clear */
 424	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
 425
 426	/* E-MAC interrupt enable register */
 427	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
 428}
 429
 430/* Device init function for Ethernet AVB */
 431static int ravb_dmac_init(struct net_device *ndev)
 432{
 433	struct ravb_private *priv = netdev_priv(ndev);
 434	int error;
 435
 436	/* Set CONFIG mode */
 437	error = ravb_config(ndev);
 438	if (error)
 439		return error;
 440
 441	error = ravb_ring_init(ndev, RAVB_BE);
 442	if (error)
 443		return error;
 444	error = ravb_ring_init(ndev, RAVB_NC);
 445	if (error) {
 446		ravb_ring_free(ndev, RAVB_BE);
 447		return error;
 448	}
 449
 450	/* Descriptor format */
 451	ravb_ring_format(ndev, RAVB_BE);
 452	ravb_ring_format(ndev, RAVB_NC);
 453
 454#if defined(__LITTLE_ENDIAN)
 455	ravb_modify(ndev, CCC, CCC_BOC, 0);
 456#else
 457	ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
 458#endif
 459
 460	/* Set AVB RX */
 461	ravb_write(ndev,
 462		   RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
 463
 464	/* Set FIFO size */
 465	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
 466
 467	/* Timestamp enable */
 468	ravb_write(ndev, TCCR_TFEN, TCCR);
 469
 470	/* Interrupt init: */
 471	if (priv->chip_id == RCAR_GEN3) {
 472		/* Clear DIL.DPLx */
 473		ravb_write(ndev, 0, DIL);
 474		/* Set queue specific interrupt */
 475		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
 476	}
 477	/* Frame receive */
 478	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
 479	/* Disable FIFO full warning */
 480	ravb_write(ndev, 0, RIC1);
 481	/* Receive FIFO full error, descriptor empty */
 482	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
 483	/* Frame transmitted, timestamp FIFO updated */
 484	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
 485
 486	/* Setting the control will start the AVB-DMAC process. */
 487	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
 488
 489	return 0;
 490}
 491
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 492static void ravb_get_tx_tstamp(struct net_device *ndev)
 493{
 494	struct ravb_private *priv = netdev_priv(ndev);
 495	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
 496	struct skb_shared_hwtstamps shhwtstamps;
 497	struct sk_buff *skb;
 498	struct timespec64 ts;
 499	u16 tag, tfa_tag;
 500	int count;
 501	u32 tfa2;
 502
 503	count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
 504	while (count--) {
 505		tfa2 = ravb_read(ndev, TFA2);
 506		tfa_tag = (tfa2 & TFA2_TST) >> 16;
 507		ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
 508		ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
 509			    ravb_read(ndev, TFA1);
 510		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 511		shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
 512		list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
 513					 list) {
 514			skb = ts_skb->skb;
 515			tag = ts_skb->tag;
 516			list_del(&ts_skb->list);
 517			kfree(ts_skb);
 518			if (tag == tfa_tag) {
 519				skb_tstamp_tx(skb, &shhwtstamps);
 520				break;
 521			}
 522		}
 523		ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
 524	}
 525}
 526
 527static void ravb_rx_csum(struct sk_buff *skb)
 528{
 529	u8 *hw_csum;
 530
 531	/* The hardware checksum is 2 bytes appended to packet data */
 532	if (unlikely(skb->len < 2))
 533		return;
 534	hw_csum = skb_tail_pointer(skb) - 2;
 535	skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
 536	skb->ip_summed = CHECKSUM_COMPLETE;
 537	skb_trim(skb, skb->len - 2);
 538}
 539
 540/* Packet receive function for Ethernet AVB */
 541static bool ravb_rx(struct net_device *ndev, int *quota, int q)
 542{
 543	struct ravb_private *priv = netdev_priv(ndev);
 544	int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
 545	int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
 546			priv->cur_rx[q];
 547	struct net_device_stats *stats = &priv->stats[q];
 548	struct ravb_ex_rx_desc *desc;
 549	struct sk_buff *skb;
 550	dma_addr_t dma_addr;
 551	struct timespec64 ts;
 552	u8  desc_status;
 553	u16 pkt_len;
 554	int limit;
 555
 556	boguscnt = min(boguscnt, *quota);
 557	limit = boguscnt;
 558	desc = &priv->rx_ring[q][entry];
 559	while (desc->die_dt != DT_FEMPTY) {
 560		/* Descriptor type must be checked before all other reads */
 561		dma_rmb();
 562		desc_status = desc->msc;
 563		pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
 564
 565		if (--boguscnt < 0)
 566			break;
 567
 568		/* We use 0-byte descriptors to mark the DMA mapping errors */
 569		if (!pkt_len)
 570			continue;
 571
 572		if (desc_status & MSC_MC)
 573			stats->multicast++;
 574
 575		if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
 576				   MSC_CEEF)) {
 577			stats->rx_errors++;
 578			if (desc_status & MSC_CRC)
 579				stats->rx_crc_errors++;
 580			if (desc_status & MSC_RFE)
 581				stats->rx_frame_errors++;
 582			if (desc_status & (MSC_RTLF | MSC_RTSF))
 583				stats->rx_length_errors++;
 584			if (desc_status & MSC_CEEF)
 585				stats->rx_missed_errors++;
 586		} else {
 587			u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
 588
 589			skb = priv->rx_skb[q][entry];
 590			priv->rx_skb[q][entry] = NULL;
 591			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
 592					 priv->rx_buf_sz,
 593					 DMA_FROM_DEVICE);
 594			get_ts &= (q == RAVB_NC) ?
 595					RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
 596					~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
 597			if (get_ts) {
 598				struct skb_shared_hwtstamps *shhwtstamps;
 599
 600				shhwtstamps = skb_hwtstamps(skb);
 601				memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 602				ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
 603					     32) | le32_to_cpu(desc->ts_sl);
 604				ts.tv_nsec = le32_to_cpu(desc->ts_n);
 605				shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
 606			}
 607
 608			skb_put(skb, pkt_len);
 609			skb->protocol = eth_type_trans(skb, ndev);
 610			if (ndev->features & NETIF_F_RXCSUM)
 611				ravb_rx_csum(skb);
 612			napi_gro_receive(&priv->napi[q], skb);
 613			stats->rx_packets++;
 614			stats->rx_bytes += pkt_len;
 615		}
 616
 617		entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
 618		desc = &priv->rx_ring[q][entry];
 619	}
 620
 621	/* Refill the RX ring buffers. */
 622	for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
 623		entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
 624		desc = &priv->rx_ring[q][entry];
 625		desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
 
 626
 627		if (!priv->rx_skb[q][entry]) {
 628			skb = netdev_alloc_skb(ndev,
 629					       priv->rx_buf_sz +
 630					       RAVB_ALIGN - 1);
 631			if (!skb)
 632				break;	/* Better luck next round. */
 633			ravb_set_buffer_align(skb);
 634			dma_addr = dma_map_single(ndev->dev.parent, skb->data,
 635						  le16_to_cpu(desc->ds_cc),
 636						  DMA_FROM_DEVICE);
 637			skb_checksum_none_assert(skb);
 638			/* We just set the data size to 0 for a failed mapping
 639			 * which should prevent DMA  from happening...
 640			 */
 641			if (dma_mapping_error(ndev->dev.parent, dma_addr))
 642				desc->ds_cc = cpu_to_le16(0);
 643			desc->dptr = cpu_to_le32(dma_addr);
 644			priv->rx_skb[q][entry] = skb;
 645		}
 646		/* Descriptor type must be set after all the above writes */
 647		dma_wmb();
 648		desc->die_dt = DT_FEMPTY;
 649	}
 650
 651	*quota -= limit - (++boguscnt);
 652
 653	return boguscnt <= 0;
 654}
 655
 656static void ravb_rcv_snd_disable(struct net_device *ndev)
 657{
 658	/* Disable TX and RX */
 659	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
 660}
 661
 662static void ravb_rcv_snd_enable(struct net_device *ndev)
 663{
 664	/* Enable TX and RX */
 665	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
 666}
 667
 668/* function for waiting dma process finished */
 669static int ravb_stop_dma(struct net_device *ndev)
 670{
 671	int error;
 672
 673	/* Wait for stopping the hardware TX process */
 674	error = ravb_wait(ndev, TCCR,
 675			  TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
 676	if (error)
 677		return error;
 678
 679	error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
 680			  0);
 681	if (error)
 682		return error;
 683
 684	/* Stop the E-MAC's RX/TX processes. */
 685	ravb_rcv_snd_disable(ndev);
 686
 687	/* Wait for stopping the RX DMA process */
 688	error = ravb_wait(ndev, CSR, CSR_RPO, 0);
 689	if (error)
 690		return error;
 691
 692	/* Stop AVB-DMAC process */
 693	return ravb_config(ndev);
 694}
 695
 696/* E-MAC interrupt handler */
 697static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
 698{
 699	struct ravb_private *priv = netdev_priv(ndev);
 700	u32 ecsr, psr;
 701
 702	ecsr = ravb_read(ndev, ECSR);
 703	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */
 704
 705	if (ecsr & ECSR_MPD)
 706		pm_wakeup_event(&priv->pdev->dev, 0);
 707	if (ecsr & ECSR_ICD)
 708		ndev->stats.tx_carrier_errors++;
 709	if (ecsr & ECSR_LCHNG) {
 710		/* Link changed */
 711		if (priv->no_avb_link)
 712			return;
 713		psr = ravb_read(ndev, PSR);
 714		if (priv->avb_link_active_low)
 715			psr ^= PSR_LMON;
 716		if (!(psr & PSR_LMON)) {
 717			/* DIsable RX and TX */
 718			ravb_rcv_snd_disable(ndev);
 719		} else {
 720			/* Enable RX and TX */
 721			ravb_rcv_snd_enable(ndev);
 722		}
 723	}
 724}
 725
 726static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
 727{
 728	struct net_device *ndev = dev_id;
 729	struct ravb_private *priv = netdev_priv(ndev);
 730
 731	spin_lock(&priv->lock);
 732	ravb_emac_interrupt_unlocked(ndev);
 733	mmiowb();
 734	spin_unlock(&priv->lock);
 735	return IRQ_HANDLED;
 736}
 737
 738/* Error interrupt handler */
 739static void ravb_error_interrupt(struct net_device *ndev)
 740{
 741	struct ravb_private *priv = netdev_priv(ndev);
 742	u32 eis, ris2;
 743
 744	eis = ravb_read(ndev, EIS);
 745	ravb_write(ndev, ~EIS_QFS, EIS);
 746	if (eis & EIS_QFS) {
 747		ris2 = ravb_read(ndev, RIS2);
 748		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
 749
 750		/* Receive Descriptor Empty int */
 751		if (ris2 & RIS2_QFF0)
 752			priv->stats[RAVB_BE].rx_over_errors++;
 753
 754		    /* Receive Descriptor Empty int */
 755		if (ris2 & RIS2_QFF1)
 756			priv->stats[RAVB_NC].rx_over_errors++;
 757
 758		/* Receive FIFO Overflow int */
 759		if (ris2 & RIS2_RFFF)
 760			priv->rx_fifo_errors++;
 761	}
 762}
 763
 764static bool ravb_queue_interrupt(struct net_device *ndev, int q)
 765{
 766	struct ravb_private *priv = netdev_priv(ndev);
 767	u32 ris0 = ravb_read(ndev, RIS0);
 768	u32 ric0 = ravb_read(ndev, RIC0);
 769	u32 tis  = ravb_read(ndev, TIS);
 770	u32 tic  = ravb_read(ndev, TIC);
 771
 772	if (((ris0 & ric0) & BIT(q)) || ((tis  & tic)  & BIT(q))) {
 773		if (napi_schedule_prep(&priv->napi[q])) {
 774			/* Mask RX and TX interrupts */
 775			if (priv->chip_id == RCAR_GEN2) {
 776				ravb_write(ndev, ric0 & ~BIT(q), RIC0);
 777				ravb_write(ndev, tic & ~BIT(q), TIC);
 778			} else {
 779				ravb_write(ndev, BIT(q), RID0);
 780				ravb_write(ndev, BIT(q), TID);
 781			}
 782			__napi_schedule(&priv->napi[q]);
 783		} else {
 784			netdev_warn(ndev,
 785				    "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
 786				    ris0, ric0);
 787			netdev_warn(ndev,
 788				    "                    tx status 0x%08x, tx mask 0x%08x.\n",
 789				    tis, tic);
 790		}
 791		return true;
 792	}
 793	return false;
 794}
 795
 796static bool ravb_timestamp_interrupt(struct net_device *ndev)
 797{
 798	u32 tis = ravb_read(ndev, TIS);
 799
 800	if (tis & TIS_TFUF) {
 801		ravb_write(ndev, ~TIS_TFUF, TIS);
 802		ravb_get_tx_tstamp(ndev);
 803		return true;
 804	}
 805	return false;
 806}
 807
 808static irqreturn_t ravb_interrupt(int irq, void *dev_id)
 809{
 810	struct net_device *ndev = dev_id;
 811	struct ravb_private *priv = netdev_priv(ndev);
 812	irqreturn_t result = IRQ_NONE;
 813	u32 iss;
 814
 815	spin_lock(&priv->lock);
 816	/* Get interrupt status */
 817	iss = ravb_read(ndev, ISS);
 818
 819	/* Received and transmitted interrupts */
 820	if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
 
 
 
 
 821		int q;
 822
 823		/* Timestamp updated */
 824		if (ravb_timestamp_interrupt(ndev))
 
 
 825			result = IRQ_HANDLED;
 
 826
 827		/* Network control and best effort queue RX/TX */
 828		for (q = RAVB_NC; q >= RAVB_BE; q--) {
 829			if (ravb_queue_interrupt(ndev, q))
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 830				result = IRQ_HANDLED;
 
 831		}
 832	}
 833
 834	/* E-MAC status summary */
 835	if (iss & ISS_MS) {
 836		ravb_emac_interrupt_unlocked(ndev);
 837		result = IRQ_HANDLED;
 838	}
 839
 840	/* Error status summary */
 841	if (iss & ISS_ES) {
 842		ravb_error_interrupt(ndev);
 843		result = IRQ_HANDLED;
 844	}
 845
 846	/* gPTP interrupt status summary */
 847	if (iss & ISS_CGIS) {
 848		ravb_ptp_interrupt(ndev);
 849		result = IRQ_HANDLED;
 850	}
 851
 852	mmiowb();
 853	spin_unlock(&priv->lock);
 854	return result;
 855}
 856
 857/* Timestamp/Error/gPTP interrupt handler */
 858static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
 859{
 860	struct net_device *ndev = dev_id;
 861	struct ravb_private *priv = netdev_priv(ndev);
 862	irqreturn_t result = IRQ_NONE;
 863	u32 iss;
 864
 865	spin_lock(&priv->lock);
 866	/* Get interrupt status */
 867	iss = ravb_read(ndev, ISS);
 868
 869	/* Timestamp updated */
 870	if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
 871		result = IRQ_HANDLED;
 872
 873	/* Error status summary */
 874	if (iss & ISS_ES) {
 875		ravb_error_interrupt(ndev);
 876		result = IRQ_HANDLED;
 877	}
 878
 879	/* gPTP interrupt status summary */
 880	if (iss & ISS_CGIS) {
 881		ravb_ptp_interrupt(ndev);
 882		result = IRQ_HANDLED;
 883	}
 884
 885	mmiowb();
 886	spin_unlock(&priv->lock);
 887	return result;
 888}
 889
 890static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
 891{
 892	struct net_device *ndev = dev_id;
 893	struct ravb_private *priv = netdev_priv(ndev);
 894	irqreturn_t result = IRQ_NONE;
 895
 896	spin_lock(&priv->lock);
 897
 898	/* Network control/Best effort queue RX/TX */
 899	if (ravb_queue_interrupt(ndev, q))
 900		result = IRQ_HANDLED;
 901
 902	mmiowb();
 903	spin_unlock(&priv->lock);
 904	return result;
 905}
 906
 907static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
 908{
 909	return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
 910}
 911
 912static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
 913{
 914	return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
 915}
 916
 917static int ravb_poll(struct napi_struct *napi, int budget)
 918{
 919	struct net_device *ndev = napi->dev;
 920	struct ravb_private *priv = netdev_priv(ndev);
 921	unsigned long flags;
 922	int q = napi - priv->napi;
 923	int mask = BIT(q);
 924	int quota = budget;
 925	u32 ris0, tis;
 926
 927	for (;;) {
 928		tis = ravb_read(ndev, TIS);
 929		ris0 = ravb_read(ndev, RIS0);
 930		if (!((ris0 & mask) || (tis & mask)))
 931			break;
 932
 933		/* Processing RX Descriptor Ring */
 934		if (ris0 & mask) {
 935			/* Clear RX interrupt */
 936			ravb_write(ndev, ~mask, RIS0);
 937			if (ravb_rx(ndev, &quota, q))
 938				goto out;
 939		}
 940		/* Processing TX Descriptor Ring */
 941		if (tis & mask) {
 942			spin_lock_irqsave(&priv->lock, flags);
 943			/* Clear TX interrupt */
 944			ravb_write(ndev, ~mask, TIS);
 945			ravb_tx_free(ndev, q, true);
 946			netif_wake_subqueue(ndev, q);
 947			mmiowb();
 948			spin_unlock_irqrestore(&priv->lock, flags);
 949		}
 950	}
 951
 952	napi_complete(napi);
 953
 954	/* Re-enable RX/TX interrupts */
 955	spin_lock_irqsave(&priv->lock, flags);
 956	if (priv->chip_id == RCAR_GEN2) {
 957		ravb_modify(ndev, RIC0, mask, mask);
 958		ravb_modify(ndev, TIC,  mask, mask);
 959	} else {
 960		ravb_write(ndev, mask, RIE0);
 961		ravb_write(ndev, mask, TIE);
 962	}
 963	mmiowb();
 964	spin_unlock_irqrestore(&priv->lock, flags);
 965
 966	/* Receive error message handling */
 967	priv->rx_over_errors =  priv->stats[RAVB_BE].rx_over_errors;
 968	priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
 969	if (priv->rx_over_errors != ndev->stats.rx_over_errors)
 970		ndev->stats.rx_over_errors = priv->rx_over_errors;
 971	if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
 
 
 972		ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
 
 
 973out:
 974	return budget - quota;
 975}
 976
 977/* PHY state control function */
 978static void ravb_adjust_link(struct net_device *ndev)
 979{
 980	struct ravb_private *priv = netdev_priv(ndev);
 981	struct phy_device *phydev = ndev->phydev;
 982	bool new_state = false;
 983
 984	if (phydev->link) {
 985		if (phydev->duplex != priv->duplex) {
 986			new_state = true;
 987			priv->duplex = phydev->duplex;
 988			ravb_set_duplex(ndev);
 989		}
 990
 991		if (phydev->speed != priv->speed) {
 992			new_state = true;
 993			priv->speed = phydev->speed;
 994			ravb_set_rate(ndev);
 995		}
 996		if (!priv->link) {
 997			ravb_modify(ndev, ECMR, ECMR_TXF, 0);
 998			new_state = true;
 999			priv->link = phydev->link;
1000			if (priv->no_avb_link)
1001				ravb_rcv_snd_enable(ndev);
1002		}
1003	} else if (priv->link) {
1004		new_state = true;
1005		priv->link = 0;
1006		priv->speed = 0;
1007		priv->duplex = -1;
1008		if (priv->no_avb_link)
1009			ravb_rcv_snd_disable(ndev);
1010	}
1011
1012	if (new_state && netif_msg_link(priv))
1013		phy_print_status(phydev);
1014}
1015
1016static const struct soc_device_attribute r8a7795es10[] = {
1017	{ .soc_id = "r8a7795", .revision = "ES1.0", },
1018	{ /* sentinel */ }
1019};
1020
1021/* PHY init function */
1022static int ravb_phy_init(struct net_device *ndev)
1023{
1024	struct device_node *np = ndev->dev.parent->of_node;
1025	struct ravb_private *priv = netdev_priv(ndev);
1026	struct phy_device *phydev;
1027	struct device_node *pn;
1028	int err;
1029
1030	priv->link = 0;
1031	priv->speed = 0;
1032	priv->duplex = -1;
1033
1034	/* Try connecting to PHY */
1035	pn = of_parse_phandle(np, "phy-handle", 0);
1036	if (!pn) {
1037		/* In the case of a fixed PHY, the DT node associated
1038		 * to the PHY is the Ethernet MAC DT node.
1039		 */
1040		if (of_phy_is_fixed_link(np)) {
1041			err = of_phy_register_fixed_link(np);
1042			if (err)
1043				return err;
1044		}
1045		pn = of_node_get(np);
1046	}
1047	phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1048				priv->phy_interface);
1049	of_node_put(pn);
1050	if (!phydev) {
1051		netdev_err(ndev, "failed to connect PHY\n");
1052		err = -ENOENT;
1053		goto err_deregister_fixed_link;
1054	}
1055
1056	/* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1057	 * at this time.
1058	 */
1059	if (soc_device_match(r8a7795es10)) {
 
 
1060		err = phy_set_max_speed(phydev, SPEED_100);
1061		if (err) {
1062			netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1063			goto err_phy_disconnect;
 
1064		}
1065
1066		netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1067	}
1068
1069	/* 10BASE is not supported */
1070	phydev->supported &= ~PHY_10BT_FEATURES;
1071
1072	phy_attached_info(phydev);
1073
1074	return 0;
1075
1076err_phy_disconnect:
1077	phy_disconnect(phydev);
1078err_deregister_fixed_link:
1079	if (of_phy_is_fixed_link(np))
1080		of_phy_deregister_fixed_link(np);
1081
1082	return err;
1083}
1084
1085/* PHY control start function */
1086static int ravb_phy_start(struct net_device *ndev)
1087{
 
1088	int error;
1089
1090	error = ravb_phy_init(ndev);
1091	if (error)
1092		return error;
1093
1094	phy_start(ndev->phydev);
1095
1096	return 0;
1097}
1098
1099static int ravb_get_link_ksettings(struct net_device *ndev,
1100				   struct ethtool_link_ksettings *cmd)
1101{
1102	struct ravb_private *priv = netdev_priv(ndev);
 
1103	unsigned long flags;
1104
1105	if (!ndev->phydev)
1106		return -ENODEV;
1107
1108	spin_lock_irqsave(&priv->lock, flags);
1109	phy_ethtool_ksettings_get(ndev->phydev, cmd);
1110	spin_unlock_irqrestore(&priv->lock, flags);
1111
1112	return 0;
1113}
1114
1115static int ravb_set_link_ksettings(struct net_device *ndev,
1116				   const struct ethtool_link_ksettings *cmd)
1117{
1118	struct ravb_private *priv = netdev_priv(ndev);
1119	unsigned long flags;
1120	int error;
1121
1122	if (!ndev->phydev)
1123		return -ENODEV;
1124
1125	spin_lock_irqsave(&priv->lock, flags);
1126
1127	/* Disable TX and RX */
1128	ravb_rcv_snd_disable(ndev);
1129
1130	error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1131	if (error)
1132		goto error_exit;
1133
1134	if (cmd->base.duplex == DUPLEX_FULL)
1135		priv->duplex = 1;
1136	else
1137		priv->duplex = 0;
1138
1139	ravb_set_duplex(ndev);
1140
1141error_exit:
1142	mdelay(1);
1143
1144	/* Enable TX and RX */
1145	ravb_rcv_snd_enable(ndev);
1146
1147	mmiowb();
1148	spin_unlock_irqrestore(&priv->lock, flags);
1149
1150	return error;
1151}
1152
1153static int ravb_nway_reset(struct net_device *ndev)
1154{
1155	struct ravb_private *priv = netdev_priv(ndev);
1156	int error = -ENODEV;
1157	unsigned long flags;
1158
1159	if (ndev->phydev) {
1160		spin_lock_irqsave(&priv->lock, flags);
1161		error = phy_start_aneg(ndev->phydev);
1162		spin_unlock_irqrestore(&priv->lock, flags);
1163	}
1164
1165	return error;
1166}
1167
1168static u32 ravb_get_msglevel(struct net_device *ndev)
1169{
1170	struct ravb_private *priv = netdev_priv(ndev);
1171
1172	return priv->msg_enable;
1173}
1174
1175static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1176{
1177	struct ravb_private *priv = netdev_priv(ndev);
1178
1179	priv->msg_enable = value;
1180}
1181
1182static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1183	"rx_queue_0_current",
1184	"tx_queue_0_current",
1185	"rx_queue_0_dirty",
1186	"tx_queue_0_dirty",
1187	"rx_queue_0_packets",
1188	"tx_queue_0_packets",
1189	"rx_queue_0_bytes",
1190	"tx_queue_0_bytes",
1191	"rx_queue_0_mcast_packets",
1192	"rx_queue_0_errors",
1193	"rx_queue_0_crc_errors",
1194	"rx_queue_0_frame_errors",
1195	"rx_queue_0_length_errors",
1196	"rx_queue_0_missed_errors",
1197	"rx_queue_0_over_errors",
1198
1199	"rx_queue_1_current",
1200	"tx_queue_1_current",
1201	"rx_queue_1_dirty",
1202	"tx_queue_1_dirty",
1203	"rx_queue_1_packets",
1204	"tx_queue_1_packets",
1205	"rx_queue_1_bytes",
1206	"tx_queue_1_bytes",
1207	"rx_queue_1_mcast_packets",
1208	"rx_queue_1_errors",
1209	"rx_queue_1_crc_errors",
1210	"rx_queue_1_frame_errors",
1211	"rx_queue_1_length_errors",
1212	"rx_queue_1_missed_errors",
1213	"rx_queue_1_over_errors",
1214};
1215
1216#define RAVB_STATS_LEN	ARRAY_SIZE(ravb_gstrings_stats)
1217
1218static int ravb_get_sset_count(struct net_device *netdev, int sset)
1219{
1220	switch (sset) {
1221	case ETH_SS_STATS:
1222		return RAVB_STATS_LEN;
1223	default:
1224		return -EOPNOTSUPP;
1225	}
1226}
1227
1228static void ravb_get_ethtool_stats(struct net_device *ndev,
1229				   struct ethtool_stats *stats, u64 *data)
1230{
1231	struct ravb_private *priv = netdev_priv(ndev);
1232	int i = 0;
1233	int q;
1234
1235	/* Device-specific stats */
1236	for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1237		struct net_device_stats *stats = &priv->stats[q];
1238
1239		data[i++] = priv->cur_rx[q];
1240		data[i++] = priv->cur_tx[q];
1241		data[i++] = priv->dirty_rx[q];
1242		data[i++] = priv->dirty_tx[q];
1243		data[i++] = stats->rx_packets;
1244		data[i++] = stats->tx_packets;
1245		data[i++] = stats->rx_bytes;
1246		data[i++] = stats->tx_bytes;
1247		data[i++] = stats->multicast;
1248		data[i++] = stats->rx_errors;
1249		data[i++] = stats->rx_crc_errors;
1250		data[i++] = stats->rx_frame_errors;
1251		data[i++] = stats->rx_length_errors;
1252		data[i++] = stats->rx_missed_errors;
1253		data[i++] = stats->rx_over_errors;
1254	}
1255}
1256
1257static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1258{
1259	switch (stringset) {
1260	case ETH_SS_STATS:
1261		memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1262		break;
1263	}
1264}
1265
1266static void ravb_get_ringparam(struct net_device *ndev,
1267			       struct ethtool_ringparam *ring)
1268{
1269	struct ravb_private *priv = netdev_priv(ndev);
1270
1271	ring->rx_max_pending = BE_RX_RING_MAX;
1272	ring->tx_max_pending = BE_TX_RING_MAX;
1273	ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1274	ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1275}
1276
1277static int ravb_set_ringparam(struct net_device *ndev,
1278			      struct ethtool_ringparam *ring)
1279{
1280	struct ravb_private *priv = netdev_priv(ndev);
1281	int error;
1282
1283	if (ring->tx_pending > BE_TX_RING_MAX ||
1284	    ring->rx_pending > BE_RX_RING_MAX ||
1285	    ring->tx_pending < BE_TX_RING_MIN ||
1286	    ring->rx_pending < BE_RX_RING_MIN)
1287		return -EINVAL;
1288	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1289		return -EINVAL;
1290
1291	if (netif_running(ndev)) {
1292		netif_device_detach(ndev);
1293		/* Stop PTP Clock driver */
1294		if (priv->chip_id == RCAR_GEN2)
1295			ravb_ptp_stop(ndev);
1296		/* Wait for DMA stopping */
1297		error = ravb_stop_dma(ndev);
1298		if (error) {
1299			netdev_err(ndev,
1300				   "cannot set ringparam! Any AVB processes are still running?\n");
1301			return error;
1302		}
1303		synchronize_irq(ndev->irq);
1304
1305		/* Free all the skb's in the RX queue and the DMA buffers. */
1306		ravb_ring_free(ndev, RAVB_BE);
1307		ravb_ring_free(ndev, RAVB_NC);
1308	}
1309
1310	/* Set new parameters */
1311	priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1312	priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1313
1314	if (netif_running(ndev)) {
1315		error = ravb_dmac_init(ndev);
1316		if (error) {
1317			netdev_err(ndev,
1318				   "%s: ravb_dmac_init() failed, error %d\n",
1319				   __func__, error);
1320			return error;
1321		}
1322
1323		ravb_emac_init(ndev);
1324
1325		/* Initialise PTP Clock driver */
1326		if (priv->chip_id == RCAR_GEN2)
1327			ravb_ptp_init(ndev, priv->pdev);
1328
1329		netif_device_attach(ndev);
1330	}
1331
1332	return 0;
1333}
1334
1335static int ravb_get_ts_info(struct net_device *ndev,
1336			    struct ethtool_ts_info *info)
1337{
1338	struct ravb_private *priv = netdev_priv(ndev);
1339
1340	info->so_timestamping =
1341		SOF_TIMESTAMPING_TX_SOFTWARE |
1342		SOF_TIMESTAMPING_RX_SOFTWARE |
1343		SOF_TIMESTAMPING_SOFTWARE |
1344		SOF_TIMESTAMPING_TX_HARDWARE |
1345		SOF_TIMESTAMPING_RX_HARDWARE |
1346		SOF_TIMESTAMPING_RAW_HARDWARE;
1347	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1348	info->rx_filters =
1349		(1 << HWTSTAMP_FILTER_NONE) |
1350		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1351		(1 << HWTSTAMP_FILTER_ALL);
1352	info->phc_index = ptp_clock_index(priv->ptp.clock);
1353
1354	return 0;
1355}
1356
1357static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1358{
1359	struct ravb_private *priv = netdev_priv(ndev);
1360
1361	wol->supported = WAKE_MAGIC;
1362	wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1363}
1364
1365static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1366{
1367	struct ravb_private *priv = netdev_priv(ndev);
1368
1369	if (wol->wolopts & ~WAKE_MAGIC)
1370		return -EOPNOTSUPP;
1371
1372	priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1373
1374	device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1375
1376	return 0;
1377}
1378
1379static const struct ethtool_ops ravb_ethtool_ops = {
 
 
1380	.nway_reset		= ravb_nway_reset,
1381	.get_msglevel		= ravb_get_msglevel,
1382	.set_msglevel		= ravb_set_msglevel,
1383	.get_link		= ethtool_op_get_link,
1384	.get_strings		= ravb_get_strings,
1385	.get_ethtool_stats	= ravb_get_ethtool_stats,
1386	.get_sset_count		= ravb_get_sset_count,
1387	.get_ringparam		= ravb_get_ringparam,
1388	.set_ringparam		= ravb_set_ringparam,
1389	.get_ts_info		= ravb_get_ts_info,
1390	.get_link_ksettings	= ravb_get_link_ksettings,
1391	.set_link_ksettings	= ravb_set_link_ksettings,
1392	.get_wol		= ravb_get_wol,
1393	.set_wol		= ravb_set_wol,
1394};
1395
1396static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1397				struct net_device *ndev, struct device *dev,
1398				const char *ch)
1399{
1400	char *name;
1401	int error;
1402
1403	name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1404	if (!name)
1405		return -ENOMEM;
1406	error = request_irq(irq, handler, 0, name, ndev);
1407	if (error)
1408		netdev_err(ndev, "cannot request IRQ %s\n", name);
1409
1410	return error;
1411}
1412
1413/* Network device open function for Ethernet AVB */
1414static int ravb_open(struct net_device *ndev)
1415{
1416	struct ravb_private *priv = netdev_priv(ndev);
1417	struct platform_device *pdev = priv->pdev;
1418	struct device *dev = &pdev->dev;
1419	int error;
1420
1421	napi_enable(&priv->napi[RAVB_BE]);
1422	napi_enable(&priv->napi[RAVB_NC]);
1423
1424	if (priv->chip_id == RCAR_GEN2) {
1425		error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1426				    ndev->name, ndev);
 
 
 
 
 
 
 
1427		if (error) {
1428			netdev_err(ndev, "cannot request IRQ\n");
1429			goto out_napi_off;
1430		}
1431	} else {
1432		error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1433				      dev, "ch22:multi");
1434		if (error)
1435			goto out_napi_off;
1436		error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1437				      dev, "ch24:emac");
1438		if (error)
1439			goto out_free_irq;
1440		error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1441				      ndev, dev, "ch0:rx_be");
1442		if (error)
1443			goto out_free_irq_emac;
1444		error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1445				      ndev, dev, "ch18:tx_be");
1446		if (error)
1447			goto out_free_irq_be_rx;
1448		error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1449				      ndev, dev, "ch1:rx_nc");
1450		if (error)
1451			goto out_free_irq_be_tx;
1452		error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1453				      ndev, dev, "ch19:tx_nc");
1454		if (error)
1455			goto out_free_irq_nc_rx;
1456	}
1457
1458	/* Device init */
1459	error = ravb_dmac_init(ndev);
1460	if (error)
1461		goto out_free_irq_nc_tx;
1462	ravb_emac_init(ndev);
1463
1464	/* Initialise PTP Clock driver */
1465	if (priv->chip_id == RCAR_GEN2)
1466		ravb_ptp_init(ndev, priv->pdev);
1467
1468	netif_tx_start_all_queues(ndev);
1469
1470	/* PHY control start */
1471	error = ravb_phy_start(ndev);
1472	if (error)
1473		goto out_ptp_stop;
1474
1475	return 0;
1476
1477out_ptp_stop:
1478	/* Stop PTP Clock driver */
1479	if (priv->chip_id == RCAR_GEN2)
1480		ravb_ptp_stop(ndev);
1481out_free_irq_nc_tx:
1482	if (priv->chip_id == RCAR_GEN2)
1483		goto out_free_irq;
1484	free_irq(priv->tx_irqs[RAVB_NC], ndev);
1485out_free_irq_nc_rx:
1486	free_irq(priv->rx_irqs[RAVB_NC], ndev);
1487out_free_irq_be_tx:
1488	free_irq(priv->tx_irqs[RAVB_BE], ndev);
1489out_free_irq_be_rx:
1490	free_irq(priv->rx_irqs[RAVB_BE], ndev);
1491out_free_irq_emac:
1492	free_irq(priv->emac_irq, ndev);
1493out_free_irq:
1494	free_irq(ndev->irq, ndev);
1495out_napi_off:
1496	napi_disable(&priv->napi[RAVB_NC]);
1497	napi_disable(&priv->napi[RAVB_BE]);
1498	return error;
1499}
1500
1501/* Timeout function for Ethernet AVB */
1502static void ravb_tx_timeout(struct net_device *ndev)
1503{
1504	struct ravb_private *priv = netdev_priv(ndev);
1505
1506	netif_err(priv, tx_err, ndev,
1507		  "transmit timed out, status %08x, resetting...\n",
1508		  ravb_read(ndev, ISS));
1509
1510	/* tx_errors count up */
1511	ndev->stats.tx_errors++;
1512
1513	schedule_work(&priv->work);
1514}
1515
1516static void ravb_tx_timeout_work(struct work_struct *work)
1517{
1518	struct ravb_private *priv = container_of(work, struct ravb_private,
1519						 work);
1520	struct net_device *ndev = priv->ndev;
1521
1522	netif_tx_stop_all_queues(ndev);
1523
1524	/* Stop PTP Clock driver */
1525	if (priv->chip_id == RCAR_GEN2)
1526		ravb_ptp_stop(ndev);
1527
1528	/* Wait for DMA stopping */
1529	ravb_stop_dma(ndev);
1530
1531	ravb_ring_free(ndev, RAVB_BE);
1532	ravb_ring_free(ndev, RAVB_NC);
1533
1534	/* Device init */
1535	ravb_dmac_init(ndev);
1536	ravb_emac_init(ndev);
1537
1538	/* Initialise PTP Clock driver */
1539	if (priv->chip_id == RCAR_GEN2)
1540		ravb_ptp_init(ndev, priv->pdev);
1541
1542	netif_tx_start_all_queues(ndev);
1543}
1544
1545/* Packet transmit function for Ethernet AVB */
1546static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1547{
1548	struct ravb_private *priv = netdev_priv(ndev);
1549	u16 q = skb_get_queue_mapping(skb);
1550	struct ravb_tstamp_skb *ts_skb;
1551	struct ravb_tx_desc *desc;
1552	unsigned long flags;
1553	u32 dma_addr;
1554	void *buffer;
1555	u32 entry;
1556	u32 len;
1557
1558	spin_lock_irqsave(&priv->lock, flags);
1559	if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1560	    NUM_TX_DESC) {
1561		netif_err(priv, tx_queued, ndev,
1562			  "still transmitting with the full ring!\n");
1563		netif_stop_subqueue(ndev, q);
1564		spin_unlock_irqrestore(&priv->lock, flags);
1565		return NETDEV_TX_BUSY;
1566	}
1567
1568	if (skb_put_padto(skb, ETH_ZLEN))
1569		goto exit;
1570
1571	entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1572	priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1573
 
 
 
1574	buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1575		 entry / NUM_TX_DESC * DPTR_ALIGN;
1576	len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1577	/* Zero length DMA descriptors are problematic as they seem to
1578	 * terminate DMA transfers. Avoid them by simply using a length of
1579	 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1580	 *
1581	 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1582	 * data by the call to skb_put_padto() above this is safe with
1583	 * respect to both the length of the first DMA descriptor (len)
1584	 * overflowing the available data and the length of the second DMA
1585	 * descriptor (skb->len - len) being negative.
1586	 */
1587	if (len == 0)
1588		len = DPTR_ALIGN;
1589
1590	memcpy(buffer, skb->data, len);
1591	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1592	if (dma_mapping_error(ndev->dev.parent, dma_addr))
1593		goto drop;
1594
1595	desc = &priv->tx_ring[q][entry];
1596	desc->ds_tagl = cpu_to_le16(len);
1597	desc->dptr = cpu_to_le32(dma_addr);
1598
1599	buffer = skb->data + len;
1600	len = skb->len - len;
1601	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1602	if (dma_mapping_error(ndev->dev.parent, dma_addr))
1603		goto unmap;
1604
1605	desc++;
1606	desc->ds_tagl = cpu_to_le16(len);
1607	desc->dptr = cpu_to_le32(dma_addr);
1608
1609	/* TX timestamp required */
1610	if (q == RAVB_NC) {
1611		ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1612		if (!ts_skb) {
1613			desc--;
1614			dma_unmap_single(ndev->dev.parent, dma_addr, len,
1615					 DMA_TO_DEVICE);
1616			goto unmap;
1617		}
1618		ts_skb->skb = skb;
1619		ts_skb->tag = priv->ts_skb_tag++;
1620		priv->ts_skb_tag &= 0x3ff;
1621		list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1622
1623		/* TAG and timestamp required flag */
1624		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1625		desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1626		desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1627	}
1628
1629	skb_tx_timestamp(skb);
1630	/* Descriptor type must be set after all the above writes */
1631	dma_wmb();
1632	desc->die_dt = DT_FEND;
1633	desc--;
1634	desc->die_dt = DT_FSTART;
1635
1636	ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1637
1638	priv->cur_tx[q] += NUM_TX_DESC;
1639	if (priv->cur_tx[q] - priv->dirty_tx[q] >
1640	    (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1641	    !ravb_tx_free(ndev, q, true))
1642		netif_stop_subqueue(ndev, q);
1643
1644exit:
1645	mmiowb();
1646	spin_unlock_irqrestore(&priv->lock, flags);
1647	return NETDEV_TX_OK;
1648
1649unmap:
1650	dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1651			 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1652drop:
1653	dev_kfree_skb_any(skb);
1654	priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1655	goto exit;
1656}
1657
1658static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1659			     void *accel_priv, select_queue_fallback_t fallback)
1660{
1661	/* If skb needs TX timestamp, it is handled in network control queue */
1662	return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1663							       RAVB_BE;
1664
1665}
1666
1667static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1668{
1669	struct ravb_private *priv = netdev_priv(ndev);
1670	struct net_device_stats *nstats, *stats0, *stats1;
1671
1672	nstats = &ndev->stats;
1673	stats0 = &priv->stats[RAVB_BE];
1674	stats1 = &priv->stats[RAVB_NC];
1675
1676	nstats->tx_dropped += ravb_read(ndev, TROCR);
1677	ravb_write(ndev, 0, TROCR);	/* (write clear) */
1678	nstats->collisions += ravb_read(ndev, CDCR);
1679	ravb_write(ndev, 0, CDCR);	/* (write clear) */
1680	nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1681	ravb_write(ndev, 0, LCCR);	/* (write clear) */
1682
1683	nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1684	ravb_write(ndev, 0, CERCR);	/* (write clear) */
1685	nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1686	ravb_write(ndev, 0, CEECR);	/* (write clear) */
1687
1688	nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1689	nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1690	nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1691	nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1692	nstats->multicast = stats0->multicast + stats1->multicast;
1693	nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1694	nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1695	nstats->rx_frame_errors =
1696		stats0->rx_frame_errors + stats1->rx_frame_errors;
1697	nstats->rx_length_errors =
1698		stats0->rx_length_errors + stats1->rx_length_errors;
1699	nstats->rx_missed_errors =
1700		stats0->rx_missed_errors + stats1->rx_missed_errors;
1701	nstats->rx_over_errors =
1702		stats0->rx_over_errors + stats1->rx_over_errors;
1703
1704	return nstats;
1705}
1706
1707/* Update promiscuous bit */
1708static void ravb_set_rx_mode(struct net_device *ndev)
1709{
1710	struct ravb_private *priv = netdev_priv(ndev);
1711	unsigned long flags;
1712
1713	spin_lock_irqsave(&priv->lock, flags);
1714	ravb_modify(ndev, ECMR, ECMR_PRM,
1715		    ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1716	mmiowb();
1717	spin_unlock_irqrestore(&priv->lock, flags);
1718}
1719
1720/* Device close function for Ethernet AVB */
1721static int ravb_close(struct net_device *ndev)
1722{
1723	struct device_node *np = ndev->dev.parent->of_node;
1724	struct ravb_private *priv = netdev_priv(ndev);
1725	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1726
1727	netif_tx_stop_all_queues(ndev);
1728
1729	/* Disable interrupts by clearing the interrupt masks. */
1730	ravb_write(ndev, 0, RIC0);
1731	ravb_write(ndev, 0, RIC2);
1732	ravb_write(ndev, 0, TIC);
1733
1734	/* Stop PTP Clock driver */
1735	if (priv->chip_id == RCAR_GEN2)
1736		ravb_ptp_stop(ndev);
1737
1738	/* Set the config mode to stop the AVB-DMAC's processes */
1739	if (ravb_stop_dma(ndev) < 0)
1740		netdev_err(ndev,
1741			   "device will be stopped after h/w processes are done.\n");
1742
1743	/* Clear the timestamp list */
1744	list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1745		list_del(&ts_skb->list);
1746		kfree(ts_skb);
1747	}
1748
1749	/* PHY disconnect */
1750	if (ndev->phydev) {
1751		phy_stop(ndev->phydev);
1752		phy_disconnect(ndev->phydev);
1753		if (of_phy_is_fixed_link(np))
1754			of_phy_deregister_fixed_link(np);
1755	}
1756
1757	if (priv->chip_id != RCAR_GEN2) {
1758		free_irq(priv->tx_irqs[RAVB_NC], ndev);
1759		free_irq(priv->rx_irqs[RAVB_NC], ndev);
1760		free_irq(priv->tx_irqs[RAVB_BE], ndev);
1761		free_irq(priv->rx_irqs[RAVB_BE], ndev);
1762		free_irq(priv->emac_irq, ndev);
1763	}
1764	free_irq(ndev->irq, ndev);
1765
1766	napi_disable(&priv->napi[RAVB_NC]);
1767	napi_disable(&priv->napi[RAVB_BE]);
1768
1769	/* Free all the skb's in the RX queue and the DMA buffers. */
1770	ravb_ring_free(ndev, RAVB_BE);
1771	ravb_ring_free(ndev, RAVB_NC);
1772
1773	return 0;
1774}
1775
1776static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1777{
1778	struct ravb_private *priv = netdev_priv(ndev);
1779	struct hwtstamp_config config;
1780
1781	config.flags = 0;
1782	config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1783						HWTSTAMP_TX_OFF;
1784	if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1785		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1786	else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1787		config.rx_filter = HWTSTAMP_FILTER_ALL;
1788	else
1789		config.rx_filter = HWTSTAMP_FILTER_NONE;
1790
1791	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1792		-EFAULT : 0;
1793}
1794
1795/* Control hardware time stamping */
1796static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1797{
1798	struct ravb_private *priv = netdev_priv(ndev);
1799	struct hwtstamp_config config;
1800	u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1801	u32 tstamp_tx_ctrl;
1802
1803	if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1804		return -EFAULT;
1805
1806	/* Reserved for future extensions */
1807	if (config.flags)
1808		return -EINVAL;
1809
1810	switch (config.tx_type) {
1811	case HWTSTAMP_TX_OFF:
1812		tstamp_tx_ctrl = 0;
1813		break;
1814	case HWTSTAMP_TX_ON:
1815		tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1816		break;
1817	default:
1818		return -ERANGE;
1819	}
1820
1821	switch (config.rx_filter) {
1822	case HWTSTAMP_FILTER_NONE:
1823		tstamp_rx_ctrl = 0;
1824		break;
1825	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1826		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1827		break;
1828	default:
1829		config.rx_filter = HWTSTAMP_FILTER_ALL;
1830		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1831	}
1832
1833	priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1834	priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1835
1836	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1837		-EFAULT : 0;
1838}
1839
1840/* ioctl to device function */
1841static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1842{
1843	struct phy_device *phydev = ndev->phydev;
 
1844
1845	if (!netif_running(ndev))
1846		return -EINVAL;
1847
1848	if (!phydev)
1849		return -ENODEV;
1850
1851	switch (cmd) {
1852	case SIOCGHWTSTAMP:
1853		return ravb_hwtstamp_get(ndev, req);
1854	case SIOCSHWTSTAMP:
1855		return ravb_hwtstamp_set(ndev, req);
1856	}
1857
1858	return phy_mii_ioctl(phydev, req, cmd);
1859}
1860
1861static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1862{
1863	if (netif_running(ndev))
1864		return -EBUSY;
1865
1866	ndev->mtu = new_mtu;
1867	netdev_update_features(ndev);
1868
1869	return 0;
1870}
1871
1872static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1873{
1874	struct ravb_private *priv = netdev_priv(ndev);
1875	unsigned long flags;
1876
1877	spin_lock_irqsave(&priv->lock, flags);
1878
1879	/* Disable TX and RX */
1880	ravb_rcv_snd_disable(ndev);
1881
1882	/* Modify RX Checksum setting */
1883	ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1884
1885	/* Enable TX and RX */
1886	ravb_rcv_snd_enable(ndev);
1887
1888	spin_unlock_irqrestore(&priv->lock, flags);
1889}
1890
1891static int ravb_set_features(struct net_device *ndev,
1892			     netdev_features_t features)
1893{
1894	netdev_features_t changed = ndev->features ^ features;
1895
1896	if (changed & NETIF_F_RXCSUM)
1897		ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1898
1899	ndev->features = features;
1900
1901	return 0;
1902}
1903
1904static const struct net_device_ops ravb_netdev_ops = {
1905	.ndo_open		= ravb_open,
1906	.ndo_stop		= ravb_close,
1907	.ndo_start_xmit		= ravb_start_xmit,
1908	.ndo_select_queue	= ravb_select_queue,
1909	.ndo_get_stats		= ravb_get_stats,
1910	.ndo_set_rx_mode	= ravb_set_rx_mode,
1911	.ndo_tx_timeout		= ravb_tx_timeout,
1912	.ndo_do_ioctl		= ravb_do_ioctl,
1913	.ndo_change_mtu		= ravb_change_mtu,
1914	.ndo_validate_addr	= eth_validate_addr,
1915	.ndo_set_mac_address	= eth_mac_addr,
1916	.ndo_set_features	= ravb_set_features,
1917};
1918
1919/* MDIO bus init function */
1920static int ravb_mdio_init(struct ravb_private *priv)
1921{
1922	struct platform_device *pdev = priv->pdev;
1923	struct device *dev = &pdev->dev;
1924	int error;
1925
1926	/* Bitbang init */
1927	priv->mdiobb.ops = &bb_ops;
1928
1929	/* MII controller setting */
1930	priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1931	if (!priv->mii_bus)
1932		return -ENOMEM;
1933
1934	/* Hook up MII support for ethtool */
1935	priv->mii_bus->name = "ravb_mii";
1936	priv->mii_bus->parent = dev;
1937	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1938		 pdev->name, pdev->id);
1939
1940	/* Register MDIO bus */
1941	error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1942	if (error)
1943		goto out_free_bus;
1944
1945	return 0;
1946
1947out_free_bus:
1948	free_mdio_bitbang(priv->mii_bus);
1949	return error;
1950}
1951
1952/* MDIO bus release function */
1953static int ravb_mdio_release(struct ravb_private *priv)
1954{
1955	/* Unregister mdio bus */
1956	mdiobus_unregister(priv->mii_bus);
1957
1958	/* Free bitbang info */
1959	free_mdio_bitbang(priv->mii_bus);
1960
1961	return 0;
1962}
1963
1964static const struct of_device_id ravb_match_table[] = {
1965	{ .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1966	{ .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1967	{ .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1968	{ .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1969	{ .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1970	{ }
1971};
1972MODULE_DEVICE_TABLE(of, ravb_match_table);
1973
1974static int ravb_set_gti(struct net_device *ndev)
1975{
1976	struct ravb_private *priv = netdev_priv(ndev);
1977	struct device *dev = ndev->dev.parent;
 
1978	unsigned long rate;
 
1979	uint64_t inc;
1980
1981	rate = clk_get_rate(priv->clk);
 
 
 
 
 
 
 
 
1982	if (!rate)
1983		return -EINVAL;
1984
1985	inc = 1000000000ULL << 20;
1986	do_div(inc, rate);
1987
1988	if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1989		dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1990			inc, GTI_TIV_MIN, GTI_TIV_MAX);
1991		return -EINVAL;
1992	}
1993
1994	ravb_write(ndev, inc, GTI);
1995
1996	return 0;
1997}
1998
1999static void ravb_set_config_mode(struct net_device *ndev)
2000{
2001	struct ravb_private *priv = netdev_priv(ndev);
2002
2003	if (priv->chip_id == RCAR_GEN2) {
2004		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2005		/* Set CSEL value */
2006		ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2007	} else {
2008		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2009			    CCC_GAC | CCC_CSEL_HPB);
2010	}
2011}
2012
2013/* Set tx and rx clock internal delay modes */
2014static void ravb_set_delay_mode(struct net_device *ndev)
2015{
2016	struct ravb_private *priv = netdev_priv(ndev);
2017	int set = 0;
2018
2019	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2020	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
2021		set |= APSR_DM_RDM;
2022
2023	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2024	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
2025		set |= APSR_DM_TDM;
2026
2027	ravb_modify(ndev, APSR, APSR_DM, set);
2028}
2029
2030static int ravb_probe(struct platform_device *pdev)
2031{
2032	struct device_node *np = pdev->dev.of_node;
2033	struct ravb_private *priv;
2034	enum ravb_chip_id chip_id;
2035	struct net_device *ndev;
2036	int error, irq, q;
2037	struct resource *res;
2038	int i;
2039
2040	if (!np) {
2041		dev_err(&pdev->dev,
2042			"this driver is required to be instantiated from device tree\n");
2043		return -EINVAL;
2044	}
2045
2046	/* Get base address */
2047	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2048	if (!res) {
2049		dev_err(&pdev->dev, "invalid resource\n");
2050		return -EINVAL;
2051	}
2052
2053	ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2054				  NUM_TX_QUEUE, NUM_RX_QUEUE);
2055	if (!ndev)
2056		return -ENOMEM;
2057
2058	ndev->features = NETIF_F_RXCSUM;
2059	ndev->hw_features = NETIF_F_RXCSUM;
2060
2061	pm_runtime_enable(&pdev->dev);
2062	pm_runtime_get_sync(&pdev->dev);
2063
2064	/* The Ether-specific entries in the device structure. */
2065	ndev->base_addr = res->start;
 
2066
2067	chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2068
2069	if (chip_id == RCAR_GEN3)
2070		irq = platform_get_irq_byname(pdev, "ch22");
2071	else
2072		irq = platform_get_irq(pdev, 0);
2073	if (irq < 0) {
2074		error = irq;
2075		goto out_release;
2076	}
2077	ndev->irq = irq;
2078
2079	SET_NETDEV_DEV(ndev, &pdev->dev);
2080
2081	priv = netdev_priv(ndev);
2082	priv->ndev = ndev;
2083	priv->pdev = pdev;
2084	priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2085	priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2086	priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2087	priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2088	priv->addr = devm_ioremap_resource(&pdev->dev, res);
2089	if (IS_ERR(priv->addr)) {
2090		error = PTR_ERR(priv->addr);
2091		goto out_release;
2092	}
2093
2094	spin_lock_init(&priv->lock);
2095	INIT_WORK(&priv->work, ravb_tx_timeout_work);
2096
2097	priv->phy_interface = of_get_phy_mode(np);
2098
2099	priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2100	priv->avb_link_active_low =
2101		of_property_read_bool(np, "renesas,ether-link-active-low");
2102
2103	if (chip_id == RCAR_GEN3) {
2104		irq = platform_get_irq_byname(pdev, "ch24");
2105		if (irq < 0) {
2106			error = irq;
2107			goto out_release;
2108		}
2109		priv->emac_irq = irq;
2110		for (i = 0; i < NUM_RX_QUEUE; i++) {
2111			irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2112			if (irq < 0) {
2113				error = irq;
2114				goto out_release;
2115			}
2116			priv->rx_irqs[i] = irq;
2117		}
2118		for (i = 0; i < NUM_TX_QUEUE; i++) {
2119			irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2120			if (irq < 0) {
2121				error = irq;
2122				goto out_release;
2123			}
2124			priv->tx_irqs[i] = irq;
2125		}
2126	}
2127
2128	priv->chip_id = chip_id;
2129
2130	priv->clk = devm_clk_get(&pdev->dev, NULL);
2131	if (IS_ERR(priv->clk)) {
2132		error = PTR_ERR(priv->clk);
2133		goto out_release;
2134	}
2135
2136	ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2137	ndev->min_mtu = ETH_MIN_MTU;
2138
2139	/* Set function */
2140	ndev->netdev_ops = &ravb_netdev_ops;
2141	ndev->ethtool_ops = &ravb_ethtool_ops;
2142
2143	/* Set AVB config mode */
2144	ravb_set_config_mode(ndev);
 
 
 
 
 
 
 
2145
2146	/* Set GTI value */
2147	error = ravb_set_gti(ndev);
2148	if (error)
2149		goto out_release;
2150
2151	/* Request GTI loading */
2152	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2153
2154	if (priv->chip_id != RCAR_GEN2)
2155		ravb_set_delay_mode(ndev);
2156
2157	/* Allocate descriptor base address table */
2158	priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2159	priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2160					    &priv->desc_bat_dma, GFP_KERNEL);
2161	if (!priv->desc_bat) {
2162		dev_err(&pdev->dev,
2163			"Cannot allocate desc base address table (size %d bytes)\n",
2164			priv->desc_bat_size);
2165		error = -ENOMEM;
2166		goto out_release;
2167	}
2168	for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2169		priv->desc_bat[q].die_dt = DT_EOS;
2170	ravb_write(ndev, priv->desc_bat_dma, DBAT);
2171
2172	/* Initialise HW timestamp list */
2173	INIT_LIST_HEAD(&priv->ts_skb_list);
2174
2175	/* Initialise PTP Clock driver */
2176	if (chip_id != RCAR_GEN2)
2177		ravb_ptp_init(ndev, pdev);
2178
2179	/* Debug message level */
2180	priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2181
2182	/* Read and set MAC address */
2183	ravb_read_mac_address(ndev, of_get_mac_address(np));
2184	if (!is_valid_ether_addr(ndev->dev_addr)) {
2185		dev_warn(&pdev->dev,
2186			 "no valid MAC address supplied, using a random one\n");
2187		eth_hw_addr_random(ndev);
2188	}
2189
2190	/* MDIO bus init */
2191	error = ravb_mdio_init(priv);
2192	if (error) {
2193		dev_err(&pdev->dev, "failed to initialize MDIO\n");
2194		goto out_dma_free;
2195	}
2196
2197	netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2198	netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2199
2200	/* Network device register */
2201	error = register_netdev(ndev);
2202	if (error)
2203		goto out_napi_del;
2204
2205	device_set_wakeup_capable(&pdev->dev, 1);
2206
2207	/* Print device information */
2208	netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2209		    (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2210
2211	platform_set_drvdata(pdev, ndev);
2212
2213	return 0;
2214
2215out_napi_del:
2216	netif_napi_del(&priv->napi[RAVB_NC]);
2217	netif_napi_del(&priv->napi[RAVB_BE]);
2218	ravb_mdio_release(priv);
2219out_dma_free:
2220	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2221			  priv->desc_bat_dma);
2222
2223	/* Stop PTP Clock driver */
2224	if (chip_id != RCAR_GEN2)
2225		ravb_ptp_stop(ndev);
2226out_release:
2227	free_netdev(ndev);
 
2228
2229	pm_runtime_put(&pdev->dev);
2230	pm_runtime_disable(&pdev->dev);
2231	return error;
2232}
2233
2234static int ravb_remove(struct platform_device *pdev)
2235{
2236	struct net_device *ndev = platform_get_drvdata(pdev);
2237	struct ravb_private *priv = netdev_priv(ndev);
2238
2239	/* Stop PTP Clock driver */
2240	if (priv->chip_id != RCAR_GEN2)
2241		ravb_ptp_stop(ndev);
2242
2243	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2244			  priv->desc_bat_dma);
2245	/* Set reset mode */
2246	ravb_write(ndev, CCC_OPC_RESET, CCC);
2247	pm_runtime_put_sync(&pdev->dev);
2248	unregister_netdev(ndev);
2249	netif_napi_del(&priv->napi[RAVB_NC]);
2250	netif_napi_del(&priv->napi[RAVB_BE]);
2251	ravb_mdio_release(priv);
2252	pm_runtime_disable(&pdev->dev);
2253	free_netdev(ndev);
2254	platform_set_drvdata(pdev, NULL);
2255
2256	return 0;
2257}
2258
2259static int ravb_wol_setup(struct net_device *ndev)
2260{
2261	struct ravb_private *priv = netdev_priv(ndev);
2262
2263	/* Disable interrupts by clearing the interrupt masks. */
2264	ravb_write(ndev, 0, RIC0);
2265	ravb_write(ndev, 0, RIC2);
2266	ravb_write(ndev, 0, TIC);
2267
2268	/* Only allow ECI interrupts */
2269	synchronize_irq(priv->emac_irq);
2270	napi_disable(&priv->napi[RAVB_NC]);
2271	napi_disable(&priv->napi[RAVB_BE]);
2272	ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2273
2274	/* Enable MagicPacket */
2275	ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2276
2277	return enable_irq_wake(priv->emac_irq);
2278}
2279
2280static int ravb_wol_restore(struct net_device *ndev)
2281{
2282	struct ravb_private *priv = netdev_priv(ndev);
2283	int ret;
2284
2285	napi_enable(&priv->napi[RAVB_NC]);
2286	napi_enable(&priv->napi[RAVB_BE]);
2287
2288	/* Disable MagicPacket */
2289	ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2290
2291	ret = ravb_close(ndev);
2292	if (ret < 0)
2293		return ret;
2294
2295	return disable_irq_wake(priv->emac_irq);
2296}
2297
2298static int __maybe_unused ravb_suspend(struct device *dev)
2299{
2300	struct net_device *ndev = dev_get_drvdata(dev);
2301	struct ravb_private *priv = netdev_priv(ndev);
2302	int ret;
2303
2304	if (!netif_running(ndev))
2305		return 0;
2306
2307	netif_device_detach(ndev);
2308
2309	if (priv->wol_enabled)
2310		ret = ravb_wol_setup(ndev);
2311	else
2312		ret = ravb_close(ndev);
2313
2314	return ret;
2315}
2316
2317static int __maybe_unused ravb_resume(struct device *dev)
2318{
2319	struct net_device *ndev = dev_get_drvdata(dev);
2320	struct ravb_private *priv = netdev_priv(ndev);
2321	int ret = 0;
2322
2323	/* If WoL is enabled set reset mode to rearm the WoL logic */
2324	if (priv->wol_enabled)
2325		ravb_write(ndev, CCC_OPC_RESET, CCC);
2326
2327	/* All register have been reset to default values.
2328	 * Restore all registers which where setup at probe time and
2329	 * reopen device if it was running before system suspended.
2330	 */
2331
2332	/* Set AVB config mode */
2333	ravb_set_config_mode(ndev);
2334
2335	/* Set GTI value */
2336	ret = ravb_set_gti(ndev);
2337	if (ret)
2338		return ret;
2339
2340	/* Request GTI loading */
2341	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2342
2343	if (priv->chip_id != RCAR_GEN2)
2344		ravb_set_delay_mode(ndev);
2345
2346	/* Restore descriptor base address table */
2347	ravb_write(ndev, priv->desc_bat_dma, DBAT);
2348
2349	if (netif_running(ndev)) {
2350		if (priv->wol_enabled) {
2351			ret = ravb_wol_restore(ndev);
2352			if (ret)
2353				return ret;
2354		}
2355		ret = ravb_open(ndev);
2356		if (ret < 0)
2357			return ret;
2358		netif_device_attach(ndev);
2359	}
2360
2361	return ret;
2362}
2363
2364static int __maybe_unused ravb_runtime_nop(struct device *dev)
2365{
2366	/* Runtime PM callback shared between ->runtime_suspend()
2367	 * and ->runtime_resume(). Simply returns success.
2368	 *
2369	 * This driver re-initializes all registers after
2370	 * pm_runtime_get_sync() anyway so there is no need
2371	 * to save and restore registers here.
2372	 */
2373	return 0;
2374}
2375
2376static const struct dev_pm_ops ravb_dev_pm_ops = {
2377	SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2378	SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2379};
2380
 
 
 
 
 
2381static struct platform_driver ravb_driver = {
2382	.probe		= ravb_probe,
2383	.remove		= ravb_remove,
2384	.driver = {
2385		.name	= "ravb",
2386		.pm	= &ravb_dev_pm_ops,
2387		.of_match_table = ravb_match_table,
2388	},
2389};
2390
2391module_platform_driver(ravb_driver);
2392
2393MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2394MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2395MODULE_LICENSE("GPL v2");