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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "vi.h"
29#include "vi_structs.h"
30#include "vid.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_atombios.h"
33#include "atombios_i2c.h"
34#include "clearstate_vi.h"
35
36#include "gmc/gmc_8_2_d.h"
37#include "gmc/gmc_8_2_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44#include "gca/gfx_8_0_d.h"
45#include "gca/gfx_8_0_enum.h"
46#include "gca/gfx_8_0_sh_mask.h"
47#include "gca/gfx_8_0_enum.h"
48
49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
52#include "smu/smu_7_1_3_d.h"
53
54#define GFX8_NUM_GFX_RINGS 1
55#define GFX8_MEC_HPD_SIZE 2048
56
57#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
58#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
59#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
60#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
61
62#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
63#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
64#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
65#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
66#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
67#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
68#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
69#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
70#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
71
72#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
73#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
74#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
75#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
76#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
77#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
78
79/* BPM SERDES CMD */
80#define SET_BPM_SERDES_CMD 1
81#define CLE_BPM_SERDES_CMD 0
82
83/* BPM Register Address*/
84enum {
85 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
86 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
87 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
88 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
89 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
90 BPM_REG_FGCG_MAX
91};
92
93#define RLC_FormatDirectRegListLength 14
94
95MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
96MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
97MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
98MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
99MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
100MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
101
102MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
103MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
104MODULE_FIRMWARE("amdgpu/stoney_me.bin");
105MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
106MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
107
108MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
109MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
110MODULE_FIRMWARE("amdgpu/tonga_me.bin");
111MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
112MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
113MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
114
115MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
116MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
117MODULE_FIRMWARE("amdgpu/topaz_me.bin");
118MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
119MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
120
121MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
122MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
123MODULE_FIRMWARE("amdgpu/fiji_me.bin");
124MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
125MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
126MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
127
128MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
129MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
130MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
131MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
132MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
133MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
134MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
135MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
136MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
137MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
138MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
139
140MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
141MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
142MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
143MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
144MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
145MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
146MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
147MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
148MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
149MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
150MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
151
152MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
153MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
154MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
155MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
156MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
157MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
158MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
159MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
160MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
161MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
162MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
163
164static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
165{
166 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
167 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
168 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
169 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
170 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
171 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
172 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
173 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
174 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
175 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
176 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
177 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
178 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
179 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
180 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
181 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
182};
183
184static const u32 golden_settings_tonga_a11[] =
185{
186 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
187 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
188 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
189 mmGB_GPU_ID, 0x0000000f, 0x00000000,
190 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
191 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
192 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
193 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
194 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
195 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
196 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
197 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
198 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
199 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
200 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
201 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
202};
203
204static const u32 tonga_golden_common_all[] =
205{
206 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
207 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
208 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
209 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
210 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
211 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
212 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
213 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
214};
215
216static const u32 tonga_mgcg_cgcg_init[] =
217{
218 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
221 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
222 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
223 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
224 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
225 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
226 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
227 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
228 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
229 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
230 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
231 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
232 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
233 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
236 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
237 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
238 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
239 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
240 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
242 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
243 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
244 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
245 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
246 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
247 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
248 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
249 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
250 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
251 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
252 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
253 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
254 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
255 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
256 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
257 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
258 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
259 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
260 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
261 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
262 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
263 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
264 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
265 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
266 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
267 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
268 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
269 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
270 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
271 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
272 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
273 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
274 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
275 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
276 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
277 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
278 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
279 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
280 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
281 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
282 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
283 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
284 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
285 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
286 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
287 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
288 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
289 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
290 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
291 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
292 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
293};
294
295static const u32 golden_settings_polaris11_a11[] =
296{
297 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
298 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
299 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
300 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
301 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
302 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
303 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
304 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
305 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
306 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
307 mmSQ_CONFIG, 0x07f80000, 0x01180000,
308 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
309 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
310 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
311 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
312 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
313 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
314};
315
316static const u32 polaris11_golden_common_all[] =
317{
318 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
319 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
320 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
321 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
322 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
323 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
324};
325
326static const u32 golden_settings_polaris10_a11[] =
327{
328 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
329 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
330 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
331 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
332 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
333 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
334 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
335 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
336 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
337 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
338 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
339 mmSQ_CONFIG, 0x07f80000, 0x07180000,
340 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
341 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
342 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
343 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
344 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
345};
346
347static const u32 polaris10_golden_common_all[] =
348{
349 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
350 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
351 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
352 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
353 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
354 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
355 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
356 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
357};
358
359static const u32 fiji_golden_common_all[] =
360{
361 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
362 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
363 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
364 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
365 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
367 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
368 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
369 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
370 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
371};
372
373static const u32 golden_settings_fiji_a10[] =
374{
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
380 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
381 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
382 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
383 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
384 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
385 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
386};
387
388static const u32 fiji_mgcg_cgcg_init[] =
389{
390 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
391 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
392 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
393 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
394 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
395 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
396 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
397 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
398 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
399 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
400 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
401 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
402 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
403 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
404 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
405 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
406 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
407 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
408 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
409 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
410 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
411 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
412 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
413 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
414 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
415 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
416 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
417 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
418 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
419 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
420 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
421 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
422 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
423 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
424 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
425};
426
427static const u32 golden_settings_iceland_a11[] =
428{
429 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
430 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
431 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
432 mmGB_GPU_ID, 0x0000000f, 0x00000000,
433 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
434 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
435 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
436 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
437 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
438 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
439 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
440 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
441 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
442 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
443 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
444 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
445};
446
447static const u32 iceland_golden_common_all[] =
448{
449 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
450 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
451 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
452 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
453 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
454 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
455 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
456 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
457};
458
459static const u32 iceland_mgcg_cgcg_init[] =
460{
461 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
462 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
463 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
464 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
465 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
466 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
467 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
468 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
469 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
470 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
471 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
472 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
473 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
474 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
475 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
476 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
477 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
478 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
479 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
480 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
481 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
482 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
483 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
484 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
485 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
486 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
487 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
488 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
489 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
490 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
491 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
492 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
493 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
494 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
495 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
496 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
497 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
498 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
499 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
500 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
501 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
502 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
503 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
504 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
505 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
506 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
507 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
508 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
509 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
510 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
511 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
512 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
513 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
514 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
515 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
516 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
517 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
518 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
519 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
520 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
521 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
522 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
523 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
524 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
525};
526
527static const u32 cz_golden_settings_a11[] =
528{
529 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
530 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
531 mmGB_GPU_ID, 0x0000000f, 0x00000000,
532 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
533 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
534 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
535 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
536 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
537 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
538 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
539 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
540 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
541};
542
543static const u32 cz_golden_common_all[] =
544{
545 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
546 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
547 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
548 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
549 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
550 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
551 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
552 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
553};
554
555static const u32 cz_mgcg_cgcg_init[] =
556{
557 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
558 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
559 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
560 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
561 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
562 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
563 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
564 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
565 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
566 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
567 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
568 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
569 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
570 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
571 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
572 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
573 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
574 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
575 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
576 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
577 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
578 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
579 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
580 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
581 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
582 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
583 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
584 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
585 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
586 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
587 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
588 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
589 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
590 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
591 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
592 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
593 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
594 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
595 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
596 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
597 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
598 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
599 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
600 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
601 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
602 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
603 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
604 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
605 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
606 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
607 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
608 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
609 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
610 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
611 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
612 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
613 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
614 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
615 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
616 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
617 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
618 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
619 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
620 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
621 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
622 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
623 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
624 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
625 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
626 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
627 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
628 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
629 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
630 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
631 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
632};
633
634static const u32 stoney_golden_settings_a11[] =
635{
636 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
637 mmGB_GPU_ID, 0x0000000f, 0x00000000,
638 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
639 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
640 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
641 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
642 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
643 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
644 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
645 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
646};
647
648static const u32 stoney_golden_common_all[] =
649{
650 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
651 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
652 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
653 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
654 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
655 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
656 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
657 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
658};
659
660static const u32 stoney_mgcg_cgcg_init[] =
661{
662 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
663 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
664 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
665 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
666 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
667};
668
669static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
670static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
671static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
672static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
673static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
674static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
675static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
676static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
677
678static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
679{
680 switch (adev->asic_type) {
681 case CHIP_TOPAZ:
682 amdgpu_device_program_register_sequence(adev,
683 iceland_mgcg_cgcg_init,
684 ARRAY_SIZE(iceland_mgcg_cgcg_init));
685 amdgpu_device_program_register_sequence(adev,
686 golden_settings_iceland_a11,
687 ARRAY_SIZE(golden_settings_iceland_a11));
688 amdgpu_device_program_register_sequence(adev,
689 iceland_golden_common_all,
690 ARRAY_SIZE(iceland_golden_common_all));
691 break;
692 case CHIP_FIJI:
693 amdgpu_device_program_register_sequence(adev,
694 fiji_mgcg_cgcg_init,
695 ARRAY_SIZE(fiji_mgcg_cgcg_init));
696 amdgpu_device_program_register_sequence(adev,
697 golden_settings_fiji_a10,
698 ARRAY_SIZE(golden_settings_fiji_a10));
699 amdgpu_device_program_register_sequence(adev,
700 fiji_golden_common_all,
701 ARRAY_SIZE(fiji_golden_common_all));
702 break;
703
704 case CHIP_TONGA:
705 amdgpu_device_program_register_sequence(adev,
706 tonga_mgcg_cgcg_init,
707 ARRAY_SIZE(tonga_mgcg_cgcg_init));
708 amdgpu_device_program_register_sequence(adev,
709 golden_settings_tonga_a11,
710 ARRAY_SIZE(golden_settings_tonga_a11));
711 amdgpu_device_program_register_sequence(adev,
712 tonga_golden_common_all,
713 ARRAY_SIZE(tonga_golden_common_all));
714 break;
715 case CHIP_POLARIS11:
716 case CHIP_POLARIS12:
717 amdgpu_device_program_register_sequence(adev,
718 golden_settings_polaris11_a11,
719 ARRAY_SIZE(golden_settings_polaris11_a11));
720 amdgpu_device_program_register_sequence(adev,
721 polaris11_golden_common_all,
722 ARRAY_SIZE(polaris11_golden_common_all));
723 break;
724 case CHIP_POLARIS10:
725 amdgpu_device_program_register_sequence(adev,
726 golden_settings_polaris10_a11,
727 ARRAY_SIZE(golden_settings_polaris10_a11));
728 amdgpu_device_program_register_sequence(adev,
729 polaris10_golden_common_all,
730 ARRAY_SIZE(polaris10_golden_common_all));
731 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
732 if (adev->pdev->revision == 0xc7 &&
733 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
734 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
735 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
736 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
737 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
738 }
739 break;
740 case CHIP_CARRIZO:
741 amdgpu_device_program_register_sequence(adev,
742 cz_mgcg_cgcg_init,
743 ARRAY_SIZE(cz_mgcg_cgcg_init));
744 amdgpu_device_program_register_sequence(adev,
745 cz_golden_settings_a11,
746 ARRAY_SIZE(cz_golden_settings_a11));
747 amdgpu_device_program_register_sequence(adev,
748 cz_golden_common_all,
749 ARRAY_SIZE(cz_golden_common_all));
750 break;
751 case CHIP_STONEY:
752 amdgpu_device_program_register_sequence(adev,
753 stoney_mgcg_cgcg_init,
754 ARRAY_SIZE(stoney_mgcg_cgcg_init));
755 amdgpu_device_program_register_sequence(adev,
756 stoney_golden_settings_a11,
757 ARRAY_SIZE(stoney_golden_settings_a11));
758 amdgpu_device_program_register_sequence(adev,
759 stoney_golden_common_all,
760 ARRAY_SIZE(stoney_golden_common_all));
761 break;
762 default:
763 break;
764 }
765}
766
767static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
768{
769 adev->gfx.scratch.num_reg = 8;
770 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
771 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
772}
773
774static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
775{
776 struct amdgpu_device *adev = ring->adev;
777 uint32_t scratch;
778 uint32_t tmp = 0;
779 unsigned i;
780 int r;
781
782 r = amdgpu_gfx_scratch_get(adev, &scratch);
783 if (r) {
784 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
785 return r;
786 }
787 WREG32(scratch, 0xCAFEDEAD);
788 r = amdgpu_ring_alloc(ring, 3);
789 if (r) {
790 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
791 ring->idx, r);
792 amdgpu_gfx_scratch_free(adev, scratch);
793 return r;
794 }
795 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
796 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
797 amdgpu_ring_write(ring, 0xDEADBEEF);
798 amdgpu_ring_commit(ring);
799
800 for (i = 0; i < adev->usec_timeout; i++) {
801 tmp = RREG32(scratch);
802 if (tmp == 0xDEADBEEF)
803 break;
804 DRM_UDELAY(1);
805 }
806 if (i < adev->usec_timeout) {
807 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
808 ring->idx, i);
809 } else {
810 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
811 ring->idx, scratch, tmp);
812 r = -EINVAL;
813 }
814 amdgpu_gfx_scratch_free(adev, scratch);
815 return r;
816}
817
818static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
819{
820 struct amdgpu_device *adev = ring->adev;
821 struct amdgpu_ib ib;
822 struct dma_fence *f = NULL;
823 uint32_t scratch;
824 uint32_t tmp = 0;
825 long r;
826
827 r = amdgpu_gfx_scratch_get(adev, &scratch);
828 if (r) {
829 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
830 return r;
831 }
832 WREG32(scratch, 0xCAFEDEAD);
833 memset(&ib, 0, sizeof(ib));
834 r = amdgpu_ib_get(adev, NULL, 256, &ib);
835 if (r) {
836 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
837 goto err1;
838 }
839 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
840 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
841 ib.ptr[2] = 0xDEADBEEF;
842 ib.length_dw = 3;
843
844 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
845 if (r)
846 goto err2;
847
848 r = dma_fence_wait_timeout(f, false, timeout);
849 if (r == 0) {
850 DRM_ERROR("amdgpu: IB test timed out.\n");
851 r = -ETIMEDOUT;
852 goto err2;
853 } else if (r < 0) {
854 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
855 goto err2;
856 }
857 tmp = RREG32(scratch);
858 if (tmp == 0xDEADBEEF) {
859 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
860 r = 0;
861 } else {
862 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
863 scratch, tmp);
864 r = -EINVAL;
865 }
866err2:
867 amdgpu_ib_free(adev, &ib, NULL);
868 dma_fence_put(f);
869err1:
870 amdgpu_gfx_scratch_free(adev, scratch);
871 return r;
872}
873
874
875static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
876{
877 release_firmware(adev->gfx.pfp_fw);
878 adev->gfx.pfp_fw = NULL;
879 release_firmware(adev->gfx.me_fw);
880 adev->gfx.me_fw = NULL;
881 release_firmware(adev->gfx.ce_fw);
882 adev->gfx.ce_fw = NULL;
883 release_firmware(adev->gfx.rlc_fw);
884 adev->gfx.rlc_fw = NULL;
885 release_firmware(adev->gfx.mec_fw);
886 adev->gfx.mec_fw = NULL;
887 if ((adev->asic_type != CHIP_STONEY) &&
888 (adev->asic_type != CHIP_TOPAZ))
889 release_firmware(adev->gfx.mec2_fw);
890 adev->gfx.mec2_fw = NULL;
891
892 kfree(adev->gfx.rlc.register_list_format);
893}
894
895static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
896{
897 const char *chip_name;
898 char fw_name[30];
899 int err;
900 struct amdgpu_firmware_info *info = NULL;
901 const struct common_firmware_header *header = NULL;
902 const struct gfx_firmware_header_v1_0 *cp_hdr;
903 const struct rlc_firmware_header_v2_0 *rlc_hdr;
904 unsigned int *tmp = NULL, i;
905
906 DRM_DEBUG("\n");
907
908 switch (adev->asic_type) {
909 case CHIP_TOPAZ:
910 chip_name = "topaz";
911 break;
912 case CHIP_TONGA:
913 chip_name = "tonga";
914 break;
915 case CHIP_CARRIZO:
916 chip_name = "carrizo";
917 break;
918 case CHIP_FIJI:
919 chip_name = "fiji";
920 break;
921 case CHIP_POLARIS11:
922 chip_name = "polaris11";
923 break;
924 case CHIP_POLARIS10:
925 chip_name = "polaris10";
926 break;
927 case CHIP_POLARIS12:
928 chip_name = "polaris12";
929 break;
930 case CHIP_STONEY:
931 chip_name = "stoney";
932 break;
933 default:
934 BUG();
935 }
936
937 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
938 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
939 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
940 if (err == -ENOENT) {
941 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
942 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
943 }
944 } else {
945 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
946 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
947 }
948 if (err)
949 goto out;
950 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
951 if (err)
952 goto out;
953 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
954 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
955 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
956
957 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
958 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
959 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
960 if (err == -ENOENT) {
961 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
962 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
963 }
964 } else {
965 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
966 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
967 }
968 if (err)
969 goto out;
970 err = amdgpu_ucode_validate(adev->gfx.me_fw);
971 if (err)
972 goto out;
973 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
974 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
975
976 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
977
978 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
979 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
980 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
981 if (err == -ENOENT) {
982 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
983 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
984 }
985 } else {
986 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
987 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
988 }
989 if (err)
990 goto out;
991 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
992 if (err)
993 goto out;
994 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
995 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
996 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
997
998 /*
999 * Support for MCBP/Virtualization in combination with chained IBs is
1000 * formal released on feature version #46
1001 */
1002 if (adev->gfx.ce_feature_version >= 46 &&
1003 adev->gfx.pfp_feature_version >= 46) {
1004 adev->virt.chained_ib_support = true;
1005 DRM_INFO("Chained IB support enabled!\n");
1006 } else
1007 adev->virt.chained_ib_support = false;
1008
1009 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1010 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1011 if (err)
1012 goto out;
1013 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1014 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1015 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1016 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1017
1018 adev->gfx.rlc.save_and_restore_offset =
1019 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1020 adev->gfx.rlc.clear_state_descriptor_offset =
1021 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1022 adev->gfx.rlc.avail_scratch_ram_locations =
1023 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1024 adev->gfx.rlc.reg_restore_list_size =
1025 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1026 adev->gfx.rlc.reg_list_format_start =
1027 le32_to_cpu(rlc_hdr->reg_list_format_start);
1028 adev->gfx.rlc.reg_list_format_separate_start =
1029 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1030 adev->gfx.rlc.starting_offsets_start =
1031 le32_to_cpu(rlc_hdr->starting_offsets_start);
1032 adev->gfx.rlc.reg_list_format_size_bytes =
1033 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1034 adev->gfx.rlc.reg_list_size_bytes =
1035 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1036
1037 adev->gfx.rlc.register_list_format =
1038 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1039 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1040
1041 if (!adev->gfx.rlc.register_list_format) {
1042 err = -ENOMEM;
1043 goto out;
1044 }
1045
1046 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1047 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1048 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
1049 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1050
1051 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1052
1053 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1054 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1055 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
1056 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1057
1058 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1059 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1060 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1061 if (err == -ENOENT) {
1062 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1063 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1064 }
1065 } else {
1066 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1067 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1068 }
1069 if (err)
1070 goto out;
1071 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1072 if (err)
1073 goto out;
1074 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1075 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1076 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1077
1078 if ((adev->asic_type != CHIP_STONEY) &&
1079 (adev->asic_type != CHIP_TOPAZ)) {
1080 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1081 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1082 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1083 if (err == -ENOENT) {
1084 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1085 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1086 }
1087 } else {
1088 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1089 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1090 }
1091 if (!err) {
1092 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1093 if (err)
1094 goto out;
1095 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1096 adev->gfx.mec2_fw->data;
1097 adev->gfx.mec2_fw_version =
1098 le32_to_cpu(cp_hdr->header.ucode_version);
1099 adev->gfx.mec2_feature_version =
1100 le32_to_cpu(cp_hdr->ucode_feature_version);
1101 } else {
1102 err = 0;
1103 adev->gfx.mec2_fw = NULL;
1104 }
1105 }
1106
1107 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
1108 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1109 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1110 info->fw = adev->gfx.pfp_fw;
1111 header = (const struct common_firmware_header *)info->fw->data;
1112 adev->firmware.fw_size +=
1113 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1114
1115 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1116 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1117 info->fw = adev->gfx.me_fw;
1118 header = (const struct common_firmware_header *)info->fw->data;
1119 adev->firmware.fw_size +=
1120 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1121
1122 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1123 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1124 info->fw = adev->gfx.ce_fw;
1125 header = (const struct common_firmware_header *)info->fw->data;
1126 adev->firmware.fw_size +=
1127 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1128
1129 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1130 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1131 info->fw = adev->gfx.rlc_fw;
1132 header = (const struct common_firmware_header *)info->fw->data;
1133 adev->firmware.fw_size +=
1134 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1135
1136 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1137 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1138 info->fw = adev->gfx.mec_fw;
1139 header = (const struct common_firmware_header *)info->fw->data;
1140 adev->firmware.fw_size +=
1141 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1142
1143 /* we need account JT in */
1144 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1145 adev->firmware.fw_size +=
1146 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1147
1148 if (amdgpu_sriov_vf(adev)) {
1149 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1150 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1151 info->fw = adev->gfx.mec_fw;
1152 adev->firmware.fw_size +=
1153 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1154 }
1155
1156 if (adev->gfx.mec2_fw) {
1157 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1158 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1159 info->fw = adev->gfx.mec2_fw;
1160 header = (const struct common_firmware_header *)info->fw->data;
1161 adev->firmware.fw_size +=
1162 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1163 }
1164
1165 }
1166
1167out:
1168 if (err) {
1169 dev_err(adev->dev,
1170 "gfx8: Failed to load firmware \"%s\"\n",
1171 fw_name);
1172 release_firmware(adev->gfx.pfp_fw);
1173 adev->gfx.pfp_fw = NULL;
1174 release_firmware(adev->gfx.me_fw);
1175 adev->gfx.me_fw = NULL;
1176 release_firmware(adev->gfx.ce_fw);
1177 adev->gfx.ce_fw = NULL;
1178 release_firmware(adev->gfx.rlc_fw);
1179 adev->gfx.rlc_fw = NULL;
1180 release_firmware(adev->gfx.mec_fw);
1181 adev->gfx.mec_fw = NULL;
1182 release_firmware(adev->gfx.mec2_fw);
1183 adev->gfx.mec2_fw = NULL;
1184 }
1185 return err;
1186}
1187
1188static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1189 volatile u32 *buffer)
1190{
1191 u32 count = 0, i;
1192 const struct cs_section_def *sect = NULL;
1193 const struct cs_extent_def *ext = NULL;
1194
1195 if (adev->gfx.rlc.cs_data == NULL)
1196 return;
1197 if (buffer == NULL)
1198 return;
1199
1200 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1201 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1202
1203 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1204 buffer[count++] = cpu_to_le32(0x80000000);
1205 buffer[count++] = cpu_to_le32(0x80000000);
1206
1207 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1208 for (ext = sect->section; ext->extent != NULL; ++ext) {
1209 if (sect->id == SECT_CONTEXT) {
1210 buffer[count++] =
1211 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1212 buffer[count++] = cpu_to_le32(ext->reg_index -
1213 PACKET3_SET_CONTEXT_REG_START);
1214 for (i = 0; i < ext->reg_count; i++)
1215 buffer[count++] = cpu_to_le32(ext->extent[i]);
1216 } else {
1217 return;
1218 }
1219 }
1220 }
1221
1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1223 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1224 PACKET3_SET_CONTEXT_REG_START);
1225 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1226 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1227
1228 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1229 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1230
1231 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1232 buffer[count++] = cpu_to_le32(0);
1233}
1234
1235static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1236{
1237 const __le32 *fw_data;
1238 volatile u32 *dst_ptr;
1239 int me, i, max_me = 4;
1240 u32 bo_offset = 0;
1241 u32 table_offset, table_size;
1242
1243 if (adev->asic_type == CHIP_CARRIZO)
1244 max_me = 5;
1245
1246 /* write the cp table buffer */
1247 dst_ptr = adev->gfx.rlc.cp_table_ptr;
1248 for (me = 0; me < max_me; me++) {
1249 if (me == 0) {
1250 const struct gfx_firmware_header_v1_0 *hdr =
1251 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1252 fw_data = (const __le32 *)
1253 (adev->gfx.ce_fw->data +
1254 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1255 table_offset = le32_to_cpu(hdr->jt_offset);
1256 table_size = le32_to_cpu(hdr->jt_size);
1257 } else if (me == 1) {
1258 const struct gfx_firmware_header_v1_0 *hdr =
1259 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1260 fw_data = (const __le32 *)
1261 (adev->gfx.pfp_fw->data +
1262 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1263 table_offset = le32_to_cpu(hdr->jt_offset);
1264 table_size = le32_to_cpu(hdr->jt_size);
1265 } else if (me == 2) {
1266 const struct gfx_firmware_header_v1_0 *hdr =
1267 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1268 fw_data = (const __le32 *)
1269 (adev->gfx.me_fw->data +
1270 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1271 table_offset = le32_to_cpu(hdr->jt_offset);
1272 table_size = le32_to_cpu(hdr->jt_size);
1273 } else if (me == 3) {
1274 const struct gfx_firmware_header_v1_0 *hdr =
1275 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1276 fw_data = (const __le32 *)
1277 (adev->gfx.mec_fw->data +
1278 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1279 table_offset = le32_to_cpu(hdr->jt_offset);
1280 table_size = le32_to_cpu(hdr->jt_size);
1281 } else if (me == 4) {
1282 const struct gfx_firmware_header_v1_0 *hdr =
1283 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1284 fw_data = (const __le32 *)
1285 (adev->gfx.mec2_fw->data +
1286 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1287 table_offset = le32_to_cpu(hdr->jt_offset);
1288 table_size = le32_to_cpu(hdr->jt_size);
1289 }
1290
1291 for (i = 0; i < table_size; i ++) {
1292 dst_ptr[bo_offset + i] =
1293 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1294 }
1295
1296 bo_offset += table_size;
1297 }
1298}
1299
1300static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1301{
1302 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
1303 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
1304}
1305
1306static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1307{
1308 volatile u32 *dst_ptr;
1309 u32 dws;
1310 const struct cs_section_def *cs_data;
1311 int r;
1312
1313 adev->gfx.rlc.cs_data = vi_cs_data;
1314
1315 cs_data = adev->gfx.rlc.cs_data;
1316
1317 if (cs_data) {
1318 /* clear state block */
1319 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1320
1321 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1322 AMDGPU_GEM_DOMAIN_VRAM,
1323 &adev->gfx.rlc.clear_state_obj,
1324 &adev->gfx.rlc.clear_state_gpu_addr,
1325 (void **)&adev->gfx.rlc.cs_ptr);
1326 if (r) {
1327 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1328 gfx_v8_0_rlc_fini(adev);
1329 return r;
1330 }
1331
1332 /* set up the cs buffer */
1333 dst_ptr = adev->gfx.rlc.cs_ptr;
1334 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1335 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1336 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1337 }
1338
1339 if ((adev->asic_type == CHIP_CARRIZO) ||
1340 (adev->asic_type == CHIP_STONEY)) {
1341 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1342 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1343 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1344 &adev->gfx.rlc.cp_table_obj,
1345 &adev->gfx.rlc.cp_table_gpu_addr,
1346 (void **)&adev->gfx.rlc.cp_table_ptr);
1347 if (r) {
1348 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1349 return r;
1350 }
1351
1352 cz_init_cp_jump_table(adev);
1353
1354 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1355 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1356 }
1357
1358 return 0;
1359}
1360
1361static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1362{
1363 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1364}
1365
1366static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1367{
1368 int r;
1369 u32 *hpd;
1370 size_t mec_hpd_size;
1371
1372 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1373
1374 /* take ownership of the relevant compute queues */
1375 amdgpu_gfx_compute_queue_acquire(adev);
1376
1377 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1378
1379 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1380 AMDGPU_GEM_DOMAIN_GTT,
1381 &adev->gfx.mec.hpd_eop_obj,
1382 &adev->gfx.mec.hpd_eop_gpu_addr,
1383 (void **)&hpd);
1384 if (r) {
1385 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1386 return r;
1387 }
1388
1389 memset(hpd, 0, mec_hpd_size);
1390
1391 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1392 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1393
1394 return 0;
1395}
1396
1397static const u32 vgpr_init_compute_shader[] =
1398{
1399 0x7e000209, 0x7e020208,
1400 0x7e040207, 0x7e060206,
1401 0x7e080205, 0x7e0a0204,
1402 0x7e0c0203, 0x7e0e0202,
1403 0x7e100201, 0x7e120200,
1404 0x7e140209, 0x7e160208,
1405 0x7e180207, 0x7e1a0206,
1406 0x7e1c0205, 0x7e1e0204,
1407 0x7e200203, 0x7e220202,
1408 0x7e240201, 0x7e260200,
1409 0x7e280209, 0x7e2a0208,
1410 0x7e2c0207, 0x7e2e0206,
1411 0x7e300205, 0x7e320204,
1412 0x7e340203, 0x7e360202,
1413 0x7e380201, 0x7e3a0200,
1414 0x7e3c0209, 0x7e3e0208,
1415 0x7e400207, 0x7e420206,
1416 0x7e440205, 0x7e460204,
1417 0x7e480203, 0x7e4a0202,
1418 0x7e4c0201, 0x7e4e0200,
1419 0x7e500209, 0x7e520208,
1420 0x7e540207, 0x7e560206,
1421 0x7e580205, 0x7e5a0204,
1422 0x7e5c0203, 0x7e5e0202,
1423 0x7e600201, 0x7e620200,
1424 0x7e640209, 0x7e660208,
1425 0x7e680207, 0x7e6a0206,
1426 0x7e6c0205, 0x7e6e0204,
1427 0x7e700203, 0x7e720202,
1428 0x7e740201, 0x7e760200,
1429 0x7e780209, 0x7e7a0208,
1430 0x7e7c0207, 0x7e7e0206,
1431 0xbf8a0000, 0xbf810000,
1432};
1433
1434static const u32 sgpr_init_compute_shader[] =
1435{
1436 0xbe8a0100, 0xbe8c0102,
1437 0xbe8e0104, 0xbe900106,
1438 0xbe920108, 0xbe940100,
1439 0xbe960102, 0xbe980104,
1440 0xbe9a0106, 0xbe9c0108,
1441 0xbe9e0100, 0xbea00102,
1442 0xbea20104, 0xbea40106,
1443 0xbea60108, 0xbea80100,
1444 0xbeaa0102, 0xbeac0104,
1445 0xbeae0106, 0xbeb00108,
1446 0xbeb20100, 0xbeb40102,
1447 0xbeb60104, 0xbeb80106,
1448 0xbeba0108, 0xbebc0100,
1449 0xbebe0102, 0xbec00104,
1450 0xbec20106, 0xbec40108,
1451 0xbec60100, 0xbec80102,
1452 0xbee60004, 0xbee70005,
1453 0xbeea0006, 0xbeeb0007,
1454 0xbee80008, 0xbee90009,
1455 0xbefc0000, 0xbf8a0000,
1456 0xbf810000, 0x00000000,
1457};
1458
1459static const u32 vgpr_init_regs[] =
1460{
1461 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1462 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1463 mmCOMPUTE_NUM_THREAD_X, 256*4,
1464 mmCOMPUTE_NUM_THREAD_Y, 1,
1465 mmCOMPUTE_NUM_THREAD_Z, 1,
1466 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1467 mmCOMPUTE_PGM_RSRC2, 20,
1468 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1469 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1470 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1471 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1472 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1473 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1474 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1475 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1476 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1477 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1478};
1479
1480static const u32 sgpr1_init_regs[] =
1481{
1482 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1483 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1484 mmCOMPUTE_NUM_THREAD_X, 256*5,
1485 mmCOMPUTE_NUM_THREAD_Y, 1,
1486 mmCOMPUTE_NUM_THREAD_Z, 1,
1487 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1488 mmCOMPUTE_PGM_RSRC2, 20,
1489 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1490 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1491 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1492 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1493 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1494 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1495 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1496 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1497 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1498 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1499};
1500
1501static const u32 sgpr2_init_regs[] =
1502{
1503 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1504 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1505 mmCOMPUTE_NUM_THREAD_X, 256*5,
1506 mmCOMPUTE_NUM_THREAD_Y, 1,
1507 mmCOMPUTE_NUM_THREAD_Z, 1,
1508 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1509 mmCOMPUTE_PGM_RSRC2, 20,
1510 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1511 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1512 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1513 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1514 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1515 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1516 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1517 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1518 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1519 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1520};
1521
1522static const u32 sec_ded_counter_registers[] =
1523{
1524 mmCPC_EDC_ATC_CNT,
1525 mmCPC_EDC_SCRATCH_CNT,
1526 mmCPC_EDC_UCODE_CNT,
1527 mmCPF_EDC_ATC_CNT,
1528 mmCPF_EDC_ROQ_CNT,
1529 mmCPF_EDC_TAG_CNT,
1530 mmCPG_EDC_ATC_CNT,
1531 mmCPG_EDC_DMA_CNT,
1532 mmCPG_EDC_TAG_CNT,
1533 mmDC_EDC_CSINVOC_CNT,
1534 mmDC_EDC_RESTORE_CNT,
1535 mmDC_EDC_STATE_CNT,
1536 mmGDS_EDC_CNT,
1537 mmGDS_EDC_GRBM_CNT,
1538 mmGDS_EDC_OA_DED,
1539 mmSPI_EDC_CNT,
1540 mmSQC_ATC_EDC_GATCL1_CNT,
1541 mmSQC_EDC_CNT,
1542 mmSQ_EDC_DED_CNT,
1543 mmSQ_EDC_INFO,
1544 mmSQ_EDC_SEC_CNT,
1545 mmTCC_EDC_CNT,
1546 mmTCP_ATC_EDC_GATCL1_CNT,
1547 mmTCP_EDC_CNT,
1548 mmTD_EDC_CNT
1549};
1550
1551static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1552{
1553 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1554 struct amdgpu_ib ib;
1555 struct dma_fence *f = NULL;
1556 int r, i;
1557 u32 tmp;
1558 unsigned total_size, vgpr_offset, sgpr_offset;
1559 u64 gpu_addr;
1560
1561 /* only supported on CZ */
1562 if (adev->asic_type != CHIP_CARRIZO)
1563 return 0;
1564
1565 /* bail if the compute ring is not ready */
1566 if (!ring->ready)
1567 return 0;
1568
1569 tmp = RREG32(mmGB_EDC_MODE);
1570 WREG32(mmGB_EDC_MODE, 0);
1571
1572 total_size =
1573 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1574 total_size +=
1575 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1576 total_size +=
1577 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1578 total_size = ALIGN(total_size, 256);
1579 vgpr_offset = total_size;
1580 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1581 sgpr_offset = total_size;
1582 total_size += sizeof(sgpr_init_compute_shader);
1583
1584 /* allocate an indirect buffer to put the commands in */
1585 memset(&ib, 0, sizeof(ib));
1586 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1587 if (r) {
1588 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1589 return r;
1590 }
1591
1592 /* load the compute shaders */
1593 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1594 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1595
1596 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1597 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1598
1599 /* init the ib length to 0 */
1600 ib.length_dw = 0;
1601
1602 /* VGPR */
1603 /* write the register state for the compute dispatch */
1604 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1605 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1606 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1607 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1608 }
1609 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1610 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1611 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1612 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1613 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1614 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1615
1616 /* write dispatch packet */
1617 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1618 ib.ptr[ib.length_dw++] = 8; /* x */
1619 ib.ptr[ib.length_dw++] = 1; /* y */
1620 ib.ptr[ib.length_dw++] = 1; /* z */
1621 ib.ptr[ib.length_dw++] =
1622 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1623
1624 /* write CS partial flush packet */
1625 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1626 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1627
1628 /* SGPR1 */
1629 /* write the register state for the compute dispatch */
1630 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1631 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1632 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1633 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1634 }
1635 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1636 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1637 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1638 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1639 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1640 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1641
1642 /* write dispatch packet */
1643 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1644 ib.ptr[ib.length_dw++] = 8; /* x */
1645 ib.ptr[ib.length_dw++] = 1; /* y */
1646 ib.ptr[ib.length_dw++] = 1; /* z */
1647 ib.ptr[ib.length_dw++] =
1648 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1649
1650 /* write CS partial flush packet */
1651 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1652 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1653
1654 /* SGPR2 */
1655 /* write the register state for the compute dispatch */
1656 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1657 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1658 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1659 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1660 }
1661 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1662 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1663 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1664 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1665 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1666 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1667
1668 /* write dispatch packet */
1669 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1670 ib.ptr[ib.length_dw++] = 8; /* x */
1671 ib.ptr[ib.length_dw++] = 1; /* y */
1672 ib.ptr[ib.length_dw++] = 1; /* z */
1673 ib.ptr[ib.length_dw++] =
1674 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1675
1676 /* write CS partial flush packet */
1677 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1678 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1679
1680 /* shedule the ib on the ring */
1681 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1682 if (r) {
1683 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1684 goto fail;
1685 }
1686
1687 /* wait for the GPU to finish processing the IB */
1688 r = dma_fence_wait(f, false);
1689 if (r) {
1690 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1691 goto fail;
1692 }
1693
1694 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1695 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1696 WREG32(mmGB_EDC_MODE, tmp);
1697
1698 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1699 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1700 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1701
1702
1703 /* read back registers to clear the counters */
1704 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1705 RREG32(sec_ded_counter_registers[i]);
1706
1707fail:
1708 amdgpu_ib_free(adev, &ib, NULL);
1709 dma_fence_put(f);
1710
1711 return r;
1712}
1713
1714static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1715{
1716 u32 gb_addr_config;
1717 u32 mc_shared_chmap, mc_arb_ramcfg;
1718 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1719 u32 tmp;
1720 int ret;
1721
1722 switch (adev->asic_type) {
1723 case CHIP_TOPAZ:
1724 adev->gfx.config.max_shader_engines = 1;
1725 adev->gfx.config.max_tile_pipes = 2;
1726 adev->gfx.config.max_cu_per_sh = 6;
1727 adev->gfx.config.max_sh_per_se = 1;
1728 adev->gfx.config.max_backends_per_se = 2;
1729 adev->gfx.config.max_texture_channel_caches = 2;
1730 adev->gfx.config.max_gprs = 256;
1731 adev->gfx.config.max_gs_threads = 32;
1732 adev->gfx.config.max_hw_contexts = 8;
1733
1734 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1735 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1736 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1737 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1738 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1739 break;
1740 case CHIP_FIJI:
1741 adev->gfx.config.max_shader_engines = 4;
1742 adev->gfx.config.max_tile_pipes = 16;
1743 adev->gfx.config.max_cu_per_sh = 16;
1744 adev->gfx.config.max_sh_per_se = 1;
1745 adev->gfx.config.max_backends_per_se = 4;
1746 adev->gfx.config.max_texture_channel_caches = 16;
1747 adev->gfx.config.max_gprs = 256;
1748 adev->gfx.config.max_gs_threads = 32;
1749 adev->gfx.config.max_hw_contexts = 8;
1750
1751 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1752 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1753 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1754 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1755 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1756 break;
1757 case CHIP_POLARIS11:
1758 case CHIP_POLARIS12:
1759 ret = amdgpu_atombios_get_gfx_info(adev);
1760 if (ret)
1761 return ret;
1762 adev->gfx.config.max_gprs = 256;
1763 adev->gfx.config.max_gs_threads = 32;
1764 adev->gfx.config.max_hw_contexts = 8;
1765
1766 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1767 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1768 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1769 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1770 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1771 break;
1772 case CHIP_POLARIS10:
1773 ret = amdgpu_atombios_get_gfx_info(adev);
1774 if (ret)
1775 return ret;
1776 adev->gfx.config.max_gprs = 256;
1777 adev->gfx.config.max_gs_threads = 32;
1778 adev->gfx.config.max_hw_contexts = 8;
1779
1780 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1781 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1782 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1783 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1784 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1785 break;
1786 case CHIP_TONGA:
1787 adev->gfx.config.max_shader_engines = 4;
1788 adev->gfx.config.max_tile_pipes = 8;
1789 adev->gfx.config.max_cu_per_sh = 8;
1790 adev->gfx.config.max_sh_per_se = 1;
1791 adev->gfx.config.max_backends_per_se = 2;
1792 adev->gfx.config.max_texture_channel_caches = 8;
1793 adev->gfx.config.max_gprs = 256;
1794 adev->gfx.config.max_gs_threads = 32;
1795 adev->gfx.config.max_hw_contexts = 8;
1796
1797 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1798 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1799 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1800 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1801 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1802 break;
1803 case CHIP_CARRIZO:
1804 adev->gfx.config.max_shader_engines = 1;
1805 adev->gfx.config.max_tile_pipes = 2;
1806 adev->gfx.config.max_sh_per_se = 1;
1807 adev->gfx.config.max_backends_per_se = 2;
1808 adev->gfx.config.max_cu_per_sh = 8;
1809 adev->gfx.config.max_texture_channel_caches = 2;
1810 adev->gfx.config.max_gprs = 256;
1811 adev->gfx.config.max_gs_threads = 32;
1812 adev->gfx.config.max_hw_contexts = 8;
1813
1814 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1815 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1816 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1817 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1818 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1819 break;
1820 case CHIP_STONEY:
1821 adev->gfx.config.max_shader_engines = 1;
1822 adev->gfx.config.max_tile_pipes = 2;
1823 adev->gfx.config.max_sh_per_se = 1;
1824 adev->gfx.config.max_backends_per_se = 1;
1825 adev->gfx.config.max_cu_per_sh = 3;
1826 adev->gfx.config.max_texture_channel_caches = 2;
1827 adev->gfx.config.max_gprs = 256;
1828 adev->gfx.config.max_gs_threads = 16;
1829 adev->gfx.config.max_hw_contexts = 8;
1830
1831 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1832 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1833 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1834 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1835 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1836 break;
1837 default:
1838 adev->gfx.config.max_shader_engines = 2;
1839 adev->gfx.config.max_tile_pipes = 4;
1840 adev->gfx.config.max_cu_per_sh = 2;
1841 adev->gfx.config.max_sh_per_se = 1;
1842 adev->gfx.config.max_backends_per_se = 2;
1843 adev->gfx.config.max_texture_channel_caches = 4;
1844 adev->gfx.config.max_gprs = 256;
1845 adev->gfx.config.max_gs_threads = 32;
1846 adev->gfx.config.max_hw_contexts = 8;
1847
1848 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1849 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1850 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1851 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1852 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1853 break;
1854 }
1855
1856 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1857 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1858 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1859
1860 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1861 adev->gfx.config.mem_max_burst_length_bytes = 256;
1862 if (adev->flags & AMD_IS_APU) {
1863 /* Get memory bank mapping mode. */
1864 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1865 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1866 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1867
1868 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1869 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1870 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1871
1872 /* Validate settings in case only one DIMM installed. */
1873 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1874 dimm00_addr_map = 0;
1875 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1876 dimm01_addr_map = 0;
1877 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1878 dimm10_addr_map = 0;
1879 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1880 dimm11_addr_map = 0;
1881
1882 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1883 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1884 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1885 adev->gfx.config.mem_row_size_in_kb = 2;
1886 else
1887 adev->gfx.config.mem_row_size_in_kb = 1;
1888 } else {
1889 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1890 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1891 if (adev->gfx.config.mem_row_size_in_kb > 4)
1892 adev->gfx.config.mem_row_size_in_kb = 4;
1893 }
1894
1895 adev->gfx.config.shader_engine_tile_size = 32;
1896 adev->gfx.config.num_gpus = 1;
1897 adev->gfx.config.multi_gpu_tile_size = 64;
1898
1899 /* fix up row size */
1900 switch (adev->gfx.config.mem_row_size_in_kb) {
1901 case 1:
1902 default:
1903 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1904 break;
1905 case 2:
1906 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1907 break;
1908 case 4:
1909 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1910 break;
1911 }
1912 adev->gfx.config.gb_addr_config = gb_addr_config;
1913
1914 return 0;
1915}
1916
1917static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1918 int mec, int pipe, int queue)
1919{
1920 int r;
1921 unsigned irq_type;
1922 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1923
1924 ring = &adev->gfx.compute_ring[ring_id];
1925
1926 /* mec0 is me1 */
1927 ring->me = mec + 1;
1928 ring->pipe = pipe;
1929 ring->queue = queue;
1930
1931 ring->ring_obj = NULL;
1932 ring->use_doorbell = true;
1933 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1934 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1935 + (ring_id * GFX8_MEC_HPD_SIZE);
1936 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1937
1938 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1939 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1940 + ring->pipe;
1941
1942 /* type-2 packets are deprecated on MEC, use type-3 instead */
1943 r = amdgpu_ring_init(adev, ring, 1024,
1944 &adev->gfx.eop_irq, irq_type);
1945 if (r)
1946 return r;
1947
1948
1949 return 0;
1950}
1951
1952static int gfx_v8_0_sw_init(void *handle)
1953{
1954 int i, j, k, r, ring_id;
1955 struct amdgpu_ring *ring;
1956 struct amdgpu_kiq *kiq;
1957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1958
1959 switch (adev->asic_type) {
1960 case CHIP_FIJI:
1961 case CHIP_TONGA:
1962 case CHIP_POLARIS11:
1963 case CHIP_POLARIS12:
1964 case CHIP_POLARIS10:
1965 case CHIP_CARRIZO:
1966 adev->gfx.mec.num_mec = 2;
1967 break;
1968 case CHIP_TOPAZ:
1969 case CHIP_STONEY:
1970 default:
1971 adev->gfx.mec.num_mec = 1;
1972 break;
1973 }
1974
1975 adev->gfx.mec.num_pipe_per_mec = 4;
1976 adev->gfx.mec.num_queue_per_pipe = 8;
1977
1978 /* KIQ event */
1979 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);
1980 if (r)
1981 return r;
1982
1983 /* EOP Event */
1984 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
1985 if (r)
1986 return r;
1987
1988 /* Privileged reg */
1989 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
1990 &adev->gfx.priv_reg_irq);
1991 if (r)
1992 return r;
1993
1994 /* Privileged inst */
1995 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
1996 &adev->gfx.priv_inst_irq);
1997 if (r)
1998 return r;
1999
2000 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2001
2002 gfx_v8_0_scratch_init(adev);
2003
2004 r = gfx_v8_0_init_microcode(adev);
2005 if (r) {
2006 DRM_ERROR("Failed to load gfx firmware!\n");
2007 return r;
2008 }
2009
2010 r = gfx_v8_0_rlc_init(adev);
2011 if (r) {
2012 DRM_ERROR("Failed to init rlc BOs!\n");
2013 return r;
2014 }
2015
2016 r = gfx_v8_0_mec_init(adev);
2017 if (r) {
2018 DRM_ERROR("Failed to init MEC BOs!\n");
2019 return r;
2020 }
2021
2022 /* set up the gfx ring */
2023 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2024 ring = &adev->gfx.gfx_ring[i];
2025 ring->ring_obj = NULL;
2026 sprintf(ring->name, "gfx");
2027 /* no gfx doorbells on iceland */
2028 if (adev->asic_type != CHIP_TOPAZ) {
2029 ring->use_doorbell = true;
2030 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
2031 }
2032
2033 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2034 AMDGPU_CP_IRQ_GFX_EOP);
2035 if (r)
2036 return r;
2037 }
2038
2039
2040 /* set up the compute queues - allocate horizontally across pipes */
2041 ring_id = 0;
2042 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2043 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2044 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2045 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2046 continue;
2047
2048 r = gfx_v8_0_compute_ring_init(adev,
2049 ring_id,
2050 i, k, j);
2051 if (r)
2052 return r;
2053
2054 ring_id++;
2055 }
2056 }
2057 }
2058
2059 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2060 if (r) {
2061 DRM_ERROR("Failed to init KIQ BOs!\n");
2062 return r;
2063 }
2064
2065 kiq = &adev->gfx.kiq;
2066 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2067 if (r)
2068 return r;
2069
2070 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2071 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2072 if (r)
2073 return r;
2074
2075 /* reserve GDS, GWS and OA resource for gfx */
2076 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
2077 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
2078 &adev->gds.gds_gfx_bo, NULL, NULL);
2079 if (r)
2080 return r;
2081
2082 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
2083 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
2084 &adev->gds.gws_gfx_bo, NULL, NULL);
2085 if (r)
2086 return r;
2087
2088 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
2089 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
2090 &adev->gds.oa_gfx_bo, NULL, NULL);
2091 if (r)
2092 return r;
2093
2094 adev->gfx.ce_ram_size = 0x8000;
2095
2096 r = gfx_v8_0_gpu_early_init(adev);
2097 if (r)
2098 return r;
2099
2100 return 0;
2101}
2102
2103static int gfx_v8_0_sw_fini(void *handle)
2104{
2105 int i;
2106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2107
2108 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
2109 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
2110 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
2111
2112 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2113 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2114 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2115 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2116
2117 amdgpu_gfx_compute_mqd_sw_fini(adev);
2118 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
2119 amdgpu_gfx_kiq_fini(adev);
2120
2121 gfx_v8_0_mec_fini(adev);
2122 gfx_v8_0_rlc_fini(adev);
2123 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2124 &adev->gfx.rlc.clear_state_gpu_addr,
2125 (void **)&adev->gfx.rlc.cs_ptr);
2126 if ((adev->asic_type == CHIP_CARRIZO) ||
2127 (adev->asic_type == CHIP_STONEY)) {
2128 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2129 &adev->gfx.rlc.cp_table_gpu_addr,
2130 (void **)&adev->gfx.rlc.cp_table_ptr);
2131 }
2132 gfx_v8_0_free_microcode(adev);
2133
2134 return 0;
2135}
2136
2137static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2138{
2139 uint32_t *modearray, *mod2array;
2140 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2141 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2142 u32 reg_offset;
2143
2144 modearray = adev->gfx.config.tile_mode_array;
2145 mod2array = adev->gfx.config.macrotile_mode_array;
2146
2147 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2148 modearray[reg_offset] = 0;
2149
2150 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2151 mod2array[reg_offset] = 0;
2152
2153 switch (adev->asic_type) {
2154 case CHIP_TOPAZ:
2155 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2156 PIPE_CONFIG(ADDR_SURF_P2) |
2157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2159 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2160 PIPE_CONFIG(ADDR_SURF_P2) |
2161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2163 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2164 PIPE_CONFIG(ADDR_SURF_P2) |
2165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2167 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2168 PIPE_CONFIG(ADDR_SURF_P2) |
2169 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2171 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2172 PIPE_CONFIG(ADDR_SURF_P2) |
2173 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2174 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2175 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2176 PIPE_CONFIG(ADDR_SURF_P2) |
2177 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2178 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2179 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2180 PIPE_CONFIG(ADDR_SURF_P2) |
2181 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2182 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2183 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2184 PIPE_CONFIG(ADDR_SURF_P2));
2185 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2186 PIPE_CONFIG(ADDR_SURF_P2) |
2187 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2189 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2190 PIPE_CONFIG(ADDR_SURF_P2) |
2191 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2193 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2194 PIPE_CONFIG(ADDR_SURF_P2) |
2195 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2197 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2198 PIPE_CONFIG(ADDR_SURF_P2) |
2199 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2201 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2202 PIPE_CONFIG(ADDR_SURF_P2) |
2203 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2205 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2206 PIPE_CONFIG(ADDR_SURF_P2) |
2207 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2209 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2210 PIPE_CONFIG(ADDR_SURF_P2) |
2211 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2213 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2214 PIPE_CONFIG(ADDR_SURF_P2) |
2215 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2217 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2218 PIPE_CONFIG(ADDR_SURF_P2) |
2219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2221 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2222 PIPE_CONFIG(ADDR_SURF_P2) |
2223 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2225 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2226 PIPE_CONFIG(ADDR_SURF_P2) |
2227 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2229 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2230 PIPE_CONFIG(ADDR_SURF_P2) |
2231 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2233 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2234 PIPE_CONFIG(ADDR_SURF_P2) |
2235 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2237 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2238 PIPE_CONFIG(ADDR_SURF_P2) |
2239 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2240 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2241 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2242 PIPE_CONFIG(ADDR_SURF_P2) |
2243 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2245 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2246 PIPE_CONFIG(ADDR_SURF_P2) |
2247 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2249 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2250 PIPE_CONFIG(ADDR_SURF_P2) |
2251 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2253 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2254 PIPE_CONFIG(ADDR_SURF_P2) |
2255 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2256 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2257
2258 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2261 NUM_BANKS(ADDR_SURF_8_BANK));
2262 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2265 NUM_BANKS(ADDR_SURF_8_BANK));
2266 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2269 NUM_BANKS(ADDR_SURF_8_BANK));
2270 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2273 NUM_BANKS(ADDR_SURF_8_BANK));
2274 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2277 NUM_BANKS(ADDR_SURF_8_BANK));
2278 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2281 NUM_BANKS(ADDR_SURF_8_BANK));
2282 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2285 NUM_BANKS(ADDR_SURF_8_BANK));
2286 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2289 NUM_BANKS(ADDR_SURF_16_BANK));
2290 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2293 NUM_BANKS(ADDR_SURF_16_BANK));
2294 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2297 NUM_BANKS(ADDR_SURF_16_BANK));
2298 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2301 NUM_BANKS(ADDR_SURF_16_BANK));
2302 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2303 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2304 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2305 NUM_BANKS(ADDR_SURF_16_BANK));
2306 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2307 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2308 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2309 NUM_BANKS(ADDR_SURF_16_BANK));
2310 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2311 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2312 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2313 NUM_BANKS(ADDR_SURF_8_BANK));
2314
2315 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2316 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2317 reg_offset != 23)
2318 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2319
2320 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2321 if (reg_offset != 7)
2322 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2323
2324 break;
2325 case CHIP_FIJI:
2326 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2335 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2340 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2341 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2342 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2343 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2345 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2346 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2347 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2348 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2349 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2350 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2351 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2352 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2353 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2354 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2355 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2357 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2358 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2359 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2360 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2364 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2368 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2372 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2376 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2380 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2381 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2384 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2388 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2392 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2393 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2396 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2397 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2409 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2416 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2417 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2420 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2424 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2425 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2428 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2429 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2430 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2432 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2433 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2434 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2436 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2437 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2438 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2440 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2441 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2442 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2443 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2444 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2445 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2446 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2447 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2448
2449 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_8_BANK));
2469 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472 NUM_BANKS(ADDR_SURF_8_BANK));
2473 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2476 NUM_BANKS(ADDR_SURF_8_BANK));
2477 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480 NUM_BANKS(ADDR_SURF_8_BANK));
2481 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2484 NUM_BANKS(ADDR_SURF_8_BANK));
2485 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2488 NUM_BANKS(ADDR_SURF_8_BANK));
2489 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2492 NUM_BANKS(ADDR_SURF_8_BANK));
2493 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2496 NUM_BANKS(ADDR_SURF_8_BANK));
2497 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2500 NUM_BANKS(ADDR_SURF_8_BANK));
2501 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2504 NUM_BANKS(ADDR_SURF_4_BANK));
2505
2506 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2507 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2508
2509 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2510 if (reg_offset != 7)
2511 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2512
2513 break;
2514 case CHIP_TONGA:
2515 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2529 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2530 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2531 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2532 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2535 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2536 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2537 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2538 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2539 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2540 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2541 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2542 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2543 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2544 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2546 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2547 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2548 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2549 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2561 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2562 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2565 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2569 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2573 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2577 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2581 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2582 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2585 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2586 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2605 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2606 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2609 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2613 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2614 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2617 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2618 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2619 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2620 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2621 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2622 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2623 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2624 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2625 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2626 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2627 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2629 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2630 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2631 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2632 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2633 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2634 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2635 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2636 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2637
2638 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2649 NUM_BANKS(ADDR_SURF_16_BANK));
2650 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2653 NUM_BANKS(ADDR_SURF_16_BANK));
2654 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2657 NUM_BANKS(ADDR_SURF_16_BANK));
2658 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2661 NUM_BANKS(ADDR_SURF_16_BANK));
2662 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2665 NUM_BANKS(ADDR_SURF_16_BANK));
2666 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2669 NUM_BANKS(ADDR_SURF_16_BANK));
2670 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2673 NUM_BANKS(ADDR_SURF_16_BANK));
2674 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2677 NUM_BANKS(ADDR_SURF_16_BANK));
2678 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2681 NUM_BANKS(ADDR_SURF_16_BANK));
2682 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2685 NUM_BANKS(ADDR_SURF_8_BANK));
2686 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2689 NUM_BANKS(ADDR_SURF_4_BANK));
2690 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2693 NUM_BANKS(ADDR_SURF_4_BANK));
2694
2695 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2696 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2697
2698 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2699 if (reg_offset != 7)
2700 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2701
2702 break;
2703 case CHIP_POLARIS11:
2704 case CHIP_POLARIS12:
2705 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2708 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2709 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2712 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2713 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2716 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2717 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2718 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2720 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2721 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2722 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2724 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2725 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2726 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2727 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2728 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2729 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2730 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2732 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2733 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2734 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2736 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2737 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2738 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2739 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2740 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2743 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2744 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2747 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2748 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2751 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2752 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2755 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2756 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2759 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2760 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2762 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2763 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2764 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2767 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2768 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2771 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2772 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2774 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2775 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2776 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2779 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2780 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2783 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2784 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2787 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2788 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2791 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2792 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2794 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2795 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2796 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2798 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2799 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2800 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2801 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2803 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2807 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2808 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2809 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2810 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2811 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2812 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2813 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2814 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2815 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2816 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2817 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2818 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2819 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2820 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2821 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2822 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2823 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2824 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2825 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2826 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2827
2828 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2831 NUM_BANKS(ADDR_SURF_16_BANK));
2832
2833 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2836 NUM_BANKS(ADDR_SURF_16_BANK));
2837
2838 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2841 NUM_BANKS(ADDR_SURF_16_BANK));
2842
2843 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2846 NUM_BANKS(ADDR_SURF_16_BANK));
2847
2848 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2851 NUM_BANKS(ADDR_SURF_16_BANK));
2852
2853 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2856 NUM_BANKS(ADDR_SURF_16_BANK));
2857
2858 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2859 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2860 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2861 NUM_BANKS(ADDR_SURF_16_BANK));
2862
2863 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2866 NUM_BANKS(ADDR_SURF_16_BANK));
2867
2868 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2871 NUM_BANKS(ADDR_SURF_16_BANK));
2872
2873 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2876 NUM_BANKS(ADDR_SURF_16_BANK));
2877
2878 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2879 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2880 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2881 NUM_BANKS(ADDR_SURF_16_BANK));
2882
2883 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2886 NUM_BANKS(ADDR_SURF_16_BANK));
2887
2888 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2891 NUM_BANKS(ADDR_SURF_8_BANK));
2892
2893 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2895 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2896 NUM_BANKS(ADDR_SURF_4_BANK));
2897
2898 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2899 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2900
2901 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2902 if (reg_offset != 7)
2903 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2904
2905 break;
2906 case CHIP_POLARIS10:
2907 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2908 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2910 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2911 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2914 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2915 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2916 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2918 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2919 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2922 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2923 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2924 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2925 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2926 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2927 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2928 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2930 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2931 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2932 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2933 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2934 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2935 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2936 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2938 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2939 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2940 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2941 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2942 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2943 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2944 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2945 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2946 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2947 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2948 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2949 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2950 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2951 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2952 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2953 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2954 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2955 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2957 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2959 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2961 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2962 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2963 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2964 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2965 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2966 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2968 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2969 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2973 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2974 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2975 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2976 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2977 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2978 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2979 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2980 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2981 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2983 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2985 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2986 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2987 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2988 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2989 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2990 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2991 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2993 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2994 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2995 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2997 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2998 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2999 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3000 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3001 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3002 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3003 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3005 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3006 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3007 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3009 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3010 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3011 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3012 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3013 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3014 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3015 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3017 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3018 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3019 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3020 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3021 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3022 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3023 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3024 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3025 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3026 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3027 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3028 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3029
3030 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3033 NUM_BANKS(ADDR_SURF_16_BANK));
3034
3035 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3038 NUM_BANKS(ADDR_SURF_16_BANK));
3039
3040 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3043 NUM_BANKS(ADDR_SURF_16_BANK));
3044
3045 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3048 NUM_BANKS(ADDR_SURF_16_BANK));
3049
3050 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3053 NUM_BANKS(ADDR_SURF_16_BANK));
3054
3055 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3058 NUM_BANKS(ADDR_SURF_16_BANK));
3059
3060 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3063 NUM_BANKS(ADDR_SURF_16_BANK));
3064
3065 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3068 NUM_BANKS(ADDR_SURF_16_BANK));
3069
3070 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3073 NUM_BANKS(ADDR_SURF_16_BANK));
3074
3075 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3078 NUM_BANKS(ADDR_SURF_16_BANK));
3079
3080 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3083 NUM_BANKS(ADDR_SURF_16_BANK));
3084
3085 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3086 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3087 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3088 NUM_BANKS(ADDR_SURF_8_BANK));
3089
3090 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3093 NUM_BANKS(ADDR_SURF_4_BANK));
3094
3095 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3096 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3097 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3098 NUM_BANKS(ADDR_SURF_4_BANK));
3099
3100 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3101 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3102
3103 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3104 if (reg_offset != 7)
3105 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3106
3107 break;
3108 case CHIP_STONEY:
3109 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3110 PIPE_CONFIG(ADDR_SURF_P2) |
3111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3112 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3113 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3114 PIPE_CONFIG(ADDR_SURF_P2) |
3115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3116 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3117 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3118 PIPE_CONFIG(ADDR_SURF_P2) |
3119 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3120 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3121 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3122 PIPE_CONFIG(ADDR_SURF_P2) |
3123 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3124 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3125 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3126 PIPE_CONFIG(ADDR_SURF_P2) |
3127 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3128 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3129 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3130 PIPE_CONFIG(ADDR_SURF_P2) |
3131 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3132 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3133 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3134 PIPE_CONFIG(ADDR_SURF_P2) |
3135 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3136 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3137 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3138 PIPE_CONFIG(ADDR_SURF_P2));
3139 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3140 PIPE_CONFIG(ADDR_SURF_P2) |
3141 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3143 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3144 PIPE_CONFIG(ADDR_SURF_P2) |
3145 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3147 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3148 PIPE_CONFIG(ADDR_SURF_P2) |
3149 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3151 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3155 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3156 PIPE_CONFIG(ADDR_SURF_P2) |
3157 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3158 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3159 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3160 PIPE_CONFIG(ADDR_SURF_P2) |
3161 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3163 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3164 PIPE_CONFIG(ADDR_SURF_P2) |
3165 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3167 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3168 PIPE_CONFIG(ADDR_SURF_P2) |
3169 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3170 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3171 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3172 PIPE_CONFIG(ADDR_SURF_P2) |
3173 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3175 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3176 PIPE_CONFIG(ADDR_SURF_P2) |
3177 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3179 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3180 PIPE_CONFIG(ADDR_SURF_P2) |
3181 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3182 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3183 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3184 PIPE_CONFIG(ADDR_SURF_P2) |
3185 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3186 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3187 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3188 PIPE_CONFIG(ADDR_SURF_P2) |
3189 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3191 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3192 PIPE_CONFIG(ADDR_SURF_P2) |
3193 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3194 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3195 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3196 PIPE_CONFIG(ADDR_SURF_P2) |
3197 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3198 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3199 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3200 PIPE_CONFIG(ADDR_SURF_P2) |
3201 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3202 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3203 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3204 PIPE_CONFIG(ADDR_SURF_P2) |
3205 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3206 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3207 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3208 PIPE_CONFIG(ADDR_SURF_P2) |
3209 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3210 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3211
3212 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3215 NUM_BANKS(ADDR_SURF_8_BANK));
3216 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3219 NUM_BANKS(ADDR_SURF_8_BANK));
3220 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3223 NUM_BANKS(ADDR_SURF_8_BANK));
3224 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3227 NUM_BANKS(ADDR_SURF_8_BANK));
3228 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3231 NUM_BANKS(ADDR_SURF_8_BANK));
3232 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3235 NUM_BANKS(ADDR_SURF_8_BANK));
3236 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3239 NUM_BANKS(ADDR_SURF_8_BANK));
3240 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3243 NUM_BANKS(ADDR_SURF_16_BANK));
3244 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3247 NUM_BANKS(ADDR_SURF_16_BANK));
3248 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3249 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3251 NUM_BANKS(ADDR_SURF_16_BANK));
3252 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3255 NUM_BANKS(ADDR_SURF_16_BANK));
3256 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3259 NUM_BANKS(ADDR_SURF_16_BANK));
3260 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3263 NUM_BANKS(ADDR_SURF_16_BANK));
3264 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3265 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3266 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3267 NUM_BANKS(ADDR_SURF_8_BANK));
3268
3269 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3270 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3271 reg_offset != 23)
3272 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3273
3274 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3275 if (reg_offset != 7)
3276 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3277
3278 break;
3279 default:
3280 dev_warn(adev->dev,
3281 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3282 adev->asic_type);
3283
3284 case CHIP_CARRIZO:
3285 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3286 PIPE_CONFIG(ADDR_SURF_P2) |
3287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3288 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3289 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3290 PIPE_CONFIG(ADDR_SURF_P2) |
3291 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3292 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3293 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3294 PIPE_CONFIG(ADDR_SURF_P2) |
3295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3296 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3297 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3298 PIPE_CONFIG(ADDR_SURF_P2) |
3299 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3300 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3301 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3302 PIPE_CONFIG(ADDR_SURF_P2) |
3303 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3304 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3305 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3306 PIPE_CONFIG(ADDR_SURF_P2) |
3307 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3308 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3309 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3310 PIPE_CONFIG(ADDR_SURF_P2) |
3311 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3312 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3313 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3314 PIPE_CONFIG(ADDR_SURF_P2));
3315 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3316 PIPE_CONFIG(ADDR_SURF_P2) |
3317 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3319 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3320 PIPE_CONFIG(ADDR_SURF_P2) |
3321 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3323 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3324 PIPE_CONFIG(ADDR_SURF_P2) |
3325 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3326 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3327 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3328 PIPE_CONFIG(ADDR_SURF_P2) |
3329 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3331 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3332 PIPE_CONFIG(ADDR_SURF_P2) |
3333 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3334 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3335 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3336 PIPE_CONFIG(ADDR_SURF_P2) |
3337 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3338 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3339 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3340 PIPE_CONFIG(ADDR_SURF_P2) |
3341 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3342 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3343 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3344 PIPE_CONFIG(ADDR_SURF_P2) |
3345 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3346 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3347 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3348 PIPE_CONFIG(ADDR_SURF_P2) |
3349 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3350 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3351 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3352 PIPE_CONFIG(ADDR_SURF_P2) |
3353 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3354 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3355 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3356 PIPE_CONFIG(ADDR_SURF_P2) |
3357 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3358 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3359 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3360 PIPE_CONFIG(ADDR_SURF_P2) |
3361 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3362 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3363 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3364 PIPE_CONFIG(ADDR_SURF_P2) |
3365 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3366 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3367 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3368 PIPE_CONFIG(ADDR_SURF_P2) |
3369 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3370 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3371 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3372 PIPE_CONFIG(ADDR_SURF_P2) |
3373 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3374 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3375 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3376 PIPE_CONFIG(ADDR_SURF_P2) |
3377 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3378 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3379 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3380 PIPE_CONFIG(ADDR_SURF_P2) |
3381 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3382 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3383 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3384 PIPE_CONFIG(ADDR_SURF_P2) |
3385 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3386 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3387
3388 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3389 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3390 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3391 NUM_BANKS(ADDR_SURF_8_BANK));
3392 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3393 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3394 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3395 NUM_BANKS(ADDR_SURF_8_BANK));
3396 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3399 NUM_BANKS(ADDR_SURF_8_BANK));
3400 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3401 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3402 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3403 NUM_BANKS(ADDR_SURF_8_BANK));
3404 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3405 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3406 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3407 NUM_BANKS(ADDR_SURF_8_BANK));
3408 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3411 NUM_BANKS(ADDR_SURF_8_BANK));
3412 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3413 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3414 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3415 NUM_BANKS(ADDR_SURF_8_BANK));
3416 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3419 NUM_BANKS(ADDR_SURF_16_BANK));
3420 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3423 NUM_BANKS(ADDR_SURF_16_BANK));
3424 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3425 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3426 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3427 NUM_BANKS(ADDR_SURF_16_BANK));
3428 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3431 NUM_BANKS(ADDR_SURF_16_BANK));
3432 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3435 NUM_BANKS(ADDR_SURF_16_BANK));
3436 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3439 NUM_BANKS(ADDR_SURF_16_BANK));
3440 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3442 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3443 NUM_BANKS(ADDR_SURF_8_BANK));
3444
3445 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3446 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3447 reg_offset != 23)
3448 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3449
3450 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3451 if (reg_offset != 7)
3452 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3453
3454 break;
3455 }
3456}
3457
3458static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3459 u32 se_num, u32 sh_num, u32 instance)
3460{
3461 u32 data;
3462
3463 if (instance == 0xffffffff)
3464 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3465 else
3466 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3467
3468 if (se_num == 0xffffffff)
3469 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3470 else
3471 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3472
3473 if (sh_num == 0xffffffff)
3474 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3475 else
3476 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3477
3478 WREG32(mmGRBM_GFX_INDEX, data);
3479}
3480
3481static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3482 u32 me, u32 pipe, u32 q)
3483{
3484 vi_srbm_select(adev, me, pipe, q, 0);
3485}
3486
3487static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3488{
3489 u32 data, mask;
3490
3491 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3492 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3493
3494 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3495
3496 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3497 adev->gfx.config.max_sh_per_se);
3498
3499 return (~data) & mask;
3500}
3501
3502static void
3503gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3504{
3505 switch (adev->asic_type) {
3506 case CHIP_FIJI:
3507 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3508 RB_XSEL2(1) | PKR_MAP(2) |
3509 PKR_XSEL(1) | PKR_YSEL(1) |
3510 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3511 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3512 SE_PAIR_YSEL(2);
3513 break;
3514 case CHIP_TONGA:
3515 case CHIP_POLARIS10:
3516 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3517 SE_XSEL(1) | SE_YSEL(1);
3518 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3519 SE_PAIR_YSEL(2);
3520 break;
3521 case CHIP_TOPAZ:
3522 case CHIP_CARRIZO:
3523 *rconf |= RB_MAP_PKR0(2);
3524 *rconf1 |= 0x0;
3525 break;
3526 case CHIP_POLARIS11:
3527 case CHIP_POLARIS12:
3528 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3529 SE_XSEL(1) | SE_YSEL(1);
3530 *rconf1 |= 0x0;
3531 break;
3532 case CHIP_STONEY:
3533 *rconf |= 0x0;
3534 *rconf1 |= 0x0;
3535 break;
3536 default:
3537 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3538 break;
3539 }
3540}
3541
3542static void
3543gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3544 u32 raster_config, u32 raster_config_1,
3545 unsigned rb_mask, unsigned num_rb)
3546{
3547 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3548 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3549 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3550 unsigned rb_per_se = num_rb / num_se;
3551 unsigned se_mask[4];
3552 unsigned se;
3553
3554 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3555 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3556 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3557 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3558
3559 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3560 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3561 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3562
3563 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3564 (!se_mask[2] && !se_mask[3]))) {
3565 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3566
3567 if (!se_mask[0] && !se_mask[1]) {
3568 raster_config_1 |=
3569 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3570 } else {
3571 raster_config_1 |=
3572 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3573 }
3574 }
3575
3576 for (se = 0; se < num_se; se++) {
3577 unsigned raster_config_se = raster_config;
3578 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3579 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3580 int idx = (se / 2) * 2;
3581
3582 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3583 raster_config_se &= ~SE_MAP_MASK;
3584
3585 if (!se_mask[idx]) {
3586 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3587 } else {
3588 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3589 }
3590 }
3591
3592 pkr0_mask &= rb_mask;
3593 pkr1_mask &= rb_mask;
3594 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3595 raster_config_se &= ~PKR_MAP_MASK;
3596
3597 if (!pkr0_mask) {
3598 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3599 } else {
3600 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3601 }
3602 }
3603
3604 if (rb_per_se >= 2) {
3605 unsigned rb0_mask = 1 << (se * rb_per_se);
3606 unsigned rb1_mask = rb0_mask << 1;
3607
3608 rb0_mask &= rb_mask;
3609 rb1_mask &= rb_mask;
3610 if (!rb0_mask || !rb1_mask) {
3611 raster_config_se &= ~RB_MAP_PKR0_MASK;
3612
3613 if (!rb0_mask) {
3614 raster_config_se |=
3615 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3616 } else {
3617 raster_config_se |=
3618 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3619 }
3620 }
3621
3622 if (rb_per_se > 2) {
3623 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3624 rb1_mask = rb0_mask << 1;
3625 rb0_mask &= rb_mask;
3626 rb1_mask &= rb_mask;
3627 if (!rb0_mask || !rb1_mask) {
3628 raster_config_se &= ~RB_MAP_PKR1_MASK;
3629
3630 if (!rb0_mask) {
3631 raster_config_se |=
3632 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3633 } else {
3634 raster_config_se |=
3635 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3636 }
3637 }
3638 }
3639 }
3640
3641 /* GRBM_GFX_INDEX has a different offset on VI */
3642 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3643 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3644 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3645 }
3646
3647 /* GRBM_GFX_INDEX has a different offset on VI */
3648 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3649}
3650
3651static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3652{
3653 int i, j;
3654 u32 data;
3655 u32 raster_config = 0, raster_config_1 = 0;
3656 u32 active_rbs = 0;
3657 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3658 adev->gfx.config.max_sh_per_se;
3659 unsigned num_rb_pipes;
3660
3661 mutex_lock(&adev->grbm_idx_mutex);
3662 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3663 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3664 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3665 data = gfx_v8_0_get_rb_active_bitmap(adev);
3666 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3667 rb_bitmap_width_per_sh);
3668 }
3669 }
3670 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3671
3672 adev->gfx.config.backend_enable_mask = active_rbs;
3673 adev->gfx.config.num_rbs = hweight32(active_rbs);
3674
3675 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3676 adev->gfx.config.max_shader_engines, 16);
3677
3678 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3679
3680 if (!adev->gfx.config.backend_enable_mask ||
3681 adev->gfx.config.num_rbs >= num_rb_pipes) {
3682 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3683 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3684 } else {
3685 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3686 adev->gfx.config.backend_enable_mask,
3687 num_rb_pipes);
3688 }
3689
3690 /* cache the values for userspace */
3691 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3692 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3693 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3694 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3695 RREG32(mmCC_RB_BACKEND_DISABLE);
3696 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3697 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3698 adev->gfx.config.rb_config[i][j].raster_config =
3699 RREG32(mmPA_SC_RASTER_CONFIG);
3700 adev->gfx.config.rb_config[i][j].raster_config_1 =
3701 RREG32(mmPA_SC_RASTER_CONFIG_1);
3702 }
3703 }
3704 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3705 mutex_unlock(&adev->grbm_idx_mutex);
3706}
3707
3708/**
3709 * gfx_v8_0_init_compute_vmid - gart enable
3710 *
3711 * @adev: amdgpu_device pointer
3712 *
3713 * Initialize compute vmid sh_mem registers
3714 *
3715 */
3716#define DEFAULT_SH_MEM_BASES (0x6000)
3717#define FIRST_COMPUTE_VMID (8)
3718#define LAST_COMPUTE_VMID (16)
3719static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3720{
3721 int i;
3722 uint32_t sh_mem_config;
3723 uint32_t sh_mem_bases;
3724
3725 /*
3726 * Configure apertures:
3727 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3728 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3729 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3730 */
3731 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3732
3733 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3734 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3735 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3736 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3737 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3738 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3739
3740 mutex_lock(&adev->srbm_mutex);
3741 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3742 vi_srbm_select(adev, 0, 0, 0, i);
3743 /* CP and shaders */
3744 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3745 WREG32(mmSH_MEM_APE1_BASE, 1);
3746 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3747 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3748 }
3749 vi_srbm_select(adev, 0, 0, 0, 0);
3750 mutex_unlock(&adev->srbm_mutex);
3751}
3752
3753static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3754{
3755 switch (adev->asic_type) {
3756 default:
3757 adev->gfx.config.double_offchip_lds_buf = 1;
3758 break;
3759 case CHIP_CARRIZO:
3760 case CHIP_STONEY:
3761 adev->gfx.config.double_offchip_lds_buf = 0;
3762 break;
3763 }
3764}
3765
3766static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3767{
3768 u32 tmp, sh_static_mem_cfg;
3769 int i;
3770
3771 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3772 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3773 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3774 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3775
3776 gfx_v8_0_tiling_mode_table_init(adev);
3777 gfx_v8_0_setup_rb(adev);
3778 gfx_v8_0_get_cu_info(adev);
3779 gfx_v8_0_config_init(adev);
3780
3781 /* XXX SH_MEM regs */
3782 /* where to put LDS, scratch, GPUVM in FSA64 space */
3783 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3784 SWIZZLE_ENABLE, 1);
3785 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3786 ELEMENT_SIZE, 1);
3787 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3788 INDEX_STRIDE, 3);
3789 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3790
3791 mutex_lock(&adev->srbm_mutex);
3792 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3793 vi_srbm_select(adev, 0, 0, 0, i);
3794 /* CP and shaders */
3795 if (i == 0) {
3796 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3797 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3798 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3799 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3800 WREG32(mmSH_MEM_CONFIG, tmp);
3801 WREG32(mmSH_MEM_BASES, 0);
3802 } else {
3803 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3804 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3805 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3806 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3807 WREG32(mmSH_MEM_CONFIG, tmp);
3808 tmp = adev->gmc.shared_aperture_start >> 48;
3809 WREG32(mmSH_MEM_BASES, tmp);
3810 }
3811
3812 WREG32(mmSH_MEM_APE1_BASE, 1);
3813 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3814 }
3815 vi_srbm_select(adev, 0, 0, 0, 0);
3816 mutex_unlock(&adev->srbm_mutex);
3817
3818 gfx_v8_0_init_compute_vmid(adev);
3819
3820 mutex_lock(&adev->grbm_idx_mutex);
3821 /*
3822 * making sure that the following register writes will be broadcasted
3823 * to all the shaders
3824 */
3825 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3826
3827 WREG32(mmPA_SC_FIFO_SIZE,
3828 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3829 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3830 (adev->gfx.config.sc_prim_fifo_size_backend <<
3831 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3832 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3833 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3834 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3835 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3836
3837 tmp = RREG32(mmSPI_ARB_PRIORITY);
3838 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3839 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3840 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3841 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3842 WREG32(mmSPI_ARB_PRIORITY, tmp);
3843
3844 mutex_unlock(&adev->grbm_idx_mutex);
3845
3846}
3847
3848static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3849{
3850 u32 i, j, k;
3851 u32 mask;
3852
3853 mutex_lock(&adev->grbm_idx_mutex);
3854 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3855 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3856 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3857 for (k = 0; k < adev->usec_timeout; k++) {
3858 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3859 break;
3860 udelay(1);
3861 }
3862 if (k == adev->usec_timeout) {
3863 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3864 0xffffffff, 0xffffffff);
3865 mutex_unlock(&adev->grbm_idx_mutex);
3866 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3867 i, j);
3868 return;
3869 }
3870 }
3871 }
3872 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3873 mutex_unlock(&adev->grbm_idx_mutex);
3874
3875 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3876 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3877 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3878 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3879 for (k = 0; k < adev->usec_timeout; k++) {
3880 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3881 break;
3882 udelay(1);
3883 }
3884}
3885
3886static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3887 bool enable)
3888{
3889 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3890
3891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3894 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3895
3896 WREG32(mmCP_INT_CNTL_RING0, tmp);
3897}
3898
3899static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3900{
3901 /* csib */
3902 WREG32(mmRLC_CSIB_ADDR_HI,
3903 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3904 WREG32(mmRLC_CSIB_ADDR_LO,
3905 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3906 WREG32(mmRLC_CSIB_LENGTH,
3907 adev->gfx.rlc.clear_state_size);
3908}
3909
3910static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3911 int ind_offset,
3912 int list_size,
3913 int *unique_indices,
3914 int *indices_count,
3915 int max_indices,
3916 int *ind_start_offsets,
3917 int *offset_count,
3918 int max_offset)
3919{
3920 int indices;
3921 bool new_entry = true;
3922
3923 for (; ind_offset < list_size; ind_offset++) {
3924
3925 if (new_entry) {
3926 new_entry = false;
3927 ind_start_offsets[*offset_count] = ind_offset;
3928 *offset_count = *offset_count + 1;
3929 BUG_ON(*offset_count >= max_offset);
3930 }
3931
3932 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3933 new_entry = true;
3934 continue;
3935 }
3936
3937 ind_offset += 2;
3938
3939 /* look for the matching indice */
3940 for (indices = 0;
3941 indices < *indices_count;
3942 indices++) {
3943 if (unique_indices[indices] ==
3944 register_list_format[ind_offset])
3945 break;
3946 }
3947
3948 if (indices >= *indices_count) {
3949 unique_indices[*indices_count] =
3950 register_list_format[ind_offset];
3951 indices = *indices_count;
3952 *indices_count = *indices_count + 1;
3953 BUG_ON(*indices_count >= max_indices);
3954 }
3955
3956 register_list_format[ind_offset] = indices;
3957 }
3958}
3959
3960static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3961{
3962 int i, temp, data;
3963 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3964 int indices_count = 0;
3965 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3966 int offset_count = 0;
3967
3968 int list_size;
3969 unsigned int *register_list_format =
3970 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3971 if (!register_list_format)
3972 return -ENOMEM;
3973 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3974 adev->gfx.rlc.reg_list_format_size_bytes);
3975
3976 gfx_v8_0_parse_ind_reg_list(register_list_format,
3977 RLC_FormatDirectRegListLength,
3978 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3979 unique_indices,
3980 &indices_count,
3981 ARRAY_SIZE(unique_indices),
3982 indirect_start_offsets,
3983 &offset_count,
3984 ARRAY_SIZE(indirect_start_offsets));
3985
3986 /* save and restore list */
3987 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3988
3989 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3990 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3991 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3992
3993 /* indirect list */
3994 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3995 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3996 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3997
3998 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3999 list_size = list_size >> 1;
4000 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
4001 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
4002
4003 /* starting offsets starts */
4004 WREG32(mmRLC_GPM_SCRATCH_ADDR,
4005 adev->gfx.rlc.starting_offsets_start);
4006 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
4007 WREG32(mmRLC_GPM_SCRATCH_DATA,
4008 indirect_start_offsets[i]);
4009
4010 /* unique indices */
4011 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
4012 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
4013 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
4014 if (unique_indices[i] != 0) {
4015 WREG32(temp + i, unique_indices[i] & 0x3FFFF);
4016 WREG32(data + i, unique_indices[i] >> 20);
4017 }
4018 }
4019 kfree(register_list_format);
4020
4021 return 0;
4022}
4023
4024static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
4025{
4026 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4027}
4028
4029static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
4030{
4031 uint32_t data;
4032
4033 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4034
4035 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4036 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4037 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4038 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4039 WREG32(mmRLC_PG_DELAY, data);
4040
4041 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4042 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4043
4044}
4045
4046static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4047 bool enable)
4048{
4049 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4050}
4051
4052static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4053 bool enable)
4054{
4055 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4056}
4057
4058static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4059{
4060 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4061}
4062
4063static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4064{
4065 if ((adev->asic_type == CHIP_CARRIZO) ||
4066 (adev->asic_type == CHIP_STONEY)) {
4067 gfx_v8_0_init_csb(adev);
4068 gfx_v8_0_init_save_restore_list(adev);
4069 gfx_v8_0_enable_save_restore_machine(adev);
4070 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4071 gfx_v8_0_init_power_gating(adev);
4072 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4073 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4074 (adev->asic_type == CHIP_POLARIS12)) {
4075 gfx_v8_0_init_csb(adev);
4076 gfx_v8_0_init_save_restore_list(adev);
4077 gfx_v8_0_enable_save_restore_machine(adev);
4078 gfx_v8_0_init_power_gating(adev);
4079 }
4080
4081}
4082
4083static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4084{
4085 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4086
4087 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4088 gfx_v8_0_wait_for_rlc_serdes(adev);
4089}
4090
4091static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4092{
4093 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4094 udelay(50);
4095
4096 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4097 udelay(50);
4098}
4099
4100static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4101{
4102 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4103
4104 /* carrizo do enable cp interrupt after cp inited */
4105 if (!(adev->flags & AMD_IS_APU))
4106 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4107
4108 udelay(50);
4109}
4110
4111static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
4112{
4113 const struct rlc_firmware_header_v2_0 *hdr;
4114 const __le32 *fw_data;
4115 unsigned i, fw_size;
4116
4117 if (!adev->gfx.rlc_fw)
4118 return -EINVAL;
4119
4120 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4121 amdgpu_ucode_print_rlc_hdr(&hdr->header);
4122
4123 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4124 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4125 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4126
4127 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
4128 for (i = 0; i < fw_size; i++)
4129 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
4130 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4131
4132 return 0;
4133}
4134
4135static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4136{
4137 int r;
4138 u32 tmp;
4139
4140 gfx_v8_0_rlc_stop(adev);
4141
4142 /* disable CG */
4143 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
4144 tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
4145 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4146 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
4147 if (adev->asic_type == CHIP_POLARIS11 ||
4148 adev->asic_type == CHIP_POLARIS10 ||
4149 adev->asic_type == CHIP_POLARIS12) {
4150 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
4151 tmp &= ~0x3;
4152 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
4153 }
4154
4155 /* disable PG */
4156 WREG32(mmRLC_PG_CNTL, 0);
4157
4158 gfx_v8_0_rlc_reset(adev);
4159 gfx_v8_0_init_pg(adev);
4160
4161
4162 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4163 /* legacy rlc firmware loading */
4164 r = gfx_v8_0_rlc_load_microcode(adev);
4165 if (r)
4166 return r;
4167 }
4168
4169 gfx_v8_0_rlc_start(adev);
4170
4171 return 0;
4172}
4173
4174static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4175{
4176 int i;
4177 u32 tmp = RREG32(mmCP_ME_CNTL);
4178
4179 if (enable) {
4180 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4181 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4182 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4183 } else {
4184 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4185 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4186 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4187 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4188 adev->gfx.gfx_ring[i].ready = false;
4189 }
4190 WREG32(mmCP_ME_CNTL, tmp);
4191 udelay(50);
4192}
4193
4194static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
4195{
4196 const struct gfx_firmware_header_v1_0 *pfp_hdr;
4197 const struct gfx_firmware_header_v1_0 *ce_hdr;
4198 const struct gfx_firmware_header_v1_0 *me_hdr;
4199 const __le32 *fw_data;
4200 unsigned i, fw_size;
4201
4202 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
4203 return -EINVAL;
4204
4205 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
4206 adev->gfx.pfp_fw->data;
4207 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
4208 adev->gfx.ce_fw->data;
4209 me_hdr = (const struct gfx_firmware_header_v1_0 *)
4210 adev->gfx.me_fw->data;
4211
4212 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
4213 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
4214 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
4215
4216 gfx_v8_0_cp_gfx_enable(adev, false);
4217
4218 /* PFP */
4219 fw_data = (const __le32 *)
4220 (adev->gfx.pfp_fw->data +
4221 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
4222 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
4223 WREG32(mmCP_PFP_UCODE_ADDR, 0);
4224 for (i = 0; i < fw_size; i++)
4225 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4226 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
4227
4228 /* CE */
4229 fw_data = (const __le32 *)
4230 (adev->gfx.ce_fw->data +
4231 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
4232 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
4233 WREG32(mmCP_CE_UCODE_ADDR, 0);
4234 for (i = 0; i < fw_size; i++)
4235 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4236 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
4237
4238 /* ME */
4239 fw_data = (const __le32 *)
4240 (adev->gfx.me_fw->data +
4241 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
4242 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
4243 WREG32(mmCP_ME_RAM_WADDR, 0);
4244 for (i = 0; i < fw_size; i++)
4245 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4246 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
4247
4248 return 0;
4249}
4250
4251static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4252{
4253 u32 count = 0;
4254 const struct cs_section_def *sect = NULL;
4255 const struct cs_extent_def *ext = NULL;
4256
4257 /* begin clear state */
4258 count += 2;
4259 /* context control state */
4260 count += 3;
4261
4262 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4263 for (ext = sect->section; ext->extent != NULL; ++ext) {
4264 if (sect->id == SECT_CONTEXT)
4265 count += 2 + ext->reg_count;
4266 else
4267 return 0;
4268 }
4269 }
4270 /* pa_sc_raster_config/pa_sc_raster_config1 */
4271 count += 4;
4272 /* end clear state */
4273 count += 2;
4274 /* clear state */
4275 count += 2;
4276
4277 return count;
4278}
4279
4280static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4281{
4282 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4283 const struct cs_section_def *sect = NULL;
4284 const struct cs_extent_def *ext = NULL;
4285 int r, i;
4286
4287 /* init the CP */
4288 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4289 WREG32(mmCP_ENDIAN_SWAP, 0);
4290 WREG32(mmCP_DEVICE_ID, 1);
4291
4292 gfx_v8_0_cp_gfx_enable(adev, true);
4293
4294 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4295 if (r) {
4296 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4297 return r;
4298 }
4299
4300 /* clear state buffer */
4301 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4302 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4303
4304 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4305 amdgpu_ring_write(ring, 0x80000000);
4306 amdgpu_ring_write(ring, 0x80000000);
4307
4308 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4309 for (ext = sect->section; ext->extent != NULL; ++ext) {
4310 if (sect->id == SECT_CONTEXT) {
4311 amdgpu_ring_write(ring,
4312 PACKET3(PACKET3_SET_CONTEXT_REG,
4313 ext->reg_count));
4314 amdgpu_ring_write(ring,
4315 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4316 for (i = 0; i < ext->reg_count; i++)
4317 amdgpu_ring_write(ring, ext->extent[i]);
4318 }
4319 }
4320 }
4321
4322 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4323 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4324 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4325 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4326
4327 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4328 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4329
4330 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4331 amdgpu_ring_write(ring, 0);
4332
4333 /* init the CE partitions */
4334 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4335 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4336 amdgpu_ring_write(ring, 0x8000);
4337 amdgpu_ring_write(ring, 0x8000);
4338
4339 amdgpu_ring_commit(ring);
4340
4341 return 0;
4342}
4343static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4344{
4345 u32 tmp;
4346 /* no gfx doorbells on iceland */
4347 if (adev->asic_type == CHIP_TOPAZ)
4348 return;
4349
4350 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4351
4352 if (ring->use_doorbell) {
4353 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4354 DOORBELL_OFFSET, ring->doorbell_index);
4355 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4356 DOORBELL_HIT, 0);
4357 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4358 DOORBELL_EN, 1);
4359 } else {
4360 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4361 }
4362
4363 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4364
4365 if (adev->flags & AMD_IS_APU)
4366 return;
4367
4368 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4369 DOORBELL_RANGE_LOWER,
4370 AMDGPU_DOORBELL_GFX_RING0);
4371 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4372
4373 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4374 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4375}
4376
4377static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4378{
4379 struct amdgpu_ring *ring;
4380 u32 tmp;
4381 u32 rb_bufsz;
4382 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4383 int r;
4384
4385 /* Set the write pointer delay */
4386 WREG32(mmCP_RB_WPTR_DELAY, 0);
4387
4388 /* set the RB to use vmid 0 */
4389 WREG32(mmCP_RB_VMID, 0);
4390
4391 /* Set ring buffer size */
4392 ring = &adev->gfx.gfx_ring[0];
4393 rb_bufsz = order_base_2(ring->ring_size / 8);
4394 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4395 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4396 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4397 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4398#ifdef __BIG_ENDIAN
4399 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4400#endif
4401 WREG32(mmCP_RB0_CNTL, tmp);
4402
4403 /* Initialize the ring buffer's read and write pointers */
4404 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4405 ring->wptr = 0;
4406 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4407
4408 /* set the wb address wether it's enabled or not */
4409 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4410 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4411 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4412
4413 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4414 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4415 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4416 mdelay(1);
4417 WREG32(mmCP_RB0_CNTL, tmp);
4418
4419 rb_addr = ring->gpu_addr >> 8;
4420 WREG32(mmCP_RB0_BASE, rb_addr);
4421 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4422
4423 gfx_v8_0_set_cpg_door_bell(adev, ring);
4424 /* start the ring */
4425 amdgpu_ring_clear_ring(ring);
4426 gfx_v8_0_cp_gfx_start(adev);
4427 ring->ready = true;
4428 r = amdgpu_ring_test_ring(ring);
4429 if (r)
4430 ring->ready = false;
4431
4432 return r;
4433}
4434
4435static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4436{
4437 int i;
4438
4439 if (enable) {
4440 WREG32(mmCP_MEC_CNTL, 0);
4441 } else {
4442 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4443 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4444 adev->gfx.compute_ring[i].ready = false;
4445 adev->gfx.kiq.ring.ready = false;
4446 }
4447 udelay(50);
4448}
4449
4450static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4451{
4452 const struct gfx_firmware_header_v1_0 *mec_hdr;
4453 const __le32 *fw_data;
4454 unsigned i, fw_size;
4455
4456 if (!adev->gfx.mec_fw)
4457 return -EINVAL;
4458
4459 gfx_v8_0_cp_compute_enable(adev, false);
4460
4461 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4462 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
4463
4464 fw_data = (const __le32 *)
4465 (adev->gfx.mec_fw->data +
4466 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4467 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4468
4469 /* MEC1 */
4470 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
4471 for (i = 0; i < fw_size; i++)
4472 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
4473 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
4474
4475 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
4476 if (adev->gfx.mec2_fw) {
4477 const struct gfx_firmware_header_v1_0 *mec2_hdr;
4478
4479 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4480 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
4481
4482 fw_data = (const __le32 *)
4483 (adev->gfx.mec2_fw->data +
4484 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4485 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4486
4487 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
4488 for (i = 0; i < fw_size; i++)
4489 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
4490 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
4491 }
4492
4493 return 0;
4494}
4495
4496/* KIQ functions */
4497static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4498{
4499 uint32_t tmp;
4500 struct amdgpu_device *adev = ring->adev;
4501
4502 /* tell RLC which is KIQ queue */
4503 tmp = RREG32(mmRLC_CP_SCHEDULERS);
4504 tmp &= 0xffffff00;
4505 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4506 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4507 tmp |= 0x80;
4508 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4509}
4510
4511static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4512{
4513 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4514 uint32_t scratch, tmp = 0;
4515 uint64_t queue_mask = 0;
4516 int r, i;
4517
4518 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4519 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4520 continue;
4521
4522 /* This situation may be hit in the future if a new HW
4523 * generation exposes more than 64 queues. If so, the
4524 * definition of queue_mask needs updating */
4525 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4526 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4527 break;
4528 }
4529
4530 queue_mask |= (1ull << i);
4531 }
4532
4533 r = amdgpu_gfx_scratch_get(adev, &scratch);
4534 if (r) {
4535 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
4536 return r;
4537 }
4538 WREG32(scratch, 0xCAFEDEAD);
4539
4540 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11);
4541 if (r) {
4542 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4543 amdgpu_gfx_scratch_free(adev, scratch);
4544 return r;
4545 }
4546 /* set resources */
4547 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4548 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4549 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4550 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4551 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4552 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4553 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4554 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4555 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4556 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4557 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4558 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4559
4560 /* map queues */
4561 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4562 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4563 amdgpu_ring_write(kiq_ring,
4564 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4565 amdgpu_ring_write(kiq_ring,
4566 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4567 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4568 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4569 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4570 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4571 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4572 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4573 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4574 }
4575 /* write to scratch for completion */
4576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4577 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
4578 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
4579 amdgpu_ring_commit(kiq_ring);
4580
4581 for (i = 0; i < adev->usec_timeout; i++) {
4582 tmp = RREG32(scratch);
4583 if (tmp == 0xDEADBEEF)
4584 break;
4585 DRM_UDELAY(1);
4586 }
4587 if (i >= adev->usec_timeout) {
4588 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
4589 scratch, tmp);
4590 r = -EINVAL;
4591 }
4592 amdgpu_gfx_scratch_free(adev, scratch);
4593
4594 return r;
4595}
4596
4597static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4598{
4599 int i, r = 0;
4600
4601 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4602 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4603 for (i = 0; i < adev->usec_timeout; i++) {
4604 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4605 break;
4606 udelay(1);
4607 }
4608 if (i == adev->usec_timeout)
4609 r = -ETIMEDOUT;
4610 }
4611 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4612 WREG32(mmCP_HQD_PQ_RPTR, 0);
4613 WREG32(mmCP_HQD_PQ_WPTR, 0);
4614
4615 return r;
4616}
4617
4618static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4619{
4620 struct amdgpu_device *adev = ring->adev;
4621 struct vi_mqd *mqd = ring->mqd_ptr;
4622 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4623 uint32_t tmp;
4624
4625 mqd->header = 0xC0310800;
4626 mqd->compute_pipelinestat_enable = 0x00000001;
4627 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4628 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4629 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4630 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4631 mqd->compute_misc_reserved = 0x00000003;
4632 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4633 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4634 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4635 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4636 eop_base_addr = ring->eop_gpu_addr >> 8;
4637 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4638 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4639
4640 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4641 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4642 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4643 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4644
4645 mqd->cp_hqd_eop_control = tmp;
4646
4647 /* enable doorbell? */
4648 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4649 CP_HQD_PQ_DOORBELL_CONTROL,
4650 DOORBELL_EN,
4651 ring->use_doorbell ? 1 : 0);
4652
4653 mqd->cp_hqd_pq_doorbell_control = tmp;
4654
4655 /* set the pointer to the MQD */
4656 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4657 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4658
4659 /* set MQD vmid to 0 */
4660 tmp = RREG32(mmCP_MQD_CONTROL);
4661 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4662 mqd->cp_mqd_control = tmp;
4663
4664 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4665 hqd_gpu_addr = ring->gpu_addr >> 8;
4666 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4667 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4668
4669 /* set up the HQD, this is similar to CP_RB0_CNTL */
4670 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4672 (order_base_2(ring->ring_size / 4) - 1));
4673 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4674 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4675#ifdef __BIG_ENDIAN
4676 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4677#endif
4678 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4679 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4680 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4681 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4682 mqd->cp_hqd_pq_control = tmp;
4683
4684 /* set the wb address whether it's enabled or not */
4685 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4686 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4687 mqd->cp_hqd_pq_rptr_report_addr_hi =
4688 upper_32_bits(wb_gpu_addr) & 0xffff;
4689
4690 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4691 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4692 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4693 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4694
4695 tmp = 0;
4696 /* enable the doorbell if requested */
4697 if (ring->use_doorbell) {
4698 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4699 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4700 DOORBELL_OFFSET, ring->doorbell_index);
4701
4702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4703 DOORBELL_EN, 1);
4704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4705 DOORBELL_SOURCE, 0);
4706 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4707 DOORBELL_HIT, 0);
4708 }
4709
4710 mqd->cp_hqd_pq_doorbell_control = tmp;
4711
4712 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4713 ring->wptr = 0;
4714 mqd->cp_hqd_pq_wptr = ring->wptr;
4715 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4716
4717 /* set the vmid for the queue */
4718 mqd->cp_hqd_vmid = 0;
4719
4720 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4721 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4722 mqd->cp_hqd_persistent_state = tmp;
4723
4724 /* set MTYPE */
4725 tmp = RREG32(mmCP_HQD_IB_CONTROL);
4726 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4727 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4728 mqd->cp_hqd_ib_control = tmp;
4729
4730 tmp = RREG32(mmCP_HQD_IQ_TIMER);
4731 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4732 mqd->cp_hqd_iq_timer = tmp;
4733
4734 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4735 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4736 mqd->cp_hqd_ctx_save_control = tmp;
4737
4738 /* defaults */
4739 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4740 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4741 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
4742 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
4743 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4744 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4745 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4746 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4747 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4748 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4749 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4750 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4751 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4752 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4753 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4754
4755 /* activate the queue */
4756 mqd->cp_hqd_active = 1;
4757
4758 return 0;
4759}
4760
4761int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4762 struct vi_mqd *mqd)
4763{
4764 uint32_t mqd_reg;
4765 uint32_t *mqd_data;
4766
4767 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4768 mqd_data = &mqd->cp_mqd_base_addr_lo;
4769
4770 /* disable wptr polling */
4771 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4772
4773 /* program all HQD registers */
4774 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4775 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4776
4777 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4778 * This is safe since EOP RPTR==WPTR for any inactive HQD
4779 * on ASICs that do not support context-save.
4780 * EOP writes/reads can start anywhere in the ring.
4781 */
4782 if (adev->asic_type != CHIP_TONGA) {
4783 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4784 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4785 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4786 }
4787
4788 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4789 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4790
4791 /* activate the HQD */
4792 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4793 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4794
4795 return 0;
4796}
4797
4798static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4799{
4800 struct amdgpu_device *adev = ring->adev;
4801 struct vi_mqd *mqd = ring->mqd_ptr;
4802 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4803
4804 gfx_v8_0_kiq_setting(ring);
4805
4806 if (adev->in_gpu_reset) { /* for GPU_RESET case */
4807 /* reset MQD to a clean status */
4808 if (adev->gfx.mec.mqd_backup[mqd_idx])
4809 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4810
4811 /* reset ring buffer */
4812 ring->wptr = 0;
4813 amdgpu_ring_clear_ring(ring);
4814 mutex_lock(&adev->srbm_mutex);
4815 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4816 gfx_v8_0_mqd_commit(adev, mqd);
4817 vi_srbm_select(adev, 0, 0, 0, 0);
4818 mutex_unlock(&adev->srbm_mutex);
4819 } else {
4820 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4821 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4822 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4823 mutex_lock(&adev->srbm_mutex);
4824 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4825 gfx_v8_0_mqd_init(ring);
4826 gfx_v8_0_mqd_commit(adev, mqd);
4827 vi_srbm_select(adev, 0, 0, 0, 0);
4828 mutex_unlock(&adev->srbm_mutex);
4829
4830 if (adev->gfx.mec.mqd_backup[mqd_idx])
4831 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4832 }
4833
4834 return 0;
4835}
4836
4837static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4838{
4839 struct amdgpu_device *adev = ring->adev;
4840 struct vi_mqd *mqd = ring->mqd_ptr;
4841 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4842
4843 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
4844 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4845 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4846 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4847 mutex_lock(&adev->srbm_mutex);
4848 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4849 gfx_v8_0_mqd_init(ring);
4850 vi_srbm_select(adev, 0, 0, 0, 0);
4851 mutex_unlock(&adev->srbm_mutex);
4852
4853 if (adev->gfx.mec.mqd_backup[mqd_idx])
4854 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4855 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
4856 /* reset MQD to a clean status */
4857 if (adev->gfx.mec.mqd_backup[mqd_idx])
4858 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4859 /* reset ring buffer */
4860 ring->wptr = 0;
4861 amdgpu_ring_clear_ring(ring);
4862 } else {
4863 amdgpu_ring_clear_ring(ring);
4864 }
4865 return 0;
4866}
4867
4868static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4869{
4870 if (adev->asic_type > CHIP_TONGA) {
4871 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);
4872 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);
4873 }
4874 /* enable doorbells */
4875 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4876}
4877
4878static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4879{
4880 struct amdgpu_ring *ring = NULL;
4881 int r = 0, i;
4882
4883 gfx_v8_0_cp_compute_enable(adev, true);
4884
4885 ring = &adev->gfx.kiq.ring;
4886
4887 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4888 if (unlikely(r != 0))
4889 goto done;
4890
4891 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4892 if (!r) {
4893 r = gfx_v8_0_kiq_init_queue(ring);
4894 amdgpu_bo_kunmap(ring->mqd_obj);
4895 ring->mqd_ptr = NULL;
4896 }
4897 amdgpu_bo_unreserve(ring->mqd_obj);
4898 if (r)
4899 goto done;
4900
4901 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4902 ring = &adev->gfx.compute_ring[i];
4903
4904 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4905 if (unlikely(r != 0))
4906 goto done;
4907 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4908 if (!r) {
4909 r = gfx_v8_0_kcq_init_queue(ring);
4910 amdgpu_bo_kunmap(ring->mqd_obj);
4911 ring->mqd_ptr = NULL;
4912 }
4913 amdgpu_bo_unreserve(ring->mqd_obj);
4914 if (r)
4915 goto done;
4916 }
4917
4918 gfx_v8_0_set_mec_doorbell_range(adev);
4919
4920 r = gfx_v8_0_kiq_kcq_enable(adev);
4921 if (r)
4922 goto done;
4923
4924 /* Test KIQ */
4925 ring = &adev->gfx.kiq.ring;
4926 ring->ready = true;
4927 r = amdgpu_ring_test_ring(ring);
4928 if (r) {
4929 ring->ready = false;
4930 goto done;
4931 }
4932
4933 /* Test KCQs */
4934 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4935 ring = &adev->gfx.compute_ring[i];
4936 ring->ready = true;
4937 r = amdgpu_ring_test_ring(ring);
4938 if (r)
4939 ring->ready = false;
4940 }
4941
4942done:
4943 return r;
4944}
4945
4946static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4947{
4948 int r;
4949
4950 if (!(adev->flags & AMD_IS_APU))
4951 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4952
4953 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4954 /* legacy firmware loading */
4955 r = gfx_v8_0_cp_gfx_load_microcode(adev);
4956 if (r)
4957 return r;
4958
4959 r = gfx_v8_0_cp_compute_load_microcode(adev);
4960 if (r)
4961 return r;
4962 }
4963
4964 r = gfx_v8_0_cp_gfx_resume(adev);
4965 if (r)
4966 return r;
4967
4968 r = gfx_v8_0_kiq_resume(adev);
4969 if (r)
4970 return r;
4971
4972 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4973
4974 return 0;
4975}
4976
4977static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4978{
4979 gfx_v8_0_cp_gfx_enable(adev, enable);
4980 gfx_v8_0_cp_compute_enable(adev, enable);
4981}
4982
4983static int gfx_v8_0_hw_init(void *handle)
4984{
4985 int r;
4986 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4987
4988 gfx_v8_0_init_golden_registers(adev);
4989 gfx_v8_0_gpu_init(adev);
4990
4991 r = gfx_v8_0_rlc_resume(adev);
4992 if (r)
4993 return r;
4994
4995 r = gfx_v8_0_cp_resume(adev);
4996
4997 return r;
4998}
4999
5000static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
5001{
5002 struct amdgpu_device *adev = kiq_ring->adev;
5003 uint32_t scratch, tmp = 0;
5004 int r, i;
5005
5006 r = amdgpu_gfx_scratch_get(adev, &scratch);
5007 if (r) {
5008 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
5009 return r;
5010 }
5011 WREG32(scratch, 0xCAFEDEAD);
5012
5013 r = amdgpu_ring_alloc(kiq_ring, 10);
5014 if (r) {
5015 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
5016 amdgpu_gfx_scratch_free(adev, scratch);
5017 return r;
5018 }
5019
5020 /* unmap queues */
5021 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
5022 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
5023 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
5024 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
5025 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
5026 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
5027 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
5028 amdgpu_ring_write(kiq_ring, 0);
5029 amdgpu_ring_write(kiq_ring, 0);
5030 amdgpu_ring_write(kiq_ring, 0);
5031 /* write to scratch for completion */
5032 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
5033 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
5034 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
5035 amdgpu_ring_commit(kiq_ring);
5036
5037 for (i = 0; i < adev->usec_timeout; i++) {
5038 tmp = RREG32(scratch);
5039 if (tmp == 0xDEADBEEF)
5040 break;
5041 DRM_UDELAY(1);
5042 }
5043 if (i >= adev->usec_timeout) {
5044 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
5045 r = -EINVAL;
5046 }
5047 amdgpu_gfx_scratch_free(adev, scratch);
5048 return r;
5049}
5050
5051static int gfx_v8_0_hw_fini(void *handle)
5052{
5053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5054 int i;
5055
5056 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
5057 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
5058
5059 /* disable KCQ to avoid CPC touch memory not valid anymore */
5060 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5061 gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
5062
5063 if (amdgpu_sriov_vf(adev)) {
5064 pr_debug("For SRIOV client, shouldn't do anything.\n");
5065 return 0;
5066 }
5067 gfx_v8_0_cp_enable(adev, false);
5068 gfx_v8_0_rlc_stop(adev);
5069
5070 amdgpu_device_ip_set_powergating_state(adev,
5071 AMD_IP_BLOCK_TYPE_GFX,
5072 AMD_PG_STATE_UNGATE);
5073
5074 return 0;
5075}
5076
5077static int gfx_v8_0_suspend(void *handle)
5078{
5079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5080 adev->gfx.in_suspend = true;
5081 return gfx_v8_0_hw_fini(adev);
5082}
5083
5084static int gfx_v8_0_resume(void *handle)
5085{
5086 int r;
5087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5088
5089 r = gfx_v8_0_hw_init(adev);
5090 adev->gfx.in_suspend = false;
5091 return r;
5092}
5093
5094static bool gfx_v8_0_is_idle(void *handle)
5095{
5096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5097
5098 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
5099 return false;
5100 else
5101 return true;
5102}
5103
5104static int gfx_v8_0_wait_for_idle(void *handle)
5105{
5106 unsigned i;
5107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5108
5109 for (i = 0; i < adev->usec_timeout; i++) {
5110 if (gfx_v8_0_is_idle(handle))
5111 return 0;
5112
5113 udelay(1);
5114 }
5115 return -ETIMEDOUT;
5116}
5117
5118static bool gfx_v8_0_check_soft_reset(void *handle)
5119{
5120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5121 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5122 u32 tmp;
5123
5124 /* GRBM_STATUS */
5125 tmp = RREG32(mmGRBM_STATUS);
5126 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5127 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5128 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5129 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5130 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5131 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
5132 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5133 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5134 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
5135 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5136 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
5137 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5138 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5139 }
5140
5141 /* GRBM_STATUS2 */
5142 tmp = RREG32(mmGRBM_STATUS2);
5143 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
5144 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5145 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5146
5147 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
5148 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
5149 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
5150 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5151 SOFT_RESET_CPF, 1);
5152 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5153 SOFT_RESET_CPC, 1);
5154 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5155 SOFT_RESET_CPG, 1);
5156 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
5157 SOFT_RESET_GRBM, 1);
5158 }
5159
5160 /* SRBM_STATUS */
5161 tmp = RREG32(mmSRBM_STATUS);
5162 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5163 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5164 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5165 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
5166 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5167 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
5168
5169 if (grbm_soft_reset || srbm_soft_reset) {
5170 adev->gfx.grbm_soft_reset = grbm_soft_reset;
5171 adev->gfx.srbm_soft_reset = srbm_soft_reset;
5172 return true;
5173 } else {
5174 adev->gfx.grbm_soft_reset = 0;
5175 adev->gfx.srbm_soft_reset = 0;
5176 return false;
5177 }
5178}
5179
5180static int gfx_v8_0_pre_soft_reset(void *handle)
5181{
5182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5183 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5184
5185 if ((!adev->gfx.grbm_soft_reset) &&
5186 (!adev->gfx.srbm_soft_reset))
5187 return 0;
5188
5189 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5190 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5191
5192 /* stop the rlc */
5193 gfx_v8_0_rlc_stop(adev);
5194
5195 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5196 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5197 /* Disable GFX parsing/prefetching */
5198 gfx_v8_0_cp_gfx_enable(adev, false);
5199
5200 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5201 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5202 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5203 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5204 int i;
5205
5206 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5207 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5208
5209 mutex_lock(&adev->srbm_mutex);
5210 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5211 gfx_v8_0_deactivate_hqd(adev, 2);
5212 vi_srbm_select(adev, 0, 0, 0, 0);
5213 mutex_unlock(&adev->srbm_mutex);
5214 }
5215 /* Disable MEC parsing/prefetching */
5216 gfx_v8_0_cp_compute_enable(adev, false);
5217 }
5218
5219 return 0;
5220}
5221
5222static int gfx_v8_0_soft_reset(void *handle)
5223{
5224 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5225 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5226 u32 tmp;
5227
5228 if ((!adev->gfx.grbm_soft_reset) &&
5229 (!adev->gfx.srbm_soft_reset))
5230 return 0;
5231
5232 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5233 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5234
5235 if (grbm_soft_reset || srbm_soft_reset) {
5236 tmp = RREG32(mmGMCON_DEBUG);
5237 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5238 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5239 WREG32(mmGMCON_DEBUG, tmp);
5240 udelay(50);
5241 }
5242
5243 if (grbm_soft_reset) {
5244 tmp = RREG32(mmGRBM_SOFT_RESET);
5245 tmp |= grbm_soft_reset;
5246 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5247 WREG32(mmGRBM_SOFT_RESET, tmp);
5248 tmp = RREG32(mmGRBM_SOFT_RESET);
5249
5250 udelay(50);
5251
5252 tmp &= ~grbm_soft_reset;
5253 WREG32(mmGRBM_SOFT_RESET, tmp);
5254 tmp = RREG32(mmGRBM_SOFT_RESET);
5255 }
5256
5257 if (srbm_soft_reset) {
5258 tmp = RREG32(mmSRBM_SOFT_RESET);
5259 tmp |= srbm_soft_reset;
5260 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5261 WREG32(mmSRBM_SOFT_RESET, tmp);
5262 tmp = RREG32(mmSRBM_SOFT_RESET);
5263
5264 udelay(50);
5265
5266 tmp &= ~srbm_soft_reset;
5267 WREG32(mmSRBM_SOFT_RESET, tmp);
5268 tmp = RREG32(mmSRBM_SOFT_RESET);
5269 }
5270
5271 if (grbm_soft_reset || srbm_soft_reset) {
5272 tmp = RREG32(mmGMCON_DEBUG);
5273 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5274 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5275 WREG32(mmGMCON_DEBUG, tmp);
5276 }
5277
5278 /* Wait a little for things to settle down */
5279 udelay(50);
5280
5281 return 0;
5282}
5283
5284static int gfx_v8_0_post_soft_reset(void *handle)
5285{
5286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5287 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5288
5289 if ((!adev->gfx.grbm_soft_reset) &&
5290 (!adev->gfx.srbm_soft_reset))
5291 return 0;
5292
5293 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5294 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5295
5296 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5297 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5298 gfx_v8_0_cp_gfx_resume(adev);
5299
5300 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5301 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5302 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5303 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5304 int i;
5305
5306 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5307 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5308
5309 mutex_lock(&adev->srbm_mutex);
5310 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5311 gfx_v8_0_deactivate_hqd(adev, 2);
5312 vi_srbm_select(adev, 0, 0, 0, 0);
5313 mutex_unlock(&adev->srbm_mutex);
5314 }
5315 gfx_v8_0_kiq_resume(adev);
5316 }
5317 gfx_v8_0_rlc_start(adev);
5318
5319 return 0;
5320}
5321
5322/**
5323 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5324 *
5325 * @adev: amdgpu_device pointer
5326 *
5327 * Fetches a GPU clock counter snapshot.
5328 * Returns the 64 bit clock counter snapshot.
5329 */
5330static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5331{
5332 uint64_t clock;
5333
5334 mutex_lock(&adev->gfx.gpu_clock_mutex);
5335 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5336 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5337 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5338 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5339 return clock;
5340}
5341
5342static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5343 uint32_t vmid,
5344 uint32_t gds_base, uint32_t gds_size,
5345 uint32_t gws_base, uint32_t gws_size,
5346 uint32_t oa_base, uint32_t oa_size)
5347{
5348 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
5349 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
5350
5351 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
5352 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
5353
5354 oa_base = oa_base >> AMDGPU_OA_SHIFT;
5355 oa_size = oa_size >> AMDGPU_OA_SHIFT;
5356
5357 /* GDS Base */
5358 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5359 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5360 WRITE_DATA_DST_SEL(0)));
5361 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5362 amdgpu_ring_write(ring, 0);
5363 amdgpu_ring_write(ring, gds_base);
5364
5365 /* GDS Size */
5366 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5367 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5368 WRITE_DATA_DST_SEL(0)));
5369 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5370 amdgpu_ring_write(ring, 0);
5371 amdgpu_ring_write(ring, gds_size);
5372
5373 /* GWS */
5374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5375 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5376 WRITE_DATA_DST_SEL(0)));
5377 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5378 amdgpu_ring_write(ring, 0);
5379 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5380
5381 /* OA */
5382 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5383 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5384 WRITE_DATA_DST_SEL(0)));
5385 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5386 amdgpu_ring_write(ring, 0);
5387 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5388}
5389
5390static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5391{
5392 WREG32(mmSQ_IND_INDEX,
5393 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5394 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5395 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5396 (SQ_IND_INDEX__FORCE_READ_MASK));
5397 return RREG32(mmSQ_IND_DATA);
5398}
5399
5400static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5401 uint32_t wave, uint32_t thread,
5402 uint32_t regno, uint32_t num, uint32_t *out)
5403{
5404 WREG32(mmSQ_IND_INDEX,
5405 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5406 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5407 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5408 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5409 (SQ_IND_INDEX__FORCE_READ_MASK) |
5410 (SQ_IND_INDEX__AUTO_INCR_MASK));
5411 while (num--)
5412 *(out++) = RREG32(mmSQ_IND_DATA);
5413}
5414
5415static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5416{
5417 /* type 0 wave data */
5418 dst[(*no_fields)++] = 0;
5419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5420 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5421 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5422 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5423 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5424 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5425 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5426 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5427 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5428 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5429 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5430 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5431 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5432 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5433 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5434 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5435 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5436 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5437}
5438
5439static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5440 uint32_t wave, uint32_t start,
5441 uint32_t size, uint32_t *dst)
5442{
5443 wave_read_regs(
5444 adev, simd, wave, 0,
5445 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5446}
5447
5448
5449static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5450 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5451 .select_se_sh = &gfx_v8_0_select_se_sh,
5452 .read_wave_data = &gfx_v8_0_read_wave_data,
5453 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5454 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5455};
5456
5457static int gfx_v8_0_early_init(void *handle)
5458{
5459 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5460
5461 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5462 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
5463 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5464 gfx_v8_0_set_ring_funcs(adev);
5465 gfx_v8_0_set_irq_funcs(adev);
5466 gfx_v8_0_set_gds_init(adev);
5467 gfx_v8_0_set_rlc_funcs(adev);
5468
5469 return 0;
5470}
5471
5472static int gfx_v8_0_late_init(void *handle)
5473{
5474 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5475 int r;
5476
5477 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5478 if (r)
5479 return r;
5480
5481 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5482 if (r)
5483 return r;
5484
5485 /* requires IBs so do in late init after IB pool is initialized */
5486 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5487 if (r)
5488 return r;
5489
5490 amdgpu_device_ip_set_powergating_state(adev,
5491 AMD_IP_BLOCK_TYPE_GFX,
5492 AMD_PG_STATE_GATE);
5493
5494 return 0;
5495}
5496
5497static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5498 bool enable)
5499{
5500 if ((adev->asic_type == CHIP_POLARIS11) ||
5501 (adev->asic_type == CHIP_POLARIS12))
5502 /* Send msg to SMU via Powerplay */
5503 amdgpu_device_ip_set_powergating_state(adev,
5504 AMD_IP_BLOCK_TYPE_SMC,
5505 enable ?
5506 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
5507
5508 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5509}
5510
5511static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5512 bool enable)
5513{
5514 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5515}
5516
5517static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5518 bool enable)
5519{
5520 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5521}
5522
5523static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5524 bool enable)
5525{
5526 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5527}
5528
5529static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5530 bool enable)
5531{
5532 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5533
5534 /* Read any GFX register to wake up GFX. */
5535 if (!enable)
5536 RREG32(mmDB_RENDER_CONTROL);
5537}
5538
5539static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5540 bool enable)
5541{
5542 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5543 cz_enable_gfx_cg_power_gating(adev, true);
5544 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5545 cz_enable_gfx_pipeline_power_gating(adev, true);
5546 } else {
5547 cz_enable_gfx_cg_power_gating(adev, false);
5548 cz_enable_gfx_pipeline_power_gating(adev, false);
5549 }
5550}
5551
5552static int gfx_v8_0_set_powergating_state(void *handle,
5553 enum amd_powergating_state state)
5554{
5555 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5556 bool enable = (state == AMD_PG_STATE_GATE);
5557
5558 if (amdgpu_sriov_vf(adev))
5559 return 0;
5560
5561 switch (adev->asic_type) {
5562 case CHIP_CARRIZO:
5563 case CHIP_STONEY:
5564
5565 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5566 cz_enable_sck_slow_down_on_power_up(adev, true);
5567 cz_enable_sck_slow_down_on_power_down(adev, true);
5568 } else {
5569 cz_enable_sck_slow_down_on_power_up(adev, false);
5570 cz_enable_sck_slow_down_on_power_down(adev, false);
5571 }
5572 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5573 cz_enable_cp_power_gating(adev, true);
5574 else
5575 cz_enable_cp_power_gating(adev, false);
5576
5577 cz_update_gfx_cg_power_gating(adev, enable);
5578
5579 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5580 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5581 else
5582 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5583
5584 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5585 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5586 else
5587 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5588 break;
5589 case CHIP_POLARIS11:
5590 case CHIP_POLARIS12:
5591 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5592 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5593 else
5594 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5595
5596 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5597 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5598 else
5599 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5600
5601 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5602 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5603 else
5604 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5605 break;
5606 default:
5607 break;
5608 }
5609
5610 return 0;
5611}
5612
5613static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5614{
5615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5616 int data;
5617
5618 if (amdgpu_sriov_vf(adev))
5619 *flags = 0;
5620
5621 /* AMD_CG_SUPPORT_GFX_MGCG */
5622 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5623 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5624 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5625
5626 /* AMD_CG_SUPPORT_GFX_CGLG */
5627 data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5628 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5629 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5630
5631 /* AMD_CG_SUPPORT_GFX_CGLS */
5632 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5633 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5634
5635 /* AMD_CG_SUPPORT_GFX_CGTS */
5636 data = RREG32(mmCGTS_SM_CTRL_REG);
5637 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5638 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5639
5640 /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5641 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5642 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5643
5644 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5645 data = RREG32(mmRLC_MEM_SLP_CNTL);
5646 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5647 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5648
5649 /* AMD_CG_SUPPORT_GFX_CP_LS */
5650 data = RREG32(mmCP_MEM_SLP_CNTL);
5651 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5652 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5653}
5654
5655static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5656 uint32_t reg_addr, uint32_t cmd)
5657{
5658 uint32_t data;
5659
5660 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5661
5662 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5663 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5664
5665 data = RREG32(mmRLC_SERDES_WR_CTRL);
5666 if (adev->asic_type == CHIP_STONEY)
5667 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5668 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5669 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5670 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5671 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5672 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5673 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5674 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5675 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5676 else
5677 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5678 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5679 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5680 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5681 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5682 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5683 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5684 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5685 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5686 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5687 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5688 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5689 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5690 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5691 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5692
5693 WREG32(mmRLC_SERDES_WR_CTRL, data);
5694}
5695
5696#define MSG_ENTER_RLC_SAFE_MODE 1
5697#define MSG_EXIT_RLC_SAFE_MODE 0
5698#define RLC_GPR_REG2__REQ_MASK 0x00000001
5699#define RLC_GPR_REG2__REQ__SHIFT 0
5700#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5701#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5702
5703static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
5704{
5705 u32 data;
5706 unsigned i;
5707
5708 data = RREG32(mmRLC_CNTL);
5709 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5710 return;
5711
5712 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5713 data |= RLC_SAFE_MODE__CMD_MASK;
5714 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5715 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5716 WREG32(mmRLC_SAFE_MODE, data);
5717
5718 for (i = 0; i < adev->usec_timeout; i++) {
5719 if ((RREG32(mmRLC_GPM_STAT) &
5720 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5721 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5722 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5723 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5724 break;
5725 udelay(1);
5726 }
5727
5728 for (i = 0; i < adev->usec_timeout; i++) {
5729 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5730 break;
5731 udelay(1);
5732 }
5733 adev->gfx.rlc.in_safe_mode = true;
5734 }
5735}
5736
5737static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
5738{
5739 u32 data = 0;
5740 unsigned i;
5741
5742 data = RREG32(mmRLC_CNTL);
5743 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5744 return;
5745
5746 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5747 if (adev->gfx.rlc.in_safe_mode) {
5748 data |= RLC_SAFE_MODE__CMD_MASK;
5749 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5750 WREG32(mmRLC_SAFE_MODE, data);
5751 adev->gfx.rlc.in_safe_mode = false;
5752 }
5753 }
5754
5755 for (i = 0; i < adev->usec_timeout; i++) {
5756 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5757 break;
5758 udelay(1);
5759 }
5760}
5761
5762static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5763 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5764 .exit_safe_mode = iceland_exit_rlc_safe_mode
5765};
5766
5767static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5768 bool enable)
5769{
5770 uint32_t temp, data;
5771
5772 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5773
5774 /* It is disabled by HW by default */
5775 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5776 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5777 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5778 /* 1 - RLC memory Light sleep */
5779 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5780
5781 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5782 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5783 }
5784
5785 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5786 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5787 if (adev->flags & AMD_IS_APU)
5788 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5789 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5790 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5791 else
5792 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5793 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5794 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5795 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5796
5797 if (temp != data)
5798 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5799
5800 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5801 gfx_v8_0_wait_for_rlc_serdes(adev);
5802
5803 /* 5 - clear mgcg override */
5804 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5805
5806 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5807 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5808 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5809 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5810 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5811 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5812 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5813 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5814 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5815 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5816 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5817 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5818 if (temp != data)
5819 WREG32(mmCGTS_SM_CTRL_REG, data);
5820 }
5821 udelay(50);
5822
5823 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5824 gfx_v8_0_wait_for_rlc_serdes(adev);
5825 } else {
5826 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5827 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5828 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5829 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5830 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5831 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5832 if (temp != data)
5833 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5834
5835 /* 2 - disable MGLS in RLC */
5836 data = RREG32(mmRLC_MEM_SLP_CNTL);
5837 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5838 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5839 WREG32(mmRLC_MEM_SLP_CNTL, data);
5840 }
5841
5842 /* 3 - disable MGLS in CP */
5843 data = RREG32(mmCP_MEM_SLP_CNTL);
5844 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5845 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5846 WREG32(mmCP_MEM_SLP_CNTL, data);
5847 }
5848
5849 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5850 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5851 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5852 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5853 if (temp != data)
5854 WREG32(mmCGTS_SM_CTRL_REG, data);
5855
5856 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5857 gfx_v8_0_wait_for_rlc_serdes(adev);
5858
5859 /* 6 - set mgcg override */
5860 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5861
5862 udelay(50);
5863
5864 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5865 gfx_v8_0_wait_for_rlc_serdes(adev);
5866 }
5867
5868 adev->gfx.rlc.funcs->exit_safe_mode(adev);
5869}
5870
5871static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5872 bool enable)
5873{
5874 uint32_t temp, temp1, data, data1;
5875
5876 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5877
5878 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5879
5880 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5881 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5882 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5883 if (temp1 != data1)
5884 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5885
5886 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5887 gfx_v8_0_wait_for_rlc_serdes(adev);
5888
5889 /* 2 - clear cgcg override */
5890 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5891
5892 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5893 gfx_v8_0_wait_for_rlc_serdes(adev);
5894
5895 /* 3 - write cmd to set CGLS */
5896 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5897
5898 /* 4 - enable cgcg */
5899 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5900
5901 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5902 /* enable cgls*/
5903 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5904
5905 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5906 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5907
5908 if (temp1 != data1)
5909 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5910 } else {
5911 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5912 }
5913
5914 if (temp != data)
5915 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5916
5917 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5918 * Cmp_busy/GFX_Idle interrupts
5919 */
5920 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5921 } else {
5922 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5923 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5924
5925 /* TEST CGCG */
5926 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5927 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5928 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5929 if (temp1 != data1)
5930 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5931
5932 /* read gfx register to wake up cgcg */
5933 RREG32(mmCB_CGTT_SCLK_CTRL);
5934 RREG32(mmCB_CGTT_SCLK_CTRL);
5935 RREG32(mmCB_CGTT_SCLK_CTRL);
5936 RREG32(mmCB_CGTT_SCLK_CTRL);
5937
5938 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5939 gfx_v8_0_wait_for_rlc_serdes(adev);
5940
5941 /* write cmd to Set CGCG Overrride */
5942 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5943
5944 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5945 gfx_v8_0_wait_for_rlc_serdes(adev);
5946
5947 /* write cmd to Clear CGLS */
5948 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5949
5950 /* disable cgcg, cgls should be disabled too. */
5951 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5952 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5953 if (temp != data)
5954 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5955 /* enable interrupts again for PG */
5956 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5957 }
5958
5959 gfx_v8_0_wait_for_rlc_serdes(adev);
5960
5961 adev->gfx.rlc.funcs->exit_safe_mode(adev);
5962}
5963static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5964 bool enable)
5965{
5966 if (enable) {
5967 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5968 * === MGCG + MGLS + TS(CG/LS) ===
5969 */
5970 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5971 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5972 } else {
5973 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5974 * === CGCG + CGLS ===
5975 */
5976 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5977 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5978 }
5979 return 0;
5980}
5981
5982static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5983 enum amd_clockgating_state state)
5984{
5985 uint32_t msg_id, pp_state = 0;
5986 uint32_t pp_support_state = 0;
5987
5988 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5989 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5990 pp_support_state = PP_STATE_SUPPORT_LS;
5991 pp_state = PP_STATE_LS;
5992 }
5993 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5994 pp_support_state |= PP_STATE_SUPPORT_CG;
5995 pp_state |= PP_STATE_CG;
5996 }
5997 if (state == AMD_CG_STATE_UNGATE)
5998 pp_state = 0;
5999
6000 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6001 PP_BLOCK_GFX_CG,
6002 pp_support_state,
6003 pp_state);
6004 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6005 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6006 }
6007
6008 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
6009 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
6010 pp_support_state = PP_STATE_SUPPORT_LS;
6011 pp_state = PP_STATE_LS;
6012 }
6013
6014 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
6015 pp_support_state |= PP_STATE_SUPPORT_CG;
6016 pp_state |= PP_STATE_CG;
6017 }
6018
6019 if (state == AMD_CG_STATE_UNGATE)
6020 pp_state = 0;
6021
6022 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6023 PP_BLOCK_GFX_MG,
6024 pp_support_state,
6025 pp_state);
6026 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6027 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6028 }
6029
6030 return 0;
6031}
6032
6033static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
6034 enum amd_clockgating_state state)
6035{
6036
6037 uint32_t msg_id, pp_state = 0;
6038 uint32_t pp_support_state = 0;
6039
6040 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
6041 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
6042 pp_support_state = PP_STATE_SUPPORT_LS;
6043 pp_state = PP_STATE_LS;
6044 }
6045 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
6046 pp_support_state |= PP_STATE_SUPPORT_CG;
6047 pp_state |= PP_STATE_CG;
6048 }
6049 if (state == AMD_CG_STATE_UNGATE)
6050 pp_state = 0;
6051
6052 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6053 PP_BLOCK_GFX_CG,
6054 pp_support_state,
6055 pp_state);
6056 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6057 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6058 }
6059
6060 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
6061 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
6062 pp_support_state = PP_STATE_SUPPORT_LS;
6063 pp_state = PP_STATE_LS;
6064 }
6065 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
6066 pp_support_state |= PP_STATE_SUPPORT_CG;
6067 pp_state |= PP_STATE_CG;
6068 }
6069 if (state == AMD_CG_STATE_UNGATE)
6070 pp_state = 0;
6071
6072 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6073 PP_BLOCK_GFX_3D,
6074 pp_support_state,
6075 pp_state);
6076 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6077 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6078 }
6079
6080 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
6081 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
6082 pp_support_state = PP_STATE_SUPPORT_LS;
6083 pp_state = PP_STATE_LS;
6084 }
6085
6086 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
6087 pp_support_state |= PP_STATE_SUPPORT_CG;
6088 pp_state |= PP_STATE_CG;
6089 }
6090
6091 if (state == AMD_CG_STATE_UNGATE)
6092 pp_state = 0;
6093
6094 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6095 PP_BLOCK_GFX_MG,
6096 pp_support_state,
6097 pp_state);
6098 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6099 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6100 }
6101
6102 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
6103 pp_support_state = PP_STATE_SUPPORT_LS;
6104
6105 if (state == AMD_CG_STATE_UNGATE)
6106 pp_state = 0;
6107 else
6108 pp_state = PP_STATE_LS;
6109
6110 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6111 PP_BLOCK_GFX_RLC,
6112 pp_support_state,
6113 pp_state);
6114 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6115 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6116 }
6117
6118 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
6119 pp_support_state = PP_STATE_SUPPORT_LS;
6120
6121 if (state == AMD_CG_STATE_UNGATE)
6122 pp_state = 0;
6123 else
6124 pp_state = PP_STATE_LS;
6125 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6126 PP_BLOCK_GFX_CP,
6127 pp_support_state,
6128 pp_state);
6129 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
6130 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6131 }
6132
6133 return 0;
6134}
6135
6136static int gfx_v8_0_set_clockgating_state(void *handle,
6137 enum amd_clockgating_state state)
6138{
6139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6140
6141 if (amdgpu_sriov_vf(adev))
6142 return 0;
6143
6144 switch (adev->asic_type) {
6145 case CHIP_FIJI:
6146 case CHIP_CARRIZO:
6147 case CHIP_STONEY:
6148 gfx_v8_0_update_gfx_clock_gating(adev,
6149 state == AMD_CG_STATE_GATE);
6150 break;
6151 case CHIP_TONGA:
6152 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
6153 break;
6154 case CHIP_POLARIS10:
6155 case CHIP_POLARIS11:
6156 case CHIP_POLARIS12:
6157 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6158 break;
6159 default:
6160 break;
6161 }
6162 return 0;
6163}
6164
6165static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6166{
6167 return ring->adev->wb.wb[ring->rptr_offs];
6168}
6169
6170static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6171{
6172 struct amdgpu_device *adev = ring->adev;
6173
6174 if (ring->use_doorbell)
6175 /* XXX check if swapping is necessary on BE */
6176 return ring->adev->wb.wb[ring->wptr_offs];
6177 else
6178 return RREG32(mmCP_RB0_WPTR);
6179}
6180
6181static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6182{
6183 struct amdgpu_device *adev = ring->adev;
6184
6185 if (ring->use_doorbell) {
6186 /* XXX check if swapping is necessary on BE */
6187 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6188 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6189 } else {
6190 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6191 (void)RREG32(mmCP_RB0_WPTR);
6192 }
6193}
6194
6195static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6196{
6197 u32 ref_and_mask, reg_mem_engine;
6198
6199 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6200 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6201 switch (ring->me) {
6202 case 1:
6203 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6204 break;
6205 case 2:
6206 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6207 break;
6208 default:
6209 return;
6210 }
6211 reg_mem_engine = 0;
6212 } else {
6213 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6214 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6215 }
6216
6217 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6218 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6219 WAIT_REG_MEM_FUNCTION(3) | /* == */
6220 reg_mem_engine));
6221 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6222 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6223 amdgpu_ring_write(ring, ref_and_mask);
6224 amdgpu_ring_write(ring, ref_and_mask);
6225 amdgpu_ring_write(ring, 0x20); /* poll interval */
6226}
6227
6228static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6229{
6230 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6231 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6232 EVENT_INDEX(4));
6233
6234 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6235 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6236 EVENT_INDEX(0));
6237}
6238
6239static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6240 struct amdgpu_ib *ib,
6241 unsigned vmid, bool ctx_switch)
6242{
6243 u32 header, control = 0;
6244
6245 if (ib->flags & AMDGPU_IB_FLAG_CE)
6246 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6247 else
6248 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6249
6250 control |= ib->length_dw | (vmid << 24);
6251
6252 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6253 control |= INDIRECT_BUFFER_PRE_ENB(1);
6254
6255 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
6256 gfx_v8_0_ring_emit_de_meta(ring);
6257 }
6258
6259 amdgpu_ring_write(ring, header);
6260 amdgpu_ring_write(ring,
6261#ifdef __BIG_ENDIAN
6262 (2 << 0) |
6263#endif
6264 (ib->gpu_addr & 0xFFFFFFFC));
6265 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6266 amdgpu_ring_write(ring, control);
6267}
6268
6269static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6270 struct amdgpu_ib *ib,
6271 unsigned vmid, bool ctx_switch)
6272{
6273 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6274
6275 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6276 amdgpu_ring_write(ring,
6277#ifdef __BIG_ENDIAN
6278 (2 << 0) |
6279#endif
6280 (ib->gpu_addr & 0xFFFFFFFC));
6281 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6282 amdgpu_ring_write(ring, control);
6283}
6284
6285static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6286 u64 seq, unsigned flags)
6287{
6288 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6289 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6290
6291 /* EVENT_WRITE_EOP - flush caches, send int */
6292 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6293 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6294 EOP_TC_ACTION_EN |
6295 EOP_TC_WB_ACTION_EN |
6296 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6297 EVENT_INDEX(5)));
6298 amdgpu_ring_write(ring, addr & 0xfffffffc);
6299 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6300 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6301 amdgpu_ring_write(ring, lower_32_bits(seq));
6302 amdgpu_ring_write(ring, upper_32_bits(seq));
6303
6304}
6305
6306static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6307{
6308 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6309 uint32_t seq = ring->fence_drv.sync_seq;
6310 uint64_t addr = ring->fence_drv.gpu_addr;
6311
6312 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6313 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6314 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6315 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6316 amdgpu_ring_write(ring, addr & 0xfffffffc);
6317 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6318 amdgpu_ring_write(ring, seq);
6319 amdgpu_ring_write(ring, 0xffffffff);
6320 amdgpu_ring_write(ring, 4); /* poll interval */
6321}
6322
6323static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6324 unsigned vmid, uint64_t pd_addr)
6325{
6326 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6327
6328 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6329
6330 /* wait for the invalidate to complete */
6331 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6332 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6333 WAIT_REG_MEM_FUNCTION(0) | /* always */
6334 WAIT_REG_MEM_ENGINE(0))); /* me */
6335 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6336 amdgpu_ring_write(ring, 0);
6337 amdgpu_ring_write(ring, 0); /* ref */
6338 amdgpu_ring_write(ring, 0); /* mask */
6339 amdgpu_ring_write(ring, 0x20); /* poll interval */
6340
6341 /* compute doesn't have PFP */
6342 if (usepfp) {
6343 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6344 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6345 amdgpu_ring_write(ring, 0x0);
6346 }
6347}
6348
6349static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6350{
6351 return ring->adev->wb.wb[ring->wptr_offs];
6352}
6353
6354static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6355{
6356 struct amdgpu_device *adev = ring->adev;
6357
6358 /* XXX check if swapping is necessary on BE */
6359 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6360 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6361}
6362
6363static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
6364 bool acquire)
6365{
6366 struct amdgpu_device *adev = ring->adev;
6367 int pipe_num, tmp, reg;
6368 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
6369
6370 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
6371
6372 /* first me only has 2 entries, GFX and HP3D */
6373 if (ring->me > 0)
6374 pipe_num -= 2;
6375
6376 reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
6377 tmp = RREG32(reg);
6378 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
6379 WREG32(reg, tmp);
6380}
6381
6382static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
6383 struct amdgpu_ring *ring,
6384 bool acquire)
6385{
6386 int i, pipe;
6387 bool reserve;
6388 struct amdgpu_ring *iring;
6389
6390 mutex_lock(&adev->gfx.pipe_reserve_mutex);
6391 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
6392 if (acquire)
6393 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6394 else
6395 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6396
6397 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
6398 /* Clear all reservations - everyone reacquires all resources */
6399 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
6400 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
6401 true);
6402
6403 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
6404 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
6405 true);
6406 } else {
6407 /* Lower all pipes without a current reservation */
6408 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
6409 iring = &adev->gfx.gfx_ring[i];
6410 pipe = amdgpu_gfx_queue_to_bit(adev,
6411 iring->me,
6412 iring->pipe,
6413 0);
6414 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6415 gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6416 }
6417
6418 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
6419 iring = &adev->gfx.compute_ring[i];
6420 pipe = amdgpu_gfx_queue_to_bit(adev,
6421 iring->me,
6422 iring->pipe,
6423 0);
6424 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6425 gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6426 }
6427 }
6428
6429 mutex_unlock(&adev->gfx.pipe_reserve_mutex);
6430}
6431
6432static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
6433 struct amdgpu_ring *ring,
6434 bool acquire)
6435{
6436 uint32_t pipe_priority = acquire ? 0x2 : 0x0;
6437 uint32_t queue_priority = acquire ? 0xf : 0x0;
6438
6439 mutex_lock(&adev->srbm_mutex);
6440 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6441
6442 WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
6443 WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
6444
6445 vi_srbm_select(adev, 0, 0, 0, 0);
6446 mutex_unlock(&adev->srbm_mutex);
6447}
6448static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
6449 enum drm_sched_priority priority)
6450{
6451 struct amdgpu_device *adev = ring->adev;
6452 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
6453
6454 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
6455 return;
6456
6457 gfx_v8_0_hqd_set_priority(adev, ring, acquire);
6458 gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
6459}
6460
6461static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6462 u64 addr, u64 seq,
6463 unsigned flags)
6464{
6465 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6466 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6467
6468 /* RELEASE_MEM - flush caches, send int */
6469 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6470 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6471 EOP_TC_ACTION_EN |
6472 EOP_TC_WB_ACTION_EN |
6473 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6474 EVENT_INDEX(5)));
6475 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6476 amdgpu_ring_write(ring, addr & 0xfffffffc);
6477 amdgpu_ring_write(ring, upper_32_bits(addr));
6478 amdgpu_ring_write(ring, lower_32_bits(seq));
6479 amdgpu_ring_write(ring, upper_32_bits(seq));
6480}
6481
6482static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6483 u64 seq, unsigned int flags)
6484{
6485 /* we only allocate 32bit for each seq wb address */
6486 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6487
6488 /* write fence seq to the "addr" */
6489 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6490 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6491 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6492 amdgpu_ring_write(ring, lower_32_bits(addr));
6493 amdgpu_ring_write(ring, upper_32_bits(addr));
6494 amdgpu_ring_write(ring, lower_32_bits(seq));
6495
6496 if (flags & AMDGPU_FENCE_FLAG_INT) {
6497 /* set register to trigger INT */
6498 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6499 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6500 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6501 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6502 amdgpu_ring_write(ring, 0);
6503 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6504 }
6505}
6506
6507static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6508{
6509 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6510 amdgpu_ring_write(ring, 0);
6511}
6512
6513static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6514{
6515 uint32_t dw2 = 0;
6516
6517 if (amdgpu_sriov_vf(ring->adev))
6518 gfx_v8_0_ring_emit_ce_meta(ring);
6519
6520 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6521 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6522 gfx_v8_0_ring_emit_vgt_flush(ring);
6523 /* set load_global_config & load_global_uconfig */
6524 dw2 |= 0x8001;
6525 /* set load_cs_sh_regs */
6526 dw2 |= 0x01000000;
6527 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6528 dw2 |= 0x10002;
6529
6530 /* set load_ce_ram if preamble presented */
6531 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6532 dw2 |= 0x10000000;
6533 } else {
6534 /* still load_ce_ram if this is the first time preamble presented
6535 * although there is no context switch happens.
6536 */
6537 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6538 dw2 |= 0x10000000;
6539 }
6540
6541 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6542 amdgpu_ring_write(ring, dw2);
6543 amdgpu_ring_write(ring, 0);
6544}
6545
6546static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6547{
6548 unsigned ret;
6549
6550 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6551 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6552 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6553 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6554 ret = ring->wptr & ring->buf_mask;
6555 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6556 return ret;
6557}
6558
6559static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6560{
6561 unsigned cur;
6562
6563 BUG_ON(offset > ring->buf_mask);
6564 BUG_ON(ring->ring[offset] != 0x55aa55aa);
6565
6566 cur = (ring->wptr & ring->buf_mask) - 1;
6567 if (likely(cur > offset))
6568 ring->ring[offset] = cur - offset;
6569 else
6570 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6571}
6572
6573static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
6574{
6575 struct amdgpu_device *adev = ring->adev;
6576
6577 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6578 amdgpu_ring_write(ring, 0 | /* src: register*/
6579 (5 << 8) | /* dst: memory */
6580 (1 << 20)); /* write confirm */
6581 amdgpu_ring_write(ring, reg);
6582 amdgpu_ring_write(ring, 0);
6583 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6584 adev->virt.reg_val_offs * 4));
6585 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6586 adev->virt.reg_val_offs * 4));
6587}
6588
6589static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6590 uint32_t val)
6591{
6592 uint32_t cmd;
6593
6594 switch (ring->funcs->type) {
6595 case AMDGPU_RING_TYPE_GFX:
6596 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6597 break;
6598 case AMDGPU_RING_TYPE_KIQ:
6599 cmd = 1 << 16; /* no inc addr */
6600 break;
6601 default:
6602 cmd = WR_CONFIRM;
6603 break;
6604 }
6605
6606 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6607 amdgpu_ring_write(ring, cmd);
6608 amdgpu_ring_write(ring, reg);
6609 amdgpu_ring_write(ring, 0);
6610 amdgpu_ring_write(ring, val);
6611}
6612
6613static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6614 enum amdgpu_interrupt_state state)
6615{
6616 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6617 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6618}
6619
6620static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6621 int me, int pipe,
6622 enum amdgpu_interrupt_state state)
6623{
6624 u32 mec_int_cntl, mec_int_cntl_reg;
6625
6626 /*
6627 * amdgpu controls only the first MEC. That's why this function only
6628 * handles the setting of interrupts for this specific MEC. All other
6629 * pipes' interrupts are set by amdkfd.
6630 */
6631
6632 if (me == 1) {
6633 switch (pipe) {
6634 case 0:
6635 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6636 break;
6637 case 1:
6638 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6639 break;
6640 case 2:
6641 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6642 break;
6643 case 3:
6644 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6645 break;
6646 default:
6647 DRM_DEBUG("invalid pipe %d\n", pipe);
6648 return;
6649 }
6650 } else {
6651 DRM_DEBUG("invalid me %d\n", me);
6652 return;
6653 }
6654
6655 switch (state) {
6656 case AMDGPU_IRQ_STATE_DISABLE:
6657 mec_int_cntl = RREG32(mec_int_cntl_reg);
6658 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6659 WREG32(mec_int_cntl_reg, mec_int_cntl);
6660 break;
6661 case AMDGPU_IRQ_STATE_ENABLE:
6662 mec_int_cntl = RREG32(mec_int_cntl_reg);
6663 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6664 WREG32(mec_int_cntl_reg, mec_int_cntl);
6665 break;
6666 default:
6667 break;
6668 }
6669}
6670
6671static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6672 struct amdgpu_irq_src *source,
6673 unsigned type,
6674 enum amdgpu_interrupt_state state)
6675{
6676 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6677 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6678
6679 return 0;
6680}
6681
6682static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6683 struct amdgpu_irq_src *source,
6684 unsigned type,
6685 enum amdgpu_interrupt_state state)
6686{
6687 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6688 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6689
6690 return 0;
6691}
6692
6693static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6694 struct amdgpu_irq_src *src,
6695 unsigned type,
6696 enum amdgpu_interrupt_state state)
6697{
6698 switch (type) {
6699 case AMDGPU_CP_IRQ_GFX_EOP:
6700 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6701 break;
6702 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6703 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6704 break;
6705 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6706 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6707 break;
6708 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6709 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6710 break;
6711 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6712 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6713 break;
6714 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6715 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6716 break;
6717 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6718 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6719 break;
6720 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6721 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6722 break;
6723 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6724 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6725 break;
6726 default:
6727 break;
6728 }
6729 return 0;
6730}
6731
6732static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6733 struct amdgpu_irq_src *source,
6734 struct amdgpu_iv_entry *entry)
6735{
6736 int i;
6737 u8 me_id, pipe_id, queue_id;
6738 struct amdgpu_ring *ring;
6739
6740 DRM_DEBUG("IH: CP EOP\n");
6741 me_id = (entry->ring_id & 0x0c) >> 2;
6742 pipe_id = (entry->ring_id & 0x03) >> 0;
6743 queue_id = (entry->ring_id & 0x70) >> 4;
6744
6745 switch (me_id) {
6746 case 0:
6747 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6748 break;
6749 case 1:
6750 case 2:
6751 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6752 ring = &adev->gfx.compute_ring[i];
6753 /* Per-queue interrupt is supported for MEC starting from VI.
6754 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6755 */
6756 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6757 amdgpu_fence_process(ring);
6758 }
6759 break;
6760 }
6761 return 0;
6762}
6763
6764static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6765 struct amdgpu_irq_src *source,
6766 struct amdgpu_iv_entry *entry)
6767{
6768 DRM_ERROR("Illegal register access in command stream\n");
6769 schedule_work(&adev->reset_work);
6770 return 0;
6771}
6772
6773static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6774 struct amdgpu_irq_src *source,
6775 struct amdgpu_iv_entry *entry)
6776{
6777 DRM_ERROR("Illegal instruction in command stream\n");
6778 schedule_work(&adev->reset_work);
6779 return 0;
6780}
6781
6782static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
6783 struct amdgpu_irq_src *src,
6784 unsigned int type,
6785 enum amdgpu_interrupt_state state)
6786{
6787 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
6788
6789 switch (type) {
6790 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
6791 WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE,
6792 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6793 if (ring->me == 1)
6794 WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL,
6795 ring->pipe,
6796 GENERIC2_INT_ENABLE,
6797 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6798 else
6799 WREG32_FIELD_OFFSET(CP_ME2_PIPE0_INT_CNTL,
6800 ring->pipe,
6801 GENERIC2_INT_ENABLE,
6802 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6803 break;
6804 default:
6805 BUG(); /* kiq only support GENERIC2_INT now */
6806 break;
6807 }
6808 return 0;
6809}
6810
6811static int gfx_v8_0_kiq_irq(struct amdgpu_device *adev,
6812 struct amdgpu_irq_src *source,
6813 struct amdgpu_iv_entry *entry)
6814{
6815 u8 me_id, pipe_id, queue_id;
6816 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
6817
6818 me_id = (entry->ring_id & 0x0c) >> 2;
6819 pipe_id = (entry->ring_id & 0x03) >> 0;
6820 queue_id = (entry->ring_id & 0x70) >> 4;
6821 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
6822 me_id, pipe_id, queue_id);
6823
6824 amdgpu_fence_process(ring);
6825 return 0;
6826}
6827
6828static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6829 .name = "gfx_v8_0",
6830 .early_init = gfx_v8_0_early_init,
6831 .late_init = gfx_v8_0_late_init,
6832 .sw_init = gfx_v8_0_sw_init,
6833 .sw_fini = gfx_v8_0_sw_fini,
6834 .hw_init = gfx_v8_0_hw_init,
6835 .hw_fini = gfx_v8_0_hw_fini,
6836 .suspend = gfx_v8_0_suspend,
6837 .resume = gfx_v8_0_resume,
6838 .is_idle = gfx_v8_0_is_idle,
6839 .wait_for_idle = gfx_v8_0_wait_for_idle,
6840 .check_soft_reset = gfx_v8_0_check_soft_reset,
6841 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6842 .soft_reset = gfx_v8_0_soft_reset,
6843 .post_soft_reset = gfx_v8_0_post_soft_reset,
6844 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6845 .set_powergating_state = gfx_v8_0_set_powergating_state,
6846 .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6847};
6848
6849static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6850 .type = AMDGPU_RING_TYPE_GFX,
6851 .align_mask = 0xff,
6852 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6853 .support_64bit_ptrs = false,
6854 .get_rptr = gfx_v8_0_ring_get_rptr,
6855 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6856 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6857 .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6858 5 + /* COND_EXEC */
6859 7 + /* PIPELINE_SYNC */
6860 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6861 8 + /* FENCE for VM_FLUSH */
6862 20 + /* GDS switch */
6863 4 + /* double SWITCH_BUFFER,
6864 the first COND_EXEC jump to the place just
6865 prior to this double SWITCH_BUFFER */
6866 5 + /* COND_EXEC */
6867 7 + /* HDP_flush */
6868 4 + /* VGT_flush */
6869 14 + /* CE_META */
6870 31 + /* DE_META */
6871 3 + /* CNTX_CTRL */
6872 5 + /* HDP_INVL */
6873 8 + 8 + /* FENCE x2 */
6874 2, /* SWITCH_BUFFER */
6875 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6876 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6877 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6878 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6879 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6880 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6881 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6882 .test_ring = gfx_v8_0_ring_test_ring,
6883 .test_ib = gfx_v8_0_ring_test_ib,
6884 .insert_nop = amdgpu_ring_insert_nop,
6885 .pad_ib = amdgpu_ring_generic_pad_ib,
6886 .emit_switch_buffer = gfx_v8_ring_emit_sb,
6887 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6888 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6889 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6890 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6891};
6892
6893static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6894 .type = AMDGPU_RING_TYPE_COMPUTE,
6895 .align_mask = 0xff,
6896 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6897 .support_64bit_ptrs = false,
6898 .get_rptr = gfx_v8_0_ring_get_rptr,
6899 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6900 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6901 .emit_frame_size =
6902 20 + /* gfx_v8_0_ring_emit_gds_switch */
6903 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6904 5 + /* hdp_invalidate */
6905 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6906 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6907 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6908 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
6909 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6910 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6911 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6912 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6913 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6914 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6915 .test_ring = gfx_v8_0_ring_test_ring,
6916 .test_ib = gfx_v8_0_ring_test_ib,
6917 .insert_nop = amdgpu_ring_insert_nop,
6918 .pad_ib = amdgpu_ring_generic_pad_ib,
6919 .set_priority = gfx_v8_0_ring_set_priority_compute,
6920 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6921};
6922
6923static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6924 .type = AMDGPU_RING_TYPE_KIQ,
6925 .align_mask = 0xff,
6926 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6927 .support_64bit_ptrs = false,
6928 .get_rptr = gfx_v8_0_ring_get_rptr,
6929 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6930 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6931 .emit_frame_size =
6932 20 + /* gfx_v8_0_ring_emit_gds_switch */
6933 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6934 5 + /* hdp_invalidate */
6935 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6936 17 + /* gfx_v8_0_ring_emit_vm_flush */
6937 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6938 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
6939 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6940 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
6941 .test_ring = gfx_v8_0_ring_test_ring,
6942 .test_ib = gfx_v8_0_ring_test_ib,
6943 .insert_nop = amdgpu_ring_insert_nop,
6944 .pad_ib = amdgpu_ring_generic_pad_ib,
6945 .emit_rreg = gfx_v8_0_ring_emit_rreg,
6946 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6947};
6948
6949static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6950{
6951 int i;
6952
6953 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
6954
6955 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6956 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6957
6958 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6959 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6960}
6961
6962static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6963 .set = gfx_v8_0_set_eop_interrupt_state,
6964 .process = gfx_v8_0_eop_irq,
6965};
6966
6967static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6968 .set = gfx_v8_0_set_priv_reg_fault_state,
6969 .process = gfx_v8_0_priv_reg_irq,
6970};
6971
6972static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6973 .set = gfx_v8_0_set_priv_inst_fault_state,
6974 .process = gfx_v8_0_priv_inst_irq,
6975};
6976
6977static const struct amdgpu_irq_src_funcs gfx_v8_0_kiq_irq_funcs = {
6978 .set = gfx_v8_0_kiq_set_interrupt_state,
6979 .process = gfx_v8_0_kiq_irq,
6980};
6981
6982static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6983{
6984 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6985 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6986
6987 adev->gfx.priv_reg_irq.num_types = 1;
6988 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6989
6990 adev->gfx.priv_inst_irq.num_types = 1;
6991 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
6992
6993 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
6994 adev->gfx.kiq.irq.funcs = &gfx_v8_0_kiq_irq_funcs;
6995}
6996
6997static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
6998{
6999 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7000}
7001
7002static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7003{
7004 /* init asci gds info */
7005 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
7006 adev->gds.gws.total_size = 64;
7007 adev->gds.oa.total_size = 16;
7008
7009 if (adev->gds.mem.total_size == 64 * 1024) {
7010 adev->gds.mem.gfx_partition_size = 4096;
7011 adev->gds.mem.cs_partition_size = 4096;
7012
7013 adev->gds.gws.gfx_partition_size = 4;
7014 adev->gds.gws.cs_partition_size = 4;
7015
7016 adev->gds.oa.gfx_partition_size = 4;
7017 adev->gds.oa.cs_partition_size = 1;
7018 } else {
7019 adev->gds.mem.gfx_partition_size = 1024;
7020 adev->gds.mem.cs_partition_size = 1024;
7021
7022 adev->gds.gws.gfx_partition_size = 16;
7023 adev->gds.gws.cs_partition_size = 16;
7024
7025 adev->gds.oa.gfx_partition_size = 4;
7026 adev->gds.oa.cs_partition_size = 4;
7027 }
7028}
7029
7030static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7031 u32 bitmap)
7032{
7033 u32 data;
7034
7035 if (!bitmap)
7036 return;
7037
7038 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7039 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7040
7041 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7042}
7043
7044static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7045{
7046 u32 data, mask;
7047
7048 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7049 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7050
7051 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7052
7053 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7054}
7055
7056static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7057{
7058 int i, j, k, counter, active_cu_number = 0;
7059 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7060 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7061 unsigned disable_masks[4 * 2];
7062 u32 ao_cu_num;
7063
7064 memset(cu_info, 0, sizeof(*cu_info));
7065
7066 if (adev->flags & AMD_IS_APU)
7067 ao_cu_num = 2;
7068 else
7069 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7070
7071 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7072
7073 mutex_lock(&adev->grbm_idx_mutex);
7074 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7075 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7076 mask = 1;
7077 ao_bitmap = 0;
7078 counter = 0;
7079 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7080 if (i < 4 && j < 2)
7081 gfx_v8_0_set_user_cu_inactive_bitmap(
7082 adev, disable_masks[i * 2 + j]);
7083 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7084 cu_info->bitmap[i][j] = bitmap;
7085
7086 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7087 if (bitmap & mask) {
7088 if (counter < ao_cu_num)
7089 ao_bitmap |= mask;
7090 counter ++;
7091 }
7092 mask <<= 1;
7093 }
7094 active_cu_number += counter;
7095 if (i < 2 && j < 2)
7096 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7097 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7098 }
7099 }
7100 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7101 mutex_unlock(&adev->grbm_idx_mutex);
7102
7103 cu_info->number = active_cu_number;
7104 cu_info->ao_cu_mask = ao_cu_mask;
7105 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7106 cu_info->max_waves_per_simd = 10;
7107 cu_info->max_scratch_slots_per_cu = 32;
7108 cu_info->wave_front_size = 64;
7109 cu_info->lds_size = 64;
7110}
7111
7112const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7113{
7114 .type = AMD_IP_BLOCK_TYPE_GFX,
7115 .major = 8,
7116 .minor = 0,
7117 .rev = 0,
7118 .funcs = &gfx_v8_0_ip_funcs,
7119};
7120
7121const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7122{
7123 .type = AMD_IP_BLOCK_TYPE_GFX,
7124 .major = 8,
7125 .minor = 1,
7126 .rev = 0,
7127 .funcs = &gfx_v8_0_ip_funcs,
7128};
7129
7130static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7131{
7132 uint64_t ce_payload_addr;
7133 int cnt_ce;
7134 union {
7135 struct vi_ce_ib_state regular;
7136 struct vi_ce_ib_state_chained_ib chained;
7137 } ce_payload = {};
7138
7139 if (ring->adev->virt.chained_ib_support) {
7140 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7141 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7142 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7143 } else {
7144 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7145 offsetof(struct vi_gfx_meta_data, ce_payload);
7146 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7147 }
7148
7149 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7150 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7151 WRITE_DATA_DST_SEL(8) |
7152 WR_CONFIRM) |
7153 WRITE_DATA_CACHE_POLICY(0));
7154 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7155 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7156 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7157}
7158
7159static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7160{
7161 uint64_t de_payload_addr, gds_addr, csa_addr;
7162 int cnt_de;
7163 union {
7164 struct vi_de_ib_state regular;
7165 struct vi_de_ib_state_chained_ib chained;
7166 } de_payload = {};
7167
7168 csa_addr = amdgpu_csa_vaddr(ring->adev);
7169 gds_addr = csa_addr + 4096;
7170 if (ring->adev->virt.chained_ib_support) {
7171 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7172 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7173 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7174 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7175 } else {
7176 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7177 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7178 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7179 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7180 }
7181
7182 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7183 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7184 WRITE_DATA_DST_SEL(8) |
7185 WR_CONFIRM) |
7186 WRITE_DATA_CACHE_POLICY(0));
7187 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7188 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7189 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7190}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_vi.h"
31
32#include "gmc/gmc_8_2_d.h"
33#include "gmc/gmc_8_2_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44#include "gca/gfx_8_0_enum.h"
45
46#include "dce/dce_10_0_d.h"
47#include "dce/dce_10_0_sh_mask.h"
48
49#define GFX8_NUM_GFX_RINGS 1
50#define GFX8_NUM_COMPUTE_RINGS 8
51
52#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
53#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
54#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
55
56#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
57#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
58#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
59#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
60#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
61#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
62#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
63#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
64#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
65
66#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
67#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
68#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
69#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
70#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
71#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
72
73/* BPM SERDES CMD */
74#define SET_BPM_SERDES_CMD 1
75#define CLE_BPM_SERDES_CMD 0
76
77/* BPM Register Address*/
78enum {
79 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
80 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
81 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
82 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
83 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
84 BPM_REG_FGCG_MAX
85};
86
87MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
88MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
89MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
90MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
91MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
92MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
93
94MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
95MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
96MODULE_FIRMWARE("amdgpu/stoney_me.bin");
97MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
98MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
99
100MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
101MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
102MODULE_FIRMWARE("amdgpu/tonga_me.bin");
103MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
104MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
105MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
106
107MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
108MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
109MODULE_FIRMWARE("amdgpu/topaz_me.bin");
110MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
111MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
112
113MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
114MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
115MODULE_FIRMWARE("amdgpu/fiji_me.bin");
116MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
117MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
118MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
119
120static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
121{
122 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
123 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
124 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
125 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
126 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
127 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
128 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
129 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
130 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
131 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
132 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
133 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
134 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
135 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
136 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
137 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
138};
139
140static const u32 golden_settings_tonga_a11[] =
141{
142 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
143 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
144 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
145 mmGB_GPU_ID, 0x0000000f, 0x00000000,
146 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
147 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
148 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
149 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
150 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
151 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
152 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
153 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
154 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
155 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
156 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
157};
158
159static const u32 tonga_golden_common_all[] =
160{
161 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
162 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
163 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
164 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
165 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
166 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
167 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
168 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
169};
170
171static const u32 tonga_mgcg_cgcg_init[] =
172{
173 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
174 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
175 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
176 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
177 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
178 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
179 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
180 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
181 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
182 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
183 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
184 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
185 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
186 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
187 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
188 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
189 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
190 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
191 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
192 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
193 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
194 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
195 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
196 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
197 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
198 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
199 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
200 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
201 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
202 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
203 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
204 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
205 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
206 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
207 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
208 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
209 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
210 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
211 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
212 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
213 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
214 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
215 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
216 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
217 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
218 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
219 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
220 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
221 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
222 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
223 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
224 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
225 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
226 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
227 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
228 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
229 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
230 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
231 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
232 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
233 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
234 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
235 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
236 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
237 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
238 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
239 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
240 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
241 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
242 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
243 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
244 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
245 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
246 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
247 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
248};
249
250static const u32 fiji_golden_common_all[] =
251{
252 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
253 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
254 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
255 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
256 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
257 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
258 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
259 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
260 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
261 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
262};
263
264static const u32 golden_settings_fiji_a10[] =
265{
266 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
267 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
268 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
269 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
270 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
271 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
272 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
273 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
274 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
275 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
276 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
277};
278
279static const u32 fiji_mgcg_cgcg_init[] =
280{
281 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
282 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
283 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
284 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
285 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
286 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
287 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
288 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
289 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
290 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
291 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
292 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
293 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
294 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
295 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
296 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
297 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
298 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
299 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
300 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
301 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
302 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
303 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
304 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
305 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
306 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
307 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
308 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
309 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
310 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
311 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
312 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
313 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
314 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
315 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
316};
317
318static const u32 golden_settings_iceland_a11[] =
319{
320 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
321 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
322 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
324 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
326 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
327 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
328 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
329 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
330 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
331 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
332 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
333 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
334 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
335};
336
337static const u32 iceland_golden_common_all[] =
338{
339 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
340 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
341 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
342 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
343 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
344 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
345 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
346 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
347};
348
349static const u32 iceland_mgcg_cgcg_init[] =
350{
351 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
352 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
353 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
354 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
355 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
356 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
357 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
358 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
359 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
360 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
362 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
365 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
366 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
367 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
368 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
369 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
370 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
371 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
372 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
373 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
374 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
375 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
376 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
377 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
378 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
379 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
380 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
381 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
382 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
383 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
384 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
385 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
386 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
387 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
388 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
389 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
390 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
391 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
392 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
393 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
394 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
395 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
396 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
397 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
398 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
399 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
400 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
401 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
402 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
403 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
404 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
405 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
406 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
407 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
408 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
409 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
410 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
411 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
412 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
413 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
414 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
415};
416
417static const u32 cz_golden_settings_a11[] =
418{
419 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmGB_GPU_ID, 0x0000000f, 0x00000000,
422 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
423 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
426 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
427 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
428 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
429};
430
431static const u32 cz_golden_common_all[] =
432{
433 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
434 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
435 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
436 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
437 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
438 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
439 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
440 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
441};
442
443static const u32 cz_mgcg_cgcg_init[] =
444{
445 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
446 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
447 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
452 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
453 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
454 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
455 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
456 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
459 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
460 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
461 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
462 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
463 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
464 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
465 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
466 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
467 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
468 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
469 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
470 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
471 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
472 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
473 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
474 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
475 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
476 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
477 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
478 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
479 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
480 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
481 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
482 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
483 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
484 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
485 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
486 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
487 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
488 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
489 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
490 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
491 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
492 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
493 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
494 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
495 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
496 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
497 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
498 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
499 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
500 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
501 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
502 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
503 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
504 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
505 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
506 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
507 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
508 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
509 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
510 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
511 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
512 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
513 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
514 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
515 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
516 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
517 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
518 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
519 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
520};
521
522static const u32 stoney_golden_settings_a11[] =
523{
524 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
525 mmGB_GPU_ID, 0x0000000f, 0x00000000,
526 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
527 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
528 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
529 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
530 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
531 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
532 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
533 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
534};
535
536static const u32 stoney_golden_common_all[] =
537{
538 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
539 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
540 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
541 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
542 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
543 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
544 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
545 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
546};
547
548static const u32 stoney_mgcg_cgcg_init[] =
549{
550 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
551 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
552 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
553 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
554 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
555 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
556};
557
558static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
559static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
560static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
561
562static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
563{
564 switch (adev->asic_type) {
565 case CHIP_TOPAZ:
566 amdgpu_program_register_sequence(adev,
567 iceland_mgcg_cgcg_init,
568 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
569 amdgpu_program_register_sequence(adev,
570 golden_settings_iceland_a11,
571 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
572 amdgpu_program_register_sequence(adev,
573 iceland_golden_common_all,
574 (const u32)ARRAY_SIZE(iceland_golden_common_all));
575 break;
576 case CHIP_FIJI:
577 amdgpu_program_register_sequence(adev,
578 fiji_mgcg_cgcg_init,
579 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
580 amdgpu_program_register_sequence(adev,
581 golden_settings_fiji_a10,
582 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
583 amdgpu_program_register_sequence(adev,
584 fiji_golden_common_all,
585 (const u32)ARRAY_SIZE(fiji_golden_common_all));
586 break;
587
588 case CHIP_TONGA:
589 amdgpu_program_register_sequence(adev,
590 tonga_mgcg_cgcg_init,
591 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
592 amdgpu_program_register_sequence(adev,
593 golden_settings_tonga_a11,
594 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
595 amdgpu_program_register_sequence(adev,
596 tonga_golden_common_all,
597 (const u32)ARRAY_SIZE(tonga_golden_common_all));
598 break;
599 case CHIP_CARRIZO:
600 amdgpu_program_register_sequence(adev,
601 cz_mgcg_cgcg_init,
602 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
603 amdgpu_program_register_sequence(adev,
604 cz_golden_settings_a11,
605 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
606 amdgpu_program_register_sequence(adev,
607 cz_golden_common_all,
608 (const u32)ARRAY_SIZE(cz_golden_common_all));
609 break;
610 case CHIP_STONEY:
611 amdgpu_program_register_sequence(adev,
612 stoney_mgcg_cgcg_init,
613 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
614 amdgpu_program_register_sequence(adev,
615 stoney_golden_settings_a11,
616 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
617 amdgpu_program_register_sequence(adev,
618 stoney_golden_common_all,
619 (const u32)ARRAY_SIZE(stoney_golden_common_all));
620 break;
621 default:
622 break;
623 }
624}
625
626static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
627{
628 int i;
629
630 adev->gfx.scratch.num_reg = 7;
631 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
632 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
633 adev->gfx.scratch.free[i] = true;
634 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
635 }
636}
637
638static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
639{
640 struct amdgpu_device *adev = ring->adev;
641 uint32_t scratch;
642 uint32_t tmp = 0;
643 unsigned i;
644 int r;
645
646 r = amdgpu_gfx_scratch_get(adev, &scratch);
647 if (r) {
648 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
649 return r;
650 }
651 WREG32(scratch, 0xCAFEDEAD);
652 r = amdgpu_ring_alloc(ring, 3);
653 if (r) {
654 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
655 ring->idx, r);
656 amdgpu_gfx_scratch_free(adev, scratch);
657 return r;
658 }
659 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
660 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
661 amdgpu_ring_write(ring, 0xDEADBEEF);
662 amdgpu_ring_commit(ring);
663
664 for (i = 0; i < adev->usec_timeout; i++) {
665 tmp = RREG32(scratch);
666 if (tmp == 0xDEADBEEF)
667 break;
668 DRM_UDELAY(1);
669 }
670 if (i < adev->usec_timeout) {
671 DRM_INFO("ring test on %d succeeded in %d usecs\n",
672 ring->idx, i);
673 } else {
674 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
675 ring->idx, scratch, tmp);
676 r = -EINVAL;
677 }
678 amdgpu_gfx_scratch_free(adev, scratch);
679 return r;
680}
681
682static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
683{
684 struct amdgpu_device *adev = ring->adev;
685 struct amdgpu_ib ib;
686 struct fence *f = NULL;
687 uint32_t scratch;
688 uint32_t tmp = 0;
689 unsigned i;
690 int r;
691
692 r = amdgpu_gfx_scratch_get(adev, &scratch);
693 if (r) {
694 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
695 return r;
696 }
697 WREG32(scratch, 0xCAFEDEAD);
698 memset(&ib, 0, sizeof(ib));
699 r = amdgpu_ib_get(adev, NULL, 256, &ib);
700 if (r) {
701 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
702 goto err1;
703 }
704 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
705 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
706 ib.ptr[2] = 0xDEADBEEF;
707 ib.length_dw = 3;
708
709 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
710 if (r)
711 goto err2;
712
713 r = fence_wait(f, false);
714 if (r) {
715 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
716 goto err2;
717 }
718 for (i = 0; i < adev->usec_timeout; i++) {
719 tmp = RREG32(scratch);
720 if (tmp == 0xDEADBEEF)
721 break;
722 DRM_UDELAY(1);
723 }
724 if (i < adev->usec_timeout) {
725 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
726 ring->idx, i);
727 goto err2;
728 } else {
729 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
730 scratch, tmp);
731 r = -EINVAL;
732 }
733err2:
734 fence_put(f);
735 amdgpu_ib_free(adev, &ib, NULL);
736 fence_put(f);
737err1:
738 amdgpu_gfx_scratch_free(adev, scratch);
739 return r;
740}
741
742static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
743{
744 const char *chip_name;
745 char fw_name[30];
746 int err;
747 struct amdgpu_firmware_info *info = NULL;
748 const struct common_firmware_header *header = NULL;
749 const struct gfx_firmware_header_v1_0 *cp_hdr;
750
751 DRM_DEBUG("\n");
752
753 switch (adev->asic_type) {
754 case CHIP_TOPAZ:
755 chip_name = "topaz";
756 break;
757 case CHIP_TONGA:
758 chip_name = "tonga";
759 break;
760 case CHIP_CARRIZO:
761 chip_name = "carrizo";
762 break;
763 case CHIP_FIJI:
764 chip_name = "fiji";
765 break;
766 case CHIP_STONEY:
767 chip_name = "stoney";
768 break;
769 default:
770 BUG();
771 }
772
773 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
774 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
775 if (err)
776 goto out;
777 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
778 if (err)
779 goto out;
780 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
781 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
782 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
783
784 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
785 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
786 if (err)
787 goto out;
788 err = amdgpu_ucode_validate(adev->gfx.me_fw);
789 if (err)
790 goto out;
791 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
792 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
793 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
794
795 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
796 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
797 if (err)
798 goto out;
799 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
800 if (err)
801 goto out;
802 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
803 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
804 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
805
806 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
807 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
808 if (err)
809 goto out;
810 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
811 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
812 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
813 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
814
815 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
816 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
817 if (err)
818 goto out;
819 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
820 if (err)
821 goto out;
822 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
823 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
824 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
825
826 if ((adev->asic_type != CHIP_STONEY) &&
827 (adev->asic_type != CHIP_TOPAZ)) {
828 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
829 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
830 if (!err) {
831 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
832 if (err)
833 goto out;
834 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
835 adev->gfx.mec2_fw->data;
836 adev->gfx.mec2_fw_version =
837 le32_to_cpu(cp_hdr->header.ucode_version);
838 adev->gfx.mec2_feature_version =
839 le32_to_cpu(cp_hdr->ucode_feature_version);
840 } else {
841 err = 0;
842 adev->gfx.mec2_fw = NULL;
843 }
844 }
845
846 if (adev->firmware.smu_load) {
847 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
848 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
849 info->fw = adev->gfx.pfp_fw;
850 header = (const struct common_firmware_header *)info->fw->data;
851 adev->firmware.fw_size +=
852 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
853
854 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
855 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
856 info->fw = adev->gfx.me_fw;
857 header = (const struct common_firmware_header *)info->fw->data;
858 adev->firmware.fw_size +=
859 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
860
861 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
862 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
863 info->fw = adev->gfx.ce_fw;
864 header = (const struct common_firmware_header *)info->fw->data;
865 adev->firmware.fw_size +=
866 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
867
868 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
869 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
870 info->fw = adev->gfx.rlc_fw;
871 header = (const struct common_firmware_header *)info->fw->data;
872 adev->firmware.fw_size +=
873 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
874
875 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
876 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
877 info->fw = adev->gfx.mec_fw;
878 header = (const struct common_firmware_header *)info->fw->data;
879 adev->firmware.fw_size +=
880 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
881
882 if (adev->gfx.mec2_fw) {
883 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
884 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
885 info->fw = adev->gfx.mec2_fw;
886 header = (const struct common_firmware_header *)info->fw->data;
887 adev->firmware.fw_size +=
888 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
889 }
890
891 }
892
893out:
894 if (err) {
895 dev_err(adev->dev,
896 "gfx8: Failed to load firmware \"%s\"\n",
897 fw_name);
898 release_firmware(adev->gfx.pfp_fw);
899 adev->gfx.pfp_fw = NULL;
900 release_firmware(adev->gfx.me_fw);
901 adev->gfx.me_fw = NULL;
902 release_firmware(adev->gfx.ce_fw);
903 adev->gfx.ce_fw = NULL;
904 release_firmware(adev->gfx.rlc_fw);
905 adev->gfx.rlc_fw = NULL;
906 release_firmware(adev->gfx.mec_fw);
907 adev->gfx.mec_fw = NULL;
908 release_firmware(adev->gfx.mec2_fw);
909 adev->gfx.mec2_fw = NULL;
910 }
911 return err;
912}
913
914static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
915{
916 int r;
917
918 if (adev->gfx.mec.hpd_eop_obj) {
919 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
920 if (unlikely(r != 0))
921 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
922 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
923 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
924
925 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
926 adev->gfx.mec.hpd_eop_obj = NULL;
927 }
928}
929
930#define MEC_HPD_SIZE 2048
931
932static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
933{
934 int r;
935 u32 *hpd;
936
937 /*
938 * we assign only 1 pipe because all other pipes will
939 * be handled by KFD
940 */
941 adev->gfx.mec.num_mec = 1;
942 adev->gfx.mec.num_pipe = 1;
943 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
944
945 if (adev->gfx.mec.hpd_eop_obj == NULL) {
946 r = amdgpu_bo_create(adev,
947 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
948 PAGE_SIZE, true,
949 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
950 &adev->gfx.mec.hpd_eop_obj);
951 if (r) {
952 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
953 return r;
954 }
955 }
956
957 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
958 if (unlikely(r != 0)) {
959 gfx_v8_0_mec_fini(adev);
960 return r;
961 }
962 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
963 &adev->gfx.mec.hpd_eop_gpu_addr);
964 if (r) {
965 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
966 gfx_v8_0_mec_fini(adev);
967 return r;
968 }
969 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
970 if (r) {
971 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
972 gfx_v8_0_mec_fini(adev);
973 return r;
974 }
975
976 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
977
978 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
979 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
980
981 return 0;
982}
983
984static const u32 vgpr_init_compute_shader[] =
985{
986 0x7e000209, 0x7e020208,
987 0x7e040207, 0x7e060206,
988 0x7e080205, 0x7e0a0204,
989 0x7e0c0203, 0x7e0e0202,
990 0x7e100201, 0x7e120200,
991 0x7e140209, 0x7e160208,
992 0x7e180207, 0x7e1a0206,
993 0x7e1c0205, 0x7e1e0204,
994 0x7e200203, 0x7e220202,
995 0x7e240201, 0x7e260200,
996 0x7e280209, 0x7e2a0208,
997 0x7e2c0207, 0x7e2e0206,
998 0x7e300205, 0x7e320204,
999 0x7e340203, 0x7e360202,
1000 0x7e380201, 0x7e3a0200,
1001 0x7e3c0209, 0x7e3e0208,
1002 0x7e400207, 0x7e420206,
1003 0x7e440205, 0x7e460204,
1004 0x7e480203, 0x7e4a0202,
1005 0x7e4c0201, 0x7e4e0200,
1006 0x7e500209, 0x7e520208,
1007 0x7e540207, 0x7e560206,
1008 0x7e580205, 0x7e5a0204,
1009 0x7e5c0203, 0x7e5e0202,
1010 0x7e600201, 0x7e620200,
1011 0x7e640209, 0x7e660208,
1012 0x7e680207, 0x7e6a0206,
1013 0x7e6c0205, 0x7e6e0204,
1014 0x7e700203, 0x7e720202,
1015 0x7e740201, 0x7e760200,
1016 0x7e780209, 0x7e7a0208,
1017 0x7e7c0207, 0x7e7e0206,
1018 0xbf8a0000, 0xbf810000,
1019};
1020
1021static const u32 sgpr_init_compute_shader[] =
1022{
1023 0xbe8a0100, 0xbe8c0102,
1024 0xbe8e0104, 0xbe900106,
1025 0xbe920108, 0xbe940100,
1026 0xbe960102, 0xbe980104,
1027 0xbe9a0106, 0xbe9c0108,
1028 0xbe9e0100, 0xbea00102,
1029 0xbea20104, 0xbea40106,
1030 0xbea60108, 0xbea80100,
1031 0xbeaa0102, 0xbeac0104,
1032 0xbeae0106, 0xbeb00108,
1033 0xbeb20100, 0xbeb40102,
1034 0xbeb60104, 0xbeb80106,
1035 0xbeba0108, 0xbebc0100,
1036 0xbebe0102, 0xbec00104,
1037 0xbec20106, 0xbec40108,
1038 0xbec60100, 0xbec80102,
1039 0xbee60004, 0xbee70005,
1040 0xbeea0006, 0xbeeb0007,
1041 0xbee80008, 0xbee90009,
1042 0xbefc0000, 0xbf8a0000,
1043 0xbf810000, 0x00000000,
1044};
1045
1046static const u32 vgpr_init_regs[] =
1047{
1048 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1049 mmCOMPUTE_RESOURCE_LIMITS, 0,
1050 mmCOMPUTE_NUM_THREAD_X, 256*4,
1051 mmCOMPUTE_NUM_THREAD_Y, 1,
1052 mmCOMPUTE_NUM_THREAD_Z, 1,
1053 mmCOMPUTE_PGM_RSRC2, 20,
1054 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1055 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1056 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1057 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1058 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1059 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1060 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1061 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1062 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1063 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1064};
1065
1066static const u32 sgpr1_init_regs[] =
1067{
1068 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1069 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1070 mmCOMPUTE_NUM_THREAD_X, 256*5,
1071 mmCOMPUTE_NUM_THREAD_Y, 1,
1072 mmCOMPUTE_NUM_THREAD_Z, 1,
1073 mmCOMPUTE_PGM_RSRC2, 20,
1074 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1075 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1076 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1077 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1078 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1079 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1080 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1081 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1082 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1083 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1084};
1085
1086static const u32 sgpr2_init_regs[] =
1087{
1088 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1089 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1090 mmCOMPUTE_NUM_THREAD_X, 256*5,
1091 mmCOMPUTE_NUM_THREAD_Y, 1,
1092 mmCOMPUTE_NUM_THREAD_Z, 1,
1093 mmCOMPUTE_PGM_RSRC2, 20,
1094 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1095 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1096 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1097 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1098 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1099 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1100 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1101 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1102 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1103 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1104};
1105
1106static const u32 sec_ded_counter_registers[] =
1107{
1108 mmCPC_EDC_ATC_CNT,
1109 mmCPC_EDC_SCRATCH_CNT,
1110 mmCPC_EDC_UCODE_CNT,
1111 mmCPF_EDC_ATC_CNT,
1112 mmCPF_EDC_ROQ_CNT,
1113 mmCPF_EDC_TAG_CNT,
1114 mmCPG_EDC_ATC_CNT,
1115 mmCPG_EDC_DMA_CNT,
1116 mmCPG_EDC_TAG_CNT,
1117 mmDC_EDC_CSINVOC_CNT,
1118 mmDC_EDC_RESTORE_CNT,
1119 mmDC_EDC_STATE_CNT,
1120 mmGDS_EDC_CNT,
1121 mmGDS_EDC_GRBM_CNT,
1122 mmGDS_EDC_OA_DED,
1123 mmSPI_EDC_CNT,
1124 mmSQC_ATC_EDC_GATCL1_CNT,
1125 mmSQC_EDC_CNT,
1126 mmSQ_EDC_DED_CNT,
1127 mmSQ_EDC_INFO,
1128 mmSQ_EDC_SEC_CNT,
1129 mmTCC_EDC_CNT,
1130 mmTCP_ATC_EDC_GATCL1_CNT,
1131 mmTCP_EDC_CNT,
1132 mmTD_EDC_CNT
1133};
1134
1135static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1136{
1137 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1138 struct amdgpu_ib ib;
1139 struct fence *f = NULL;
1140 int r, i;
1141 u32 tmp;
1142 unsigned total_size, vgpr_offset, sgpr_offset;
1143 u64 gpu_addr;
1144
1145 /* only supported on CZ */
1146 if (adev->asic_type != CHIP_CARRIZO)
1147 return 0;
1148
1149 /* bail if the compute ring is not ready */
1150 if (!ring->ready)
1151 return 0;
1152
1153 tmp = RREG32(mmGB_EDC_MODE);
1154 WREG32(mmGB_EDC_MODE, 0);
1155
1156 total_size =
1157 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1158 total_size +=
1159 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1160 total_size +=
1161 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1162 total_size = ALIGN(total_size, 256);
1163 vgpr_offset = total_size;
1164 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1165 sgpr_offset = total_size;
1166 total_size += sizeof(sgpr_init_compute_shader);
1167
1168 /* allocate an indirect buffer to put the commands in */
1169 memset(&ib, 0, sizeof(ib));
1170 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1171 if (r) {
1172 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1173 return r;
1174 }
1175
1176 /* load the compute shaders */
1177 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1178 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1179
1180 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1181 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1182
1183 /* init the ib length to 0 */
1184 ib.length_dw = 0;
1185
1186 /* VGPR */
1187 /* write the register state for the compute dispatch */
1188 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1189 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1190 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1191 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1192 }
1193 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1194 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1195 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1196 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1197 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1198 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1199
1200 /* write dispatch packet */
1201 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1202 ib.ptr[ib.length_dw++] = 8; /* x */
1203 ib.ptr[ib.length_dw++] = 1; /* y */
1204 ib.ptr[ib.length_dw++] = 1; /* z */
1205 ib.ptr[ib.length_dw++] =
1206 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1207
1208 /* write CS partial flush packet */
1209 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1210 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1211
1212 /* SGPR1 */
1213 /* write the register state for the compute dispatch */
1214 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1215 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1216 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1217 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1218 }
1219 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1220 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1221 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1222 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1223 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1224 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1225
1226 /* write dispatch packet */
1227 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1228 ib.ptr[ib.length_dw++] = 8; /* x */
1229 ib.ptr[ib.length_dw++] = 1; /* y */
1230 ib.ptr[ib.length_dw++] = 1; /* z */
1231 ib.ptr[ib.length_dw++] =
1232 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1233
1234 /* write CS partial flush packet */
1235 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1236 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1237
1238 /* SGPR2 */
1239 /* write the register state for the compute dispatch */
1240 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1241 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1242 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1243 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1244 }
1245 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1246 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1247 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1248 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1249 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1250 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1251
1252 /* write dispatch packet */
1253 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1254 ib.ptr[ib.length_dw++] = 8; /* x */
1255 ib.ptr[ib.length_dw++] = 1; /* y */
1256 ib.ptr[ib.length_dw++] = 1; /* z */
1257 ib.ptr[ib.length_dw++] =
1258 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1259
1260 /* write CS partial flush packet */
1261 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1262 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1263
1264 /* shedule the ib on the ring */
1265 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1266 if (r) {
1267 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1268 goto fail;
1269 }
1270
1271 /* wait for the GPU to finish processing the IB */
1272 r = fence_wait(f, false);
1273 if (r) {
1274 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1275 goto fail;
1276 }
1277
1278 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1279 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1280 WREG32(mmGB_EDC_MODE, tmp);
1281
1282 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1283 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1284 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1285
1286
1287 /* read back registers to clear the counters */
1288 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1289 RREG32(sec_ded_counter_registers[i]);
1290
1291fail:
1292 fence_put(f);
1293 amdgpu_ib_free(adev, &ib, NULL);
1294 fence_put(f);
1295
1296 return r;
1297}
1298
1299static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1300{
1301 u32 gb_addr_config;
1302 u32 mc_shared_chmap, mc_arb_ramcfg;
1303 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1304 u32 tmp;
1305
1306 switch (adev->asic_type) {
1307 case CHIP_TOPAZ:
1308 adev->gfx.config.max_shader_engines = 1;
1309 adev->gfx.config.max_tile_pipes = 2;
1310 adev->gfx.config.max_cu_per_sh = 6;
1311 adev->gfx.config.max_sh_per_se = 1;
1312 adev->gfx.config.max_backends_per_se = 2;
1313 adev->gfx.config.max_texture_channel_caches = 2;
1314 adev->gfx.config.max_gprs = 256;
1315 adev->gfx.config.max_gs_threads = 32;
1316 adev->gfx.config.max_hw_contexts = 8;
1317
1318 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1319 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1320 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1321 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1322 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1323 break;
1324 case CHIP_FIJI:
1325 adev->gfx.config.max_shader_engines = 4;
1326 adev->gfx.config.max_tile_pipes = 16;
1327 adev->gfx.config.max_cu_per_sh = 16;
1328 adev->gfx.config.max_sh_per_se = 1;
1329 adev->gfx.config.max_backends_per_se = 4;
1330 adev->gfx.config.max_texture_channel_caches = 16;
1331 adev->gfx.config.max_gprs = 256;
1332 adev->gfx.config.max_gs_threads = 32;
1333 adev->gfx.config.max_hw_contexts = 8;
1334
1335 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1336 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1337 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1338 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1339 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1340 break;
1341 case CHIP_TONGA:
1342 adev->gfx.config.max_shader_engines = 4;
1343 adev->gfx.config.max_tile_pipes = 8;
1344 adev->gfx.config.max_cu_per_sh = 8;
1345 adev->gfx.config.max_sh_per_se = 1;
1346 adev->gfx.config.max_backends_per_se = 2;
1347 adev->gfx.config.max_texture_channel_caches = 8;
1348 adev->gfx.config.max_gprs = 256;
1349 adev->gfx.config.max_gs_threads = 32;
1350 adev->gfx.config.max_hw_contexts = 8;
1351
1352 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1353 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1354 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1355 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1356 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1357 break;
1358 case CHIP_CARRIZO:
1359 adev->gfx.config.max_shader_engines = 1;
1360 adev->gfx.config.max_tile_pipes = 2;
1361 adev->gfx.config.max_sh_per_se = 1;
1362 adev->gfx.config.max_backends_per_se = 2;
1363
1364 switch (adev->pdev->revision) {
1365 case 0xc4:
1366 case 0x84:
1367 case 0xc8:
1368 case 0xcc:
1369 case 0xe1:
1370 case 0xe3:
1371 /* B10 */
1372 adev->gfx.config.max_cu_per_sh = 8;
1373 break;
1374 case 0xc5:
1375 case 0x81:
1376 case 0x85:
1377 case 0xc9:
1378 case 0xcd:
1379 case 0xe2:
1380 case 0xe4:
1381 /* B8 */
1382 adev->gfx.config.max_cu_per_sh = 6;
1383 break;
1384 case 0xc6:
1385 case 0xca:
1386 case 0xce:
1387 case 0x88:
1388 /* B6 */
1389 adev->gfx.config.max_cu_per_sh = 6;
1390 break;
1391 case 0xc7:
1392 case 0x87:
1393 case 0xcb:
1394 case 0xe5:
1395 case 0x89:
1396 default:
1397 /* B4 */
1398 adev->gfx.config.max_cu_per_sh = 4;
1399 break;
1400 }
1401
1402 adev->gfx.config.max_texture_channel_caches = 2;
1403 adev->gfx.config.max_gprs = 256;
1404 adev->gfx.config.max_gs_threads = 32;
1405 adev->gfx.config.max_hw_contexts = 8;
1406
1407 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1408 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1409 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1410 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1411 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1412 break;
1413 case CHIP_STONEY:
1414 adev->gfx.config.max_shader_engines = 1;
1415 adev->gfx.config.max_tile_pipes = 2;
1416 adev->gfx.config.max_sh_per_se = 1;
1417 adev->gfx.config.max_backends_per_se = 1;
1418
1419 switch (adev->pdev->revision) {
1420 case 0xc0:
1421 case 0xc1:
1422 case 0xc2:
1423 case 0xc4:
1424 case 0xc8:
1425 case 0xc9:
1426 adev->gfx.config.max_cu_per_sh = 3;
1427 break;
1428 case 0xd0:
1429 case 0xd1:
1430 case 0xd2:
1431 default:
1432 adev->gfx.config.max_cu_per_sh = 2;
1433 break;
1434 }
1435
1436 adev->gfx.config.max_texture_channel_caches = 2;
1437 adev->gfx.config.max_gprs = 256;
1438 adev->gfx.config.max_gs_threads = 16;
1439 adev->gfx.config.max_hw_contexts = 8;
1440
1441 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1442 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1443 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1444 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1445 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1446 break;
1447 default:
1448 adev->gfx.config.max_shader_engines = 2;
1449 adev->gfx.config.max_tile_pipes = 4;
1450 adev->gfx.config.max_cu_per_sh = 2;
1451 adev->gfx.config.max_sh_per_se = 1;
1452 adev->gfx.config.max_backends_per_se = 2;
1453 adev->gfx.config.max_texture_channel_caches = 4;
1454 adev->gfx.config.max_gprs = 256;
1455 adev->gfx.config.max_gs_threads = 32;
1456 adev->gfx.config.max_hw_contexts = 8;
1457
1458 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1459 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1460 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1461 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1462 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1463 break;
1464 }
1465
1466 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1467 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1468 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1469
1470 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1471 adev->gfx.config.mem_max_burst_length_bytes = 256;
1472 if (adev->flags & AMD_IS_APU) {
1473 /* Get memory bank mapping mode. */
1474 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1475 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1476 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1477
1478 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1479 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1480 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1481
1482 /* Validate settings in case only one DIMM installed. */
1483 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1484 dimm00_addr_map = 0;
1485 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1486 dimm01_addr_map = 0;
1487 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1488 dimm10_addr_map = 0;
1489 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1490 dimm11_addr_map = 0;
1491
1492 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1493 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1494 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1495 adev->gfx.config.mem_row_size_in_kb = 2;
1496 else
1497 adev->gfx.config.mem_row_size_in_kb = 1;
1498 } else {
1499 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1500 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1501 if (adev->gfx.config.mem_row_size_in_kb > 4)
1502 adev->gfx.config.mem_row_size_in_kb = 4;
1503 }
1504
1505 adev->gfx.config.shader_engine_tile_size = 32;
1506 adev->gfx.config.num_gpus = 1;
1507 adev->gfx.config.multi_gpu_tile_size = 64;
1508
1509 /* fix up row size */
1510 switch (adev->gfx.config.mem_row_size_in_kb) {
1511 case 1:
1512 default:
1513 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1514 break;
1515 case 2:
1516 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1517 break;
1518 case 4:
1519 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1520 break;
1521 }
1522 adev->gfx.config.gb_addr_config = gb_addr_config;
1523}
1524
1525static int gfx_v8_0_sw_init(void *handle)
1526{
1527 int i, r;
1528 struct amdgpu_ring *ring;
1529 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531 /* EOP Event */
1532 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1533 if (r)
1534 return r;
1535
1536 /* Privileged reg */
1537 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1538 if (r)
1539 return r;
1540
1541 /* Privileged inst */
1542 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1543 if (r)
1544 return r;
1545
1546 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1547
1548 gfx_v8_0_scratch_init(adev);
1549
1550 r = gfx_v8_0_init_microcode(adev);
1551 if (r) {
1552 DRM_ERROR("Failed to load gfx firmware!\n");
1553 return r;
1554 }
1555
1556 r = gfx_v8_0_mec_init(adev);
1557 if (r) {
1558 DRM_ERROR("Failed to init MEC BOs!\n");
1559 return r;
1560 }
1561
1562 /* set up the gfx ring */
1563 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1564 ring = &adev->gfx.gfx_ring[i];
1565 ring->ring_obj = NULL;
1566 sprintf(ring->name, "gfx");
1567 /* no gfx doorbells on iceland */
1568 if (adev->asic_type != CHIP_TOPAZ) {
1569 ring->use_doorbell = true;
1570 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1571 }
1572
1573 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1574 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1575 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1576 AMDGPU_RING_TYPE_GFX);
1577 if (r)
1578 return r;
1579 }
1580
1581 /* set up the compute queues */
1582 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1583 unsigned irq_type;
1584
1585 /* max 32 queues per MEC */
1586 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1587 DRM_ERROR("Too many (%d) compute rings!\n", i);
1588 break;
1589 }
1590 ring = &adev->gfx.compute_ring[i];
1591 ring->ring_obj = NULL;
1592 ring->use_doorbell = true;
1593 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1594 ring->me = 1; /* first MEC */
1595 ring->pipe = i / 8;
1596 ring->queue = i % 8;
1597 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1598 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1599 /* type-2 packets are deprecated on MEC, use type-3 instead */
1600 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1601 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1602 &adev->gfx.eop_irq, irq_type,
1603 AMDGPU_RING_TYPE_COMPUTE);
1604 if (r)
1605 return r;
1606 }
1607
1608 /* reserve GDS, GWS and OA resource for gfx */
1609 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1610 PAGE_SIZE, true,
1611 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1612 NULL, &adev->gds.gds_gfx_bo);
1613 if (r)
1614 return r;
1615
1616 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1617 PAGE_SIZE, true,
1618 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1619 NULL, &adev->gds.gws_gfx_bo);
1620 if (r)
1621 return r;
1622
1623 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1624 PAGE_SIZE, true,
1625 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1626 NULL, &adev->gds.oa_gfx_bo);
1627 if (r)
1628 return r;
1629
1630 adev->gfx.ce_ram_size = 0x8000;
1631
1632 gfx_v8_0_gpu_early_init(adev);
1633
1634 return 0;
1635}
1636
1637static int gfx_v8_0_sw_fini(void *handle)
1638{
1639 int i;
1640 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1641
1642 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1643 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1644 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1645
1646 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1647 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1648 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1649 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1650
1651 gfx_v8_0_mec_fini(adev);
1652
1653 return 0;
1654}
1655
1656static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1657{
1658 uint32_t *modearray, *mod2array;
1659 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1660 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1661 u32 reg_offset;
1662
1663 modearray = adev->gfx.config.tile_mode_array;
1664 mod2array = adev->gfx.config.macrotile_mode_array;
1665
1666 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1667 modearray[reg_offset] = 0;
1668
1669 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1670 mod2array[reg_offset] = 0;
1671
1672 switch (adev->asic_type) {
1673 case CHIP_TOPAZ:
1674 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1675 PIPE_CONFIG(ADDR_SURF_P2) |
1676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1677 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1678 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1679 PIPE_CONFIG(ADDR_SURF_P2) |
1680 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1681 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1682 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1683 PIPE_CONFIG(ADDR_SURF_P2) |
1684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1685 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1686 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1687 PIPE_CONFIG(ADDR_SURF_P2) |
1688 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1689 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1690 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1691 PIPE_CONFIG(ADDR_SURF_P2) |
1692 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1693 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1694 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1695 PIPE_CONFIG(ADDR_SURF_P2) |
1696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1697 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1698 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1699 PIPE_CONFIG(ADDR_SURF_P2) |
1700 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1701 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1702 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1703 PIPE_CONFIG(ADDR_SURF_P2));
1704 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1705 PIPE_CONFIG(ADDR_SURF_P2) |
1706 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1707 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1708 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1709 PIPE_CONFIG(ADDR_SURF_P2) |
1710 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1711 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1712 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1713 PIPE_CONFIG(ADDR_SURF_P2) |
1714 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1715 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1716 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1717 PIPE_CONFIG(ADDR_SURF_P2) |
1718 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1719 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1720 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1721 PIPE_CONFIG(ADDR_SURF_P2) |
1722 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1723 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1724 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1725 PIPE_CONFIG(ADDR_SURF_P2) |
1726 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1727 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1728 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1729 PIPE_CONFIG(ADDR_SURF_P2) |
1730 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1731 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1732 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1733 PIPE_CONFIG(ADDR_SURF_P2) |
1734 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1735 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1736 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1737 PIPE_CONFIG(ADDR_SURF_P2) |
1738 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1739 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1740 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1741 PIPE_CONFIG(ADDR_SURF_P2) |
1742 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1743 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1744 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1745 PIPE_CONFIG(ADDR_SURF_P2) |
1746 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1747 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1748 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1749 PIPE_CONFIG(ADDR_SURF_P2) |
1750 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1751 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1752 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1753 PIPE_CONFIG(ADDR_SURF_P2) |
1754 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1755 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1756 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1757 PIPE_CONFIG(ADDR_SURF_P2) |
1758 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1759 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1760 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1761 PIPE_CONFIG(ADDR_SURF_P2) |
1762 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1763 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1764 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1765 PIPE_CONFIG(ADDR_SURF_P2) |
1766 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1767 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1768 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1769 PIPE_CONFIG(ADDR_SURF_P2) |
1770 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1771 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1772 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1773 PIPE_CONFIG(ADDR_SURF_P2) |
1774 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1775 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1776
1777 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1778 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1779 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1780 NUM_BANKS(ADDR_SURF_8_BANK));
1781 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1784 NUM_BANKS(ADDR_SURF_8_BANK));
1785 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1788 NUM_BANKS(ADDR_SURF_8_BANK));
1789 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1792 NUM_BANKS(ADDR_SURF_8_BANK));
1793 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1796 NUM_BANKS(ADDR_SURF_8_BANK));
1797 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1800 NUM_BANKS(ADDR_SURF_8_BANK));
1801 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1804 NUM_BANKS(ADDR_SURF_8_BANK));
1805 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1808 NUM_BANKS(ADDR_SURF_16_BANK));
1809 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1812 NUM_BANKS(ADDR_SURF_16_BANK));
1813 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1816 NUM_BANKS(ADDR_SURF_16_BANK));
1817 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1820 NUM_BANKS(ADDR_SURF_16_BANK));
1821 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1824 NUM_BANKS(ADDR_SURF_16_BANK));
1825 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1828 NUM_BANKS(ADDR_SURF_16_BANK));
1829 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1832 NUM_BANKS(ADDR_SURF_8_BANK));
1833
1834 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1835 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
1836 reg_offset != 23)
1837 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
1838
1839 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1840 if (reg_offset != 7)
1841 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
1842
1843 break;
1844 case CHIP_FIJI:
1845 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1846 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1848 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1849 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1850 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1852 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1853 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1854 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1855 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1856 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1857 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1858 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1860 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1861 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1862 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1864 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1865 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1866 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1868 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1869 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1870 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1872 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1873 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1874 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1876 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1877 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1878 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1879 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1880 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1881 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1882 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1883 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1884 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1885 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1886 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1887 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1888 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1889 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1890 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1891 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1892 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1893 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1894 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1895 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1896 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1897 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1898 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1899 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1900 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1901 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1902 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1903 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1904 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1905 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1906 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1907 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1908 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1909 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1910 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1911 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1912 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1913 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1914 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1915 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1916 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1917 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1918 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1919 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1920 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1921 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1922 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1923 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1924 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1925 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1926 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1927 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1928 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1929 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1930 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1931 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1932 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1933 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1934 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1935 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1936 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1937 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1938 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1939 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1940 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1941 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1942 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1943 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1944 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1945 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1946 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1947 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1948 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1949 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1951 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1952 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1953 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1954 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1955 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1956 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1957 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1958 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1959 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1960 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1961 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1962 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1963 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1964 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1965 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1966 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1967
1968 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1971 NUM_BANKS(ADDR_SURF_8_BANK));
1972 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1975 NUM_BANKS(ADDR_SURF_8_BANK));
1976 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1977 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1978 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1979 NUM_BANKS(ADDR_SURF_8_BANK));
1980 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1983 NUM_BANKS(ADDR_SURF_8_BANK));
1984 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1985 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1986 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1987 NUM_BANKS(ADDR_SURF_8_BANK));
1988 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1991 NUM_BANKS(ADDR_SURF_8_BANK));
1992 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1995 NUM_BANKS(ADDR_SURF_8_BANK));
1996 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1999 NUM_BANKS(ADDR_SURF_8_BANK));
2000 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2003 NUM_BANKS(ADDR_SURF_8_BANK));
2004 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2007 NUM_BANKS(ADDR_SURF_8_BANK));
2008 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2011 NUM_BANKS(ADDR_SURF_8_BANK));
2012 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2015 NUM_BANKS(ADDR_SURF_8_BANK));
2016 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2019 NUM_BANKS(ADDR_SURF_8_BANK));
2020 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2023 NUM_BANKS(ADDR_SURF_4_BANK));
2024
2025 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2026 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2027
2028 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2029 if (reg_offset != 7)
2030 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2031
2032 break;
2033 case CHIP_TONGA:
2034 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2035 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2037 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2038 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2039 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2041 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2042 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2043 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2045 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2046 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2047 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2049 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2050 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2051 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2052 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2053 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2054 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2055 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2057 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2058 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2059 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2060 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2061 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2062 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2063 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2065 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2066 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2067 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2068 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2069 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2070 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2071 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2072 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2073 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2074 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2075 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2076 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2077 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2078 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2079 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2080 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2081 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2082 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2083 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2084 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2085 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2086 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2087 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2088 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2089 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2090 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2092 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2093 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2094 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2095 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2096 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2097 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2098 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2099 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2100 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2101 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2102 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2104 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2105 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2106 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2108 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2109 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2110 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2111 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2112 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2113 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2114 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2116 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2117 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2118 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2119 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2120 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2121 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2122 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2123 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2124 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2125 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2126 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2127 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2128 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2129 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2130 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2131 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2132 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2133 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2134 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2135 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2136 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2137 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2138 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2140 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2141 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2142 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2143 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2144 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2145 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2146 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2147 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2148 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2149 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2152 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2153 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2155 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2156
2157 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2160 NUM_BANKS(ADDR_SURF_16_BANK));
2161 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2164 NUM_BANKS(ADDR_SURF_16_BANK));
2165 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2168 NUM_BANKS(ADDR_SURF_16_BANK));
2169 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2172 NUM_BANKS(ADDR_SURF_16_BANK));
2173 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2176 NUM_BANKS(ADDR_SURF_16_BANK));
2177 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2180 NUM_BANKS(ADDR_SURF_16_BANK));
2181 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2184 NUM_BANKS(ADDR_SURF_16_BANK));
2185 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2186 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2187 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2188 NUM_BANKS(ADDR_SURF_16_BANK));
2189 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2192 NUM_BANKS(ADDR_SURF_16_BANK));
2193 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2194 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2195 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2196 NUM_BANKS(ADDR_SURF_16_BANK));
2197 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2200 NUM_BANKS(ADDR_SURF_16_BANK));
2201 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2204 NUM_BANKS(ADDR_SURF_8_BANK));
2205 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2208 NUM_BANKS(ADDR_SURF_4_BANK));
2209 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2212 NUM_BANKS(ADDR_SURF_4_BANK));
2213
2214 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2215 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2216
2217 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2218 if (reg_offset != 7)
2219 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2220
2221 break;
2222 case CHIP_STONEY:
2223 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2224 PIPE_CONFIG(ADDR_SURF_P2) |
2225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2227 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2228 PIPE_CONFIG(ADDR_SURF_P2) |
2229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2231 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2232 PIPE_CONFIG(ADDR_SURF_P2) |
2233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2235 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2236 PIPE_CONFIG(ADDR_SURF_P2) |
2237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2239 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2240 PIPE_CONFIG(ADDR_SURF_P2) |
2241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2243 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2244 PIPE_CONFIG(ADDR_SURF_P2) |
2245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2247 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2248 PIPE_CONFIG(ADDR_SURF_P2) |
2249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2251 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2252 PIPE_CONFIG(ADDR_SURF_P2));
2253 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2254 PIPE_CONFIG(ADDR_SURF_P2) |
2255 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2256 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2257 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2258 PIPE_CONFIG(ADDR_SURF_P2) |
2259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2261 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2262 PIPE_CONFIG(ADDR_SURF_P2) |
2263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2265 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2266 PIPE_CONFIG(ADDR_SURF_P2) |
2267 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2269 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2270 PIPE_CONFIG(ADDR_SURF_P2) |
2271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2272 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2273 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2274 PIPE_CONFIG(ADDR_SURF_P2) |
2275 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2277 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2278 PIPE_CONFIG(ADDR_SURF_P2) |
2279 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2280 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2281 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2282 PIPE_CONFIG(ADDR_SURF_P2) |
2283 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2284 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2285 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2286 PIPE_CONFIG(ADDR_SURF_P2) |
2287 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2289 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2290 PIPE_CONFIG(ADDR_SURF_P2) |
2291 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2292 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2293 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2294 PIPE_CONFIG(ADDR_SURF_P2) |
2295 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2296 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2297 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2298 PIPE_CONFIG(ADDR_SURF_P2) |
2299 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2301 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2302 PIPE_CONFIG(ADDR_SURF_P2) |
2303 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2305 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2306 PIPE_CONFIG(ADDR_SURF_P2) |
2307 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2309 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2310 PIPE_CONFIG(ADDR_SURF_P2) |
2311 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2313 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2314 PIPE_CONFIG(ADDR_SURF_P2) |
2315 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2317 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2318 PIPE_CONFIG(ADDR_SURF_P2) |
2319 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2321 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2322 PIPE_CONFIG(ADDR_SURF_P2) |
2323 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2325
2326 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2329 NUM_BANKS(ADDR_SURF_8_BANK));
2330 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2331 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2332 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2333 NUM_BANKS(ADDR_SURF_8_BANK));
2334 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2335 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2336 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2337 NUM_BANKS(ADDR_SURF_8_BANK));
2338 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2341 NUM_BANKS(ADDR_SURF_8_BANK));
2342 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2345 NUM_BANKS(ADDR_SURF_8_BANK));
2346 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2349 NUM_BANKS(ADDR_SURF_8_BANK));
2350 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2353 NUM_BANKS(ADDR_SURF_8_BANK));
2354 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2357 NUM_BANKS(ADDR_SURF_16_BANK));
2358 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2361 NUM_BANKS(ADDR_SURF_16_BANK));
2362 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2365 NUM_BANKS(ADDR_SURF_16_BANK));
2366 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2369 NUM_BANKS(ADDR_SURF_16_BANK));
2370 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2371 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2372 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2373 NUM_BANKS(ADDR_SURF_16_BANK));
2374 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2375 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2376 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2377 NUM_BANKS(ADDR_SURF_16_BANK));
2378 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2381 NUM_BANKS(ADDR_SURF_8_BANK));
2382
2383 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2384 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2385 reg_offset != 23)
2386 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2387
2388 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2389 if (reg_offset != 7)
2390 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2391
2392 break;
2393 default:
2394 dev_warn(adev->dev,
2395 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
2396 adev->asic_type);
2397
2398 case CHIP_CARRIZO:
2399 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2400 PIPE_CONFIG(ADDR_SURF_P2) |
2401 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2403 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2404 PIPE_CONFIG(ADDR_SURF_P2) |
2405 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2407 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2408 PIPE_CONFIG(ADDR_SURF_P2) |
2409 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2411 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2412 PIPE_CONFIG(ADDR_SURF_P2) |
2413 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2415 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2416 PIPE_CONFIG(ADDR_SURF_P2) |
2417 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2419 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2420 PIPE_CONFIG(ADDR_SURF_P2) |
2421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2423 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2424 PIPE_CONFIG(ADDR_SURF_P2) |
2425 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2427 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2428 PIPE_CONFIG(ADDR_SURF_P2));
2429 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2430 PIPE_CONFIG(ADDR_SURF_P2) |
2431 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2432 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2433 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2434 PIPE_CONFIG(ADDR_SURF_P2) |
2435 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2436 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2437 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2438 PIPE_CONFIG(ADDR_SURF_P2) |
2439 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2440 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2441 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2442 PIPE_CONFIG(ADDR_SURF_P2) |
2443 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2444 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2445 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2446 PIPE_CONFIG(ADDR_SURF_P2) |
2447 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2448 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2449 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2450 PIPE_CONFIG(ADDR_SURF_P2) |
2451 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2452 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2453 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2454 PIPE_CONFIG(ADDR_SURF_P2) |
2455 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2457 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2458 PIPE_CONFIG(ADDR_SURF_P2) |
2459 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2461 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2462 PIPE_CONFIG(ADDR_SURF_P2) |
2463 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2465 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2466 PIPE_CONFIG(ADDR_SURF_P2) |
2467 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2469 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2470 PIPE_CONFIG(ADDR_SURF_P2) |
2471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2473 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2474 PIPE_CONFIG(ADDR_SURF_P2) |
2475 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2476 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2477 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2478 PIPE_CONFIG(ADDR_SURF_P2) |
2479 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2480 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2481 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2482 PIPE_CONFIG(ADDR_SURF_P2) |
2483 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2485 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2486 PIPE_CONFIG(ADDR_SURF_P2) |
2487 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2488 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2489 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2490 PIPE_CONFIG(ADDR_SURF_P2) |
2491 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2492 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2493 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2494 PIPE_CONFIG(ADDR_SURF_P2) |
2495 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2496 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2497 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2498 PIPE_CONFIG(ADDR_SURF_P2) |
2499 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2500 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2501
2502 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2505 NUM_BANKS(ADDR_SURF_8_BANK));
2506 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2509 NUM_BANKS(ADDR_SURF_8_BANK));
2510 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2513 NUM_BANKS(ADDR_SURF_8_BANK));
2514 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2517 NUM_BANKS(ADDR_SURF_8_BANK));
2518 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2521 NUM_BANKS(ADDR_SURF_8_BANK));
2522 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2525 NUM_BANKS(ADDR_SURF_8_BANK));
2526 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2529 NUM_BANKS(ADDR_SURF_8_BANK));
2530 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2533 NUM_BANKS(ADDR_SURF_16_BANK));
2534 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2537 NUM_BANKS(ADDR_SURF_16_BANK));
2538 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2541 NUM_BANKS(ADDR_SURF_16_BANK));
2542 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2543 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2544 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2545 NUM_BANKS(ADDR_SURF_16_BANK));
2546 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2547 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2548 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2549 NUM_BANKS(ADDR_SURF_16_BANK));
2550 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2553 NUM_BANKS(ADDR_SURF_16_BANK));
2554 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2555 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2556 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2557 NUM_BANKS(ADDR_SURF_8_BANK));
2558
2559 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2560 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2561 reg_offset != 23)
2562 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2563
2564 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2565 if (reg_offset != 7)
2566 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2567
2568 break;
2569 }
2570}
2571
2572void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2573{
2574 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2575
2576 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2577 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2578 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2579 } else if (se_num == 0xffffffff) {
2580 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2581 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2582 } else if (sh_num == 0xffffffff) {
2583 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2584 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2585 } else {
2586 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2588 }
2589 WREG32(mmGRBM_GFX_INDEX, data);
2590}
2591
2592static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2593{
2594 return (u32)((1ULL << bit_width) - 1);
2595}
2596
2597static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2598{
2599 u32 data, mask;
2600
2601 data = RREG32(mmCC_RB_BACKEND_DISABLE);
2602 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2603
2604 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2605 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2606
2607 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
2608 adev->gfx.config.max_sh_per_se);
2609
2610 return (~data) & mask;
2611}
2612
2613static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
2614{
2615 int i, j;
2616 u32 data;
2617 u32 active_rbs = 0;
2618 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2619 adev->gfx.config.max_sh_per_se;
2620
2621 mutex_lock(&adev->grbm_idx_mutex);
2622 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2623 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2624 gfx_v8_0_select_se_sh(adev, i, j);
2625 data = gfx_v8_0_get_rb_active_bitmap(adev);
2626 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2627 rb_bitmap_width_per_sh);
2628 }
2629 }
2630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2631 mutex_unlock(&adev->grbm_idx_mutex);
2632
2633 adev->gfx.config.backend_enable_mask = active_rbs;
2634 adev->gfx.config.num_rbs = hweight32(active_rbs);
2635}
2636
2637/**
2638 * gfx_v8_0_init_compute_vmid - gart enable
2639 *
2640 * @rdev: amdgpu_device pointer
2641 *
2642 * Initialize compute vmid sh_mem registers
2643 *
2644 */
2645#define DEFAULT_SH_MEM_BASES (0x6000)
2646#define FIRST_COMPUTE_VMID (8)
2647#define LAST_COMPUTE_VMID (16)
2648static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2649{
2650 int i;
2651 uint32_t sh_mem_config;
2652 uint32_t sh_mem_bases;
2653
2654 /*
2655 * Configure apertures:
2656 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2657 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2658 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2659 */
2660 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2661
2662 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2663 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2664 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2665 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2666 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2667 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2668
2669 mutex_lock(&adev->srbm_mutex);
2670 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2671 vi_srbm_select(adev, 0, 0, 0, i);
2672 /* CP and shaders */
2673 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2674 WREG32(mmSH_MEM_APE1_BASE, 1);
2675 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2676 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2677 }
2678 vi_srbm_select(adev, 0, 0, 0, 0);
2679 mutex_unlock(&adev->srbm_mutex);
2680}
2681
2682static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2683{
2684 u32 tmp;
2685 int i;
2686
2687 tmp = RREG32(mmGRBM_CNTL);
2688 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2689 WREG32(mmGRBM_CNTL, tmp);
2690
2691 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2692 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2693 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2694
2695 gfx_v8_0_tiling_mode_table_init(adev);
2696
2697 gfx_v8_0_setup_rb(adev);
2698
2699 /* XXX SH_MEM regs */
2700 /* where to put LDS, scratch, GPUVM in FSA64 space */
2701 mutex_lock(&adev->srbm_mutex);
2702 for (i = 0; i < 16; i++) {
2703 vi_srbm_select(adev, 0, 0, 0, i);
2704 /* CP and shaders */
2705 if (i == 0) {
2706 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2707 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2708 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2709 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2710 WREG32(mmSH_MEM_CONFIG, tmp);
2711 } else {
2712 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2713 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2714 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2715 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2716 WREG32(mmSH_MEM_CONFIG, tmp);
2717 }
2718
2719 WREG32(mmSH_MEM_APE1_BASE, 1);
2720 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2721 WREG32(mmSH_MEM_BASES, 0);
2722 }
2723 vi_srbm_select(adev, 0, 0, 0, 0);
2724 mutex_unlock(&adev->srbm_mutex);
2725
2726 gfx_v8_0_init_compute_vmid(adev);
2727
2728 mutex_lock(&adev->grbm_idx_mutex);
2729 /*
2730 * making sure that the following register writes will be broadcasted
2731 * to all the shaders
2732 */
2733 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2734
2735 WREG32(mmPA_SC_FIFO_SIZE,
2736 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2737 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2738 (adev->gfx.config.sc_prim_fifo_size_backend <<
2739 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2740 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2741 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2742 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2743 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2744 mutex_unlock(&adev->grbm_idx_mutex);
2745
2746}
2747
2748static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2749{
2750 u32 i, j, k;
2751 u32 mask;
2752
2753 mutex_lock(&adev->grbm_idx_mutex);
2754 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2755 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2756 gfx_v8_0_select_se_sh(adev, i, j);
2757 for (k = 0; k < adev->usec_timeout; k++) {
2758 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2759 break;
2760 udelay(1);
2761 }
2762 }
2763 }
2764 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2765 mutex_unlock(&adev->grbm_idx_mutex);
2766
2767 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2768 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2769 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2770 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2771 for (k = 0; k < adev->usec_timeout; k++) {
2772 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2773 break;
2774 udelay(1);
2775 }
2776}
2777
2778static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2779 bool enable)
2780{
2781 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2782
2783 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2784 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2785 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2786 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2787
2788 WREG32(mmCP_INT_CNTL_RING0, tmp);
2789}
2790
2791void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2792{
2793 u32 tmp = RREG32(mmRLC_CNTL);
2794
2795 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2796 WREG32(mmRLC_CNTL, tmp);
2797
2798 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2799
2800 gfx_v8_0_wait_for_rlc_serdes(adev);
2801}
2802
2803static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2804{
2805 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2806
2807 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2808 WREG32(mmGRBM_SOFT_RESET, tmp);
2809 udelay(50);
2810 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2811 WREG32(mmGRBM_SOFT_RESET, tmp);
2812 udelay(50);
2813}
2814
2815static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2816{
2817 u32 tmp = RREG32(mmRLC_CNTL);
2818
2819 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2820 WREG32(mmRLC_CNTL, tmp);
2821
2822 /* carrizo do enable cp interrupt after cp inited */
2823 if (!(adev->flags & AMD_IS_APU))
2824 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2825
2826 udelay(50);
2827}
2828
2829static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2830{
2831 const struct rlc_firmware_header_v2_0 *hdr;
2832 const __le32 *fw_data;
2833 unsigned i, fw_size;
2834
2835 if (!adev->gfx.rlc_fw)
2836 return -EINVAL;
2837
2838 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2839 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2840
2841 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2842 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2843 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2844
2845 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2846 for (i = 0; i < fw_size; i++)
2847 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2848 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2849
2850 return 0;
2851}
2852
2853static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2854{
2855 int r;
2856
2857 gfx_v8_0_rlc_stop(adev);
2858
2859 /* disable CG */
2860 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2861
2862 /* disable PG */
2863 WREG32(mmRLC_PG_CNTL, 0);
2864
2865 gfx_v8_0_rlc_reset(adev);
2866
2867 if (!adev->pp_enabled) {
2868 if (!adev->firmware.smu_load) {
2869 /* legacy rlc firmware loading */
2870 r = gfx_v8_0_rlc_load_microcode(adev);
2871 if (r)
2872 return r;
2873 } else {
2874 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2875 AMDGPU_UCODE_ID_RLC_G);
2876 if (r)
2877 return -EINVAL;
2878 }
2879 }
2880
2881 gfx_v8_0_rlc_start(adev);
2882
2883 return 0;
2884}
2885
2886static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2887{
2888 int i;
2889 u32 tmp = RREG32(mmCP_ME_CNTL);
2890
2891 if (enable) {
2892 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2893 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2894 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2895 } else {
2896 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2897 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2898 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2899 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2900 adev->gfx.gfx_ring[i].ready = false;
2901 }
2902 WREG32(mmCP_ME_CNTL, tmp);
2903 udelay(50);
2904}
2905
2906static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2907{
2908 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2909 const struct gfx_firmware_header_v1_0 *ce_hdr;
2910 const struct gfx_firmware_header_v1_0 *me_hdr;
2911 const __le32 *fw_data;
2912 unsigned i, fw_size;
2913
2914 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2915 return -EINVAL;
2916
2917 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2918 adev->gfx.pfp_fw->data;
2919 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2920 adev->gfx.ce_fw->data;
2921 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2922 adev->gfx.me_fw->data;
2923
2924 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2925 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2926 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2927
2928 gfx_v8_0_cp_gfx_enable(adev, false);
2929
2930 /* PFP */
2931 fw_data = (const __le32 *)
2932 (adev->gfx.pfp_fw->data +
2933 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2934 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2935 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2936 for (i = 0; i < fw_size; i++)
2937 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2938 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2939
2940 /* CE */
2941 fw_data = (const __le32 *)
2942 (adev->gfx.ce_fw->data +
2943 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2944 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2945 WREG32(mmCP_CE_UCODE_ADDR, 0);
2946 for (i = 0; i < fw_size; i++)
2947 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2948 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2949
2950 /* ME */
2951 fw_data = (const __le32 *)
2952 (adev->gfx.me_fw->data +
2953 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2954 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2955 WREG32(mmCP_ME_RAM_WADDR, 0);
2956 for (i = 0; i < fw_size; i++)
2957 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2958 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2959
2960 return 0;
2961}
2962
2963static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2964{
2965 u32 count = 0;
2966 const struct cs_section_def *sect = NULL;
2967 const struct cs_extent_def *ext = NULL;
2968
2969 /* begin clear state */
2970 count += 2;
2971 /* context control state */
2972 count += 3;
2973
2974 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2975 for (ext = sect->section; ext->extent != NULL; ++ext) {
2976 if (sect->id == SECT_CONTEXT)
2977 count += 2 + ext->reg_count;
2978 else
2979 return 0;
2980 }
2981 }
2982 /* pa_sc_raster_config/pa_sc_raster_config1 */
2983 count += 4;
2984 /* end clear state */
2985 count += 2;
2986 /* clear state */
2987 count += 2;
2988
2989 return count;
2990}
2991
2992static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2993{
2994 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2995 const struct cs_section_def *sect = NULL;
2996 const struct cs_extent_def *ext = NULL;
2997 int r, i;
2998
2999 /* init the CP */
3000 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3001 WREG32(mmCP_ENDIAN_SWAP, 0);
3002 WREG32(mmCP_DEVICE_ID, 1);
3003
3004 gfx_v8_0_cp_gfx_enable(adev, true);
3005
3006 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
3007 if (r) {
3008 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3009 return r;
3010 }
3011
3012 /* clear state buffer */
3013 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3014 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3015
3016 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3017 amdgpu_ring_write(ring, 0x80000000);
3018 amdgpu_ring_write(ring, 0x80000000);
3019
3020 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3021 for (ext = sect->section; ext->extent != NULL; ++ext) {
3022 if (sect->id == SECT_CONTEXT) {
3023 amdgpu_ring_write(ring,
3024 PACKET3(PACKET3_SET_CONTEXT_REG,
3025 ext->reg_count));
3026 amdgpu_ring_write(ring,
3027 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3028 for (i = 0; i < ext->reg_count; i++)
3029 amdgpu_ring_write(ring, ext->extent[i]);
3030 }
3031 }
3032 }
3033
3034 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3035 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3036 switch (adev->asic_type) {
3037 case CHIP_TONGA:
3038 amdgpu_ring_write(ring, 0x16000012);
3039 amdgpu_ring_write(ring, 0x0000002A);
3040 break;
3041 case CHIP_FIJI:
3042 amdgpu_ring_write(ring, 0x3a00161a);
3043 amdgpu_ring_write(ring, 0x0000002e);
3044 break;
3045 case CHIP_TOPAZ:
3046 case CHIP_CARRIZO:
3047 amdgpu_ring_write(ring, 0x00000002);
3048 amdgpu_ring_write(ring, 0x00000000);
3049 break;
3050 case CHIP_STONEY:
3051 amdgpu_ring_write(ring, 0x00000000);
3052 amdgpu_ring_write(ring, 0x00000000);
3053 break;
3054 default:
3055 BUG();
3056 }
3057
3058 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3059 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3060
3061 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3062 amdgpu_ring_write(ring, 0);
3063
3064 /* init the CE partitions */
3065 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3066 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3067 amdgpu_ring_write(ring, 0x8000);
3068 amdgpu_ring_write(ring, 0x8000);
3069
3070 amdgpu_ring_commit(ring);
3071
3072 return 0;
3073}
3074
3075static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
3076{
3077 struct amdgpu_ring *ring;
3078 u32 tmp;
3079 u32 rb_bufsz;
3080 u64 rb_addr, rptr_addr;
3081 int r;
3082
3083 /* Set the write pointer delay */
3084 WREG32(mmCP_RB_WPTR_DELAY, 0);
3085
3086 /* set the RB to use vmid 0 */
3087 WREG32(mmCP_RB_VMID, 0);
3088
3089 /* Set ring buffer size */
3090 ring = &adev->gfx.gfx_ring[0];
3091 rb_bufsz = order_base_2(ring->ring_size / 8);
3092 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3093 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3094 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
3095 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
3096#ifdef __BIG_ENDIAN
3097 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3098#endif
3099 WREG32(mmCP_RB0_CNTL, tmp);
3100
3101 /* Initialize the ring buffer's read and write pointers */
3102 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
3103 ring->wptr = 0;
3104 WREG32(mmCP_RB0_WPTR, ring->wptr);
3105
3106 /* set the wb address wether it's enabled or not */
3107 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3108 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3109 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
3110
3111 mdelay(1);
3112 WREG32(mmCP_RB0_CNTL, tmp);
3113
3114 rb_addr = ring->gpu_addr >> 8;
3115 WREG32(mmCP_RB0_BASE, rb_addr);
3116 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3117
3118 /* no gfx doorbells on iceland */
3119 if (adev->asic_type != CHIP_TOPAZ) {
3120 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
3121 if (ring->use_doorbell) {
3122 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3123 DOORBELL_OFFSET, ring->doorbell_index);
3124 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3125 DOORBELL_EN, 1);
3126 } else {
3127 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3128 DOORBELL_EN, 0);
3129 }
3130 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
3131
3132 if (adev->asic_type == CHIP_TONGA) {
3133 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3134 DOORBELL_RANGE_LOWER,
3135 AMDGPU_DOORBELL_GFX_RING0);
3136 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3137
3138 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
3139 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3140 }
3141
3142 }
3143
3144 /* start the ring */
3145 gfx_v8_0_cp_gfx_start(adev);
3146 ring->ready = true;
3147 r = amdgpu_ring_test_ring(ring);
3148 if (r) {
3149 ring->ready = false;
3150 return r;
3151 }
3152
3153 return 0;
3154}
3155
3156static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3157{
3158 int i;
3159
3160 if (enable) {
3161 WREG32(mmCP_MEC_CNTL, 0);
3162 } else {
3163 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3164 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3165 adev->gfx.compute_ring[i].ready = false;
3166 }
3167 udelay(50);
3168}
3169
3170static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3171{
3172 const struct gfx_firmware_header_v1_0 *mec_hdr;
3173 const __le32 *fw_data;
3174 unsigned i, fw_size;
3175
3176 if (!adev->gfx.mec_fw)
3177 return -EINVAL;
3178
3179 gfx_v8_0_cp_compute_enable(adev, false);
3180
3181 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3182 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3183
3184 fw_data = (const __le32 *)
3185 (adev->gfx.mec_fw->data +
3186 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3187 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3188
3189 /* MEC1 */
3190 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3191 for (i = 0; i < fw_size; i++)
3192 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
3193 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3194
3195 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3196 if (adev->gfx.mec2_fw) {
3197 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3198
3199 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3200 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3201
3202 fw_data = (const __le32 *)
3203 (adev->gfx.mec2_fw->data +
3204 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3205 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3206
3207 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3208 for (i = 0; i < fw_size; i++)
3209 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
3210 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
3211 }
3212
3213 return 0;
3214}
3215
3216struct vi_mqd {
3217 uint32_t header; /* ordinal0 */
3218 uint32_t compute_dispatch_initiator; /* ordinal1 */
3219 uint32_t compute_dim_x; /* ordinal2 */
3220 uint32_t compute_dim_y; /* ordinal3 */
3221 uint32_t compute_dim_z; /* ordinal4 */
3222 uint32_t compute_start_x; /* ordinal5 */
3223 uint32_t compute_start_y; /* ordinal6 */
3224 uint32_t compute_start_z; /* ordinal7 */
3225 uint32_t compute_num_thread_x; /* ordinal8 */
3226 uint32_t compute_num_thread_y; /* ordinal9 */
3227 uint32_t compute_num_thread_z; /* ordinal10 */
3228 uint32_t compute_pipelinestat_enable; /* ordinal11 */
3229 uint32_t compute_perfcount_enable; /* ordinal12 */
3230 uint32_t compute_pgm_lo; /* ordinal13 */
3231 uint32_t compute_pgm_hi; /* ordinal14 */
3232 uint32_t compute_tba_lo; /* ordinal15 */
3233 uint32_t compute_tba_hi; /* ordinal16 */
3234 uint32_t compute_tma_lo; /* ordinal17 */
3235 uint32_t compute_tma_hi; /* ordinal18 */
3236 uint32_t compute_pgm_rsrc1; /* ordinal19 */
3237 uint32_t compute_pgm_rsrc2; /* ordinal20 */
3238 uint32_t compute_vmid; /* ordinal21 */
3239 uint32_t compute_resource_limits; /* ordinal22 */
3240 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
3241 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
3242 uint32_t compute_tmpring_size; /* ordinal25 */
3243 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
3244 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
3245 uint32_t compute_restart_x; /* ordinal28 */
3246 uint32_t compute_restart_y; /* ordinal29 */
3247 uint32_t compute_restart_z; /* ordinal30 */
3248 uint32_t compute_thread_trace_enable; /* ordinal31 */
3249 uint32_t compute_misc_reserved; /* ordinal32 */
3250 uint32_t compute_dispatch_id; /* ordinal33 */
3251 uint32_t compute_threadgroup_id; /* ordinal34 */
3252 uint32_t compute_relaunch; /* ordinal35 */
3253 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
3254 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
3255 uint32_t compute_wave_restore_control; /* ordinal38 */
3256 uint32_t reserved9; /* ordinal39 */
3257 uint32_t reserved10; /* ordinal40 */
3258 uint32_t reserved11; /* ordinal41 */
3259 uint32_t reserved12; /* ordinal42 */
3260 uint32_t reserved13; /* ordinal43 */
3261 uint32_t reserved14; /* ordinal44 */
3262 uint32_t reserved15; /* ordinal45 */
3263 uint32_t reserved16; /* ordinal46 */
3264 uint32_t reserved17; /* ordinal47 */
3265 uint32_t reserved18; /* ordinal48 */
3266 uint32_t reserved19; /* ordinal49 */
3267 uint32_t reserved20; /* ordinal50 */
3268 uint32_t reserved21; /* ordinal51 */
3269 uint32_t reserved22; /* ordinal52 */
3270 uint32_t reserved23; /* ordinal53 */
3271 uint32_t reserved24; /* ordinal54 */
3272 uint32_t reserved25; /* ordinal55 */
3273 uint32_t reserved26; /* ordinal56 */
3274 uint32_t reserved27; /* ordinal57 */
3275 uint32_t reserved28; /* ordinal58 */
3276 uint32_t reserved29; /* ordinal59 */
3277 uint32_t reserved30; /* ordinal60 */
3278 uint32_t reserved31; /* ordinal61 */
3279 uint32_t reserved32; /* ordinal62 */
3280 uint32_t reserved33; /* ordinal63 */
3281 uint32_t reserved34; /* ordinal64 */
3282 uint32_t compute_user_data_0; /* ordinal65 */
3283 uint32_t compute_user_data_1; /* ordinal66 */
3284 uint32_t compute_user_data_2; /* ordinal67 */
3285 uint32_t compute_user_data_3; /* ordinal68 */
3286 uint32_t compute_user_data_4; /* ordinal69 */
3287 uint32_t compute_user_data_5; /* ordinal70 */
3288 uint32_t compute_user_data_6; /* ordinal71 */
3289 uint32_t compute_user_data_7; /* ordinal72 */
3290 uint32_t compute_user_data_8; /* ordinal73 */
3291 uint32_t compute_user_data_9; /* ordinal74 */
3292 uint32_t compute_user_data_10; /* ordinal75 */
3293 uint32_t compute_user_data_11; /* ordinal76 */
3294 uint32_t compute_user_data_12; /* ordinal77 */
3295 uint32_t compute_user_data_13; /* ordinal78 */
3296 uint32_t compute_user_data_14; /* ordinal79 */
3297 uint32_t compute_user_data_15; /* ordinal80 */
3298 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
3299 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
3300 uint32_t reserved35; /* ordinal83 */
3301 uint32_t reserved36; /* ordinal84 */
3302 uint32_t reserved37; /* ordinal85 */
3303 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
3304 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
3305 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
3306 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
3307 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
3308 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
3309 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
3310 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
3311 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
3312 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
3313 uint32_t reserved38; /* ordinal96 */
3314 uint32_t reserved39; /* ordinal97 */
3315 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
3316 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
3317 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
3318 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
3319 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
3320 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
3321 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
3322 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
3323 uint32_t reserved40; /* ordinal106 */
3324 uint32_t reserved41; /* ordinal107 */
3325 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
3326 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
3327 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
3328 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
3329 uint32_t reserved42; /* ordinal112 */
3330 uint32_t reserved43; /* ordinal113 */
3331 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
3332 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
3333 uint32_t cp_packet_id_lo; /* ordinal116 */
3334 uint32_t cp_packet_id_hi; /* ordinal117 */
3335 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
3336 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
3337 uint32_t gds_save_base_addr_lo; /* ordinal120 */
3338 uint32_t gds_save_base_addr_hi; /* ordinal121 */
3339 uint32_t gds_save_mask_lo; /* ordinal122 */
3340 uint32_t gds_save_mask_hi; /* ordinal123 */
3341 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
3342 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
3343 uint32_t reserved44; /* ordinal126 */
3344 uint32_t reserved45; /* ordinal127 */
3345 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
3346 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
3347 uint32_t cp_hqd_active; /* ordinal130 */
3348 uint32_t cp_hqd_vmid; /* ordinal131 */
3349 uint32_t cp_hqd_persistent_state; /* ordinal132 */
3350 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
3351 uint32_t cp_hqd_queue_priority; /* ordinal134 */
3352 uint32_t cp_hqd_quantum; /* ordinal135 */
3353 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
3354 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
3355 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
3356 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
3357 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
3358 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
3359 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
3360 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
3361 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
3362 uint32_t cp_hqd_pq_control; /* ordinal145 */
3363 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
3364 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
3365 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
3366 uint32_t cp_hqd_ib_control; /* ordinal149 */
3367 uint32_t cp_hqd_iq_timer; /* ordinal150 */
3368 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
3369 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
3370 uint32_t cp_hqd_dma_offload; /* ordinal153 */
3371 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
3372 uint32_t cp_hqd_msg_type; /* ordinal155 */
3373 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
3374 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
3375 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
3376 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
3377 uint32_t cp_hqd_hq_status0; /* ordinal160 */
3378 uint32_t cp_hqd_hq_control0; /* ordinal161 */
3379 uint32_t cp_mqd_control; /* ordinal162 */
3380 uint32_t cp_hqd_hq_status1; /* ordinal163 */
3381 uint32_t cp_hqd_hq_control1; /* ordinal164 */
3382 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
3383 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
3384 uint32_t cp_hqd_eop_control; /* ordinal167 */
3385 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
3386 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
3387 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
3388 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
3389 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
3390 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
3391 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
3392 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
3393 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
3394 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
3395 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
3396 uint32_t cp_hqd_error; /* ordinal179 */
3397 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
3398 uint32_t cp_hqd_eop_dones; /* ordinal181 */
3399 uint32_t reserved46; /* ordinal182 */
3400 uint32_t reserved47; /* ordinal183 */
3401 uint32_t reserved48; /* ordinal184 */
3402 uint32_t reserved49; /* ordinal185 */
3403 uint32_t reserved50; /* ordinal186 */
3404 uint32_t reserved51; /* ordinal187 */
3405 uint32_t reserved52; /* ordinal188 */
3406 uint32_t reserved53; /* ordinal189 */
3407 uint32_t reserved54; /* ordinal190 */
3408 uint32_t reserved55; /* ordinal191 */
3409 uint32_t iqtimer_pkt_header; /* ordinal192 */
3410 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
3411 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
3412 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
3413 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
3414 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
3415 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
3416 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
3417 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
3418 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
3419 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
3420 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
3421 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
3422 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
3423 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
3424 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
3425 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
3426 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
3427 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
3428 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
3429 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
3430 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
3431 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
3432 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
3433 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
3434 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
3435 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
3436 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
3437 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
3438 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
3439 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
3440 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
3441 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
3442 uint32_t reserved56; /* ordinal225 */
3443 uint32_t reserved57; /* ordinal226 */
3444 uint32_t reserved58; /* ordinal227 */
3445 uint32_t set_resources_header; /* ordinal228 */
3446 uint32_t set_resources_dw1; /* ordinal229 */
3447 uint32_t set_resources_dw2; /* ordinal230 */
3448 uint32_t set_resources_dw3; /* ordinal231 */
3449 uint32_t set_resources_dw4; /* ordinal232 */
3450 uint32_t set_resources_dw5; /* ordinal233 */
3451 uint32_t set_resources_dw6; /* ordinal234 */
3452 uint32_t set_resources_dw7; /* ordinal235 */
3453 uint32_t reserved59; /* ordinal236 */
3454 uint32_t reserved60; /* ordinal237 */
3455 uint32_t reserved61; /* ordinal238 */
3456 uint32_t reserved62; /* ordinal239 */
3457 uint32_t reserved63; /* ordinal240 */
3458 uint32_t reserved64; /* ordinal241 */
3459 uint32_t reserved65; /* ordinal242 */
3460 uint32_t reserved66; /* ordinal243 */
3461 uint32_t reserved67; /* ordinal244 */
3462 uint32_t reserved68; /* ordinal245 */
3463 uint32_t reserved69; /* ordinal246 */
3464 uint32_t reserved70; /* ordinal247 */
3465 uint32_t reserved71; /* ordinal248 */
3466 uint32_t reserved72; /* ordinal249 */
3467 uint32_t reserved73; /* ordinal250 */
3468 uint32_t reserved74; /* ordinal251 */
3469 uint32_t reserved75; /* ordinal252 */
3470 uint32_t reserved76; /* ordinal253 */
3471 uint32_t reserved77; /* ordinal254 */
3472 uint32_t reserved78; /* ordinal255 */
3473
3474 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3475};
3476
3477static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3478{
3479 int i, r;
3480
3481 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3482 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3483
3484 if (ring->mqd_obj) {
3485 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3486 if (unlikely(r != 0))
3487 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3488
3489 amdgpu_bo_unpin(ring->mqd_obj);
3490 amdgpu_bo_unreserve(ring->mqd_obj);
3491
3492 amdgpu_bo_unref(&ring->mqd_obj);
3493 ring->mqd_obj = NULL;
3494 }
3495 }
3496}
3497
3498static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3499{
3500 int r, i, j;
3501 u32 tmp;
3502 bool use_doorbell = true;
3503 u64 hqd_gpu_addr;
3504 u64 mqd_gpu_addr;
3505 u64 eop_gpu_addr;
3506 u64 wb_gpu_addr;
3507 u32 *buf;
3508 struct vi_mqd *mqd;
3509
3510 /* init the pipes */
3511 mutex_lock(&adev->srbm_mutex);
3512 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3513 int me = (i < 4) ? 1 : 2;
3514 int pipe = (i < 4) ? i : (i - 4);
3515
3516 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3517 eop_gpu_addr >>= 8;
3518
3519 vi_srbm_select(adev, me, pipe, 0, 0);
3520
3521 /* write the EOP addr */
3522 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3523 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3524
3525 /* set the VMID assigned */
3526 WREG32(mmCP_HQD_VMID, 0);
3527
3528 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3529 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3530 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3531 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3532 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3533 }
3534 vi_srbm_select(adev, 0, 0, 0, 0);
3535 mutex_unlock(&adev->srbm_mutex);
3536
3537 /* init the queues. Just two for now. */
3538 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3539 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3540
3541 if (ring->mqd_obj == NULL) {
3542 r = amdgpu_bo_create(adev,
3543 sizeof(struct vi_mqd),
3544 PAGE_SIZE, true,
3545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3546 NULL, &ring->mqd_obj);
3547 if (r) {
3548 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3549 return r;
3550 }
3551 }
3552
3553 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3554 if (unlikely(r != 0)) {
3555 gfx_v8_0_cp_compute_fini(adev);
3556 return r;
3557 }
3558 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3559 &mqd_gpu_addr);
3560 if (r) {
3561 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3562 gfx_v8_0_cp_compute_fini(adev);
3563 return r;
3564 }
3565 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3566 if (r) {
3567 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3568 gfx_v8_0_cp_compute_fini(adev);
3569 return r;
3570 }
3571
3572 /* init the mqd struct */
3573 memset(buf, 0, sizeof(struct vi_mqd));
3574
3575 mqd = (struct vi_mqd *)buf;
3576 mqd->header = 0xC0310800;
3577 mqd->compute_pipelinestat_enable = 0x00000001;
3578 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3579 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3580 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3581 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3582 mqd->compute_misc_reserved = 0x00000003;
3583
3584 mutex_lock(&adev->srbm_mutex);
3585 vi_srbm_select(adev, ring->me,
3586 ring->pipe,
3587 ring->queue, 0);
3588
3589 /* disable wptr polling */
3590 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3591 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3592 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3593
3594 mqd->cp_hqd_eop_base_addr_lo =
3595 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3596 mqd->cp_hqd_eop_base_addr_hi =
3597 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3598
3599 /* enable doorbell? */
3600 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3601 if (use_doorbell) {
3602 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3603 } else {
3604 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3605 }
3606 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3607 mqd->cp_hqd_pq_doorbell_control = tmp;
3608
3609 /* disable the queue if it's active */
3610 mqd->cp_hqd_dequeue_request = 0;
3611 mqd->cp_hqd_pq_rptr = 0;
3612 mqd->cp_hqd_pq_wptr= 0;
3613 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3614 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3615 for (j = 0; j < adev->usec_timeout; j++) {
3616 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3617 break;
3618 udelay(1);
3619 }
3620 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3621 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3622 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3623 }
3624
3625 /* set the pointer to the MQD */
3626 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3627 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3628 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3629 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3630
3631 /* set MQD vmid to 0 */
3632 tmp = RREG32(mmCP_MQD_CONTROL);
3633 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3634 WREG32(mmCP_MQD_CONTROL, tmp);
3635 mqd->cp_mqd_control = tmp;
3636
3637 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3638 hqd_gpu_addr = ring->gpu_addr >> 8;
3639 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3640 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3641 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3642 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3643
3644 /* set up the HQD, this is similar to CP_RB0_CNTL */
3645 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3646 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3647 (order_base_2(ring->ring_size / 4) - 1));
3648 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3649 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3650#ifdef __BIG_ENDIAN
3651 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3652#endif
3653 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3655 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3656 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3657 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3658 mqd->cp_hqd_pq_control = tmp;
3659
3660 /* set the wb address wether it's enabled or not */
3661 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3662 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3663 mqd->cp_hqd_pq_rptr_report_addr_hi =
3664 upper_32_bits(wb_gpu_addr) & 0xffff;
3665 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3666 mqd->cp_hqd_pq_rptr_report_addr_lo);
3667 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3668 mqd->cp_hqd_pq_rptr_report_addr_hi);
3669
3670 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3671 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3672 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3673 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3674 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3675 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3676 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3677
3678 /* enable the doorbell if requested */
3679 if (use_doorbell) {
3680 if ((adev->asic_type == CHIP_CARRIZO) ||
3681 (adev->asic_type == CHIP_FIJI) ||
3682 (adev->asic_type == CHIP_STONEY)) {
3683 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3684 AMDGPU_DOORBELL_KIQ << 2);
3685 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3686 AMDGPU_DOORBELL_MEC_RING7 << 2);
3687 }
3688 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3689 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3690 DOORBELL_OFFSET, ring->doorbell_index);
3691 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3692 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3693 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3694 mqd->cp_hqd_pq_doorbell_control = tmp;
3695
3696 } else {
3697 mqd->cp_hqd_pq_doorbell_control = 0;
3698 }
3699 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3700 mqd->cp_hqd_pq_doorbell_control);
3701
3702 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3703 ring->wptr = 0;
3704 mqd->cp_hqd_pq_wptr = ring->wptr;
3705 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3706 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3707
3708 /* set the vmid for the queue */
3709 mqd->cp_hqd_vmid = 0;
3710 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3711
3712 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3713 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3714 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3715 mqd->cp_hqd_persistent_state = tmp;
3716 if (adev->asic_type == CHIP_STONEY) {
3717 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
3718 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
3719 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
3720 }
3721
3722 /* activate the queue */
3723 mqd->cp_hqd_active = 1;
3724 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3725
3726 vi_srbm_select(adev, 0, 0, 0, 0);
3727 mutex_unlock(&adev->srbm_mutex);
3728
3729 amdgpu_bo_kunmap(ring->mqd_obj);
3730 amdgpu_bo_unreserve(ring->mqd_obj);
3731 }
3732
3733 if (use_doorbell) {
3734 tmp = RREG32(mmCP_PQ_STATUS);
3735 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3736 WREG32(mmCP_PQ_STATUS, tmp);
3737 }
3738
3739 gfx_v8_0_cp_compute_enable(adev, true);
3740
3741 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3743
3744 ring->ready = true;
3745 r = amdgpu_ring_test_ring(ring);
3746 if (r)
3747 ring->ready = false;
3748 }
3749
3750 return 0;
3751}
3752
3753static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3754{
3755 int r;
3756
3757 if (!(adev->flags & AMD_IS_APU))
3758 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3759
3760 if (!adev->pp_enabled) {
3761 if (!adev->firmware.smu_load) {
3762 /* legacy firmware loading */
3763 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3764 if (r)
3765 return r;
3766
3767 r = gfx_v8_0_cp_compute_load_microcode(adev);
3768 if (r)
3769 return r;
3770 } else {
3771 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3772 AMDGPU_UCODE_ID_CP_CE);
3773 if (r)
3774 return -EINVAL;
3775
3776 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3777 AMDGPU_UCODE_ID_CP_PFP);
3778 if (r)
3779 return -EINVAL;
3780
3781 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3782 AMDGPU_UCODE_ID_CP_ME);
3783 if (r)
3784 return -EINVAL;
3785
3786 if (adev->asic_type == CHIP_TOPAZ) {
3787 r = gfx_v8_0_cp_compute_load_microcode(adev);
3788 if (r)
3789 return r;
3790 } else {
3791 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3792 AMDGPU_UCODE_ID_CP_MEC1);
3793 if (r)
3794 return -EINVAL;
3795 }
3796 }
3797 }
3798
3799 r = gfx_v8_0_cp_gfx_resume(adev);
3800 if (r)
3801 return r;
3802
3803 r = gfx_v8_0_cp_compute_resume(adev);
3804 if (r)
3805 return r;
3806
3807 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3808
3809 return 0;
3810}
3811
3812static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3813{
3814 gfx_v8_0_cp_gfx_enable(adev, enable);
3815 gfx_v8_0_cp_compute_enable(adev, enable);
3816}
3817
3818static int gfx_v8_0_hw_init(void *handle)
3819{
3820 int r;
3821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3822
3823 gfx_v8_0_init_golden_registers(adev);
3824
3825 gfx_v8_0_gpu_init(adev);
3826
3827 r = gfx_v8_0_rlc_resume(adev);
3828 if (r)
3829 return r;
3830
3831 r = gfx_v8_0_cp_resume(adev);
3832 if (r)
3833 return r;
3834
3835 return r;
3836}
3837
3838static int gfx_v8_0_hw_fini(void *handle)
3839{
3840 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3841
3842 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3843 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3844 gfx_v8_0_cp_enable(adev, false);
3845 gfx_v8_0_rlc_stop(adev);
3846 gfx_v8_0_cp_compute_fini(adev);
3847
3848 return 0;
3849}
3850
3851static int gfx_v8_0_suspend(void *handle)
3852{
3853 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3854
3855 return gfx_v8_0_hw_fini(adev);
3856}
3857
3858static int gfx_v8_0_resume(void *handle)
3859{
3860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3861
3862 return gfx_v8_0_hw_init(adev);
3863}
3864
3865static bool gfx_v8_0_is_idle(void *handle)
3866{
3867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3868
3869 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3870 return false;
3871 else
3872 return true;
3873}
3874
3875static int gfx_v8_0_wait_for_idle(void *handle)
3876{
3877 unsigned i;
3878 u32 tmp;
3879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3880
3881 for (i = 0; i < adev->usec_timeout; i++) {
3882 /* read MC_STATUS */
3883 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3884
3885 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3886 return 0;
3887 udelay(1);
3888 }
3889 return -ETIMEDOUT;
3890}
3891
3892static void gfx_v8_0_print_status(void *handle)
3893{
3894 int i;
3895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3896
3897 dev_info(adev->dev, "GFX 8.x registers\n");
3898 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3899 RREG32(mmGRBM_STATUS));
3900 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3901 RREG32(mmGRBM_STATUS2));
3902 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3903 RREG32(mmGRBM_STATUS_SE0));
3904 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3905 RREG32(mmGRBM_STATUS_SE1));
3906 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3907 RREG32(mmGRBM_STATUS_SE2));
3908 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3909 RREG32(mmGRBM_STATUS_SE3));
3910 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3911 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3912 RREG32(mmCP_STALLED_STAT1));
3913 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3914 RREG32(mmCP_STALLED_STAT2));
3915 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3916 RREG32(mmCP_STALLED_STAT3));
3917 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3918 RREG32(mmCP_CPF_BUSY_STAT));
3919 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3920 RREG32(mmCP_CPF_STALLED_STAT1));
3921 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3922 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3923 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3924 RREG32(mmCP_CPC_STALLED_STAT1));
3925 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3926
3927 for (i = 0; i < 32; i++) {
3928 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3929 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3930 }
3931 for (i = 0; i < 16; i++) {
3932 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3933 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3934 }
3935 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3936 dev_info(adev->dev, " se: %d\n", i);
3937 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3938 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3939 RREG32(mmPA_SC_RASTER_CONFIG));
3940 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3941 RREG32(mmPA_SC_RASTER_CONFIG_1));
3942 }
3943 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3944
3945 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3946 RREG32(mmGB_ADDR_CONFIG));
3947 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3948 RREG32(mmHDP_ADDR_CONFIG));
3949 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3950 RREG32(mmDMIF_ADDR_CALC));
3951
3952 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3953 RREG32(mmCP_MEQ_THRESHOLDS));
3954 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3955 RREG32(mmSX_DEBUG_1));
3956 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3957 RREG32(mmTA_CNTL_AUX));
3958 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3959 RREG32(mmSPI_CONFIG_CNTL));
3960 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3961 RREG32(mmSQ_CONFIG));
3962 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3963 RREG32(mmDB_DEBUG));
3964 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3965 RREG32(mmDB_DEBUG2));
3966 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3967 RREG32(mmDB_DEBUG3));
3968 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3969 RREG32(mmCB_HW_CONTROL));
3970 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3971 RREG32(mmSPI_CONFIG_CNTL_1));
3972 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3973 RREG32(mmPA_SC_FIFO_SIZE));
3974 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3975 RREG32(mmVGT_NUM_INSTANCES));
3976 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3977 RREG32(mmCP_PERFMON_CNTL));
3978 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3979 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3980 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3981 RREG32(mmVGT_CACHE_INVALIDATION));
3982 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3983 RREG32(mmVGT_GS_VERTEX_REUSE));
3984 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3985 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3986 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3987 RREG32(mmPA_CL_ENHANCE));
3988 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3989 RREG32(mmPA_SC_ENHANCE));
3990
3991 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3992 RREG32(mmCP_ME_CNTL));
3993 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3994 RREG32(mmCP_MAX_CONTEXT));
3995 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3996 RREG32(mmCP_ENDIAN_SWAP));
3997 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3998 RREG32(mmCP_DEVICE_ID));
3999
4000 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4001 RREG32(mmCP_SEM_WAIT_TIMER));
4002
4003 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4004 RREG32(mmCP_RB_WPTR_DELAY));
4005 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4006 RREG32(mmCP_RB_VMID));
4007 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4008 RREG32(mmCP_RB0_CNTL));
4009 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4010 RREG32(mmCP_RB0_WPTR));
4011 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4012 RREG32(mmCP_RB0_RPTR_ADDR));
4013 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4014 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4015 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4016 RREG32(mmCP_RB0_CNTL));
4017 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4018 RREG32(mmCP_RB0_BASE));
4019 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4020 RREG32(mmCP_RB0_BASE_HI));
4021 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4022 RREG32(mmCP_MEC_CNTL));
4023 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4024 RREG32(mmCP_CPF_DEBUG));
4025
4026 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4027 RREG32(mmSCRATCH_ADDR));
4028 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4029 RREG32(mmSCRATCH_UMSK));
4030
4031 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4032 RREG32(mmCP_INT_CNTL_RING0));
4033 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4034 RREG32(mmRLC_LB_CNTL));
4035 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4036 RREG32(mmRLC_CNTL));
4037 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4038 RREG32(mmRLC_CGCG_CGLS_CTRL));
4039 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4040 RREG32(mmRLC_LB_CNTR_INIT));
4041 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4042 RREG32(mmRLC_LB_CNTR_MAX));
4043 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4044 RREG32(mmRLC_LB_INIT_CU_MASK));
4045 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4046 RREG32(mmRLC_LB_PARAMS));
4047 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4048 RREG32(mmRLC_LB_CNTL));
4049 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4050 RREG32(mmRLC_MC_CNTL));
4051 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4052 RREG32(mmRLC_UCODE_CNTL));
4053
4054 mutex_lock(&adev->srbm_mutex);
4055 for (i = 0; i < 16; i++) {
4056 vi_srbm_select(adev, 0, 0, 0, i);
4057 dev_info(adev->dev, " VM %d:\n", i);
4058 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4059 RREG32(mmSH_MEM_CONFIG));
4060 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4061 RREG32(mmSH_MEM_APE1_BASE));
4062 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
4063 RREG32(mmSH_MEM_APE1_LIMIT));
4064 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4065 RREG32(mmSH_MEM_BASES));
4066 }
4067 vi_srbm_select(adev, 0, 0, 0, 0);
4068 mutex_unlock(&adev->srbm_mutex);
4069}
4070
4071static int gfx_v8_0_soft_reset(void *handle)
4072{
4073 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4074 u32 tmp;
4075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4076
4077 /* GRBM_STATUS */
4078 tmp = RREG32(mmGRBM_STATUS);
4079 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4080 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4081 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4082 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4083 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4084 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4085 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4086 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4087 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4088 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4089 }
4090
4091 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4093 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4094 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4095 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4096 }
4097
4098 /* GRBM_STATUS2 */
4099 tmp = RREG32(mmGRBM_STATUS2);
4100 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4101 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4102 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4103
4104 /* SRBM_STATUS */
4105 tmp = RREG32(mmSRBM_STATUS);
4106 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4107 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4108 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4109
4110 if (grbm_soft_reset || srbm_soft_reset) {
4111 gfx_v8_0_print_status((void *)adev);
4112 /* stop the rlc */
4113 gfx_v8_0_rlc_stop(adev);
4114
4115 /* Disable GFX parsing/prefetching */
4116 gfx_v8_0_cp_gfx_enable(adev, false);
4117
4118 /* Disable MEC parsing/prefetching */
4119 gfx_v8_0_cp_compute_enable(adev, false);
4120
4121 if (grbm_soft_reset || srbm_soft_reset) {
4122 tmp = RREG32(mmGMCON_DEBUG);
4123 tmp = REG_SET_FIELD(tmp,
4124 GMCON_DEBUG, GFX_STALL, 1);
4125 tmp = REG_SET_FIELD(tmp,
4126 GMCON_DEBUG, GFX_CLEAR, 1);
4127 WREG32(mmGMCON_DEBUG, tmp);
4128
4129 udelay(50);
4130 }
4131
4132 if (grbm_soft_reset) {
4133 tmp = RREG32(mmGRBM_SOFT_RESET);
4134 tmp |= grbm_soft_reset;
4135 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4136 WREG32(mmGRBM_SOFT_RESET, tmp);
4137 tmp = RREG32(mmGRBM_SOFT_RESET);
4138
4139 udelay(50);
4140
4141 tmp &= ~grbm_soft_reset;
4142 WREG32(mmGRBM_SOFT_RESET, tmp);
4143 tmp = RREG32(mmGRBM_SOFT_RESET);
4144 }
4145
4146 if (srbm_soft_reset) {
4147 tmp = RREG32(mmSRBM_SOFT_RESET);
4148 tmp |= srbm_soft_reset;
4149 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4150 WREG32(mmSRBM_SOFT_RESET, tmp);
4151 tmp = RREG32(mmSRBM_SOFT_RESET);
4152
4153 udelay(50);
4154
4155 tmp &= ~srbm_soft_reset;
4156 WREG32(mmSRBM_SOFT_RESET, tmp);
4157 tmp = RREG32(mmSRBM_SOFT_RESET);
4158 }
4159
4160 if (grbm_soft_reset || srbm_soft_reset) {
4161 tmp = RREG32(mmGMCON_DEBUG);
4162 tmp = REG_SET_FIELD(tmp,
4163 GMCON_DEBUG, GFX_STALL, 0);
4164 tmp = REG_SET_FIELD(tmp,
4165 GMCON_DEBUG, GFX_CLEAR, 0);
4166 WREG32(mmGMCON_DEBUG, tmp);
4167 }
4168
4169 /* Wait a little for things to settle down */
4170 udelay(50);
4171 gfx_v8_0_print_status((void *)adev);
4172 }
4173 return 0;
4174}
4175
4176/**
4177 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4178 *
4179 * @adev: amdgpu_device pointer
4180 *
4181 * Fetches a GPU clock counter snapshot.
4182 * Returns the 64 bit clock counter snapshot.
4183 */
4184uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4185{
4186 uint64_t clock;
4187
4188 mutex_lock(&adev->gfx.gpu_clock_mutex);
4189 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4190 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4191 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4192 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4193 return clock;
4194}
4195
4196static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4197 uint32_t vmid,
4198 uint32_t gds_base, uint32_t gds_size,
4199 uint32_t gws_base, uint32_t gws_size,
4200 uint32_t oa_base, uint32_t oa_size)
4201{
4202 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4203 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4204
4205 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4206 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4207
4208 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4209 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4210
4211 /* GDS Base */
4212 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4213 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4214 WRITE_DATA_DST_SEL(0)));
4215 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4216 amdgpu_ring_write(ring, 0);
4217 amdgpu_ring_write(ring, gds_base);
4218
4219 /* GDS Size */
4220 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4221 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4222 WRITE_DATA_DST_SEL(0)));
4223 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4224 amdgpu_ring_write(ring, 0);
4225 amdgpu_ring_write(ring, gds_size);
4226
4227 /* GWS */
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4229 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4230 WRITE_DATA_DST_SEL(0)));
4231 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4232 amdgpu_ring_write(ring, 0);
4233 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4234
4235 /* OA */
4236 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4237 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4238 WRITE_DATA_DST_SEL(0)));
4239 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4240 amdgpu_ring_write(ring, 0);
4241 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4242}
4243
4244static int gfx_v8_0_early_init(void *handle)
4245{
4246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4247
4248 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
4249 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
4250 gfx_v8_0_set_ring_funcs(adev);
4251 gfx_v8_0_set_irq_funcs(adev);
4252 gfx_v8_0_set_gds_init(adev);
4253
4254 return 0;
4255}
4256
4257static int gfx_v8_0_late_init(void *handle)
4258{
4259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4260 int r;
4261
4262 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4263 if (r)
4264 return r;
4265
4266 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4267 if (r)
4268 return r;
4269
4270 /* requires IBs so do in late init after IB pool is initialized */
4271 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
4272 if (r)
4273 return r;
4274
4275 return 0;
4276}
4277
4278static int gfx_v8_0_set_powergating_state(void *handle,
4279 enum amd_powergating_state state)
4280{
4281 return 0;
4282}
4283
4284static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
4285 uint32_t reg_addr, uint32_t cmd)
4286{
4287 uint32_t data;
4288
4289 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4290
4291 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4292 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4293
4294 data = RREG32(mmRLC_SERDES_WR_CTRL);
4295 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
4296 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
4297 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
4298 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
4299 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
4300 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
4301 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
4302 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
4303 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
4304 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
4305 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
4306 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
4307 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
4308 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
4309 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
4310
4311 WREG32(mmRLC_SERDES_WR_CTRL, data);
4312}
4313
4314static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4315 bool enable)
4316{
4317 uint32_t temp, data;
4318
4319 /* It is disabled by HW by default */
4320 if (enable) {
4321 /* 1 - RLC memory Light sleep */
4322 temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
4323 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4324 if (temp != data)
4325 WREG32(mmRLC_MEM_SLP_CNTL, data);
4326
4327 /* 2 - CP memory Light sleep */
4328 temp = data = RREG32(mmCP_MEM_SLP_CNTL);
4329 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4330 if (temp != data)
4331 WREG32(mmCP_MEM_SLP_CNTL, data);
4332
4333 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
4334 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4335 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
4336 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
4337 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
4338 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
4339
4340 if (temp != data)
4341 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4342
4343 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4344 gfx_v8_0_wait_for_rlc_serdes(adev);
4345
4346 /* 5 - clear mgcg override */
4347 fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
4348
4349 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
4350 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
4351 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
4352 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4353 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4354 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4355 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4356 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
4357 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
4358 if (temp != data)
4359 WREG32(mmCGTS_SM_CTRL_REG, data);
4360 udelay(50);
4361
4362 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4363 gfx_v8_0_wait_for_rlc_serdes(adev);
4364 } else {
4365 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
4366 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4367 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
4368 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
4369 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
4370 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
4371 if (temp != data)
4372 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4373
4374 /* 2 - disable MGLS in RLC */
4375 data = RREG32(mmRLC_MEM_SLP_CNTL);
4376 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4377 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4378 WREG32(mmRLC_MEM_SLP_CNTL, data);
4379 }
4380
4381 /* 3 - disable MGLS in CP */
4382 data = RREG32(mmCP_MEM_SLP_CNTL);
4383 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4384 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4385 WREG32(mmCP_MEM_SLP_CNTL, data);
4386 }
4387
4388 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
4389 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
4390 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
4391 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
4392 if (temp != data)
4393 WREG32(mmCGTS_SM_CTRL_REG, data);
4394
4395 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4396 gfx_v8_0_wait_for_rlc_serdes(adev);
4397
4398 /* 6 - set mgcg override */
4399 fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
4400
4401 udelay(50);
4402
4403 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4404 gfx_v8_0_wait_for_rlc_serdes(adev);
4405 }
4406}
4407
4408static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4409 bool enable)
4410{
4411 uint32_t temp, temp1, data, data1;
4412
4413 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4414
4415 if (enable) {
4416 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
4417 * Cmp_busy/GFX_Idle interrupts
4418 */
4419 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4420
4421 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4422 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
4423 if (temp1 != data1)
4424 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4425
4426 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4427 gfx_v8_0_wait_for_rlc_serdes(adev);
4428
4429 /* 3 - clear cgcg override */
4430 fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
4431
4432 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4433 gfx_v8_0_wait_for_rlc_serdes(adev);
4434
4435 /* 4 - write cmd to set CGLS */
4436 fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
4437
4438 /* 5 - enable cgcg */
4439 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4440
4441 /* enable cgls*/
4442 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4443
4444 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4445 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
4446
4447 if (temp1 != data1)
4448 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4449
4450 if (temp != data)
4451 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4452 } else {
4453 /* disable cntx_empty_int_enable & GFX Idle interrupt */
4454 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4455
4456 /* TEST CGCG */
4457 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4458 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
4459 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
4460 if (temp1 != data1)
4461 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4462
4463 /* read gfx register to wake up cgcg */
4464 RREG32(mmCB_CGTT_SCLK_CTRL);
4465 RREG32(mmCB_CGTT_SCLK_CTRL);
4466 RREG32(mmCB_CGTT_SCLK_CTRL);
4467 RREG32(mmCB_CGTT_SCLK_CTRL);
4468
4469 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4470 gfx_v8_0_wait_for_rlc_serdes(adev);
4471
4472 /* write cmd to Set CGCG Overrride */
4473 fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
4474
4475 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4476 gfx_v8_0_wait_for_rlc_serdes(adev);
4477
4478 /* write cmd to Clear CGLS */
4479 fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
4480
4481 /* disable cgcg, cgls should be disabled too. */
4482 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
4483 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4484 if (temp != data)
4485 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4486 }
4487}
4488static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
4489 bool enable)
4490{
4491 if (enable) {
4492 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
4493 * === MGCG + MGLS + TS(CG/LS) ===
4494 */
4495 fiji_update_medium_grain_clock_gating(adev, enable);
4496 fiji_update_coarse_grain_clock_gating(adev, enable);
4497 } else {
4498 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
4499 * === CGCG + CGLS ===
4500 */
4501 fiji_update_coarse_grain_clock_gating(adev, enable);
4502 fiji_update_medium_grain_clock_gating(adev, enable);
4503 }
4504 return 0;
4505}
4506
4507static int gfx_v8_0_set_clockgating_state(void *handle,
4508 enum amd_clockgating_state state)
4509{
4510 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4511
4512 switch (adev->asic_type) {
4513 case CHIP_FIJI:
4514 fiji_update_gfx_clock_gating(adev,
4515 state == AMD_CG_STATE_GATE ? true : false);
4516 break;
4517 default:
4518 break;
4519 }
4520 return 0;
4521}
4522
4523static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4524{
4525 u32 rptr;
4526
4527 rptr = ring->adev->wb.wb[ring->rptr_offs];
4528
4529 return rptr;
4530}
4531
4532static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4533{
4534 struct amdgpu_device *adev = ring->adev;
4535 u32 wptr;
4536
4537 if (ring->use_doorbell)
4538 /* XXX check if swapping is necessary on BE */
4539 wptr = ring->adev->wb.wb[ring->wptr_offs];
4540 else
4541 wptr = RREG32(mmCP_RB0_WPTR);
4542
4543 return wptr;
4544}
4545
4546static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4547{
4548 struct amdgpu_device *adev = ring->adev;
4549
4550 if (ring->use_doorbell) {
4551 /* XXX check if swapping is necessary on BE */
4552 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4553 WDOORBELL32(ring->doorbell_index, ring->wptr);
4554 } else {
4555 WREG32(mmCP_RB0_WPTR, ring->wptr);
4556 (void)RREG32(mmCP_RB0_WPTR);
4557 }
4558}
4559
4560static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4561{
4562 u32 ref_and_mask, reg_mem_engine;
4563
4564 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
4565 switch (ring->me) {
4566 case 1:
4567 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
4568 break;
4569 case 2:
4570 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
4571 break;
4572 default:
4573 return;
4574 }
4575 reg_mem_engine = 0;
4576 } else {
4577 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
4578 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
4579 }
4580
4581 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4582 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
4583 WAIT_REG_MEM_FUNCTION(3) | /* == */
4584 reg_mem_engine));
4585 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
4586 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
4587 amdgpu_ring_write(ring, ref_and_mask);
4588 amdgpu_ring_write(ring, ref_and_mask);
4589 amdgpu_ring_write(ring, 0x20); /* poll interval */
4590}
4591
4592static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
4593{
4594 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4595 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4596 WRITE_DATA_DST_SEL(0) |
4597 WR_CONFIRM));
4598 amdgpu_ring_write(ring, mmHDP_DEBUG0);
4599 amdgpu_ring_write(ring, 0);
4600 amdgpu_ring_write(ring, 1);
4601
4602}
4603
4604static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4605 struct amdgpu_ib *ib)
4606{
4607 bool need_ctx_switch = ring->current_ctx != ib->ctx;
4608 u32 header, control = 0;
4609 u32 next_rptr = ring->wptr + 5;
4610
4611 /* drop the CE preamble IB for the same context */
4612 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
4613 return;
4614
4615 if (need_ctx_switch)
4616 next_rptr += 2;
4617
4618 next_rptr += 4;
4619 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4620 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4621 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4622 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4623 amdgpu_ring_write(ring, next_rptr);
4624
4625 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
4626 if (need_ctx_switch) {
4627 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4628 amdgpu_ring_write(ring, 0);
4629 }
4630
4631 if (ib->flags & AMDGPU_IB_FLAG_CE)
4632 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4633 else
4634 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4635
4636 control |= ib->length_dw | (ib->vm_id << 24);
4637
4638 amdgpu_ring_write(ring, header);
4639 amdgpu_ring_write(ring,
4640#ifdef __BIG_ENDIAN
4641 (2 << 0) |
4642#endif
4643 (ib->gpu_addr & 0xFFFFFFFC));
4644 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4645 amdgpu_ring_write(ring, control);
4646}
4647
4648static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4649 struct amdgpu_ib *ib)
4650{
4651 u32 header, control = 0;
4652 u32 next_rptr = ring->wptr + 5;
4653
4654 control |= INDIRECT_BUFFER_VALID;
4655
4656 next_rptr += 4;
4657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4658 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4659 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4660 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4661 amdgpu_ring_write(ring, next_rptr);
4662
4663 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4664
4665 control |= ib->length_dw | (ib->vm_id << 24);
4666
4667 amdgpu_ring_write(ring, header);
4668 amdgpu_ring_write(ring,
4669#ifdef __BIG_ENDIAN
4670 (2 << 0) |
4671#endif
4672 (ib->gpu_addr & 0xFFFFFFFC));
4673 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4674 amdgpu_ring_write(ring, control);
4675}
4676
4677static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
4678 u64 seq, unsigned flags)
4679{
4680 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4681 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4682
4683 /* EVENT_WRITE_EOP - flush caches, send int */
4684 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
4685 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4686 EOP_TC_ACTION_EN |
4687 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4688 EVENT_INDEX(5)));
4689 amdgpu_ring_write(ring, addr & 0xfffffffc);
4690 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
4691 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4692 amdgpu_ring_write(ring, lower_32_bits(seq));
4693 amdgpu_ring_write(ring, upper_32_bits(seq));
4694
4695}
4696
4697static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4698{
4699 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4700 uint32_t seq = ring->fence_drv.sync_seq;
4701 uint64_t addr = ring->fence_drv.gpu_addr;
4702
4703 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4704 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4705 WAIT_REG_MEM_FUNCTION(3) | /* equal */
4706 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
4707 amdgpu_ring_write(ring, addr & 0xfffffffc);
4708 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4709 amdgpu_ring_write(ring, seq);
4710 amdgpu_ring_write(ring, 0xffffffff);
4711 amdgpu_ring_write(ring, 4); /* poll interval */
4712
4713 if (usepfp) {
4714 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4715 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4716 amdgpu_ring_write(ring, 0);
4717 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4718 amdgpu_ring_write(ring, 0);
4719 }
4720}
4721
4722static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4723 unsigned vm_id, uint64_t pd_addr)
4724{
4725 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4726
4727 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4728 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4729 WRITE_DATA_DST_SEL(0)) |
4730 WR_CONFIRM);
4731 if (vm_id < 8) {
4732 amdgpu_ring_write(ring,
4733 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4734 } else {
4735 amdgpu_ring_write(ring,
4736 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4737 }
4738 amdgpu_ring_write(ring, 0);
4739 amdgpu_ring_write(ring, pd_addr >> 12);
4740
4741 /* bits 0-15 are the VM contexts0-15 */
4742 /* invalidate the cache */
4743 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4744 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4745 WRITE_DATA_DST_SEL(0)));
4746 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4747 amdgpu_ring_write(ring, 0);
4748 amdgpu_ring_write(ring, 1 << vm_id);
4749
4750 /* wait for the invalidate to complete */
4751 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4752 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4753 WAIT_REG_MEM_FUNCTION(0) | /* always */
4754 WAIT_REG_MEM_ENGINE(0))); /* me */
4755 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4756 amdgpu_ring_write(ring, 0);
4757 amdgpu_ring_write(ring, 0); /* ref */
4758 amdgpu_ring_write(ring, 0); /* mask */
4759 amdgpu_ring_write(ring, 0x20); /* poll interval */
4760
4761 /* compute doesn't have PFP */
4762 if (usepfp) {
4763 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4764 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4765 amdgpu_ring_write(ring, 0x0);
4766 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4767 amdgpu_ring_write(ring, 0);
4768 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4769 amdgpu_ring_write(ring, 0);
4770 }
4771}
4772
4773static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4774{
4775 return ring->adev->wb.wb[ring->rptr_offs];
4776}
4777
4778static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4779{
4780 return ring->adev->wb.wb[ring->wptr_offs];
4781}
4782
4783static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4784{
4785 struct amdgpu_device *adev = ring->adev;
4786
4787 /* XXX check if swapping is necessary on BE */
4788 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4789 WDOORBELL32(ring->doorbell_index, ring->wptr);
4790}
4791
4792static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4793 u64 addr, u64 seq,
4794 unsigned flags)
4795{
4796 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4797 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4798
4799 /* RELEASE_MEM - flush caches, send int */
4800 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4801 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4802 EOP_TC_ACTION_EN |
4803 EOP_TC_WB_ACTION_EN |
4804 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4805 EVENT_INDEX(5)));
4806 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4807 amdgpu_ring_write(ring, addr & 0xfffffffc);
4808 amdgpu_ring_write(ring, upper_32_bits(addr));
4809 amdgpu_ring_write(ring, lower_32_bits(seq));
4810 amdgpu_ring_write(ring, upper_32_bits(seq));
4811}
4812
4813static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4814 enum amdgpu_interrupt_state state)
4815{
4816 u32 cp_int_cntl;
4817
4818 switch (state) {
4819 case AMDGPU_IRQ_STATE_DISABLE:
4820 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4821 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4822 TIME_STAMP_INT_ENABLE, 0);
4823 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4824 break;
4825 case AMDGPU_IRQ_STATE_ENABLE:
4826 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4827 cp_int_cntl =
4828 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4829 TIME_STAMP_INT_ENABLE, 1);
4830 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4831 break;
4832 default:
4833 break;
4834 }
4835}
4836
4837static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4838 int me, int pipe,
4839 enum amdgpu_interrupt_state state)
4840{
4841 u32 mec_int_cntl, mec_int_cntl_reg;
4842
4843 /*
4844 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4845 * handles the setting of interrupts for this specific pipe. All other
4846 * pipes' interrupts are set by amdkfd.
4847 */
4848
4849 if (me == 1) {
4850 switch (pipe) {
4851 case 0:
4852 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4853 break;
4854 default:
4855 DRM_DEBUG("invalid pipe %d\n", pipe);
4856 return;
4857 }
4858 } else {
4859 DRM_DEBUG("invalid me %d\n", me);
4860 return;
4861 }
4862
4863 switch (state) {
4864 case AMDGPU_IRQ_STATE_DISABLE:
4865 mec_int_cntl = RREG32(mec_int_cntl_reg);
4866 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4867 TIME_STAMP_INT_ENABLE, 0);
4868 WREG32(mec_int_cntl_reg, mec_int_cntl);
4869 break;
4870 case AMDGPU_IRQ_STATE_ENABLE:
4871 mec_int_cntl = RREG32(mec_int_cntl_reg);
4872 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4873 TIME_STAMP_INT_ENABLE, 1);
4874 WREG32(mec_int_cntl_reg, mec_int_cntl);
4875 break;
4876 default:
4877 break;
4878 }
4879}
4880
4881static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4882 struct amdgpu_irq_src *source,
4883 unsigned type,
4884 enum amdgpu_interrupt_state state)
4885{
4886 u32 cp_int_cntl;
4887
4888 switch (state) {
4889 case AMDGPU_IRQ_STATE_DISABLE:
4890 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4891 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4892 PRIV_REG_INT_ENABLE, 0);
4893 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4894 break;
4895 case AMDGPU_IRQ_STATE_ENABLE:
4896 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4897 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4898 PRIV_REG_INT_ENABLE, 1);
4899 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4900 break;
4901 default:
4902 break;
4903 }
4904
4905 return 0;
4906}
4907
4908static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4909 struct amdgpu_irq_src *source,
4910 unsigned type,
4911 enum amdgpu_interrupt_state state)
4912{
4913 u32 cp_int_cntl;
4914
4915 switch (state) {
4916 case AMDGPU_IRQ_STATE_DISABLE:
4917 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4918 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4919 PRIV_INSTR_INT_ENABLE, 0);
4920 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4921 break;
4922 case AMDGPU_IRQ_STATE_ENABLE:
4923 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4924 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4925 PRIV_INSTR_INT_ENABLE, 1);
4926 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4927 break;
4928 default:
4929 break;
4930 }
4931
4932 return 0;
4933}
4934
4935static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4936 struct amdgpu_irq_src *src,
4937 unsigned type,
4938 enum amdgpu_interrupt_state state)
4939{
4940 switch (type) {
4941 case AMDGPU_CP_IRQ_GFX_EOP:
4942 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4943 break;
4944 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4945 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4946 break;
4947 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4948 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4949 break;
4950 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4951 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4952 break;
4953 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4954 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4955 break;
4956 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4957 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4958 break;
4959 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4960 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4961 break;
4962 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4963 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4964 break;
4965 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4966 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4967 break;
4968 default:
4969 break;
4970 }
4971 return 0;
4972}
4973
4974static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4975 struct amdgpu_irq_src *source,
4976 struct amdgpu_iv_entry *entry)
4977{
4978 int i;
4979 u8 me_id, pipe_id, queue_id;
4980 struct amdgpu_ring *ring;
4981
4982 DRM_DEBUG("IH: CP EOP\n");
4983 me_id = (entry->ring_id & 0x0c) >> 2;
4984 pipe_id = (entry->ring_id & 0x03) >> 0;
4985 queue_id = (entry->ring_id & 0x70) >> 4;
4986
4987 switch (me_id) {
4988 case 0:
4989 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4990 break;
4991 case 1:
4992 case 2:
4993 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4994 ring = &adev->gfx.compute_ring[i];
4995 /* Per-queue interrupt is supported for MEC starting from VI.
4996 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4997 */
4998 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4999 amdgpu_fence_process(ring);
5000 }
5001 break;
5002 }
5003 return 0;
5004}
5005
5006static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
5007 struct amdgpu_irq_src *source,
5008 struct amdgpu_iv_entry *entry)
5009{
5010 DRM_ERROR("Illegal register access in command stream\n");
5011 schedule_work(&adev->reset_work);
5012 return 0;
5013}
5014
5015static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
5016 struct amdgpu_irq_src *source,
5017 struct amdgpu_iv_entry *entry)
5018{
5019 DRM_ERROR("Illegal instruction in command stream\n");
5020 schedule_work(&adev->reset_work);
5021 return 0;
5022}
5023
5024const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
5025 .early_init = gfx_v8_0_early_init,
5026 .late_init = gfx_v8_0_late_init,
5027 .sw_init = gfx_v8_0_sw_init,
5028 .sw_fini = gfx_v8_0_sw_fini,
5029 .hw_init = gfx_v8_0_hw_init,
5030 .hw_fini = gfx_v8_0_hw_fini,
5031 .suspend = gfx_v8_0_suspend,
5032 .resume = gfx_v8_0_resume,
5033 .is_idle = gfx_v8_0_is_idle,
5034 .wait_for_idle = gfx_v8_0_wait_for_idle,
5035 .soft_reset = gfx_v8_0_soft_reset,
5036 .print_status = gfx_v8_0_print_status,
5037 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
5038 .set_powergating_state = gfx_v8_0_set_powergating_state,
5039};
5040
5041static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
5042 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
5043 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
5044 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
5045 .parse_cs = NULL,
5046 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
5047 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
5048 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
5049 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
5050 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
5051 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
5052 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
5053 .test_ring = gfx_v8_0_ring_test_ring,
5054 .test_ib = gfx_v8_0_ring_test_ib,
5055 .insert_nop = amdgpu_ring_insert_nop,
5056 .pad_ib = amdgpu_ring_generic_pad_ib,
5057};
5058
5059static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
5060 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
5061 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
5062 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
5063 .parse_cs = NULL,
5064 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
5065 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
5066 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
5067 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
5068 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
5069 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
5070 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
5071 .test_ring = gfx_v8_0_ring_test_ring,
5072 .test_ib = gfx_v8_0_ring_test_ib,
5073 .insert_nop = amdgpu_ring_insert_nop,
5074 .pad_ib = amdgpu_ring_generic_pad_ib,
5075};
5076
5077static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
5078{
5079 int i;
5080
5081 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5082 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
5083
5084 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5085 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
5086}
5087
5088static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
5089 .set = gfx_v8_0_set_eop_interrupt_state,
5090 .process = gfx_v8_0_eop_irq,
5091};
5092
5093static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
5094 .set = gfx_v8_0_set_priv_reg_fault_state,
5095 .process = gfx_v8_0_priv_reg_irq,
5096};
5097
5098static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
5099 .set = gfx_v8_0_set_priv_inst_fault_state,
5100 .process = gfx_v8_0_priv_inst_irq,
5101};
5102
5103static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
5104{
5105 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5106 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
5107
5108 adev->gfx.priv_reg_irq.num_types = 1;
5109 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
5110
5111 adev->gfx.priv_inst_irq.num_types = 1;
5112 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
5113}
5114
5115static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
5116{
5117 /* init asci gds info */
5118 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5119 adev->gds.gws.total_size = 64;
5120 adev->gds.oa.total_size = 16;
5121
5122 if (adev->gds.mem.total_size == 64 * 1024) {
5123 adev->gds.mem.gfx_partition_size = 4096;
5124 adev->gds.mem.cs_partition_size = 4096;
5125
5126 adev->gds.gws.gfx_partition_size = 4;
5127 adev->gds.gws.cs_partition_size = 4;
5128
5129 adev->gds.oa.gfx_partition_size = 4;
5130 adev->gds.oa.cs_partition_size = 1;
5131 } else {
5132 adev->gds.mem.gfx_partition_size = 1024;
5133 adev->gds.mem.cs_partition_size = 1024;
5134
5135 adev->gds.gws.gfx_partition_size = 16;
5136 adev->gds.gws.cs_partition_size = 16;
5137
5138 adev->gds.oa.gfx_partition_size = 4;
5139 adev->gds.oa.cs_partition_size = 4;
5140 }
5141}
5142
5143static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
5144{
5145 u32 data, mask;
5146
5147 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
5148 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
5149
5150 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
5151 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
5152
5153 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
5154
5155 return (~data) & mask;
5156}
5157
5158int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
5159 struct amdgpu_cu_info *cu_info)
5160{
5161 int i, j, k, counter, active_cu_number = 0;
5162 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5163
5164 if (!adev || !cu_info)
5165 return -EINVAL;
5166
5167 memset(cu_info, 0, sizeof(*cu_info));
5168
5169 mutex_lock(&adev->grbm_idx_mutex);
5170 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5171 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5172 mask = 1;
5173 ao_bitmap = 0;
5174 counter = 0;
5175 gfx_v8_0_select_se_sh(adev, i, j);
5176 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
5177 cu_info->bitmap[i][j] = bitmap;
5178
5179 for (k = 0; k < 16; k ++) {
5180 if (bitmap & mask) {
5181 if (counter < 2)
5182 ao_bitmap |= mask;
5183 counter ++;
5184 }
5185 mask <<= 1;
5186 }
5187 active_cu_number += counter;
5188 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5189 }
5190 }
5191 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5192 mutex_unlock(&adev->grbm_idx_mutex);
5193
5194 cu_info->number = active_cu_number;
5195 cu_info->ao_cu_mask = ao_cu_mask;
5196
5197 return 0;
5198}