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1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "mpc8641si-pre.dtsi"
13
14/ {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x40000000>; // 1G at 0x0
21 };
22
23 lbc: localbus@ffe05000 {
24 reg = <0xffe05000 0x1000>;
25
26 ranges = <0 0 0xef800000 0x00800000
27 2 0 0xffdf8000 0x00008000
28 3 0 0xffdf0000 0x00008000>;
29
30 flash@0,0 {
31 compatible = "cfi-flash";
32 reg = <0 0 0x00800000>;
33 bank-width = <2>;
34 device-width = <2>;
35 #address-cells = <1>;
36 #size-cells = <1>;
37 partition@0 {
38 label = "kernel";
39 reg = <0x00000000 0x00300000>;
40 };
41 partition@300000 {
42 label = "firmware b";
43 reg = <0x00300000 0x00100000>;
44 read-only;
45 };
46 partition@400000 {
47 label = "fs";
48 reg = <0x00400000 0x00300000>;
49 };
50 partition@700000 {
51 label = "firmware a";
52 reg = <0x00700000 0x00100000>;
53 read-only;
54 };
55 };
56 };
57
58 soc: soc8641@ffe00000 {
59 ranges = <0x00000000 0xffe00000 0x00100000>;
60
61 enet0: ethernet@24000 {
62 tbi-handle = <&tbi0>;
63 phy-handle = <&phy0>;
64 phy-connection-type = "rgmii-id";
65 };
66
67 mdio@24520 {
68 phy0: ethernet-phy@0 {
69 interrupts = <10 1 0 0>;
70 reg = <0>;
71 };
72 phy1: ethernet-phy@1 {
73 interrupts = <10 1 0 0>;
74 reg = <1>;
75 };
76 phy2: ethernet-phy@2 {
77 interrupts = <10 1 0 0>;
78 reg = <2>;
79 };
80 phy3: ethernet-phy@3 {
81 interrupts = <10 1 0 0>;
82 reg = <3>;
83 };
84 tbi0: tbi-phy@11 {
85 reg = <0x11>;
86 device_type = "tbi-phy";
87 };
88 };
89
90 enet1: ethernet@25000 {
91 tbi-handle = <&tbi1>;
92 phy-handle = <&phy1>;
93 phy-connection-type = "rgmii-id";
94 };
95
96 mdio@25520 {
97 tbi1: tbi-phy@11 {
98 reg = <0x11>;
99 device_type = "tbi-phy";
100 };
101 };
102
103 enet2: ethernet@26000 {
104 tbi-handle = <&tbi2>;
105 phy-handle = <&phy2>;
106 phy-connection-type = "rgmii-id";
107 };
108
109 mdio@26520 {
110 tbi2: tbi-phy@11 {
111 reg = <0x11>;
112 device_type = "tbi-phy";
113 };
114 };
115
116 enet3: ethernet@27000 {
117 tbi-handle = <&tbi3>;
118 phy-handle = <&phy3>;
119 phy-connection-type = "rgmii-id";
120 };
121
122 mdio@27520 {
123 tbi3: tbi-phy@11 {
124 reg = <0x11>;
125 device_type = "tbi-phy";
126 };
127 };
128
129 rmu: rmu@d3000 {
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "fsl,srio-rmu";
133 reg = <0xd3000 0x500>;
134 ranges = <0x0 0xd3000 0x500>;
135
136 message-unit@0 {
137 compatible = "fsl,srio-msg-unit";
138 reg = <0x0 0x100>;
139 interrupts = <
140 53 2 0 0 /* msg1_tx_irq */
141 54 2 0 0>;/* msg1_rx_irq */
142 };
143 message-unit@100 {
144 compatible = "fsl,srio-msg-unit";
145 reg = <0x100 0x100>;
146 interrupts = <
147 55 2 0 0 /* msg2_tx_irq */
148 56 2 0 0>;/* msg2_rx_irq */
149 };
150 doorbell-unit@400 {
151 compatible = "fsl,srio-dbell-unit";
152 reg = <0x400 0x80>;
153 interrupts = <
154 49 2 0 0 /* bell_outb_irq */
155 50 2 0 0>;/* bell_inb_irq */
156 };
157 port-write-unit@4e0 {
158 compatible = "fsl,srio-port-write-unit";
159 reg = <0x4e0 0x20>;
160 interrupts = <48 2 0 0>;
161 };
162 };
163 };
164
165 pci0: pcie@ffe08000 {
166 reg = <0xffe08000 0x1000>;
167 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
168 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
169 interrupt-map-mask = <0xff00 0 0 7>;
170 interrupt-map = <
171 /* IDSEL 0x11 func 0 - PCI slot 1 */
172 0x8800 0 0 1 &mpic 2 1
173 0x8800 0 0 2 &mpic 3 1
174 0x8800 0 0 3 &mpic 4 1
175 0x8800 0 0 4 &mpic 1 1
176
177 /* IDSEL 0x11 func 1 - PCI slot 1 */
178 0x8900 0 0 1 &mpic 2 1
179 0x8900 0 0 2 &mpic 3 1
180 0x8900 0 0 3 &mpic 4 1
181 0x8900 0 0 4 &mpic 1 1
182
183 /* IDSEL 0x11 func 2 - PCI slot 1 */
184 0x8a00 0 0 1 &mpic 2 1
185 0x8a00 0 0 2 &mpic 3 1
186 0x8a00 0 0 3 &mpic 4 1
187 0x8a00 0 0 4 &mpic 1 1
188
189 /* IDSEL 0x11 func 3 - PCI slot 1 */
190 0x8b00 0 0 1 &mpic 2 1
191 0x8b00 0 0 2 &mpic 3 1
192 0x8b00 0 0 3 &mpic 4 1
193 0x8b00 0 0 4 &mpic 1 1
194
195 /* IDSEL 0x11 func 4 - PCI slot 1 */
196 0x8c00 0 0 1 &mpic 2 1
197 0x8c00 0 0 2 &mpic 3 1
198 0x8c00 0 0 3 &mpic 4 1
199 0x8c00 0 0 4 &mpic 1 1
200
201 /* IDSEL 0x11 func 5 - PCI slot 1 */
202 0x8d00 0 0 1 &mpic 2 1
203 0x8d00 0 0 2 &mpic 3 1
204 0x8d00 0 0 3 &mpic 4 1
205 0x8d00 0 0 4 &mpic 1 1
206
207 /* IDSEL 0x11 func 6 - PCI slot 1 */
208 0x8e00 0 0 1 &mpic 2 1
209 0x8e00 0 0 2 &mpic 3 1
210 0x8e00 0 0 3 &mpic 4 1
211 0x8e00 0 0 4 &mpic 1 1
212
213 /* IDSEL 0x11 func 7 - PCI slot 1 */
214 0x8f00 0 0 1 &mpic 2 1
215 0x8f00 0 0 2 &mpic 3 1
216 0x8f00 0 0 3 &mpic 4 1
217 0x8f00 0 0 4 &mpic 1 1
218
219 /* IDSEL 0x12 func 0 - PCI slot 2 */
220 0x9000 0 0 1 &mpic 3 1
221 0x9000 0 0 2 &mpic 4 1
222 0x9000 0 0 3 &mpic 1 1
223 0x9000 0 0 4 &mpic 2 1
224
225 /* IDSEL 0x12 func 1 - PCI slot 2 */
226 0x9100 0 0 1 &mpic 3 1
227 0x9100 0 0 2 &mpic 4 1
228 0x9100 0 0 3 &mpic 1 1
229 0x9100 0 0 4 &mpic 2 1
230
231 /* IDSEL 0x12 func 2 - PCI slot 2 */
232 0x9200 0 0 1 &mpic 3 1
233 0x9200 0 0 2 &mpic 4 1
234 0x9200 0 0 3 &mpic 1 1
235 0x9200 0 0 4 &mpic 2 1
236
237 /* IDSEL 0x12 func 3 - PCI slot 2 */
238 0x9300 0 0 1 &mpic 3 1
239 0x9300 0 0 2 &mpic 4 1
240 0x9300 0 0 3 &mpic 1 1
241 0x9300 0 0 4 &mpic 2 1
242
243 /* IDSEL 0x12 func 4 - PCI slot 2 */
244 0x9400 0 0 1 &mpic 3 1
245 0x9400 0 0 2 &mpic 4 1
246 0x9400 0 0 3 &mpic 1 1
247 0x9400 0 0 4 &mpic 2 1
248
249 /* IDSEL 0x12 func 5 - PCI slot 2 */
250 0x9500 0 0 1 &mpic 3 1
251 0x9500 0 0 2 &mpic 4 1
252 0x9500 0 0 3 &mpic 1 1
253 0x9500 0 0 4 &mpic 2 1
254
255 /* IDSEL 0x12 func 6 - PCI slot 2 */
256 0x9600 0 0 1 &mpic 3 1
257 0x9600 0 0 2 &mpic 4 1
258 0x9600 0 0 3 &mpic 1 1
259 0x9600 0 0 4 &mpic 2 1
260
261 /* IDSEL 0x12 func 7 - PCI slot 2 */
262 0x9700 0 0 1 &mpic 3 1
263 0x9700 0 0 2 &mpic 4 1
264 0x9700 0 0 3 &mpic 1 1
265 0x9700 0 0 4 &mpic 2 1
266
267 // IDSEL 0x1c USB
268 0xe000 0 0 1 &i8259 12 2
269 0xe100 0 0 2 &i8259 9 2
270 0xe200 0 0 3 &i8259 10 2
271 0xe300 0 0 4 &i8259 11 2
272
273 // IDSEL 0x1d Audio
274 0xe800 0 0 1 &i8259 6 2
275
276 // IDSEL 0x1e Legacy
277 0xf000 0 0 1 &i8259 7 2
278 0xf100 0 0 1 &i8259 7 2
279
280 // IDSEL 0x1f IDE/SATA
281 0xf800 0 0 1 &i8259 14 2
282 0xf900 0 0 1 &i8259 5 2
283 >;
284
285 pcie@0 {
286 ranges = <0x02000000 0x0 0x80000000
287 0x02000000 0x0 0x80000000
288 0x0 0x20000000
289
290 0x01000000 0x0 0x00000000
291 0x01000000 0x0 0x00000000
292 0x0 0x00010000>;
293 uli1575@0 {
294 reg = <0 0 0 0 0>;
295 #size-cells = <2>;
296 #address-cells = <3>;
297 ranges = <0x02000000 0x0 0x80000000
298 0x02000000 0x0 0x80000000
299 0x0 0x20000000
300 0x01000000 0x0 0x00000000
301 0x01000000 0x0 0x00000000
302 0x0 0x00010000>;
303 isa@1e {
304 device_type = "isa";
305 #size-cells = <1>;
306 #address-cells = <2>;
307 reg = <0xf000 0 0 0 0>;
308 ranges = <1 0 0x01000000 0 0
309 0x00001000>;
310 interrupt-parent = <&i8259>;
311
312 i8259: interrupt-controller@20 {
313 reg = <1 0x20 2
314 1 0xa0 2
315 1 0x4d0 2>;
316 interrupt-controller;
317 device_type = "interrupt-controller";
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 compatible = "chrp,iic";
321 interrupts = <9 2 0 0>;
322 };
323
324 i8042@60 {
325 #size-cells = <0>;
326 #address-cells = <1>;
327 reg = <1 0x60 1 1 0x64 1>;
328 interrupts = <1 3 12 3>;
329 interrupt-parent = <&i8259>;
330
331 keyboard@0 {
332 reg = <0>;
333 compatible = "pnpPNP,303";
334 };
335
336 mouse@1 {
337 reg = <1>;
338 compatible = "pnpPNP,f03";
339 };
340 };
341
342 rtc@70 {
343 compatible =
344 "pnpPNP,b00";
345 reg = <1 0x70 2>;
346 };
347
348 gpio@400 {
349 reg = <1 0x400 0x80>;
350 };
351 };
352 };
353 };
354
355 };
356
357 pci1: pcie@ffe09000 {
358 reg = <0xffe09000 0x1000>;
359 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
360 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
361
362 pcie@0 {
363 ranges = <0x02000000 0x0 0xa0000000
364 0x02000000 0x0 0xa0000000
365 0x0 0x20000000
366
367 0x01000000 0x0 0x00000000
368 0x01000000 0x0 0x00000000
369 0x0 0x00010000>;
370 };
371 };
372/*
373 * Only one of Rapid IO or PCI can be present due to HW limitations and
374 * due to the fact that the 2 now share address space in the new memory
375 * map. The most likely case is that we have PCI, so comment out the
376 * rapidio node. Leave it here for reference.
377
378 rapidio@ffec0000 {
379 reg = <0xffec0000 0x11000>;
380 compatible = "fsl,srio";
381 interrupts = <48 2 0 0>;
382 #address-cells = <2>;
383 #size-cells = <2>;
384 fsl,srio-rmu-handle = <&rmu>;
385 ranges;
386
387 port1 {
388 #address-cells = <2>;
389 #size-cells = <2>;
390 cell-index = <1>;
391 ranges = <0 0 0x80000000 0 0x20000000>;
392 };
393 };
394*/
395
396};
397
398/include/ "mpc8641si-post.dtsi"
1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "mpc8641si-pre.dtsi"
13
14/ {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17
18 aliases {
19 pci1 = &pci1;
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x40000000>; // 1G at 0x0
25 };
26
27 lbc: localbus@ffe05000 {
28 reg = <0xffe05000 0x1000>;
29
30 ranges = <0 0 0xef800000 0x00800000
31 2 0 0xffdf8000 0x00008000
32 3 0 0xffdf0000 0x00008000>;
33
34 flash@0,0 {
35 compatible = "cfi-flash";
36 reg = <0 0 0x00800000>;
37 bank-width = <2>;
38 device-width = <2>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 partition@0 {
42 label = "kernel";
43 reg = <0x00000000 0x00300000>;
44 };
45 partition@300000 {
46 label = "firmware b";
47 reg = <0x00300000 0x00100000>;
48 read-only;
49 };
50 partition@400000 {
51 label = "fs";
52 reg = <0x00400000 0x00300000>;
53 };
54 partition@700000 {
55 label = "firmware a";
56 reg = <0x00700000 0x00100000>;
57 read-only;
58 };
59 };
60 };
61
62 soc: soc8641@ffe00000 {
63 ranges = <0x00000000 0xffe00000 0x00100000>;
64
65 enet0: ethernet@24000 {
66 tbi-handle = <&tbi0>;
67 phy-handle = <&phy0>;
68 phy-connection-type = "rgmii-id";
69 };
70
71 mdio@24520 {
72 phy0: ethernet-phy@0 {
73 interrupts = <10 1 0 0>;
74 reg = <0>;
75 };
76 phy1: ethernet-phy@1 {
77 interrupts = <10 1 0 0>;
78 reg = <1>;
79 };
80 phy2: ethernet-phy@2 {
81 interrupts = <10 1 0 0>;
82 reg = <2>;
83 };
84 phy3: ethernet-phy@3 {
85 interrupts = <10 1 0 0>;
86 reg = <3>;
87 };
88 tbi0: tbi-phy@11 {
89 reg = <0x11>;
90 device_type = "tbi-phy";
91 };
92 };
93
94 enet1: ethernet@25000 {
95 tbi-handle = <&tbi1>;
96 phy-handle = <&phy1>;
97 phy-connection-type = "rgmii-id";
98 };
99
100 mdio@25520 {
101 tbi1: tbi-phy@11 {
102 reg = <0x11>;
103 device_type = "tbi-phy";
104 };
105 };
106
107 enet2: ethernet@26000 {
108 tbi-handle = <&tbi2>;
109 phy-handle = <&phy2>;
110 phy-connection-type = "rgmii-id";
111 };
112
113 mdio@26520 {
114 tbi2: tbi-phy@11 {
115 reg = <0x11>;
116 device_type = "tbi-phy";
117 };
118 };
119
120 enet3: ethernet@27000 {
121 tbi-handle = <&tbi3>;
122 phy-handle = <&phy3>;
123 phy-connection-type = "rgmii-id";
124 };
125
126 mdio@27520 {
127 tbi3: tbi-phy@11 {
128 reg = <0x11>;
129 device_type = "tbi-phy";
130 };
131 };
132
133 rmu: rmu@d3000 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "fsl,srio-rmu";
137 reg = <0xd3000 0x500>;
138 ranges = <0x0 0xd3000 0x500>;
139
140 message-unit@0 {
141 compatible = "fsl,srio-msg-unit";
142 reg = <0x0 0x100>;
143 interrupts = <
144 53 2 0 0 /* msg1_tx_irq */
145 54 2 0 0>;/* msg1_rx_irq */
146 };
147 message-unit@100 {
148 compatible = "fsl,srio-msg-unit";
149 reg = <0x100 0x100>;
150 interrupts = <
151 55 2 0 0 /* msg2_tx_irq */
152 56 2 0 0>;/* msg2_rx_irq */
153 };
154 doorbell-unit@400 {
155 compatible = "fsl,srio-dbell-unit";
156 reg = <0x400 0x80>;
157 interrupts = <
158 49 2 0 0 /* bell_outb_irq */
159 50 2 0 0>;/* bell_inb_irq */
160 };
161 port-write-unit@4e0 {
162 compatible = "fsl,srio-port-write-unit";
163 reg = <0x4e0 0x20>;
164 interrupts = <48 2 0 0>;
165 };
166 };
167 };
168
169 pci0: pcie@ffe08000 {
170 reg = <0xffe08000 0x1000>;
171 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
172 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
173 interrupt-map-mask = <0xff00 0 0 7>;
174 interrupt-map = <
175 /* IDSEL 0x11 func 0 - PCI slot 1 */
176 0x8800 0 0 1 &mpic 2 1
177 0x8800 0 0 2 &mpic 3 1
178 0x8800 0 0 3 &mpic 4 1
179 0x8800 0 0 4 &mpic 1 1
180
181 /* IDSEL 0x11 func 1 - PCI slot 1 */
182 0x8900 0 0 1 &mpic 2 1
183 0x8900 0 0 2 &mpic 3 1
184 0x8900 0 0 3 &mpic 4 1
185 0x8900 0 0 4 &mpic 1 1
186
187 /* IDSEL 0x11 func 2 - PCI slot 1 */
188 0x8a00 0 0 1 &mpic 2 1
189 0x8a00 0 0 2 &mpic 3 1
190 0x8a00 0 0 3 &mpic 4 1
191 0x8a00 0 0 4 &mpic 1 1
192
193 /* IDSEL 0x11 func 3 - PCI slot 1 */
194 0x8b00 0 0 1 &mpic 2 1
195 0x8b00 0 0 2 &mpic 3 1
196 0x8b00 0 0 3 &mpic 4 1
197 0x8b00 0 0 4 &mpic 1 1
198
199 /* IDSEL 0x11 func 4 - PCI slot 1 */
200 0x8c00 0 0 1 &mpic 2 1
201 0x8c00 0 0 2 &mpic 3 1
202 0x8c00 0 0 3 &mpic 4 1
203 0x8c00 0 0 4 &mpic 1 1
204
205 /* IDSEL 0x11 func 5 - PCI slot 1 */
206 0x8d00 0 0 1 &mpic 2 1
207 0x8d00 0 0 2 &mpic 3 1
208 0x8d00 0 0 3 &mpic 4 1
209 0x8d00 0 0 4 &mpic 1 1
210
211 /* IDSEL 0x11 func 6 - PCI slot 1 */
212 0x8e00 0 0 1 &mpic 2 1
213 0x8e00 0 0 2 &mpic 3 1
214 0x8e00 0 0 3 &mpic 4 1
215 0x8e00 0 0 4 &mpic 1 1
216
217 /* IDSEL 0x11 func 7 - PCI slot 1 */
218 0x8f00 0 0 1 &mpic 2 1
219 0x8f00 0 0 2 &mpic 3 1
220 0x8f00 0 0 3 &mpic 4 1
221 0x8f00 0 0 4 &mpic 1 1
222
223 /* IDSEL 0x12 func 0 - PCI slot 2 */
224 0x9000 0 0 1 &mpic 3 1
225 0x9000 0 0 2 &mpic 4 1
226 0x9000 0 0 3 &mpic 1 1
227 0x9000 0 0 4 &mpic 2 1
228
229 /* IDSEL 0x12 func 1 - PCI slot 2 */
230 0x9100 0 0 1 &mpic 3 1
231 0x9100 0 0 2 &mpic 4 1
232 0x9100 0 0 3 &mpic 1 1
233 0x9100 0 0 4 &mpic 2 1
234
235 /* IDSEL 0x12 func 2 - PCI slot 2 */
236 0x9200 0 0 1 &mpic 3 1
237 0x9200 0 0 2 &mpic 4 1
238 0x9200 0 0 3 &mpic 1 1
239 0x9200 0 0 4 &mpic 2 1
240
241 /* IDSEL 0x12 func 3 - PCI slot 2 */
242 0x9300 0 0 1 &mpic 3 1
243 0x9300 0 0 2 &mpic 4 1
244 0x9300 0 0 3 &mpic 1 1
245 0x9300 0 0 4 &mpic 2 1
246
247 /* IDSEL 0x12 func 4 - PCI slot 2 */
248 0x9400 0 0 1 &mpic 3 1
249 0x9400 0 0 2 &mpic 4 1
250 0x9400 0 0 3 &mpic 1 1
251 0x9400 0 0 4 &mpic 2 1
252
253 /* IDSEL 0x12 func 5 - PCI slot 2 */
254 0x9500 0 0 1 &mpic 3 1
255 0x9500 0 0 2 &mpic 4 1
256 0x9500 0 0 3 &mpic 1 1
257 0x9500 0 0 4 &mpic 2 1
258
259 /* IDSEL 0x12 func 6 - PCI slot 2 */
260 0x9600 0 0 1 &mpic 3 1
261 0x9600 0 0 2 &mpic 4 1
262 0x9600 0 0 3 &mpic 1 1
263 0x9600 0 0 4 &mpic 2 1
264
265 /* IDSEL 0x12 func 7 - PCI slot 2 */
266 0x9700 0 0 1 &mpic 3 1
267 0x9700 0 0 2 &mpic 4 1
268 0x9700 0 0 3 &mpic 1 1
269 0x9700 0 0 4 &mpic 2 1
270
271 // IDSEL 0x1c USB
272 0xe000 0 0 1 &i8259 12 2
273 0xe100 0 0 2 &i8259 9 2
274 0xe200 0 0 3 &i8259 10 2
275 0xe300 0 0 4 &i8259 11 2
276
277 // IDSEL 0x1d Audio
278 0xe800 0 0 1 &i8259 6 2
279
280 // IDSEL 0x1e Legacy
281 0xf000 0 0 1 &i8259 7 2
282 0xf100 0 0 1 &i8259 7 2
283
284 // IDSEL 0x1f IDE/SATA
285 0xf800 0 0 1 &i8259 14 2
286 0xf900 0 0 1 &i8259 5 2
287 >;
288
289 pcie@0 {
290 ranges = <0x02000000 0x0 0x80000000
291 0x02000000 0x0 0x80000000
292 0x0 0x20000000
293
294 0x01000000 0x0 0x00000000
295 0x01000000 0x0 0x00000000
296 0x0 0x00010000>;
297 uli1575@0 {
298 reg = <0 0 0 0 0>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 ranges = <0x02000000 0x0 0x80000000
302 0x02000000 0x0 0x80000000
303 0x0 0x20000000
304 0x01000000 0x0 0x00000000
305 0x01000000 0x0 0x00000000
306 0x0 0x00010000>;
307 isa@1e {
308 device_type = "isa";
309 #size-cells = <1>;
310 #address-cells = <2>;
311 reg = <0xf000 0 0 0 0>;
312 ranges = <1 0 0x01000000 0 0
313 0x00001000>;
314 interrupt-parent = <&i8259>;
315
316 i8259: interrupt-controller@20 {
317 reg = <1 0x20 2
318 1 0xa0 2
319 1 0x4d0 2>;
320 interrupt-controller;
321 device_type = "interrupt-controller";
322 #address-cells = <0>;
323 #interrupt-cells = <2>;
324 compatible = "chrp,iic";
325 interrupts = <9 2 0 0>;
326 };
327
328 i8042@60 {
329 #size-cells = <0>;
330 #address-cells = <1>;
331 reg = <1 0x60 1 1 0x64 1>;
332 interrupts = <1 3 12 3>;
333 interrupt-parent = <&i8259>;
334
335 keyboard@0 {
336 reg = <0>;
337 compatible = "pnpPNP,303";
338 };
339
340 mouse@1 {
341 reg = <1>;
342 compatible = "pnpPNP,f03";
343 };
344 };
345
346 rtc@70 {
347 compatible =
348 "pnpPNP,b00";
349 reg = <1 0x70 2>;
350 };
351
352 gpio@400 {
353 reg = <1 0x400 0x80>;
354 };
355 };
356 };
357 };
358
359 };
360
361 pci1: pcie@ffe09000 {
362 compatible = "fsl,mpc8641-pcie";
363 device_type = "pci";
364 #size-cells = <2>;
365 #address-cells = <3>;
366 reg = <0xffe09000 0x1000>;
367 bus-range = <0 0xff>;
368 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
369 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
370 clock-frequency = <100000000>;
371 interrupts = <25 2 0 0>;
372 interrupt-map-mask = <0xf800 0 0 7>;
373 interrupt-map = <
374 /* IDSEL 0x0 */
375 0x0000 0 0 1 &mpic 4 1
376 0x0000 0 0 2 &mpic 5 1
377 0x0000 0 0 3 &mpic 6 1
378 0x0000 0 0 4 &mpic 7 1
379 >;
380 pcie@0 {
381 reg = <0 0 0 0 0>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 device_type = "pci";
385 ranges = <0x02000000 0x0 0xa0000000
386 0x02000000 0x0 0xa0000000
387 0x0 0x20000000
388
389 0x01000000 0x0 0x00000000
390 0x01000000 0x0 0x00000000
391 0x0 0x00010000>;
392 };
393 };
394/*
395 * Only one of Rapid IO or PCI can be present due to HW limitations and
396 * due to the fact that the 2 now share address space in the new memory
397 * map. The most likely case is that we have PCI, so comment out the
398 * rapidio node. Leave it here for reference.
399
400 rapidio@ffec0000 {
401 reg = <0xffec0000 0x11000>;
402 compatible = "fsl,srio";
403 interrupts = <48 2 0 0>;
404 #address-cells = <2>;
405 #size-cells = <2>;
406 fsl,srio-rmu-handle = <&rmu>;
407 ranges;
408
409 port1 {
410 #address-cells = <2>;
411 #size-cells = <2>;
412 cell-index = <1>;
413 ranges = <0 0 0x80000000 0 0x20000000>;
414 };
415 };
416*/
417
418};
419
420/include/ "mpc8641si-post.dtsi"