Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */
11#include <linux/bug.h>
12#include <linux/init.h>
13#include <linux/export.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/pagemap.h>
22#include <linux/ptrace.h>
23#include <linux/mman.h>
24#include <linux/mm.h>
25#include <linux/bootmem.h>
26#include <linux/highmem.h>
27#include <linux/swap.h>
28#include <linux/proc_fs.h>
29#include <linux/pfn.h>
30#include <linux/hardirq.h>
31#include <linux/gfp.h>
32#include <linux/kcore.h>
33#include <linux/initrd.h>
34
35#include <asm/asm-offsets.h>
36#include <asm/bootinfo.h>
37#include <asm/cachectl.h>
38#include <asm/cpu.h>
39#include <asm/dma.h>
40#include <asm/kmap_types.h>
41#include <asm/maar.h>
42#include <asm/mmu_context.h>
43#include <asm/sections.h>
44#include <asm/pgtable.h>
45#include <asm/pgalloc.h>
46#include <asm/tlb.h>
47#include <asm/fixmap.h>
48
49/*
50 * We have up to 8 empty zeroed pages so we can map one of the right colour
51 * when needed. This is necessary only on R4000 / R4400 SC and MC versions
52 * where we have to avoid VCED / VECI exceptions for good performance at
53 * any price. Since page is never written to after the initialization we
54 * don't have to care about aliases on other CPUs.
55 */
56unsigned long empty_zero_page, zero_page_mask;
57EXPORT_SYMBOL_GPL(empty_zero_page);
58EXPORT_SYMBOL(zero_page_mask);
59
60/*
61 * Not static inline because used by IP27 special magic initialization code
62 */
63void setup_zero_pages(void)
64{
65 unsigned int order, i;
66 struct page *page;
67
68 if (cpu_has_vce)
69 order = 3;
70 else
71 order = 0;
72
73 empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
74 if (!empty_zero_page)
75 panic("Oh boy, that early out of memory?");
76
77 page = virt_to_page((void *)empty_zero_page);
78 split_page(page, order);
79 for (i = 0; i < (1 << order); i++, page++)
80 mark_page_reserved(page);
81
82 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
83}
84
85static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
86{
87 enum fixed_addresses idx;
88 unsigned long vaddr, flags, entrylo;
89 unsigned long old_ctx;
90 pte_t pte;
91 int tlbidx;
92
93 BUG_ON(Page_dcache_dirty(page));
94
95 preempt_disable();
96 pagefault_disable();
97 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
98 idx += in_interrupt() ? FIX_N_COLOURS : 0;
99 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
100 pte = mk_pte(page, prot);
101#if defined(CONFIG_XPA)
102 entrylo = pte_to_entrylo(pte.pte_high);
103#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
104 entrylo = pte.pte_high;
105#else
106 entrylo = pte_to_entrylo(pte_val(pte));
107#endif
108
109 local_irq_save(flags);
110 old_ctx = read_c0_entryhi();
111 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
112 write_c0_entrylo0(entrylo);
113 write_c0_entrylo1(entrylo);
114#ifdef CONFIG_XPA
115 if (cpu_has_xpa) {
116 entrylo = (pte.pte_low & _PFNX_MASK);
117 writex_c0_entrylo0(entrylo);
118 writex_c0_entrylo1(entrylo);
119 }
120#endif
121 tlbidx = num_wired_entries();
122 write_c0_wired(tlbidx + 1);
123 write_c0_index(tlbidx);
124 mtc0_tlbw_hazard();
125 tlb_write_indexed();
126 tlbw_use_hazard();
127 write_c0_entryhi(old_ctx);
128 local_irq_restore(flags);
129
130 return (void*) vaddr;
131}
132
133void *kmap_coherent(struct page *page, unsigned long addr)
134{
135 return __kmap_pgprot(page, addr, PAGE_KERNEL);
136}
137
138void *kmap_noncoherent(struct page *page, unsigned long addr)
139{
140 return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
141}
142
143void kunmap_coherent(void)
144{
145 unsigned int wired;
146 unsigned long flags, old_ctx;
147
148 local_irq_save(flags);
149 old_ctx = read_c0_entryhi();
150 wired = num_wired_entries() - 1;
151 write_c0_wired(wired);
152 write_c0_index(wired);
153 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
154 write_c0_entrylo0(0);
155 write_c0_entrylo1(0);
156 mtc0_tlbw_hazard();
157 tlb_write_indexed();
158 tlbw_use_hazard();
159 write_c0_entryhi(old_ctx);
160 local_irq_restore(flags);
161 pagefault_enable();
162 preempt_enable();
163}
164
165void copy_user_highpage(struct page *to, struct page *from,
166 unsigned long vaddr, struct vm_area_struct *vma)
167{
168 void *vfrom, *vto;
169
170 vto = kmap_atomic(to);
171 if (cpu_has_dc_aliases &&
172 page_mapcount(from) && !Page_dcache_dirty(from)) {
173 vfrom = kmap_coherent(from, vaddr);
174 copy_page(vto, vfrom);
175 kunmap_coherent();
176 } else {
177 vfrom = kmap_atomic(from);
178 copy_page(vto, vfrom);
179 kunmap_atomic(vfrom);
180 }
181 if ((!cpu_has_ic_fills_f_dc) ||
182 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
183 flush_data_cache_page((unsigned long)vto);
184 kunmap_atomic(vto);
185 /* Make sure this page is cleared on other CPU's too before using it */
186 smp_wmb();
187}
188
189void copy_to_user_page(struct vm_area_struct *vma,
190 struct page *page, unsigned long vaddr, void *dst, const void *src,
191 unsigned long len)
192{
193 if (cpu_has_dc_aliases &&
194 page_mapcount(page) && !Page_dcache_dirty(page)) {
195 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
196 memcpy(vto, src, len);
197 kunmap_coherent();
198 } else {
199 memcpy(dst, src, len);
200 if (cpu_has_dc_aliases)
201 SetPageDcacheDirty(page);
202 }
203 if (vma->vm_flags & VM_EXEC)
204 flush_cache_page(vma, vaddr, page_to_pfn(page));
205}
206
207void copy_from_user_page(struct vm_area_struct *vma,
208 struct page *page, unsigned long vaddr, void *dst, const void *src,
209 unsigned long len)
210{
211 if (cpu_has_dc_aliases &&
212 page_mapcount(page) && !Page_dcache_dirty(page)) {
213 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
214 memcpy(dst, vfrom, len);
215 kunmap_coherent();
216 } else {
217 memcpy(dst, src, len);
218 if (cpu_has_dc_aliases)
219 SetPageDcacheDirty(page);
220 }
221}
222EXPORT_SYMBOL_GPL(copy_from_user_page);
223
224void __init fixrange_init(unsigned long start, unsigned long end,
225 pgd_t *pgd_base)
226{
227#ifdef CONFIG_HIGHMEM
228 pgd_t *pgd;
229 pud_t *pud;
230 pmd_t *pmd;
231 pte_t *pte;
232 int i, j, k;
233 unsigned long vaddr;
234
235 vaddr = start;
236 i = __pgd_offset(vaddr);
237 j = __pud_offset(vaddr);
238 k = __pmd_offset(vaddr);
239 pgd = pgd_base + i;
240
241 for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
242 pud = (pud_t *)pgd;
243 for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
244 pmd = (pmd_t *)pud;
245 for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
246 if (pmd_none(*pmd)) {
247 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
248 set_pmd(pmd, __pmd((unsigned long)pte));
249 BUG_ON(pte != pte_offset_kernel(pmd, 0));
250 }
251 vaddr += PMD_SIZE;
252 }
253 k = 0;
254 }
255 j = 0;
256 }
257#endif
258}
259
260unsigned __weak platform_maar_init(unsigned num_pairs)
261{
262 struct maar_config cfg[BOOT_MEM_MAP_MAX];
263 unsigned i, num_configured, num_cfg = 0;
264
265 for (i = 0; i < boot_mem_map.nr_map; i++) {
266 switch (boot_mem_map.map[i].type) {
267 case BOOT_MEM_RAM:
268 case BOOT_MEM_INIT_RAM:
269 break;
270 default:
271 continue;
272 }
273
274 /* Round lower up */
275 cfg[num_cfg].lower = boot_mem_map.map[i].addr;
276 cfg[num_cfg].lower = (cfg[num_cfg].lower + 0xffff) & ~0xffff;
277
278 /* Round upper down */
279 cfg[num_cfg].upper = boot_mem_map.map[i].addr +
280 boot_mem_map.map[i].size;
281 cfg[num_cfg].upper = (cfg[num_cfg].upper & ~0xffff) - 1;
282
283 cfg[num_cfg].attrs = MIPS_MAAR_S;
284 num_cfg++;
285 }
286
287 num_configured = maar_config(cfg, num_cfg, num_pairs);
288 if (num_configured < num_cfg)
289 pr_warn("Not enough MAAR pairs (%u) for all bootmem regions (%u)\n",
290 num_pairs, num_cfg);
291
292 return num_configured;
293}
294
295void maar_init(void)
296{
297 unsigned num_maars, used, i;
298 phys_addr_t lower, upper, attr;
299 static struct {
300 struct maar_config cfgs[3];
301 unsigned used;
302 } recorded = { { { 0 } }, 0 };
303
304 if (!cpu_has_maar)
305 return;
306
307 /* Detect the number of MAARs */
308 write_c0_maari(~0);
309 back_to_back_c0_hazard();
310 num_maars = read_c0_maari() + 1;
311
312 /* MAARs should be in pairs */
313 WARN_ON(num_maars % 2);
314
315 /* Set MAARs using values we recorded already */
316 if (recorded.used) {
317 used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
318 BUG_ON(used != recorded.used);
319 } else {
320 /* Configure the required MAARs */
321 used = platform_maar_init(num_maars / 2);
322 }
323
324 /* Disable any further MAARs */
325 for (i = (used * 2); i < num_maars; i++) {
326 write_c0_maari(i);
327 back_to_back_c0_hazard();
328 write_c0_maar(0);
329 back_to_back_c0_hazard();
330 }
331
332 if (recorded.used)
333 return;
334
335 pr_info("MAAR configuration:\n");
336 for (i = 0; i < num_maars; i += 2) {
337 write_c0_maari(i);
338 back_to_back_c0_hazard();
339 upper = read_c0_maar();
340
341 write_c0_maari(i + 1);
342 back_to_back_c0_hazard();
343 lower = read_c0_maar();
344
345 attr = lower & upper;
346 lower = (lower & MIPS_MAAR_ADDR) << 4;
347 upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
348
349 pr_info(" [%d]: ", i / 2);
350 if (!(attr & MIPS_MAAR_VL)) {
351 pr_cont("disabled\n");
352 continue;
353 }
354
355 pr_cont("%pa-%pa", &lower, &upper);
356
357 if (attr & MIPS_MAAR_S)
358 pr_cont(" speculate");
359
360 pr_cont("\n");
361
362 /* Record the setup for use on secondary CPUs */
363 if (used <= ARRAY_SIZE(recorded.cfgs)) {
364 recorded.cfgs[recorded.used].lower = lower;
365 recorded.cfgs[recorded.used].upper = upper;
366 recorded.cfgs[recorded.used].attrs = attr;
367 recorded.used++;
368 }
369 }
370}
371
372#ifndef CONFIG_NEED_MULTIPLE_NODES
373int page_is_ram(unsigned long pagenr)
374{
375 int i;
376
377 for (i = 0; i < boot_mem_map.nr_map; i++) {
378 unsigned long addr, end;
379
380 switch (boot_mem_map.map[i].type) {
381 case BOOT_MEM_RAM:
382 case BOOT_MEM_INIT_RAM:
383 break;
384 default:
385 /* not usable memory */
386 continue;
387 }
388
389 addr = PFN_UP(boot_mem_map.map[i].addr);
390 end = PFN_DOWN(boot_mem_map.map[i].addr +
391 boot_mem_map.map[i].size);
392
393 if (pagenr >= addr && pagenr < end)
394 return 1;
395 }
396
397 return 0;
398}
399
400void __init paging_init(void)
401{
402 unsigned long max_zone_pfns[MAX_NR_ZONES];
403
404 pagetable_init();
405
406#ifdef CONFIG_HIGHMEM
407 kmap_init();
408#endif
409#ifdef CONFIG_ZONE_DMA
410 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
411#endif
412#ifdef CONFIG_ZONE_DMA32
413 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
414#endif
415 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
416#ifdef CONFIG_HIGHMEM
417 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
418
419 if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
420 printk(KERN_WARNING "This processor doesn't support highmem."
421 " %ldk highmem ignored\n",
422 (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
423 max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
424 }
425#endif
426
427 free_area_init_nodes(max_zone_pfns);
428}
429
430#ifdef CONFIG_64BIT
431static struct kcore_list kcore_kseg0;
432#endif
433
434static inline void mem_init_free_highmem(void)
435{
436#ifdef CONFIG_HIGHMEM
437 unsigned long tmp;
438
439 if (cpu_has_dc_aliases)
440 return;
441
442 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
443 struct page *page = pfn_to_page(tmp);
444
445 if (!page_is_ram(tmp))
446 SetPageReserved(page);
447 else
448 free_highmem_page(page);
449 }
450#endif
451}
452
453void __init mem_init(void)
454{
455#ifdef CONFIG_HIGHMEM
456#ifdef CONFIG_DISCONTIGMEM
457#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
458#endif
459 max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
460#else
461 max_mapnr = max_low_pfn;
462#endif
463 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
464
465 maar_init();
466 free_all_bootmem();
467 setup_zero_pages(); /* Setup zeroed pages. */
468 mem_init_free_highmem();
469 mem_init_print_info(NULL);
470
471#ifdef CONFIG_64BIT
472 if ((unsigned long) &_text > (unsigned long) CKSEG0)
473 /* The -4 is a hack so that user tools don't have to handle
474 the overflow. */
475 kclist_add(&kcore_kseg0, (void *) CKSEG0,
476 0x80000000 - 4, KCORE_TEXT);
477#endif
478}
479#endif /* !CONFIG_NEED_MULTIPLE_NODES */
480
481void free_init_pages(const char *what, unsigned long begin, unsigned long end)
482{
483 unsigned long pfn;
484
485 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
486 struct page *page = pfn_to_page(pfn);
487 void *addr = phys_to_virt(PFN_PHYS(pfn));
488
489 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
490 free_reserved_page(page);
491 }
492 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
493}
494
495#ifdef CONFIG_BLK_DEV_INITRD
496void free_initrd_mem(unsigned long start, unsigned long end)
497{
498 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
499 "initrd");
500}
501#endif
502
503void (*free_init_pages_eva)(void *begin, void *end) = NULL;
504
505void __ref free_initmem(void)
506{
507 prom_free_prom_memory();
508 /*
509 * Let the platform define a specific function to free the
510 * init section since EVA may have used any possible mapping
511 * between virtual and physical addresses.
512 */
513 if (free_init_pages_eva)
514 free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
515 else
516 free_initmem_default(POISON_FREE_INITMEM);
517}
518
519#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
520unsigned long pgd_current[NR_CPUS];
521#endif
522
523/*
524 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
525 * are constants. So we use the variants from asm-offset.h until that gcc
526 * will officially be retired.
527 *
528 * Align swapper_pg_dir in to 64K, allows its address to be loaded
529 * with a single LUI instruction in the TLB handlers. If we used
530 * __aligned(64K), its size would get rounded up to the alignment
531 * size, and waste space. So we place it in its own section and align
532 * it in the linker script.
533 */
534pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
535#ifndef __PAGETABLE_PUD_FOLDED
536pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
537#endif
538#ifndef __PAGETABLE_PMD_FOLDED
539pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
540EXPORT_SYMBOL_GPL(invalid_pmd_table);
541#endif
542pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
543EXPORT_SYMBOL(invalid_pte_table);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */
11#include <linux/bug.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/pagemap.h>
22#include <linux/ptrace.h>
23#include <linux/mman.h>
24#include <linux/mm.h>
25#include <linux/bootmem.h>
26#include <linux/highmem.h>
27#include <linux/swap.h>
28#include <linux/proc_fs.h>
29#include <linux/pfn.h>
30#include <linux/hardirq.h>
31#include <linux/gfp.h>
32#include <linux/kcore.h>
33
34#include <asm/asm-offsets.h>
35#include <asm/bootinfo.h>
36#include <asm/cachectl.h>
37#include <asm/cpu.h>
38#include <asm/dma.h>
39#include <asm/kmap_types.h>
40#include <asm/maar.h>
41#include <asm/mmu_context.h>
42#include <asm/sections.h>
43#include <asm/pgtable.h>
44#include <asm/pgalloc.h>
45#include <asm/tlb.h>
46#include <asm/fixmap.h>
47#include <asm/maar.h>
48
49/*
50 * We have up to 8 empty zeroed pages so we can map one of the right colour
51 * when needed. This is necessary only on R4000 / R4400 SC and MC versions
52 * where we have to avoid VCED / VECI exceptions for good performance at
53 * any price. Since page is never written to after the initialization we
54 * don't have to care about aliases on other CPUs.
55 */
56unsigned long empty_zero_page, zero_page_mask;
57EXPORT_SYMBOL_GPL(empty_zero_page);
58EXPORT_SYMBOL(zero_page_mask);
59
60/*
61 * Not static inline because used by IP27 special magic initialization code
62 */
63void setup_zero_pages(void)
64{
65 unsigned int order, i;
66 struct page *page;
67
68 if (cpu_has_vce)
69 order = 3;
70 else
71 order = 0;
72
73 empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
74 if (!empty_zero_page)
75 panic("Oh boy, that early out of memory?");
76
77 page = virt_to_page((void *)empty_zero_page);
78 split_page(page, order);
79 for (i = 0; i < (1 << order); i++, page++)
80 mark_page_reserved(page);
81
82 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
83}
84
85static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
86{
87 enum fixed_addresses idx;
88 unsigned long vaddr, flags, entrylo;
89 unsigned long old_ctx;
90 pte_t pte;
91 int tlbidx;
92
93 BUG_ON(Page_dcache_dirty(page));
94
95 preempt_disable();
96 pagefault_disable();
97 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
98 idx += in_interrupt() ? FIX_N_COLOURS : 0;
99 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
100 pte = mk_pte(page, prot);
101#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
102 entrylo = pte_to_entrylo(pte.pte_high);
103#else
104 entrylo = pte_to_entrylo(pte_val(pte));
105#endif
106
107 local_irq_save(flags);
108 old_ctx = read_c0_entryhi();
109 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
110 write_c0_entrylo0(entrylo);
111 write_c0_entrylo1(entrylo);
112#ifdef CONFIG_XPA
113 entrylo = (pte.pte_low & _PFNX_MASK);
114 writex_c0_entrylo0(entrylo);
115 writex_c0_entrylo1(entrylo);
116#endif
117 tlbidx = read_c0_wired();
118 write_c0_wired(tlbidx + 1);
119 write_c0_index(tlbidx);
120 mtc0_tlbw_hazard();
121 tlb_write_indexed();
122 tlbw_use_hazard();
123 write_c0_entryhi(old_ctx);
124 local_irq_restore(flags);
125
126 return (void*) vaddr;
127}
128
129void *kmap_coherent(struct page *page, unsigned long addr)
130{
131 return __kmap_pgprot(page, addr, PAGE_KERNEL);
132}
133
134void *kmap_noncoherent(struct page *page, unsigned long addr)
135{
136 return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
137}
138
139void kunmap_coherent(void)
140{
141 unsigned int wired;
142 unsigned long flags, old_ctx;
143
144 local_irq_save(flags);
145 old_ctx = read_c0_entryhi();
146 wired = read_c0_wired() - 1;
147 write_c0_wired(wired);
148 write_c0_index(wired);
149 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
150 write_c0_entrylo0(0);
151 write_c0_entrylo1(0);
152 mtc0_tlbw_hazard();
153 tlb_write_indexed();
154 tlbw_use_hazard();
155 write_c0_entryhi(old_ctx);
156 local_irq_restore(flags);
157 pagefault_enable();
158 preempt_enable();
159}
160
161void copy_user_highpage(struct page *to, struct page *from,
162 unsigned long vaddr, struct vm_area_struct *vma)
163{
164 void *vfrom, *vto;
165
166 vto = kmap_atomic(to);
167 if (cpu_has_dc_aliases &&
168 page_mapcount(from) && !Page_dcache_dirty(from)) {
169 vfrom = kmap_coherent(from, vaddr);
170 copy_page(vto, vfrom);
171 kunmap_coherent();
172 } else {
173 vfrom = kmap_atomic(from);
174 copy_page(vto, vfrom);
175 kunmap_atomic(vfrom);
176 }
177 if ((!cpu_has_ic_fills_f_dc) ||
178 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
179 flush_data_cache_page((unsigned long)vto);
180 kunmap_atomic(vto);
181 /* Make sure this page is cleared on other CPU's too before using it */
182 smp_wmb();
183}
184
185void copy_to_user_page(struct vm_area_struct *vma,
186 struct page *page, unsigned long vaddr, void *dst, const void *src,
187 unsigned long len)
188{
189 if (cpu_has_dc_aliases &&
190 page_mapcount(page) && !Page_dcache_dirty(page)) {
191 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
192 memcpy(vto, src, len);
193 kunmap_coherent();
194 } else {
195 memcpy(dst, src, len);
196 if (cpu_has_dc_aliases)
197 SetPageDcacheDirty(page);
198 }
199 if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
200 flush_cache_page(vma, vaddr, page_to_pfn(page));
201}
202
203void copy_from_user_page(struct vm_area_struct *vma,
204 struct page *page, unsigned long vaddr, void *dst, const void *src,
205 unsigned long len)
206{
207 if (cpu_has_dc_aliases &&
208 page_mapcount(page) && !Page_dcache_dirty(page)) {
209 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
210 memcpy(dst, vfrom, len);
211 kunmap_coherent();
212 } else {
213 memcpy(dst, src, len);
214 if (cpu_has_dc_aliases)
215 SetPageDcacheDirty(page);
216 }
217}
218EXPORT_SYMBOL_GPL(copy_from_user_page);
219
220void __init fixrange_init(unsigned long start, unsigned long end,
221 pgd_t *pgd_base)
222{
223#ifdef CONFIG_HIGHMEM
224 pgd_t *pgd;
225 pud_t *pud;
226 pmd_t *pmd;
227 pte_t *pte;
228 int i, j, k;
229 unsigned long vaddr;
230
231 vaddr = start;
232 i = __pgd_offset(vaddr);
233 j = __pud_offset(vaddr);
234 k = __pmd_offset(vaddr);
235 pgd = pgd_base + i;
236
237 for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
238 pud = (pud_t *)pgd;
239 for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
240 pmd = (pmd_t *)pud;
241 for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
242 if (pmd_none(*pmd)) {
243 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
244 set_pmd(pmd, __pmd((unsigned long)pte));
245 BUG_ON(pte != pte_offset_kernel(pmd, 0));
246 }
247 vaddr += PMD_SIZE;
248 }
249 k = 0;
250 }
251 j = 0;
252 }
253#endif
254}
255
256unsigned __weak platform_maar_init(unsigned num_pairs)
257{
258 struct maar_config cfg[BOOT_MEM_MAP_MAX];
259 unsigned i, num_configured, num_cfg = 0;
260 phys_addr_t skip;
261
262 for (i = 0; i < boot_mem_map.nr_map; i++) {
263 switch (boot_mem_map.map[i].type) {
264 case BOOT_MEM_RAM:
265 case BOOT_MEM_INIT_RAM:
266 break;
267 default:
268 continue;
269 }
270
271 skip = 0x10000 - (boot_mem_map.map[i].addr & 0xffff);
272
273 cfg[num_cfg].lower = boot_mem_map.map[i].addr;
274 cfg[num_cfg].lower += skip;
275
276 cfg[num_cfg].upper = cfg[num_cfg].lower;
277 cfg[num_cfg].upper += boot_mem_map.map[i].size - 1;
278 cfg[num_cfg].upper -= skip;
279
280 cfg[num_cfg].attrs = MIPS_MAAR_S;
281 num_cfg++;
282 }
283
284 num_configured = maar_config(cfg, num_cfg, num_pairs);
285 if (num_configured < num_cfg)
286 pr_warn("Not enough MAAR pairs (%u) for all bootmem regions (%u)\n",
287 num_pairs, num_cfg);
288
289 return num_configured;
290}
291
292void maar_init(void)
293{
294 unsigned num_maars, used, i;
295 phys_addr_t lower, upper, attr;
296 static struct {
297 struct maar_config cfgs[3];
298 unsigned used;
299 } recorded = { { { 0 } }, 0 };
300
301 if (!cpu_has_maar)
302 return;
303
304 /* Detect the number of MAARs */
305 write_c0_maari(~0);
306 back_to_back_c0_hazard();
307 num_maars = read_c0_maari() + 1;
308
309 /* MAARs should be in pairs */
310 WARN_ON(num_maars % 2);
311
312 /* Set MAARs using values we recorded already */
313 if (recorded.used) {
314 used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
315 BUG_ON(used != recorded.used);
316 } else {
317 /* Configure the required MAARs */
318 used = platform_maar_init(num_maars / 2);
319 }
320
321 /* Disable any further MAARs */
322 for (i = (used * 2); i < num_maars; i++) {
323 write_c0_maari(i);
324 back_to_back_c0_hazard();
325 write_c0_maar(0);
326 back_to_back_c0_hazard();
327 }
328
329 if (recorded.used)
330 return;
331
332 pr_info("MAAR configuration:\n");
333 for (i = 0; i < num_maars; i += 2) {
334 write_c0_maari(i);
335 back_to_back_c0_hazard();
336 upper = read_c0_maar();
337
338 write_c0_maari(i + 1);
339 back_to_back_c0_hazard();
340 lower = read_c0_maar();
341
342 attr = lower & upper;
343 lower = (lower & MIPS_MAAR_ADDR) << 4;
344 upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
345
346 pr_info(" [%d]: ", i / 2);
347 if (!(attr & MIPS_MAAR_V)) {
348 pr_cont("disabled\n");
349 continue;
350 }
351
352 pr_cont("%pa-%pa", &lower, &upper);
353
354 if (attr & MIPS_MAAR_S)
355 pr_cont(" speculate");
356
357 pr_cont("\n");
358
359 /* Record the setup for use on secondary CPUs */
360 if (used <= ARRAY_SIZE(recorded.cfgs)) {
361 recorded.cfgs[recorded.used].lower = lower;
362 recorded.cfgs[recorded.used].upper = upper;
363 recorded.cfgs[recorded.used].attrs = attr;
364 recorded.used++;
365 }
366 }
367}
368
369#ifndef CONFIG_NEED_MULTIPLE_NODES
370int page_is_ram(unsigned long pagenr)
371{
372 int i;
373
374 for (i = 0; i < boot_mem_map.nr_map; i++) {
375 unsigned long addr, end;
376
377 switch (boot_mem_map.map[i].type) {
378 case BOOT_MEM_RAM:
379 case BOOT_MEM_INIT_RAM:
380 break;
381 default:
382 /* not usable memory */
383 continue;
384 }
385
386 addr = PFN_UP(boot_mem_map.map[i].addr);
387 end = PFN_DOWN(boot_mem_map.map[i].addr +
388 boot_mem_map.map[i].size);
389
390 if (pagenr >= addr && pagenr < end)
391 return 1;
392 }
393
394 return 0;
395}
396
397void __init paging_init(void)
398{
399 unsigned long max_zone_pfns[MAX_NR_ZONES];
400 unsigned long lastpfn __maybe_unused;
401
402 pagetable_init();
403
404#ifdef CONFIG_HIGHMEM
405 kmap_init();
406#endif
407#ifdef CONFIG_ZONE_DMA
408 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
409#endif
410#ifdef CONFIG_ZONE_DMA32
411 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
412#endif
413 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
414 lastpfn = max_low_pfn;
415#ifdef CONFIG_HIGHMEM
416 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
417 lastpfn = highend_pfn;
418
419 if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
420 printk(KERN_WARNING "This processor doesn't support highmem."
421 " %ldk highmem ignored\n",
422 (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
423 max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
424 lastpfn = max_low_pfn;
425 }
426#endif
427
428 free_area_init_nodes(max_zone_pfns);
429}
430
431#ifdef CONFIG_64BIT
432static struct kcore_list kcore_kseg0;
433#endif
434
435static inline void mem_init_free_highmem(void)
436{
437#ifdef CONFIG_HIGHMEM
438 unsigned long tmp;
439
440 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
441 struct page *page = pfn_to_page(tmp);
442
443 if (!page_is_ram(tmp))
444 SetPageReserved(page);
445 else
446 free_highmem_page(page);
447 }
448#endif
449}
450
451void __init mem_init(void)
452{
453#ifdef CONFIG_HIGHMEM
454#ifdef CONFIG_DISCONTIGMEM
455#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
456#endif
457 max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
458#else
459 max_mapnr = max_low_pfn;
460#endif
461 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
462
463 maar_init();
464 free_all_bootmem();
465 setup_zero_pages(); /* Setup zeroed pages. */
466 mem_init_free_highmem();
467 mem_init_print_info(NULL);
468
469#ifdef CONFIG_64BIT
470 if ((unsigned long) &_text > (unsigned long) CKSEG0)
471 /* The -4 is a hack so that user tools don't have to handle
472 the overflow. */
473 kclist_add(&kcore_kseg0, (void *) CKSEG0,
474 0x80000000 - 4, KCORE_TEXT);
475#endif
476}
477#endif /* !CONFIG_NEED_MULTIPLE_NODES */
478
479void free_init_pages(const char *what, unsigned long begin, unsigned long end)
480{
481 unsigned long pfn;
482
483 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
484 struct page *page = pfn_to_page(pfn);
485 void *addr = phys_to_virt(PFN_PHYS(pfn));
486
487 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
488 free_reserved_page(page);
489 }
490 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
491}
492
493#ifdef CONFIG_BLK_DEV_INITRD
494void free_initrd_mem(unsigned long start, unsigned long end)
495{
496 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
497 "initrd");
498}
499#endif
500
501void (*free_init_pages_eva)(void *begin, void *end) = NULL;
502
503void __init_refok free_initmem(void)
504{
505 prom_free_prom_memory();
506 /*
507 * Let the platform define a specific function to free the
508 * init section since EVA may have used any possible mapping
509 * between virtual and physical addresses.
510 */
511 if (free_init_pages_eva)
512 free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
513 else
514 free_initmem_default(POISON_FREE_INITMEM);
515}
516
517#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
518unsigned long pgd_current[NR_CPUS];
519#endif
520
521/*
522 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
523 * are constants. So we use the variants from asm-offset.h until that gcc
524 * will officially be retired.
525 *
526 * Align swapper_pg_dir in to 64K, allows its address to be loaded
527 * with a single LUI instruction in the TLB handlers. If we used
528 * __aligned(64K), its size would get rounded up to the alignment
529 * size, and waste space. So we place it in its own section and align
530 * it in the linker script.
531 */
532pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
533#ifndef __PAGETABLE_PMD_FOLDED
534pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
535#endif
536pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;