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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "skeleton.dtsi"
5
6#include <dt-bindings/clock/qcom,gcc-apq8084.h>
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10 model = "Qualcomm APQ 8084";
11 compatible = "qcom,apq8084";
12 interrupt-parent = <&intc>;
13
14 reserved-memory {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18
19 smem_mem: smem_region@fa00000 {
20 reg = <0xfa00000 0x200000>;
21 no-map;
22 };
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "qcom,krait";
32 reg = <0>;
33 enable-method = "qcom,kpss-acc-v2";
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc0>;
36 qcom,saw = <&saw0>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "qcom,krait";
43 reg = <1>;
44 enable-method = "qcom,kpss-acc-v2";
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc1>;
47 qcom,saw = <&saw1>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
50
51 cpu@2 {
52 device_type = "cpu";
53 compatible = "qcom,krait";
54 reg = <2>;
55 enable-method = "qcom,kpss-acc-v2";
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc2>;
58 qcom,saw = <&saw2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 cpu@3 {
63 device_type = "cpu";
64 compatible = "qcom,krait";
65 reg = <3>;
66 enable-method = "qcom,kpss-acc-v2";
67 next-level-cache = <&L2>;
68 qcom,acc = <&acc3>;
69 qcom,saw = <&saw3>;
70 cpu-idle-states = <&CPU_SPC>;
71 };
72
73 L2: l2-cache {
74 compatible = "qcom,arch-cache";
75 cache-level = <2>;
76 qcom,saw = <&saw_l2>;
77 };
78
79 idle-states {
80 CPU_SPC: spc {
81 compatible = "qcom,idle-state-spc",
82 "arm,idle-state";
83 entry-latency-us = <150>;
84 exit-latency-us = <200>;
85 min-residency-us = <2000>;
86 };
87 };
88 };
89
90 firmware {
91 scm {
92 compatible = "qcom,scm";
93 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
94 clock-names = "core", "bus", "iface";
95 };
96 };
97
98 thermal-zones {
99 cpu-thermal0 {
100 polling-delay-passive = <250>;
101 polling-delay = <1000>;
102
103 thermal-sensors = <&tsens 5>;
104
105 trips {
106 cpu_alert0: trip0 {
107 temperature = <75000>;
108 hysteresis = <2000>;
109 type = "passive";
110 };
111 cpu_crit0: trip1 {
112 temperature = <110000>;
113 hysteresis = <2000>;
114 type = "critical";
115 };
116 };
117 };
118
119 cpu-thermal1 {
120 polling-delay-passive = <250>;
121 polling-delay = <1000>;
122
123 thermal-sensors = <&tsens 6>;
124
125 trips {
126 cpu_alert1: trip0 {
127 temperature = <75000>;
128 hysteresis = <2000>;
129 type = "passive";
130 };
131 cpu_crit1: trip1 {
132 temperature = <110000>;
133 hysteresis = <2000>;
134 type = "critical";
135 };
136 };
137 };
138
139 cpu-thermal2 {
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
142
143 thermal-sensors = <&tsens 7>;
144
145 trips {
146 cpu_alert2: trip0 {
147 temperature = <75000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
151 cpu_crit2: trip1 {
152 temperature = <110000>;
153 hysteresis = <2000>;
154 type = "critical";
155 };
156 };
157 };
158
159 cpu-thermal3 {
160 polling-delay-passive = <250>;
161 polling-delay = <1000>;
162
163 thermal-sensors = <&tsens 8>;
164
165 trips {
166 cpu_alert3: trip0 {
167 temperature = <75000>;
168 hysteresis = <2000>;
169 type = "passive";
170 };
171 cpu_crit3: trip1 {
172 temperature = <110000>;
173 hysteresis = <2000>;
174 type = "critical";
175 };
176 };
177 };
178 };
179
180 cpu-pmu {
181 compatible = "qcom,krait-pmu";
182 interrupts = <1 7 0xf04>;
183 };
184
185 clocks {
186 xo_board: xo_board {
187 compatible = "fixed-clock";
188 #clock-cells = <0>;
189 clock-frequency = <19200000>;
190 };
191
192 sleep_clk: sleep_clk {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <32768>;
196 };
197 };
198
199 timer {
200 compatible = "arm,armv7-timer";
201 interrupts = <1 2 0xf08>,
202 <1 3 0xf08>,
203 <1 4 0xf08>,
204 <1 1 0xf08>;
205 clock-frequency = <19200000>;
206 };
207
208 smem {
209 compatible = "qcom,smem";
210
211 qcom,rpm-msg-ram = <&rpm_msg_ram>;
212 memory-region = <&smem_mem>;
213
214 hwlocks = <&tcsr_mutex 3>;
215 };
216
217 soc: soc {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges;
221 compatible = "simple-bus";
222
223 intc: interrupt-controller@f9000000 {
224 compatible = "qcom,msm-qgic2";
225 interrupt-controller;
226 #interrupt-cells = <3>;
227 reg = <0xf9000000 0x1000>,
228 <0xf9002000 0x1000>;
229 };
230
231 apcs: syscon@f9011000 {
232 compatible = "syscon";
233 reg = <0xf9011000 0x1000>;
234 };
235
236 qfprom: qfprom@fc4bc000 {
237 #address-cells = <1>;
238 #size-cells = <1>;
239 compatible = "qcom,qfprom";
240 reg = <0xfc4bc000 0x1000>;
241 tsens_calib: calib@d0 {
242 reg = <0xd0 0x18>;
243 };
244 tsens_backup: backup@440 {
245 reg = <0x440 0x10>;
246 };
247 };
248
249 tsens: thermal-sensor@fc4a8000 {
250 compatible = "qcom,msm8974-tsens";
251 reg = <0xfc4a8000 0x2000>;
252 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
253 nvmem-cell-names = "calib", "calib_backup";
254 #thermal-sensor-cells = <1>;
255 };
256
257 timer@f9020000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges;
261 compatible = "arm,armv7-timer-mem";
262 reg = <0xf9020000 0x1000>;
263 clock-frequency = <19200000>;
264
265 frame@f9021000 {
266 frame-number = <0>;
267 interrupts = <0 8 0x4>,
268 <0 7 0x4>;
269 reg = <0xf9021000 0x1000>,
270 <0xf9022000 0x1000>;
271 };
272
273 frame@f9023000 {
274 frame-number = <1>;
275 interrupts = <0 9 0x4>;
276 reg = <0xf9023000 0x1000>;
277 status = "disabled";
278 };
279
280 frame@f9024000 {
281 frame-number = <2>;
282 interrupts = <0 10 0x4>;
283 reg = <0xf9024000 0x1000>;
284 status = "disabled";
285 };
286
287 frame@f9025000 {
288 frame-number = <3>;
289 interrupts = <0 11 0x4>;
290 reg = <0xf9025000 0x1000>;
291 status = "disabled";
292 };
293
294 frame@f9026000 {
295 frame-number = <4>;
296 interrupts = <0 12 0x4>;
297 reg = <0xf9026000 0x1000>;
298 status = "disabled";
299 };
300
301 frame@f9027000 {
302 frame-number = <5>;
303 interrupts = <0 13 0x4>;
304 reg = <0xf9027000 0x1000>;
305 status = "disabled";
306 };
307
308 frame@f9028000 {
309 frame-number = <6>;
310 interrupts = <0 14 0x4>;
311 reg = <0xf9028000 0x1000>;
312 status = "disabled";
313 };
314 };
315
316 saw0: power-controller@f9089000 {
317 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
318 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
319 };
320
321 saw1: power-controller@f9099000 {
322 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
323 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
324 };
325
326 saw2: power-controller@f90a9000 {
327 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
328 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
329 };
330
331 saw3: power-controller@f90b9000 {
332 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
333 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
334 };
335
336 saw_l2: power-controller@f9012000 {
337 compatible = "qcom,saw2";
338 reg = <0xf9012000 0x1000>;
339 regulator;
340 };
341
342 acc0: clock-controller@f9088000 {
343 compatible = "qcom,kpss-acc-v2";
344 reg = <0xf9088000 0x1000>,
345 <0xf9008000 0x1000>;
346 };
347
348 acc1: clock-controller@f9098000 {
349 compatible = "qcom,kpss-acc-v2";
350 reg = <0xf9098000 0x1000>,
351 <0xf9008000 0x1000>;
352 };
353
354 acc2: clock-controller@f90a8000 {
355 compatible = "qcom,kpss-acc-v2";
356 reg = <0xf90a8000 0x1000>,
357 <0xf9008000 0x1000>;
358 };
359
360 acc3: clock-controller@f90b8000 {
361 compatible = "qcom,kpss-acc-v2";
362 reg = <0xf90b8000 0x1000>,
363 <0xf9008000 0x1000>;
364 };
365
366 restart@fc4ab000 {
367 compatible = "qcom,pshold";
368 reg = <0xfc4ab000 0x4>;
369 };
370
371 gcc: clock-controller@fc400000 {
372 compatible = "qcom,gcc-apq8084";
373 #clock-cells = <1>;
374 #reset-cells = <1>;
375 #power-domain-cells = <1>;
376 reg = <0xfc400000 0x4000>;
377 };
378
379 tcsr_mutex_regs: syscon@fd484000 {
380 compatible = "syscon";
381 reg = <0xfd484000 0x2000>;
382 };
383
384 tcsr_mutex: hwlock {
385 compatible = "qcom,tcsr-mutex";
386 syscon = <&tcsr_mutex_regs 0 0x80>;
387 #hwlock-cells = <1>;
388 };
389
390 rpm_msg_ram: memory@fc428000 {
391 compatible = "qcom,rpm-msg-ram";
392 reg = <0xfc428000 0x4000>;
393 };
394
395 tlmm: pinctrl@fd510000 {
396 compatible = "qcom,apq8084-pinctrl";
397 reg = <0xfd510000 0x4000>;
398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 interrupts = <0 208 0>;
403 };
404
405 blsp2_uart2: serial@f995e000 {
406 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
407 reg = <0xf995e000 0x1000>;
408 interrupts = <0 114 0x0>;
409 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
410 clock-names = "core", "iface";
411 status = "disabled";
412 };
413
414 sdhci@f9824900 {
415 compatible = "qcom,sdhci-msm-v4";
416 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
417 reg-names = "hc_mem", "core_mem";
418 interrupts = <0 123 0>, <0 138 0>;
419 interrupt-names = "hc_irq", "pwr_irq";
420 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
421 <&gcc GCC_SDCC1_AHB_CLK>,
422 <&xo_board>;
423 clock-names = "core", "iface", "xo";
424 status = "disabled";
425 };
426
427 sdhci@f98a4900 {
428 compatible = "qcom,sdhci-msm-v4";
429 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
430 reg-names = "hc_mem", "core_mem";
431 interrupts = <0 125 0>, <0 221 0>;
432 interrupt-names = "hc_irq", "pwr_irq";
433 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
434 <&gcc GCC_SDCC2_AHB_CLK>,
435 <&xo_board>;
436 clock-names = "core", "iface", "xo";
437 status = "disabled";
438 };
439
440 spmi_bus: spmi@fc4cf000 {
441 compatible = "qcom,spmi-pmic-arb";
442 reg-names = "core", "intr", "cnfg";
443 reg = <0xfc4cf000 0x1000>,
444 <0xfc4cb000 0x1000>,
445 <0xfc4ca000 0x1000>;
446 interrupt-names = "periph_irq";
447 interrupts = <0 190 0>;
448 qcom,ee = <0>;
449 qcom,channel = <0>;
450 #address-cells = <2>;
451 #size-cells = <0>;
452 interrupt-controller;
453 #interrupt-cells = <4>;
454 };
455 };
456
457 smd {
458 compatible = "qcom,smd";
459
460 rpm {
461 interrupts = <0 168 1>;
462 qcom,ipc = <&apcs 8 0>;
463 qcom,smd-edge = <15>;
464
465 rpm_requests {
466 compatible = "qcom,rpm-apq8084";
467 qcom,smd-channels = "rpm_requests";
468
469 pma8084-regulators {
470 compatible = "qcom,rpm-pma8084-regulators";
471
472 pma8084_s1: s1 {};
473 pma8084_s2: s2 {};
474 pma8084_s3: s3 {};
475 pma8084_s4: s4 {};
476 pma8084_s5: s5 {};
477 pma8084_s6: s6 {};
478 pma8084_s7: s7 {};
479 pma8084_s8: s8 {};
480 pma8084_s9: s9 {};
481 pma8084_s10: s10 {};
482 pma8084_s11: s11 {};
483 pma8084_s12: s12 {};
484
485 pma8084_l1: l1 {};
486 pma8084_l2: l2 {};
487 pma8084_l3: l3 {};
488 pma8084_l4: l4 {};
489 pma8084_l5: l5 {};
490 pma8084_l6: l6 {};
491 pma8084_l7: l7 {};
492 pma8084_l8: l8 {};
493 pma8084_l9: l9 {};
494 pma8084_l10: l10 {};
495 pma8084_l11: l11 {};
496 pma8084_l12: l12 {};
497 pma8084_l13: l13 {};
498 pma8084_l14: l14 {};
499 pma8084_l15: l15 {};
500 pma8084_l16: l16 {};
501 pma8084_l17: l17 {};
502 pma8084_l18: l18 {};
503 pma8084_l19: l19 {};
504 pma8084_l20: l20 {};
505 pma8084_l21: l21 {};
506 pma8084_l22: l22 {};
507 pma8084_l23: l23 {};
508 pma8084_l24: l24 {};
509 pma8084_l25: l25 {};
510 pma8084_l26: l26 {};
511 pma8084_l27: l27 {};
512
513 pma8084_lvs1: lvs1 {};
514 pma8084_lvs2: lvs2 {};
515 pma8084_lvs3: lvs3 {};
516 pma8084_lvs4: lvs4 {};
517
518 pma8084_5vs1: 5vs1 {};
519 };
520 };
521 };
522 };
523};
1/dts-v1/;
2
3#include "skeleton.dtsi"
4
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 model = "Qualcomm APQ 8084";
10 compatible = "qcom,apq8084";
11 interrupt-parent = <&intc>;
12
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 smem_mem: smem_region@fa00000 {
19 reg = <0xfa00000 0x200000>;
20 no-map;
21 };
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "qcom,krait";
31 reg = <0>;
32 enable-method = "qcom,kpss-acc-v2";
33 next-level-cache = <&L2>;
34 qcom,acc = <&acc0>;
35 qcom,saw = <&saw0>;
36 cpu-idle-states = <&CPU_SPC>;
37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "qcom,krait";
42 reg = <1>;
43 enable-method = "qcom,kpss-acc-v2";
44 next-level-cache = <&L2>;
45 qcom,acc = <&acc1>;
46 qcom,saw = <&saw1>;
47 cpu-idle-states = <&CPU_SPC>;
48 };
49
50 cpu@2 {
51 device_type = "cpu";
52 compatible = "qcom,krait";
53 reg = <2>;
54 enable-method = "qcom,kpss-acc-v2";
55 next-level-cache = <&L2>;
56 qcom,acc = <&acc2>;
57 qcom,saw = <&saw2>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 cpu@3 {
62 device_type = "cpu";
63 compatible = "qcom,krait";
64 reg = <3>;
65 enable-method = "qcom,kpss-acc-v2";
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc3>;
68 qcom,saw = <&saw3>;
69 cpu-idle-states = <&CPU_SPC>;
70 };
71
72 L2: l2-cache {
73 compatible = "qcom,arch-cache";
74 cache-level = <2>;
75 qcom,saw = <&saw_l2>;
76 };
77
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 entry-latency-us = <150>;
83 exit-latency-us = <200>;
84 min-residency-us = <2000>;
85 };
86 };
87 };
88
89 cpu-pmu {
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 7 0xf04>;
92 };
93
94 clocks {
95 xo_board {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <19200000>;
99 };
100
101 sleep_clk {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <32768>;
105 };
106 };
107
108 timer {
109 compatible = "arm,armv7-timer";
110 interrupts = <1 2 0xf08>,
111 <1 3 0xf08>,
112 <1 4 0xf08>,
113 <1 1 0xf08>;
114 clock-frequency = <19200000>;
115 };
116
117 smem {
118 compatible = "qcom,smem";
119
120 qcom,rpm-msg-ram = <&rpm_msg_ram>;
121 memory-region = <&smem_mem>;
122
123 hwlocks = <&tcsr_mutex 3>;
124 };
125
126 soc: soc {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges;
130 compatible = "simple-bus";
131
132 intc: interrupt-controller@f9000000 {
133 compatible = "qcom,msm-qgic2";
134 interrupt-controller;
135 #interrupt-cells = <3>;
136 reg = <0xf9000000 0x1000>,
137 <0xf9002000 0x1000>;
138 };
139
140 apcs: syscon@f9011000 {
141 compatible = "syscon";
142 reg = <0xf9011000 0x1000>;
143 };
144
145 timer@f9020000 {
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges;
149 compatible = "arm,armv7-timer-mem";
150 reg = <0xf9020000 0x1000>;
151 clock-frequency = <19200000>;
152
153 frame@f9021000 {
154 frame-number = <0>;
155 interrupts = <0 8 0x4>,
156 <0 7 0x4>;
157 reg = <0xf9021000 0x1000>,
158 <0xf9022000 0x1000>;
159 };
160
161 frame@f9023000 {
162 frame-number = <1>;
163 interrupts = <0 9 0x4>;
164 reg = <0xf9023000 0x1000>;
165 status = "disabled";
166 };
167
168 frame@f9024000 {
169 frame-number = <2>;
170 interrupts = <0 10 0x4>;
171 reg = <0xf9024000 0x1000>;
172 status = "disabled";
173 };
174
175 frame@f9025000 {
176 frame-number = <3>;
177 interrupts = <0 11 0x4>;
178 reg = <0xf9025000 0x1000>;
179 status = "disabled";
180 };
181
182 frame@f9026000 {
183 frame-number = <4>;
184 interrupts = <0 12 0x4>;
185 reg = <0xf9026000 0x1000>;
186 status = "disabled";
187 };
188
189 frame@f9027000 {
190 frame-number = <5>;
191 interrupts = <0 13 0x4>;
192 reg = <0xf9027000 0x1000>;
193 status = "disabled";
194 };
195
196 frame@f9028000 {
197 frame-number = <6>;
198 interrupts = <0 14 0x4>;
199 reg = <0xf9028000 0x1000>;
200 status = "disabled";
201 };
202 };
203
204 saw0: power-controller@f9089000 {
205 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
206 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
207 };
208
209 saw1: power-controller@f9099000 {
210 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
211 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
212 };
213
214 saw2: power-controller@f90a9000 {
215 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
216 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
217 };
218
219 saw3: power-controller@f90b9000 {
220 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
221 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
222 };
223
224 saw_l2: power-controller@f9012000 {
225 compatible = "qcom,saw2";
226 reg = <0xf9012000 0x1000>;
227 regulator;
228 };
229
230 acc0: clock-controller@f9088000 {
231 compatible = "qcom,kpss-acc-v2";
232 reg = <0xf9088000 0x1000>,
233 <0xf9008000 0x1000>;
234 };
235
236 acc1: clock-controller@f9098000 {
237 compatible = "qcom,kpss-acc-v2";
238 reg = <0xf9098000 0x1000>,
239 <0xf9008000 0x1000>;
240 };
241
242 acc2: clock-controller@f90a8000 {
243 compatible = "qcom,kpss-acc-v2";
244 reg = <0xf90a8000 0x1000>,
245 <0xf9008000 0x1000>;
246 };
247
248 acc3: clock-controller@f90b8000 {
249 compatible = "qcom,kpss-acc-v2";
250 reg = <0xf90b8000 0x1000>,
251 <0xf9008000 0x1000>;
252 };
253
254 restart@fc4ab000 {
255 compatible = "qcom,pshold";
256 reg = <0xfc4ab000 0x4>;
257 };
258
259 gcc: clock-controller@fc400000 {
260 compatible = "qcom,gcc-apq8084";
261 #clock-cells = <1>;
262 #reset-cells = <1>;
263 #power-domain-cells = <1>;
264 reg = <0xfc400000 0x4000>;
265 };
266
267 tcsr_mutex_regs: syscon@fd484000 {
268 compatible = "syscon";
269 reg = <0xfd484000 0x2000>;
270 };
271
272 tcsr_mutex: hwlock {
273 compatible = "qcom,tcsr-mutex";
274 syscon = <&tcsr_mutex_regs 0 0x80>;
275 #hwlock-cells = <1>;
276 };
277
278 rpm_msg_ram: memory@fc428000 {
279 compatible = "qcom,rpm-msg-ram";
280 reg = <0xfc428000 0x4000>;
281 };
282
283 tlmm: pinctrl@fd510000 {
284 compatible = "qcom,apq8084-pinctrl";
285 reg = <0xfd510000 0x4000>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 interrupts = <0 208 0>;
291 };
292
293 blsp2_uart2: serial@f995e000 {
294 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
295 reg = <0xf995e000 0x1000>;
296 interrupts = <0 114 0x0>;
297 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
298 clock-names = "core", "iface";
299 status = "disabled";
300 };
301
302 sdhci@f9824900 {
303 compatible = "qcom,sdhci-msm-v4";
304 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
305 reg-names = "hc_mem", "core_mem";
306 interrupts = <0 123 0>, <0 138 0>;
307 interrupt-names = "hc_irq", "pwr_irq";
308 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
309 clock-names = "core", "iface";
310 status = "disabled";
311 };
312
313 sdhci@f98a4900 {
314 compatible = "qcom,sdhci-msm-v4";
315 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
316 reg-names = "hc_mem", "core_mem";
317 interrupts = <0 125 0>, <0 221 0>;
318 interrupt-names = "hc_irq", "pwr_irq";
319 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
320 clock-names = "core", "iface";
321 status = "disabled";
322 };
323
324 spmi_bus: spmi@fc4cf000 {
325 compatible = "qcom,spmi-pmic-arb";
326 reg-names = "core", "intr", "cnfg";
327 reg = <0xfc4cf000 0x1000>,
328 <0xfc4cb000 0x1000>,
329 <0xfc4ca000 0x1000>;
330 interrupt-names = "periph_irq";
331 interrupts = <0 190 0>;
332 qcom,ee = <0>;
333 qcom,channel = <0>;
334 #address-cells = <2>;
335 #size-cells = <0>;
336 interrupt-controller;
337 #interrupt-cells = <4>;
338 };
339 };
340
341 smd {
342 compatible = "qcom,smd";
343
344 rpm {
345 interrupts = <0 168 1>;
346 qcom,ipc = <&apcs 8 0>;
347 qcom,smd-edge = <15>;
348
349 rpm_requests {
350 compatible = "qcom,rpm-apq8084";
351 qcom,smd-channels = "rpm_requests";
352
353 pma8084-regulators {
354 compatible = "qcom,rpm-pma8084-regulators";
355
356 pma8084_s1: s1 {};
357 pma8084_s2: s2 {};
358 pma8084_s3: s3 {};
359 pma8084_s4: s4 {};
360 pma8084_s5: s5 {};
361 pma8084_s6: s6 {};
362 pma8084_s7: s7 {};
363 pma8084_s8: s8 {};
364 pma8084_s9: s9 {};
365 pma8084_s10: s10 {};
366 pma8084_s11: s11 {};
367 pma8084_s12: s12 {};
368
369 pma8084_l1: l1 {};
370 pma8084_l2: l2 {};
371 pma8084_l3: l3 {};
372 pma8084_l4: l4 {};
373 pma8084_l5: l5 {};
374 pma8084_l6: l6 {};
375 pma8084_l7: l7 {};
376 pma8084_l8: l8 {};
377 pma8084_l9: l9 {};
378 pma8084_l10: l10 {};
379 pma8084_l11: l11 {};
380 pma8084_l12: l12 {};
381 pma8084_l13: l13 {};
382 pma8084_l14: l14 {};
383 pma8084_l15: l15 {};
384 pma8084_l16: l16 {};
385 pma8084_l17: l17 {};
386 pma8084_l18: l18 {};
387 pma8084_l19: l19 {};
388 pma8084_l20: l20 {};
389 pma8084_l21: l21 {};
390 pma8084_l22: l22 {};
391 pma8084_l23: l23 {};
392 pma8084_l24: l24 {};
393 pma8084_l25: l25 {};
394 pma8084_l26: l26 {};
395 pma8084_l27: l27 {};
396
397 pma8084_lvs1: lvs1 {};
398 pma8084_lvs2: lvs2 {};
399 pma8084_lvs3: lvs3 {};
400 pma8084_lvs4: lvs4 {};
401
402 pma8084_5vs1: 5vs1 {};
403 };
404 };
405 };
406 };
407};