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1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
3 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "omap34xx.dtsi"
13#include <dt-bindings/input/input.h>
14
15/*
16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * for omap AES HW crypto support. When linux kernel try to access memory of AES
18 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
19 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
20 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
22 * but it is not widely used and to prevent kernel crash rather AES is disabled.
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
24 */
25&aes {
26 status = "disabled";
27};
28
29/ {
30 model = "Nokia N900";
31 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
32
33 aliases {
34 i2c0;
35 i2c1 = &i2c1;
36 i2c2 = &i2c2;
37 i2c3 = &i2c3;
38 display0 = &lcd;
39 display1 = &tv;
40 };
41
42 cpus {
43 cpu@0 {
44 cpu0-supply = <&vcc>;
45 };
46 };
47
48 leds {
49 compatible = "gpio-leds";
50 heartbeat {
51 label = "debug::sleep";
52 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
53 linux,default-trigger = "default-on";
54 pinctrl-names = "default";
55 pinctrl-0 = <&debug_leds>;
56 };
57 };
58
59 memory@80000000 {
60 device_type = "memory";
61 reg = <0x80000000 0x10000000>; /* 256 MB */
62 };
63
64 gpio_keys {
65 compatible = "gpio-keys";
66
67 camera_lens_cover {
68 label = "Camera Lens Cover";
69 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
70 linux,input-type = <EV_SW>;
71 linux,code = <SW_CAMERA_LENS_COVER>;
72 linux,can-disable;
73 };
74
75 camera_focus {
76 label = "Camera Focus";
77 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
78 linux,code = <KEY_CAMERA_FOCUS>;
79 linux,can-disable;
80 };
81
82 camera_capture {
83 label = "Camera Capture";
84 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
85 linux,code = <KEY_CAMERA>;
86 linux,can-disable;
87 };
88
89 lock_button {
90 label = "Lock Button";
91 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
92 linux,code = <KEY_SCREENLOCK>;
93 linux,can-disable;
94 };
95
96 keypad_slide {
97 label = "Keypad Slide";
98 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
99 linux,input-type = <EV_SW>;
100 linux,code = <SW_KEYPAD_SLIDE>;
101 linux,can-disable;
102 };
103
104 proximity_sensor {
105 label = "Proximity Sensor";
106 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
107 linux,input-type = <EV_SW>;
108 linux,code = <SW_FRONT_PROXIMITY>;
109 linux,can-disable;
110 };
111 };
112
113 isp1707: isp1707 {
114 compatible = "nxp,isp1707";
115 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
116 usb-phy = <&usb2_phy>;
117 };
118
119 tv: connector {
120 compatible = "composite-video-connector";
121 label = "tv";
122
123 port {
124 tv_connector_in: endpoint {
125 remote-endpoint = <&venc_out>;
126 };
127 };
128 };
129
130 sound: n900-audio {
131 compatible = "nokia,n900-audio";
132
133 nokia,cpu-dai = <&mcbsp2>;
134 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
135 nokia,headphone-amplifier = <&tpa6130a2>;
136
137 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
138 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
139 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
140 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
141 };
142
143 battery: n900-battery {
144 compatible = "nokia,n900-battery";
145 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
146 io-channel-names = "temp", "bsi", "vbat";
147 };
148
149 pwm9: dmtimer-pwm {
150 compatible = "ti,omap-dmtimer-pwm";
151 #pwm-cells = <3>;
152 ti,timers = <&timer9>;
153 ti,clock-source = <0x00>; /* timer_sys_ck */
154 };
155
156 ir: n900-ir {
157 compatible = "nokia,n900-ir";
158 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
159 };
160
161 /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
162 vctcxo: vctcxo {
163 compatible = "fixed-clock";
164 #clock-cells = <0>;
165 clock-frequency = <38400000>;
166 };
167};
168
169&isp {
170 vdds_csib-supply = <&vaux2>;
171
172 pinctrl-names = "default";
173 pinctrl-0 = <&camera_pins>;
174
175 ports {
176 port@1 {
177 reg = <1>;
178
179 csi_isp: endpoint {
180 remote-endpoint = <&csi_cam1>;
181 bus-type = <3>; /* CCP2 */
182 clock-lanes = <1>;
183 data-lanes = <0>;
184 lane-polarity = <0 0>;
185 /* Select strobe = <1> for back camera, <0> for front camera */
186 strobe = <1>;
187 };
188 };
189 };
190};
191
192&omap3_pmx_core {
193 pinctrl-names = "default";
194
195 uart2_pins: pinmux_uart2_pins {
196 pinctrl-single,pins = <
197 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
198 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
199 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
200 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
201 >;
202 };
203
204 uart3_pins: pinmux_uart3_pins {
205 pinctrl-single,pins = <
206 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
207 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
208 >;
209 };
210
211 ethernet_pins: pinmux_ethernet_pins {
212 pinctrl-single,pins = <
213 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
214 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
215 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
216 >;
217 };
218
219 gpmc_pins: pinmux_gpmc_pins {
220 pinctrl-single,pins = <
221
222 /* address lines */
223 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
224 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
225 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
226
227 /* data lines, gpmc_d0..d7 not muxable according to TRM */
228 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
229 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
230 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
231 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
232 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
233 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
234 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
235 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
236
237 /*
238 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
239 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
240 */
241 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
242 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
243 >;
244 };
245
246 i2c1_pins: pinmux_i2c1_pins {
247 pinctrl-single,pins = <
248 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
249 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
250 >;
251 };
252
253 i2c2_pins: pinmux_i2c2_pins {
254 pinctrl-single,pins = <
255 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
256 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
257 >;
258 };
259
260 i2c3_pins: pinmux_i2c3_pins {
261 pinctrl-single,pins = <
262 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
263 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
264 >;
265 };
266
267 debug_leds: pinmux_debug_led_pins {
268 pinctrl-single,pins = <
269 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
270 >;
271 };
272
273 mcspi4_pins: pinmux_mcspi4_pins {
274 pinctrl-single,pins = <
275 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
276 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
277 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
278 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
279 >;
280 };
281
282 mmc1_pins: pinmux_mmc1_pins {
283 pinctrl-single,pins = <
284 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
285 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
286 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
287 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
288 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
289 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
290 >;
291 };
292
293 mmc2_pins: pinmux_mmc2_pins {
294 pinctrl-single,pins = <
295 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
296 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
297 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
298 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
299 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
300 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
301 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
302 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
303 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
304 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
305 >;
306 };
307
308 acx565akm_pins: pinmux_acx565akm_pins {
309 pinctrl-single,pins = <
310 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
311 >;
312 };
313
314 dss_sdi_pins: pinmux_dss_sdi_pins {
315 pinctrl-single,pins = <
316 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
317 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
318 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
319 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
320
321 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
322 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
323 >;
324 };
325
326 wl1251_pins: pinmux_wl1251 {
327 pinctrl-single,pins = <
328 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
329 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
330 >;
331 };
332
333 ssi_pins: pinmux_ssi {
334 pinctrl-single,pins = <
335 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
336 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
337 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
338 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
339 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
340 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
341 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
342 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
343 >;
344 };
345
346 modem_pins: pinmux_modem {
347 pinctrl-single,pins = <
348 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
349 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
350 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
351 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
352 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
353 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
354 >;
355 };
356
357 camera_pins: pinmux_camera {
358 pinctrl-single,pins = <
359 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
360 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
361 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
362 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
363 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
364 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
365 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
366 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
367 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
368 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
369 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
370 >;
371 };
372};
373
374&i2c1 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c1_pins>;
377
378 clock-frequency = <2200000>;
379
380 twl: twl@48 {
381 reg = <0x48>;
382 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
383 interrupt-parent = <&intc>;
384 };
385};
386
387#include "twl4030.dtsi"
388#include "twl4030_omap3.dtsi"
389
390&vaux1 {
391 regulator-name = "V28";
392 regulator-min-microvolt = <2800000>;
393 regulator-max-microvolt = <2800000>;
394 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
395 regulator-always-on; /* due to battery cover sensor */
396};
397
398&vaux2 {
399 regulator-name = "VCSI";
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
402 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
403};
404
405&vaux3 {
406 regulator-name = "VMMC2_30";
407 regulator-min-microvolt = <2800000>;
408 regulator-max-microvolt = <3000000>;
409 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
410};
411
412&vaux4 {
413 regulator-name = "VCAM_ANA_28";
414 regulator-min-microvolt = <2800000>;
415 regulator-max-microvolt = <2800000>;
416 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
417};
418
419&vmmc1 {
420 regulator-name = "VMMC1";
421 regulator-min-microvolt = <1850000>;
422 regulator-max-microvolt = <3150000>;
423 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
424};
425
426&vmmc2 {
427 regulator-name = "V28_A";
428 regulator-min-microvolt = <2800000>;
429 regulator-max-microvolt = <3000000>;
430 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
431 regulator-always-on; /* due VIO leak to AIC34 VDDs */
432};
433
434&vpll1 {
435 regulator-name = "VPLL";
436 regulator-min-microvolt = <1800000>;
437 regulator-max-microvolt = <1800000>;
438 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
439 regulator-always-on;
440};
441
442&vpll2 {
443 regulator-name = "VSDI_CSI";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
447 regulator-always-on;
448};
449
450&vsim {
451 regulator-name = "VMMC2_IO_18";
452 regulator-min-microvolt = <1800000>;
453 regulator-max-microvolt = <1800000>;
454 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
455};
456
457&vio {
458 regulator-name = "VIO";
459 regulator-min-microvolt = <1800000>;
460 regulator-max-microvolt = <1800000>;
461};
462
463&vintana1 {
464 regulator-name = "VINTANA1";
465 /* fixed to 1500000 */
466 regulator-always-on;
467};
468
469&vintana2 {
470 regulator-name = "VINTANA2";
471 regulator-min-microvolt = <2750000>;
472 regulator-max-microvolt = <2750000>;
473 regulator-always-on;
474};
475
476&vintdig {
477 regulator-name = "VINTDIG";
478 /* fixed to 1500000 */
479 regulator-always-on;
480};
481
482&twl {
483 twl_audio: audio {
484 compatible = "ti,twl4030-audio";
485 ti,enable-vibra = <1>;
486 };
487
488 twl_power: power {
489 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
490 ti,use_poweroff;
491 };
492};
493
494&twl_keypad {
495 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
496 MATRIX_KEY(0x00, 0x01, KEY_O)
497 MATRIX_KEY(0x00, 0x02, KEY_P)
498 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
499 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
500 MATRIX_KEY(0x00, 0x06, KEY_A)
501 MATRIX_KEY(0x00, 0x07, KEY_S)
502
503 MATRIX_KEY(0x01, 0x00, KEY_W)
504 MATRIX_KEY(0x01, 0x01, KEY_D)
505 MATRIX_KEY(0x01, 0x02, KEY_F)
506 MATRIX_KEY(0x01, 0x03, KEY_G)
507 MATRIX_KEY(0x01, 0x04, KEY_H)
508 MATRIX_KEY(0x01, 0x05, KEY_J)
509 MATRIX_KEY(0x01, 0x06, KEY_K)
510 MATRIX_KEY(0x01, 0x07, KEY_L)
511
512 MATRIX_KEY(0x02, 0x00, KEY_E)
513 MATRIX_KEY(0x02, 0x01, KEY_DOT)
514 MATRIX_KEY(0x02, 0x02, KEY_UP)
515 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
516 MATRIX_KEY(0x02, 0x05, KEY_Z)
517 MATRIX_KEY(0x02, 0x06, KEY_X)
518 MATRIX_KEY(0x02, 0x07, KEY_C)
519 MATRIX_KEY(0x02, 0x08, KEY_F9)
520
521 MATRIX_KEY(0x03, 0x00, KEY_R)
522 MATRIX_KEY(0x03, 0x01, KEY_V)
523 MATRIX_KEY(0x03, 0x02, KEY_B)
524 MATRIX_KEY(0x03, 0x03, KEY_N)
525 MATRIX_KEY(0x03, 0x04, KEY_M)
526 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
527 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
528 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
529
530 MATRIX_KEY(0x04, 0x00, KEY_T)
531 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
532 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
533 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
534 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
535 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
536 MATRIX_KEY(0x04, 0x08, KEY_F10)
537
538 MATRIX_KEY(0x05, 0x00, KEY_Y)
539 MATRIX_KEY(0x05, 0x08, KEY_F11)
540
541 MATRIX_KEY(0x06, 0x00, KEY_U)
542
543 MATRIX_KEY(0x07, 0x00, KEY_I)
544 MATRIX_KEY(0x07, 0x01, KEY_F7)
545 MATRIX_KEY(0x07, 0x02, KEY_F8)
546 >;
547};
548
549&twl_gpio {
550 ti,pullups = <0x0>;
551 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
552};
553
554&i2c2 {
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c2_pins>;
557
558 clock-frequency = <100000>;
559
560 tlv320aic3x: tlv320aic3x@18 {
561 compatible = "ti,tlv320aic3x";
562 reg = <0x18>;
563 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
564 ai3x-gpio-func = <
565 0 /* AIC3X_GPIO1_FUNC_DISABLED */
566 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
567 >;
568
569 AVDD-supply = <&vmmc2>;
570 DRVDD-supply = <&vmmc2>;
571 IOVDD-supply = <&vio>;
572 DVDD-supply = <&vio>;
573
574 ai3x-micbias-vg = <1>;
575 };
576
577 tlv320aic3x_aux: tlv320aic3x@19 {
578 compatible = "ti,tlv320aic3x";
579 reg = <0x19>;
580 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
581
582 AVDD-supply = <&vmmc2>;
583 DRVDD-supply = <&vmmc2>;
584 IOVDD-supply = <&vio>;
585 DVDD-supply = <&vio>;
586
587 ai3x-micbias-vg = <2>;
588 };
589
590 tsl2563: tsl2563@29 {
591 compatible = "amstaos,tsl2563";
592 reg = <0x29>;
593
594 amstaos,cover-comp-gain = <16>;
595 };
596
597 adp1653: led-controller@30 {
598 compatible = "adi,adp1653";
599 reg = <0x30>;
600 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
601
602 flash {
603 flash-timeout-us = <500000>;
604 flash-max-microamp = <320000>;
605 led-max-microamp = <50000>;
606 };
607 indicator {
608 led-max-microamp = <17500>;
609 };
610 };
611
612 lp5523: lp5523@32 {
613 compatible = "national,lp5523";
614 reg = <0x32>;
615 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
616 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
617
618 chan0 {
619 chan-name = "lp5523:kb1";
620 led-cur = /bits/ 8 <50>;
621 max-cur = /bits/ 8 <100>;
622 };
623
624 chan1 {
625 chan-name = "lp5523:kb2";
626 led-cur = /bits/ 8 <50>;
627 max-cur = /bits/ 8 <100>;
628 };
629
630 chan2 {
631 chan-name = "lp5523:kb3";
632 led-cur = /bits/ 8 <50>;
633 max-cur = /bits/ 8 <100>;
634 };
635
636 chan3 {
637 chan-name = "lp5523:kb4";
638 led-cur = /bits/ 8 <50>;
639 max-cur = /bits/ 8 <100>;
640 };
641
642 chan4 {
643 chan-name = "lp5523:b";
644 led-cur = /bits/ 8 <50>;
645 max-cur = /bits/ 8 <100>;
646 };
647
648 chan5 {
649 chan-name = "lp5523:g";
650 led-cur = /bits/ 8 <50>;
651 max-cur = /bits/ 8 <100>;
652 };
653
654 chan6 {
655 chan-name = "lp5523:r";
656 led-cur = /bits/ 8 <50>;
657 max-cur = /bits/ 8 <100>;
658 };
659
660 chan7 {
661 chan-name = "lp5523:kb5";
662 led-cur = /bits/ 8 <50>;
663 max-cur = /bits/ 8 <100>;
664 };
665
666 chan8 {
667 chan-name = "lp5523:kb6";
668 led-cur = /bits/ 8 <50>;
669 max-cur = /bits/ 8 <100>;
670 };
671 };
672
673 bq27200: bq27200@55 {
674 compatible = "ti,bq27200";
675 reg = <0x55>;
676 power-supplies = <&bq24150a>;
677 };
678
679 /* Stereo headphone amplifier */
680 tpa6130a2: tpa6130a2@60 {
681 compatible = "ti,tpa6130a2";
682 reg = <0x60>;
683
684 Vdd-supply = <&vmmc2>;
685
686 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
687 };
688
689 si4713: si4713@63 {
690 compatible = "silabs,si4713";
691 reg = <0x63>;
692
693 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
694 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
695 vio-supply = <&vio>;
696 vdd-supply = <&vaux1>;
697 };
698
699 bq24150a: bq24150a@6b {
700 compatible = "ti,bq24150a";
701 reg = <0x6b>;
702
703 ti,current-limit = <100>;
704 ti,weak-battery-voltage = <3400>;
705 ti,battery-regulation-voltage = <4200>;
706 ti,charge-current = <650>;
707 ti,termination-current = <100>;
708 ti,resistor-sense = <68>;
709
710 ti,usb-charger-detection = <&isp1707>;
711 };
712};
713
714&i2c3 {
715 pinctrl-names = "default";
716 pinctrl-0 = <&i2c3_pins>;
717
718 clock-frequency = <400000>;
719
720 lis302dl: lis3lv02d@1d {
721 compatible = "st,lis3lv02d";
722 reg = <0x1d>;
723
724 Vdd-supply = <&vaux1>;
725 Vdd_IO-supply = <&vio>;
726
727 interrupt-parent = <&gpio6>;
728 interrupts = <21 20>; /* 181 and 180 */
729
730 /* click flags */
731 st,click-single-x;
732 st,click-single-y;
733 st,click-single-z;
734
735 /* Limits are 0.5g * value */
736 st,click-threshold-x = <8>;
737 st,click-threshold-y = <8>;
738 st,click-threshold-z = <10>;
739
740 /* Click must be longer than time limit */
741 st,click-time-limit = <9>;
742
743 /* Kind of debounce filter */
744 st,click-latency = <50>;
745
746 /* Interrupt line 2 for click detection */
747 st,irq2-click;
748
749 st,wakeup-x-hi;
750 st,wakeup-y-hi;
751 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
752
753 st,wakeup2-z-hi;
754 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
755
756 st,hipass1-disable;
757 st,hipass2-disable;
758
759 st,axis-x = <1>; /* LIS3_DEV_X */
760 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
761 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
762
763 st,min-limit-x = <(-32)>;
764 st,min-limit-y = <3>;
765 st,min-limit-z = <3>;
766
767 st,max-limit-x = <(-3)>;
768 st,max-limit-y = <32>;
769 st,max-limit-z = <32>;
770 };
771
772 cam1: camera@3e {
773 compatible = "toshiba,et8ek8";
774 reg = <0x3e>;
775
776 vana-supply = <&vaux4>;
777
778 clocks = <&isp 0>;
779 clock-names = "extclk";
780 clock-frequency = <9600000>;
781
782 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
783
784 lens-focus = <&ad5820>;
785
786 port {
787 csi_cam1: endpoint {
788 bus-type = <3>; /* CCP2 */
789 strobe = <1>;
790 clock-inv = <0>;
791 crc = <1>;
792
793 remote-endpoint = <&csi_isp>;
794 };
795 };
796 };
797
798 /* D/A converter for auto-focus */
799 ad5820: dac@c {
800 compatible = "adi,ad5820";
801 reg = <0x0c>;
802
803 VANA-supply = <&vaux4>;
804
805 #io-channel-cells = <0>;
806 };
807};
808
809&mmc1 {
810 pinctrl-names = "default";
811 pinctrl-0 = <&mmc1_pins>;
812 vmmc-supply = <&vmmc1>;
813 bus-width = <4>;
814 /* For debugging, it is often good idea to remove this GPIO.
815 It means you can remove back cover (to reboot by removing
816 battery) and still use the MMC card. */
817 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
818};
819
820/* most boards use vaux3, only some old versions use vmmc2 instead */
821&mmc2 {
822 pinctrl-names = "default";
823 pinctrl-0 = <&mmc2_pins>;
824 vmmc-supply = <&vaux3>;
825 vqmmc-supply = <&vsim>;
826 bus-width = <8>;
827 non-removable;
828 no-sdio;
829 no-sd;
830};
831
832&mmc3 {
833 status = "disabled";
834};
835
836&gpmc {
837 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
838 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
839 pinctrl-names = "default";
840 pinctrl-0 = <&gpmc_pins>;
841
842 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
843 onenand@0,0 {
844 #address-cells = <1>;
845 #size-cells = <1>;
846 compatible = "ti,omap2-onenand";
847 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
848
849 gpmc,sync-read;
850 gpmc,sync-write;
851 gpmc,burst-length = <16>;
852 gpmc,burst-read;
853 gpmc,burst-wrap;
854 gpmc,burst-write;
855 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
856 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
857 gpmc,cs-on-ns = <0>;
858 gpmc,cs-rd-off-ns = <87>;
859 gpmc,cs-wr-off-ns = <87>;
860 gpmc,adv-on-ns = <0>;
861 gpmc,adv-rd-off-ns = <10>;
862 gpmc,adv-wr-off-ns = <10>;
863 gpmc,oe-on-ns = <15>;
864 gpmc,oe-off-ns = <87>;
865 gpmc,we-on-ns = <0>;
866 gpmc,we-off-ns = <87>;
867 gpmc,rd-cycle-ns = <112>;
868 gpmc,wr-cycle-ns = <112>;
869 gpmc,access-ns = <81>;
870 gpmc,page-burst-access-ns = <15>;
871 gpmc,bus-turnaround-ns = <0>;
872 gpmc,cycle2cycle-delay-ns = <0>;
873 gpmc,wait-monitoring-ns = <0>;
874 gpmc,clk-activation-ns = <5>;
875 gpmc,wr-data-mux-bus-ns = <30>;
876 gpmc,wr-access-ns = <81>;
877 gpmc,sync-clk-ps = <15000>;
878
879 /*
880 * MTD partition table corresponding to Nokia's
881 * Maemo 5 (Fremantle) release.
882 */
883 partition@0 {
884 label = "bootloader";
885 reg = <0x00000000 0x00020000>;
886 read-only;
887 };
888 partition@1 {
889 label = "config";
890 reg = <0x00020000 0x00060000>;
891 };
892 partition@2 {
893 label = "log";
894 reg = <0x00080000 0x00040000>;
895 };
896 partition@3 {
897 label = "kernel";
898 reg = <0x000c0000 0x00200000>;
899 };
900 partition@4 {
901 label = "initfs";
902 reg = <0x002c0000 0x00200000>;
903 };
904 partition@5 {
905 label = "rootfs";
906 reg = <0x004c0000 0x0fb40000>;
907 };
908 };
909
910 /* Ethernet is on some early development boards and qemu */
911 ethernet@gpmc {
912 compatible = "smsc,lan91c94";
913 interrupt-parent = <&gpio2>;
914 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
915 reg = <1 0 0xf>; /* 16 byte IO range */
916 bank-width = <2>;
917 pinctrl-names = "default";
918 pinctrl-0 = <ðernet_pins>;
919 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
920 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
921 gpmc,device-width = <2>;
922 gpmc,sync-clk-ps = <0>;
923 gpmc,cs-on-ns = <0>;
924 gpmc,cs-rd-off-ns = <48>;
925 gpmc,cs-wr-off-ns = <24>;
926 gpmc,adv-on-ns = <0>;
927 gpmc,adv-rd-off-ns = <0>;
928 gpmc,adv-wr-off-ns = <0>;
929 gpmc,we-on-ns = <12>;
930 gpmc,we-off-ns = <18>;
931 gpmc,oe-on-ns = <12>;
932 gpmc,oe-off-ns = <48>;
933 gpmc,page-burst-access-ns = <0>;
934 gpmc,access-ns = <42>;
935 gpmc,rd-cycle-ns = <180>;
936 gpmc,wr-cycle-ns = <180>;
937 gpmc,bus-turnaround-ns = <0>;
938 gpmc,cycle2cycle-delay-ns = <0>;
939 gpmc,wait-monitoring-ns = <0>;
940 gpmc,clk-activation-ns = <0>;
941 gpmc,wr-access-ns = <0>;
942 gpmc,wr-data-mux-bus-ns = <12>;
943 };
944};
945
946&mcspi1 {
947 /*
948 * For some reason, touchscreen is necessary for screen to work at
949 * all on real hw. It works well without it on emulator.
950 *
951 * Also... order in the device tree actually matters here.
952 */
953 tsc2005@0 {
954 compatible = "ti,tsc2005";
955 spi-max-frequency = <6000000>;
956 reg = <0>;
957
958 vio-supply = <&vio>;
959
960 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
961 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
962
963 touchscreen-fuzz-x = <4>;
964 touchscreen-fuzz-y = <7>;
965 touchscreen-fuzz-pressure = <2>;
966 touchscreen-size-x = <4096>;
967 touchscreen-size-y = <4096>;
968 touchscreen-max-pressure = <2048>;
969
970 ti,x-plate-ohms = <280>;
971 ti,esd-recovery-timeout-ms = <8000>;
972 };
973
974 lcd: acx565akm@2 {
975 compatible = "sony,acx565akm";
976 spi-max-frequency = <6000000>;
977 reg = <2>;
978
979 pinctrl-names = "default";
980 pinctrl-0 = <&acx565akm_pins>;
981
982 label = "lcd";
983 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
984
985 port {
986 lcd_in: endpoint {
987 remote-endpoint = <&sdi_out>;
988 };
989 };
990 };
991};
992
993&mcspi4 {
994 pinctrl-names = "default";
995 pinctrl-0 = <&mcspi4_pins>;
996
997 wl1251@0 {
998 pinctrl-names = "default";
999 pinctrl-0 = <&wl1251_pins>;
1000
1001 vio-supply = <&vio>;
1002
1003 compatible = "ti,wl1251";
1004 reg = <0>;
1005 spi-max-frequency = <48000000>;
1006
1007 spi-cpol;
1008 spi-cpha;
1009
1010 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
1011
1012 interrupt-parent = <&gpio2>;
1013 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
1014
1015 clocks = <&vctcxo>;
1016 };
1017};
1018
1019&usb_otg_hs {
1020 interface-type = <0>;
1021 usb-phy = <&usb2_phy>;
1022 phys = <&usb2_phy>;
1023 phy-names = "usb2-phy";
1024 mode = <2>;
1025 power = <50>;
1026};
1027
1028&uart1 {
1029 status = "disabled";
1030};
1031
1032&uart2 {
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&uart2_pins>;
1035
1036 bcm2048: bluetooth {
1037 compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth";
1038 reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */
1039 host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
1040 bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
1041 clocks = <&vctcxo>;
1042 clock-names = "sysclk";
1043 };
1044};
1045
1046&uart3 {
1047 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
1048 pinctrl-names = "default";
1049 pinctrl-0 = <&uart3_pins>;
1050};
1051
1052&dss {
1053 status = "ok";
1054
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&dss_sdi_pins>;
1057
1058 vdds_sdi-supply = <&vaux1>;
1059
1060 ports {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063
1064 port@1 {
1065 reg = <1>;
1066
1067 sdi_out: endpoint {
1068 remote-endpoint = <&lcd_in>;
1069 datapairs = <2>;
1070 };
1071 };
1072 };
1073};
1074
1075&venc {
1076 status = "ok";
1077
1078 vdda-supply = <&vdac>;
1079
1080 port {
1081 venc_out: endpoint {
1082 remote-endpoint = <&tv_connector_in>;
1083 ti,channels = <1>;
1084 };
1085 };
1086};
1087
1088&mcbsp2 {
1089 status = "ok";
1090};
1091
1092&ssi_port1 {
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&ssi_pins>;
1095
1096 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
1097
1098 modem: hsi-client {
1099 compatible = "nokia,n900-modem";
1100
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&modem_pins>;
1103
1104 hsi-channel-ids = <0>, <1>, <2>, <3>;
1105 hsi-channel-names = "mcsaab-control",
1106 "speech-control",
1107 "speech-data",
1108 "mcsaab-data";
1109 hsi-speed-kbps = <55000>;
1110 hsi-mode = "frame";
1111 hsi-flow = "synchronized";
1112 hsi-arb-mode = "round-robin";
1113
1114 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
1115
1116 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1117 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1118 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1119 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1120 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1121 gpio-names = "cmt_apeslpx",
1122 "cmt_rst_rq",
1123 "cmt_en",
1124 "cmt_rst",
1125 "cmt_bsi";
1126 };
1127};
1128
1129&ssi_port2 {
1130 status = "disabled";
1131};
1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
3 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "omap34xx.dtsi"
13#include <dt-bindings/input/input.h>
14
15/*
16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * for omap AES HW crypto support. When linux kernel try to access memory of AES
18 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
19 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
20 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
22 * but it is not widely used and to prevent kernel crash rather AES is disabled.
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
24 */
25&aes {
26 status = "disabled";
27};
28
29/ {
30 model = "Nokia N900";
31 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
32
33 aliases {
34 i2c0;
35 i2c1 = &i2c1;
36 i2c2 = &i2c2;
37 i2c3 = &i2c3;
38 };
39
40 cpus {
41 cpu@0 {
42 cpu0-supply = <&vcc>;
43 };
44 };
45
46 leds {
47 compatible = "gpio-leds";
48 heartbeat {
49 label = "debug::sleep";
50 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */
51 linux,default-trigger = "default-on";
52 pinctrl-names = "default";
53 pinctrl-0 = <&debug_leds>;
54 };
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x80000000 0x10000000>; /* 256 MB */
60 };
61
62 gpio_keys {
63 compatible = "gpio-keys";
64
65 camera_lens_cover {
66 label = "Camera Lens Cover";
67 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
68 linux,input-type = <EV_SW>;
69 linux,code = <SW_CAMERA_LENS_COVER>;
70 linux,can-disable;
71 };
72
73 camera_focus {
74 label = "Camera Focus";
75 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
76 linux,code = <KEY_CAMERA_FOCUS>;
77 linux,can-disable;
78 };
79
80 camera_capture {
81 label = "Camera Capture";
82 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
83 linux,code = <KEY_CAMERA>;
84 linux,can-disable;
85 };
86
87 lock_button {
88 label = "Lock Button";
89 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
90 linux,code = <KEY_SCREENLOCK>;
91 linux,can-disable;
92 };
93
94 keypad_slide {
95 label = "Keypad Slide";
96 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
97 linux,input-type = <EV_SW>;
98 linux,code = <SW_KEYPAD_SLIDE>;
99 linux,can-disable;
100 };
101
102 proximity_sensor {
103 label = "Proximity Sensor";
104 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
105 linux,input-type = <EV_SW>;
106 linux,code = <SW_FRONT_PROXIMITY>;
107 linux,can-disable;
108 };
109 };
110
111 isp1707: isp1707 {
112 compatible = "nxp,isp1707";
113 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
114 usb-phy = <&usb2_phy>;
115 };
116
117 tv: connector {
118 compatible = "composite-video-connector";
119 label = "tv";
120
121 port {
122 tv_connector_in: endpoint {
123 remote-endpoint = <&venc_out>;
124 };
125 };
126 };
127
128 sound: n900-audio {
129 compatible = "nokia,n900-audio";
130
131 nokia,cpu-dai = <&mcbsp2>;
132 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
133 nokia,headphone-amplifier = <&tpa6130a2>;
134
135 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
136 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
137 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
138 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
139 };
140
141 battery: n900-battery {
142 compatible = "nokia,n900-battery";
143 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
144 io-channel-names = "temp", "bsi", "vbat";
145 };
146};
147
148&omap3_pmx_core {
149 pinctrl-names = "default";
150
151 uart2_pins: pinmux_uart2_pins {
152 pinctrl-single,pins = <
153 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
154 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
155 >;
156 };
157
158 uart3_pins: pinmux_uart3_pins {
159 pinctrl-single,pins = <
160 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
161 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
162 >;
163 };
164
165 ethernet_pins: pinmux_ethernet_pins {
166 pinctrl-single,pins = <
167 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
168 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
169 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
170 >;
171 };
172
173 gpmc_pins: pinmux_gpmc_pins {
174 pinctrl-single,pins = <
175
176 /* address lines */
177 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
178 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
179 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
180
181 /* data lines, gpmc_d0..d7 not muxable according to TRM */
182 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
183 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
184 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
185 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
186 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
187 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
188 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
189 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
190
191 /*
192 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
193 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
194 */
195 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
196 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
197 >;
198 };
199
200 i2c1_pins: pinmux_i2c1_pins {
201 pinctrl-single,pins = <
202 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
203 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
204 >;
205 };
206
207 i2c2_pins: pinmux_i2c2_pins {
208 pinctrl-single,pins = <
209 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
210 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
211 >;
212 };
213
214 i2c3_pins: pinmux_i2c3_pins {
215 pinctrl-single,pins = <
216 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
217 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
218 >;
219 };
220
221 debug_leds: pinmux_debug_led_pins {
222 pinctrl-single,pins = <
223 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
224 >;
225 };
226
227 mcspi4_pins: pinmux_mcspi4_pins {
228 pinctrl-single,pins = <
229 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
230 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
231 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
232 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
233 >;
234 };
235
236 mmc1_pins: pinmux_mmc1_pins {
237 pinctrl-single,pins = <
238 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
239 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
240 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
241 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
242 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
243 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
244 >;
245 };
246
247 mmc2_pins: pinmux_mmc2_pins {
248 pinctrl-single,pins = <
249 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
250 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
251 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
252 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
253 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
254 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
255 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
256 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
257 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
258 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
259 >;
260 };
261
262 acx565akm_pins: pinmux_acx565akm_pins {
263 pinctrl-single,pins = <
264 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
265 >;
266 };
267
268 dss_sdi_pins: pinmux_dss_sdi_pins {
269 pinctrl-single,pins = <
270 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
271 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
272 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
273 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
274
275 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
276 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
277 >;
278 };
279
280 wl1251_pins: pinmux_wl1251 {
281 pinctrl-single,pins = <
282 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
283 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
284 >;
285 };
286
287 ssi_pins: pinmux_ssi {
288 pinctrl-single,pins = <
289 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
290 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
291 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
292 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
293 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
294 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
295 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
296 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
297 >;
298 };
299
300 modem_pins: pinmux_modem {
301 pinctrl-single,pins = <
302 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
303 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
304 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
305 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
306 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
307 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
308 >;
309 };
310};
311
312&i2c1 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c1_pins>;
315
316 clock-frequency = <2200000>;
317
318 twl: twl@48 {
319 reg = <0x48>;
320 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
321 interrupt-parent = <&intc>;
322 };
323};
324
325#include "twl4030.dtsi"
326#include "twl4030_omap3.dtsi"
327
328&vaux1 {
329 regulator-name = "V28";
330 regulator-min-microvolt = <2800000>;
331 regulator-max-microvolt = <2800000>;
332 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
333 regulator-always-on; /* due to battery cover sensor */
334};
335
336&vaux2 {
337 regulator-name = "VCSI";
338 regulator-min-microvolt = <1800000>;
339 regulator-max-microvolt = <1800000>;
340 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
341};
342
343&vaux3 {
344 regulator-name = "VMMC2_30";
345 regulator-min-microvolt = <2800000>;
346 regulator-max-microvolt = <3000000>;
347 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
348};
349
350&vaux4 {
351 regulator-name = "VCAM_ANA_28";
352 regulator-min-microvolt = <2800000>;
353 regulator-max-microvolt = <2800000>;
354 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
355};
356
357&vmmc1 {
358 regulator-name = "VMMC1";
359 regulator-min-microvolt = <1850000>;
360 regulator-max-microvolt = <3150000>;
361 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
362};
363
364&vmmc2 {
365 regulator-name = "V28_A";
366 regulator-min-microvolt = <2800000>;
367 regulator-max-microvolt = <3000000>;
368 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
369 regulator-always-on; /* due VIO leak to AIC34 VDDs */
370};
371
372&vpll1 {
373 regulator-name = "VPLL";
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
376 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
377 regulator-always-on;
378};
379
380&vpll2 {
381 regulator-name = "VSDI_CSI";
382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <1800000>;
384 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
385 regulator-always-on;
386};
387
388&vsim {
389 regulator-name = "VMMC2_IO_18";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
393};
394
395&vio {
396 regulator-name = "VIO";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
399};
400
401&vintana1 {
402 regulator-name = "VINTANA1";
403 /* fixed to 1500000 */
404 regulator-always-on;
405};
406
407&vintana2 {
408 regulator-name = "VINTANA2";
409 regulator-min-microvolt = <2750000>;
410 regulator-max-microvolt = <2750000>;
411 regulator-always-on;
412};
413
414&vintdig {
415 regulator-name = "VINTDIG";
416 /* fixed to 1500000 */
417 regulator-always-on;
418};
419
420&twl {
421 twl_audio: audio {
422 compatible = "ti,twl4030-audio";
423 ti,enable-vibra = <1>;
424 };
425
426 twl_power: power {
427 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
428 ti,use_poweroff;
429 };
430};
431
432&twl_keypad {
433 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
434 MATRIX_KEY(0x00, 0x01, KEY_O)
435 MATRIX_KEY(0x00, 0x02, KEY_P)
436 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
437 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
438 MATRIX_KEY(0x00, 0x06, KEY_A)
439 MATRIX_KEY(0x00, 0x07, KEY_S)
440
441 MATRIX_KEY(0x01, 0x00, KEY_W)
442 MATRIX_KEY(0x01, 0x01, KEY_D)
443 MATRIX_KEY(0x01, 0x02, KEY_F)
444 MATRIX_KEY(0x01, 0x03, KEY_G)
445 MATRIX_KEY(0x01, 0x04, KEY_H)
446 MATRIX_KEY(0x01, 0x05, KEY_J)
447 MATRIX_KEY(0x01, 0x06, KEY_K)
448 MATRIX_KEY(0x01, 0x07, KEY_L)
449
450 MATRIX_KEY(0x02, 0x00, KEY_E)
451 MATRIX_KEY(0x02, 0x01, KEY_DOT)
452 MATRIX_KEY(0x02, 0x02, KEY_UP)
453 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
454 MATRIX_KEY(0x02, 0x05, KEY_Z)
455 MATRIX_KEY(0x02, 0x06, KEY_X)
456 MATRIX_KEY(0x02, 0x07, KEY_C)
457 MATRIX_KEY(0x02, 0x08, KEY_F9)
458
459 MATRIX_KEY(0x03, 0x00, KEY_R)
460 MATRIX_KEY(0x03, 0x01, KEY_V)
461 MATRIX_KEY(0x03, 0x02, KEY_B)
462 MATRIX_KEY(0x03, 0x03, KEY_N)
463 MATRIX_KEY(0x03, 0x04, KEY_M)
464 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
465 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
466 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
467
468 MATRIX_KEY(0x04, 0x00, KEY_T)
469 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
470 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
471 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
472 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
473 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
474 MATRIX_KEY(0x04, 0x08, KEY_F10)
475
476 MATRIX_KEY(0x05, 0x00, KEY_Y)
477 MATRIX_KEY(0x05, 0x08, KEY_F11)
478
479 MATRIX_KEY(0x06, 0x00, KEY_U)
480
481 MATRIX_KEY(0x07, 0x00, KEY_I)
482 MATRIX_KEY(0x07, 0x01, KEY_F7)
483 MATRIX_KEY(0x07, 0x02, KEY_F8)
484 >;
485};
486
487&twl_gpio {
488 ti,pullups = <0x0>;
489 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
490};
491
492&i2c2 {
493 pinctrl-names = "default";
494 pinctrl-0 = <&i2c2_pins>;
495
496 clock-frequency = <100000>;
497
498 tlv320aic3x: tlv320aic3x@18 {
499 compatible = "ti,tlv320aic3x";
500 reg = <0x18>;
501 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
502 ai3x-gpio-func = <
503 0 /* AIC3X_GPIO1_FUNC_DISABLED */
504 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
505 >;
506
507 AVDD-supply = <&vmmc2>;
508 DRVDD-supply = <&vmmc2>;
509 IOVDD-supply = <&vio>;
510 DVDD-supply = <&vio>;
511
512 ai3x-micbias-vg = <1>;
513 };
514
515 tlv320aic3x_aux: tlv320aic3x@19 {
516 compatible = "ti,tlv320aic3x";
517 reg = <0x19>;
518 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
519
520 AVDD-supply = <&vmmc2>;
521 DRVDD-supply = <&vmmc2>;
522 IOVDD-supply = <&vio>;
523 DVDD-supply = <&vio>;
524
525 ai3x-micbias-vg = <2>;
526 };
527
528 tsl2563: tsl2563@29 {
529 compatible = "amstaos,tsl2563";
530 reg = <0x29>;
531
532 amstaos,cover-comp-gain = <16>;
533 };
534
535 adp1653: led-controller@30 {
536 compatible = "adi,adp1653";
537 reg = <0x30>;
538 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
539
540 flash {
541 flash-timeout-us = <500000>;
542 flash-max-microamp = <320000>;
543 led-max-microamp = <50000>;
544 };
545 indicator {
546 led-max-microamp = <17500>;
547 };
548 };
549
550 lp5523: lp5523@32 {
551 compatible = "national,lp5523";
552 reg = <0x32>;
553 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
554 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
555
556 chan0 {
557 chan-name = "lp5523:kb1";
558 led-cur = /bits/ 8 <50>;
559 max-cur = /bits/ 8 <100>;
560 };
561
562 chan1 {
563 chan-name = "lp5523:kb2";
564 led-cur = /bits/ 8 <50>;
565 max-cur = /bits/ 8 <100>;
566 };
567
568 chan2 {
569 chan-name = "lp5523:kb3";
570 led-cur = /bits/ 8 <50>;
571 max-cur = /bits/ 8 <100>;
572 };
573
574 chan3 {
575 chan-name = "lp5523:kb4";
576 led-cur = /bits/ 8 <50>;
577 max-cur = /bits/ 8 <100>;
578 };
579
580 chan4 {
581 chan-name = "lp5523:b";
582 led-cur = /bits/ 8 <50>;
583 max-cur = /bits/ 8 <100>;
584 };
585
586 chan5 {
587 chan-name = "lp5523:g";
588 led-cur = /bits/ 8 <50>;
589 max-cur = /bits/ 8 <100>;
590 };
591
592 chan6 {
593 chan-name = "lp5523:r";
594 led-cur = /bits/ 8 <50>;
595 max-cur = /bits/ 8 <100>;
596 };
597
598 chan7 {
599 chan-name = "lp5523:kb5";
600 led-cur = /bits/ 8 <50>;
601 max-cur = /bits/ 8 <100>;
602 };
603
604 chan8 {
605 chan-name = "lp5523:kb6";
606 led-cur = /bits/ 8 <50>;
607 max-cur = /bits/ 8 <100>;
608 };
609 };
610
611 bq27200: bq27200@55 {
612 compatible = "ti,bq27200";
613 reg = <0x55>;
614 };
615
616 tpa6130a2: tpa6130a2@60 {
617 compatible = "ti,tpa6130a2";
618 reg = <0x60>;
619
620 Vdd-supply = <&vmmc2>;
621
622 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
623 };
624
625 si4713: si4713@63 {
626 compatible = "silabs,si4713";
627 reg = <0x63>;
628
629 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
630 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
631 vio-supply = <&vio>;
632 vdd-supply = <&vaux1>;
633 };
634
635 bq24150a: bq24150a@6b {
636 compatible = "ti,bq24150a";
637 reg = <0x6b>;
638
639 ti,current-limit = <100>;
640 ti,weak-battery-voltage = <3400>;
641 ti,battery-regulation-voltage = <4200>;
642 ti,charge-current = <650>;
643 ti,termination-current = <100>;
644 ti,resistor-sense = <68>;
645
646 ti,usb-charger-detection = <&isp1707>;
647 };
648};
649
650&i2c3 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&i2c3_pins>;
653
654 clock-frequency = <400000>;
655
656 lis302dl: lis3lv02d@1d {
657 compatible = "st,lis3lv02d";
658 reg = <0x1d>;
659
660 Vdd-supply = <&vaux1>;
661 Vdd_IO-supply = <&vio>;
662
663 interrupt-parent = <&gpio6>;
664 interrupts = <21 20>; /* 181 and 180 */
665
666 /* click flags */
667 st,click-single-x;
668 st,click-single-y;
669 st,click-single-z;
670
671 /* Limits are 0.5g * value */
672 st,click-threshold-x = <8>;
673 st,click-threshold-y = <8>;
674 st,click-threshold-z = <10>;
675
676 /* Click must be longer than time limit */
677 st,click-time-limit = <9>;
678
679 /* Kind of debounce filter */
680 st,click-latency = <50>;
681
682 /* Interrupt line 2 for click detection */
683 st,irq2-click;
684
685 st,wakeup-x-hi;
686 st,wakeup-y-hi;
687 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
688
689 st,wakeup2-z-hi;
690 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
691
692 st,hipass1-disable;
693 st,hipass2-disable;
694
695 st,axis-x = <1>; /* LIS3_DEV_X */
696 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
697 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
698
699 st,min-limit-x = <(-32)>;
700 st,min-limit-y = <3>;
701 st,min-limit-z = <3>;
702
703 st,max-limit-x = <(-3)>;
704 st,max-limit-y = <32>;
705 st,max-limit-z = <32>;
706 };
707};
708
709&mmc1 {
710 pinctrl-names = "default";
711 pinctrl-0 = <&mmc1_pins>;
712 vmmc-supply = <&vmmc1>;
713 bus-width = <4>;
714 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
715};
716
717/* most boards use vaux3, only some old versions use vmmc2 instead */
718&mmc2 {
719 pinctrl-names = "default";
720 pinctrl-0 = <&mmc2_pins>;
721 vmmc-supply = <&vaux3>;
722 vmmc_aux-supply = <&vsim>;
723 bus-width = <8>;
724 non-removable;
725};
726
727&mmc3 {
728 status = "disabled";
729};
730
731&gpmc {
732 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
733 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
734 pinctrl-names = "default";
735 pinctrl-0 = <&gpmc_pins>;
736
737 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
738 onenand@0,0 {
739 #address-cells = <1>;
740 #size-cells = <1>;
741 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
742
743 gpmc,sync-read;
744 gpmc,sync-write;
745 gpmc,burst-length = <16>;
746 gpmc,burst-read;
747 gpmc,burst-wrap;
748 gpmc,burst-write;
749 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
750 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
751 gpmc,cs-on-ns = <0>;
752 gpmc,cs-rd-off-ns = <87>;
753 gpmc,cs-wr-off-ns = <87>;
754 gpmc,adv-on-ns = <0>;
755 gpmc,adv-rd-off-ns = <10>;
756 gpmc,adv-wr-off-ns = <10>;
757 gpmc,oe-on-ns = <15>;
758 gpmc,oe-off-ns = <87>;
759 gpmc,we-on-ns = <0>;
760 gpmc,we-off-ns = <87>;
761 gpmc,rd-cycle-ns = <112>;
762 gpmc,wr-cycle-ns = <112>;
763 gpmc,access-ns = <81>;
764 gpmc,page-burst-access-ns = <15>;
765 gpmc,bus-turnaround-ns = <0>;
766 gpmc,cycle2cycle-delay-ns = <0>;
767 gpmc,wait-monitoring-ns = <0>;
768 gpmc,clk-activation-ns = <5>;
769 gpmc,wr-data-mux-bus-ns = <30>;
770 gpmc,wr-access-ns = <81>;
771 gpmc,sync-clk-ps = <15000>;
772
773 /*
774 * MTD partition table corresponding to Nokia's
775 * Maemo 5 (Fremantle) release.
776 */
777 partition@0 {
778 label = "bootloader";
779 reg = <0x00000000 0x00020000>;
780 read-only;
781 };
782 partition@1 {
783 label = "config";
784 reg = <0x00020000 0x00060000>;
785 };
786 partition@2 {
787 label = "log";
788 reg = <0x00080000 0x00040000>;
789 };
790 partition@3 {
791 label = "kernel";
792 reg = <0x000c0000 0x00200000>;
793 };
794 partition@4 {
795 label = "initfs";
796 reg = <0x002c0000 0x00200000>;
797 };
798 partition@5 {
799 label = "rootfs";
800 reg = <0x004c0000 0x0fb40000>;
801 };
802 };
803
804 /* Ethernet is on some early development boards and qemu */
805 ethernet@gpmc {
806 compatible = "smsc,lan91c94";
807 interrupt-parent = <&gpio2>;
808 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
809 reg = <1 0 0xf>; /* 16 byte IO range */
810 bank-width = <2>;
811 pinctrl-names = "default";
812 pinctrl-0 = <ðernet_pins>;
813 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
814 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
815 gpmc,device-width = <2>;
816 gpmc,sync-clk-ps = <0>;
817 gpmc,cs-on-ns = <0>;
818 gpmc,cs-rd-off-ns = <48>;
819 gpmc,cs-wr-off-ns = <24>;
820 gpmc,adv-on-ns = <0>;
821 gpmc,adv-rd-off-ns = <0>;
822 gpmc,adv-wr-off-ns = <0>;
823 gpmc,we-on-ns = <12>;
824 gpmc,we-off-ns = <18>;
825 gpmc,oe-on-ns = <12>;
826 gpmc,oe-off-ns = <48>;
827 gpmc,page-burst-access-ns = <0>;
828 gpmc,access-ns = <42>;
829 gpmc,rd-cycle-ns = <180>;
830 gpmc,wr-cycle-ns = <180>;
831 gpmc,bus-turnaround-ns = <0>;
832 gpmc,cycle2cycle-delay-ns = <0>;
833 gpmc,wait-monitoring-ns = <0>;
834 gpmc,clk-activation-ns = <0>;
835 gpmc,wr-access-ns = <0>;
836 gpmc,wr-data-mux-bus-ns = <12>;
837 };
838};
839
840&mcspi1 {
841 /*
842 * For some reason, touchscreen is necessary for screen to work at
843 * all on real hw. It works well without it on emulator.
844 *
845 * Also... order in the device tree actually matters here.
846 */
847 tsc2005@0 {
848 compatible = "ti,tsc2005";
849 spi-max-frequency = <6000000>;
850 reg = <0>;
851
852 vio-supply = <&vio>;
853
854 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
855 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
856
857 touchscreen-fuzz-x = <4>;
858 touchscreen-fuzz-y = <7>;
859 touchscreen-fuzz-pressure = <2>;
860 touchscreen-size-x = <4096>;
861 touchscreen-size-y = <4096>;
862 touchscreen-max-pressure = <2048>;
863
864 ti,x-plate-ohms = <280>;
865 ti,esd-recovery-timeout-ms = <8000>;
866 };
867
868 acx565akm@2 {
869 compatible = "sony,acx565akm";
870 spi-max-frequency = <6000000>;
871 reg = <2>;
872
873 pinctrl-names = "default";
874 pinctrl-0 = <&acx565akm_pins>;
875
876 label = "lcd";
877 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
878
879 port {
880 lcd_in: endpoint {
881 remote-endpoint = <&sdi_out>;
882 };
883 };
884 };
885};
886
887&mcspi4 {
888 pinctrl-names = "default";
889 pinctrl-0 = <&mcspi4_pins>;
890
891 wl1251@0 {
892 pinctrl-names = "default";
893 pinctrl-0 = <&wl1251_pins>;
894
895 vio-supply = <&vio>;
896
897 compatible = "ti,wl1251";
898 reg = <0>;
899 spi-max-frequency = <48000000>;
900
901 spi-cpol;
902 spi-cpha;
903
904 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
905
906 interrupt-parent = <&gpio2>;
907 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
908 };
909};
910
911&usb_otg_hs {
912 interface-type = <0>;
913 usb-phy = <&usb2_phy>;
914 phys = <&usb2_phy>;
915 phy-names = "usb2-phy";
916 mode = <2>;
917 power = <50>;
918};
919
920&uart1 {
921 status = "disabled";
922};
923
924&uart2 {
925 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&uart2_pins>;
928};
929
930&uart3 {
931 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&uart3_pins>;
934};
935
936&dss {
937 status = "ok";
938
939 pinctrl-names = "default";
940 pinctrl-0 = <&dss_sdi_pins>;
941
942 vdds_sdi-supply = <&vaux1>;
943
944 ports {
945 #address-cells = <1>;
946 #size-cells = <0>;
947
948 port@1 {
949 reg = <1>;
950
951 sdi_out: endpoint {
952 remote-endpoint = <&lcd_in>;
953 datapairs = <2>;
954 };
955 };
956 };
957};
958
959&venc {
960 status = "ok";
961
962 vdda-supply = <&vdac>;
963
964 port {
965 venc_out: endpoint {
966 remote-endpoint = <&tv_connector_in>;
967 ti,channels = <1>;
968 };
969 };
970};
971
972&mcbsp2 {
973 status = "ok";
974};
975
976&ssi_port1 {
977 pinctrl-names = "default";
978 pinctrl-0 = <&ssi_pins>;
979
980 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
981
982 modem: hsi-client {
983 compatible = "nokia,n900-modem";
984
985 pinctrl-names = "default";
986 pinctrl-0 = <&modem_pins>;
987
988 hsi-channel-ids = <0>, <1>, <2>, <3>;
989 hsi-channel-names = "mcsaab-control",
990 "speech-control",
991 "speech-data",
992 "mcsaab-data";
993 hsi-speed-kbps = <55000>;
994 hsi-mode = "frame";
995 hsi-flow = "synchronized";
996 hsi-arb-mode = "round-robin";
997
998 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
999
1000 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1001 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1002 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1003 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1004 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1005 gpio-names = "cmt_apeslpx",
1006 "cmt_rst_rq",
1007 "cmt_en",
1008 "cmt_rst",
1009 "cmt_bsi";
1010 };
1011};
1012
1013&ssi_port2 {
1014 status = "disabled";
1015};