Loading...
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
19 * Also for U-Boot there must be a pre-existing /memory node.
20 */
21 chosen {};
22 memory { device_type = "memory"; };
23
24 aliases {
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 serial4 = &uart5;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 compatible = "arm,arm1136jf-s";
38 device_type = "cpu";
39 reg = <0>;
40 };
41 };
42
43 avic: interrupt-controller@68000000 {
44 compatible = "fsl,imx31-avic", "fsl,avic";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 reg = <0x68000000 0x100000>;
48 };
49
50 soc {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "simple-bus";
54 interrupt-parent = <&avic>;
55 ranges;
56
57 aips@43f00000 { /* AIPS1 */
58 compatible = "fsl,aips-bus", "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x43f00000 0x100000>;
62 ranges;
63
64 uart1: serial@43f90000 {
65 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
66 reg = <0x43f90000 0x4000>;
67 interrupts = <45>;
68 clocks = <&clks 10>, <&clks 30>;
69 clock-names = "ipg", "per";
70 status = "disabled";
71 };
72
73 uart2: serial@43f94000 {
74 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
75 reg = <0x43f94000 0x4000>;
76 interrupts = <32>;
77 clocks = <&clks 10>, <&clks 31>;
78 clock-names = "ipg", "per";
79 status = "disabled";
80 };
81
82 kpp: kpp@43fa8000 {
83 compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
84 reg = <0x43fa8000 0x4000>;
85 interrupts = <24>;
86 clocks = <&clks 46>;
87 status = "disabled";
88 };
89
90 uart4: serial@43fb0000 {
91 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
92 reg = <0x43fb0000 0x4000>;
93 clocks = <&clks 10>, <&clks 49>;
94 clock-names = "ipg", "per";
95 interrupts = <46>;
96 status = "disabled";
97 };
98
99 uart5: serial@43fb4000 {
100 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
101 reg = <0x43fb4000 0x4000>;
102 interrupts = <47>;
103 clocks = <&clks 10>, <&clks 50>;
104 clock-names = "ipg", "per";
105 status = "disabled";
106 };
107 };
108
109 spba@50000000 {
110 compatible = "fsl,spba-bus", "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 reg = <0x50000000 0x100000>;
114 ranges;
115
116 uart3: serial@5000c000 {
117 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
118 reg = <0x5000c000 0x4000>;
119 interrupts = <18>;
120 clocks = <&clks 10>, <&clks 48>;
121 clock-names = "ipg", "per";
122 status = "disabled";
123 };
124
125 iim: iim@5001c000 {
126 compatible = "fsl,imx31-iim", "fsl,imx27-iim";
127 reg = <0x5001c000 0x1000>;
128 interrupts = <19>;
129 clocks = <&clks 25>;
130 };
131 };
132
133 aips@53f00000 { /* AIPS2 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x53f00000 0x100000>;
138 ranges;
139
140 clks: ccm@53f80000{
141 compatible = "fsl,imx31-ccm";
142 reg = <0x53f80000 0x4000>;
143 interrupts = <31>, <53>;
144 #clock-cells = <1>;
145 };
146
147 gpt: timer@53f90000 {
148 compatible = "fsl,imx31-gpt";
149 reg = <0x53f90000 0x4000>;
150 interrupts = <29>;
151 clocks = <&clks 10>, <&clks 22>;
152 clock-names = "ipg", "per";
153 };
154 };
155 };
156};
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 };
22
23 cpus {
24 #address-cells = <0>;
25 #size-cells = <0>;
26
27 cpu {
28 compatible = "arm,arm1136jf-s";
29 device_type = "cpu";
30 };
31 };
32
33 avic: avic-interrupt-controller@60000000 {
34 compatible = "fsl,imx31-avic", "fsl,avic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x60000000 0x100000>;
38 };
39
40 soc {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "simple-bus";
44 interrupt-parent = <&avic>;
45 ranges;
46
47 aips@43f00000 { /* AIPS1 */
48 compatible = "fsl,aips-bus", "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x43f00000 0x100000>;
52 ranges;
53
54 uart1: serial@43f90000 {
55 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
56 reg = <0x43f90000 0x4000>;
57 interrupts = <45>;
58 clocks = <&clks 10>, <&clks 30>;
59 clock-names = "ipg", "per";
60 status = "disabled";
61 };
62
63 uart2: serial@43f94000 {
64 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
65 reg = <0x43f94000 0x4000>;
66 interrupts = <32>;
67 clocks = <&clks 10>, <&clks 31>;
68 clock-names = "ipg", "per";
69 status = "disabled";
70 };
71
72 uart4: serial@43fb0000 {
73 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
74 reg = <0x43fb0000 0x4000>;
75 clocks = <&clks 10>, <&clks 49>;
76 clock-names = "ipg", "per";
77 interrupts = <46>;
78 status = "disabled";
79 };
80
81 uart5: serial@43fb4000 {
82 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
83 reg = <0x43fb4000 0x4000>;
84 interrupts = <47>;
85 clocks = <&clks 10>, <&clks 50>;
86 clock-names = "ipg", "per";
87 status = "disabled";
88 };
89 };
90
91 spba@50000000 {
92 compatible = "fsl,spba-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x50000000 0x100000>;
96 ranges;
97
98 uart3: serial@5000c000 {
99 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
100 reg = <0x5000c000 0x4000>;
101 interrupts = <18>;
102 clocks = <&clks 10>, <&clks 48>;
103 clock-names = "ipg", "per";
104 status = "disabled";
105 };
106
107 iim: iim@5001c000 {
108 compatible = "fsl,imx31-iim", "fsl,imx27-iim";
109 reg = <0x5001c000 0x1000>;
110 interrupts = <19>;
111 clocks = <&clks 25>;
112 };
113
114 clks: ccm@53f80000{
115 compatible = "fsl,imx31-ccm";
116 reg = <0x53f80000 0x4000>;
117 interrupts = <0 31 0x04 0 53 0x04>;
118 #clock-cells = <1>;
119 };
120 };
121
122 aips@53f00000 { /* AIPS2 */
123 compatible = "fsl,aips-bus", "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 reg = <0x53f00000 0x100000>;
127 ranges;
128
129 gpt: timer@53f90000 {
130 compatible = "fsl,imx31-gpt";
131 reg = <0x53f90000 0x4000>;
132 interrupts = <29>;
133 clocks = <&clks 10>, <&clks 22>;
134 clock-names = "ipg", "per";
135 };
136 };
137 };
138};