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1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include "dra7-evm-common.dtsi"
12#include "dra74x-mmc-iodelay.dtsi"
13
14/ {
15 model = "TI DRA742";
16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
17
18 memory@0 {
19 device_type = "memory";
20 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
21 };
22
23 evm_1v8_sw: fixedregulator-evm_1v8 {
24 compatible = "regulator-fixed";
25 regulator-name = "evm_1v8";
26 vin-supply = <&smps9_reg>;
27 regulator-min-microvolt = <1800000>;
28 regulator-max-microvolt = <1800000>;
29 };
30
31 evm_3v3_sd: fixedregulator-sd {
32 compatible = "regulator-fixed";
33 regulator-name = "evm_3v3_sd";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 enable-active-high;
37 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
38 };
39
40 evm_3v3_sw: fixedregulator-evm_3v3_sw {
41 compatible = "regulator-fixed";
42 regulator-name = "evm_3v3_sw";
43 vin-supply = <&sysen1>;
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
47
48 aic_dvdd: fixedregulator-aic_dvdd {
49 /* TPS77018DBVT */
50 compatible = "regulator-fixed";
51 regulator-name = "aic_dvdd";
52 vin-supply = <&evm_3v3_sw>;
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 };
56
57 extcon_usb2: extcon_usb2 {
58 compatible = "linux,extcon-usb-gpio";
59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
60 };
61
62 vtt_fixed: fixedregulator-vtt {
63 compatible = "regulator-fixed";
64 regulator-name = "vtt_fixed";
65 regulator-min-microvolt = <1350000>;
66 regulator-max-microvolt = <1350000>;
67 regulator-always-on;
68 regulator-boot-on;
69 enable-active-high;
70 vin-supply = <&sysen2>;
71 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
72 };
73
74};
75
76&dra7_pmx_core {
77 dcan1_pins_default: dcan1_pins_default {
78 pinctrl-single,pins = <
79 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
80 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
81 >;
82 };
83
84 dcan1_pins_sleep: dcan1_pins_sleep {
85 pinctrl-single,pins = <
86 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
87 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
88 >;
89 };
90};
91
92&i2c1 {
93 status = "okay";
94 clock-frequency = <400000>;
95
96 tps659038: tps659038@58 {
97 compatible = "ti,tps659038";
98 reg = <0x58>;
99 ti,palmas-override-powerhold;
100 ti,system-power-controller;
101
102 tps659038_pmic {
103 compatible = "ti,tps659038-pmic";
104
105 regulators {
106 smps123_reg: smps123 {
107 /* VDD_MPU */
108 regulator-name = "smps123";
109 regulator-min-microvolt = < 850000>;
110 regulator-max-microvolt = <1250000>;
111 regulator-always-on;
112 regulator-boot-on;
113 };
114
115 smps45_reg: smps45 {
116 /* VDD_DSPEVE */
117 regulator-name = "smps45";
118 regulator-min-microvolt = < 850000>;
119 regulator-max-microvolt = <1250000>;
120 regulator-always-on;
121 regulator-boot-on;
122 };
123
124 smps6_reg: smps6 {
125 /* VDD_GPU - over VDD_SMPS6 */
126 regulator-name = "smps6";
127 regulator-min-microvolt = <850000>;
128 regulator-max-microvolt = <1250000>;
129 regulator-always-on;
130 regulator-boot-on;
131 };
132
133 smps7_reg: smps7 {
134 /* CORE_VDD */
135 regulator-name = "smps7";
136 regulator-min-microvolt = <850000>;
137 regulator-max-microvolt = <1150000>;
138 regulator-always-on;
139 regulator-boot-on;
140 };
141
142 smps8_reg: smps8 {
143 /* VDD_IVAHD */
144 regulator-name = "smps8";
145 regulator-min-microvolt = < 850000>;
146 regulator-max-microvolt = <1250000>;
147 regulator-always-on;
148 regulator-boot-on;
149 };
150
151 smps9_reg: smps9 {
152 /* VDDS1V8 */
153 regulator-name = "smps9";
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <1800000>;
156 regulator-always-on;
157 regulator-boot-on;
158 };
159
160 ldo1_reg: ldo1 {
161 /* LDO1_OUT --> SDIO */
162 regulator-name = "ldo1";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-always-on;
166 regulator-boot-on;
167 };
168
169 ldo2_reg: ldo2 {
170 /* VDD_RTCIO */
171 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
172 regulator-name = "ldo2";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-always-on;
176 regulator-boot-on;
177 };
178
179 ldo3_reg: ldo3 {
180 /* VDDA_1V8_PHY */
181 regulator-name = "ldo3";
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <1800000>;
184 regulator-always-on;
185 regulator-boot-on;
186 };
187
188 ldo9_reg: ldo9 {
189 /* VDD_RTC */
190 regulator-name = "ldo9";
191 regulator-min-microvolt = <1050000>;
192 regulator-max-microvolt = <1050000>;
193 regulator-always-on;
194 regulator-boot-on;
195 regulator-allow-bypass;
196 };
197
198 ldoln_reg: ldoln {
199 /* VDDA_1V8_PLL */
200 regulator-name = "ldoln";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <1800000>;
203 regulator-always-on;
204 regulator-boot-on;
205 };
206
207 ldousb_reg: ldousb {
208 /* VDDA_3V_USB: VDDA_USBHS33 */
209 regulator-name = "ldousb";
210 regulator-min-microvolt = <3300000>;
211 regulator-max-microvolt = <3300000>;
212 regulator-boot-on;
213 };
214
215 /* REGEN1 is unused */
216
217 regen2: regen2 {
218 /* Needed for PMIC internal resources */
219 regulator-name = "regen2";
220 regulator-boot-on;
221 regulator-always-on;
222 };
223
224 /* REGEN3 is unused */
225
226 sysen1: sysen1 {
227 /* PMIC_REGEN_3V3 */
228 regulator-name = "sysen1";
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 sysen2: sysen2 {
234 /* PMIC_REGEN_DDR */
235 regulator-name = "sysen2";
236 regulator-boot-on;
237 regulator-always-on;
238 };
239 };
240 };
241 };
242
243 pcf_lcd: gpio@20 {
244 compatible = "ti,pcf8575", "nxp,pcf8575";
245 reg = <0x20>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-parent = <&gpio6>;
249 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253
254 pcf_gpio_21: gpio@21 {
255 compatible = "ti,pcf8575", "nxp,pcf8575";
256 reg = <0x21>;
257 lines-initial-states = <0x1408>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-parent = <&gpio6>;
261 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265
266 tlv320aic3106: tlv320aic3106@19 {
267 #sound-dai-cells = <0>;
268 compatible = "ti,tlv320aic3106";
269 reg = <0x19>;
270 adc-settle-ms = <40>;
271 ai3x-micbias-vg = <1>; /* 2.0V */
272 status = "okay";
273
274 /* Regulators */
275 AVDD-supply = <&evm_3v3_sw>;
276 IOVDD-supply = <&evm_3v3_sw>;
277 DRVDD-supply = <&evm_3v3_sw>;
278 DVDD-supply = <&aic_dvdd>;
279 };
280};
281
282&i2c2 {
283 status = "okay";
284 clock-frequency = <400000>;
285
286 pcf_hdmi: gpio@26 {
287 compatible = "ti,pcf8575", "nxp,pcf8575";
288 reg = <0x26>;
289 gpio-controller;
290 #gpio-cells = <2>;
291 p1 {
292 /* vin6_sel_s0: high: VIN6, low: audio */
293 gpio-hog;
294 gpios = <1 GPIO_ACTIVE_HIGH>;
295 output-low;
296 line-name = "vin6_sel_s0";
297 };
298 };
299};
300
301&mmc1 {
302 status = "okay";
303 vmmc-supply = <&evm_3v3_sd>;
304 vqmmc-supply = <&ldo1_reg>;
305 bus-width = <4>;
306 /*
307 * SDCD signal is not being used here - using the fact that GPIO mode
308 * is always hardwired.
309 */
310 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
311 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
312 pinctrl-0 = <&mmc1_pins_default>;
313 pinctrl-1 = <&mmc1_pins_hs>;
314 pinctrl-2 = <&mmc1_pins_sdr12>;
315 pinctrl-3 = <&mmc1_pins_sdr25>;
316 pinctrl-4 = <&mmc1_pins_sdr50>;
317 pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
318 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
319 pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
320 pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
321};
322
323&mmc2 {
324 status = "okay";
325 vmmc-supply = <&evm_1v8_sw>;
326 vqmmc-supply = <&evm_1v8_sw>;
327 bus-width = <8>;
328 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
329 pinctrl-0 = <&mmc2_pins_default>;
330 pinctrl-1 = <&mmc2_pins_hs>;
331 pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
332 pinctrl-3 = <&mmc2_pins_ddr_rev20>;
333 pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
334 pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
335};
336
337&cpu0 {
338 vdd-supply = <&smps123_reg>;
339};
340
341&omap_dwc3_2 {
342 extcon = <&extcon_usb2>;
343};
344
345&elm {
346 status = "okay";
347};
348
349&gpmc {
350 /*
351 * For the existing IOdelay configuration via U-Boot we don't
352 * support NAND on dra7-evm. Keep it disabled. Enabling it
353 * requires a different configuration by U-Boot.
354 */
355 status = "disabled";
356 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
357 nand@0,0 {
358 compatible = "ti,omap2-nand";
359 reg = <0 0 4>; /* device IO registers */
360 interrupt-parent = <&gpmc>;
361 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
362 <1 IRQ_TYPE_NONE>; /* termcount */
363 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
364 ti,nand-xfer-type = "prefetch-dma";
365 ti,nand-ecc-opt = "bch8";
366 ti,elm-id = <&elm>;
367 nand-bus-width = <16>;
368 gpmc,device-width = <2>;
369 gpmc,sync-clk-ps = <0>;
370 gpmc,cs-on-ns = <0>;
371 gpmc,cs-rd-off-ns = <80>;
372 gpmc,cs-wr-off-ns = <80>;
373 gpmc,adv-on-ns = <0>;
374 gpmc,adv-rd-off-ns = <60>;
375 gpmc,adv-wr-off-ns = <60>;
376 gpmc,we-on-ns = <10>;
377 gpmc,we-off-ns = <50>;
378 gpmc,oe-on-ns = <4>;
379 gpmc,oe-off-ns = <40>;
380 gpmc,access-ns = <40>;
381 gpmc,wr-access-ns = <80>;
382 gpmc,rd-cycle-ns = <80>;
383 gpmc,wr-cycle-ns = <80>;
384 gpmc,bus-turnaround-ns = <0>;
385 gpmc,cycle2cycle-delay-ns = <0>;
386 gpmc,clk-activation-ns = <0>;
387 gpmc,wr-data-mux-bus-ns = <0>;
388 /* MTD partition table */
389 /* All SPL-* partitions are sized to minimal length
390 * which can be independently programmable. For
391 * NAND flash this is equal to size of erase-block */
392 #address-cells = <1>;
393 #size-cells = <1>;
394 partition@0 {
395 label = "NAND.SPL";
396 reg = <0x00000000 0x000020000>;
397 };
398 partition@1 {
399 label = "NAND.SPL.backup1";
400 reg = <0x00020000 0x00020000>;
401 };
402 partition@2 {
403 label = "NAND.SPL.backup2";
404 reg = <0x00040000 0x00020000>;
405 };
406 partition@3 {
407 label = "NAND.SPL.backup3";
408 reg = <0x00060000 0x00020000>;
409 };
410 partition@4 {
411 label = "NAND.u-boot-spl-os";
412 reg = <0x00080000 0x00040000>;
413 };
414 partition@5 {
415 label = "NAND.u-boot";
416 reg = <0x000c0000 0x00100000>;
417 };
418 partition@6 {
419 label = "NAND.u-boot-env";
420 reg = <0x001c0000 0x00020000>;
421 };
422 partition@7 {
423 label = "NAND.u-boot-env.backup1";
424 reg = <0x001e0000 0x00020000>;
425 };
426 partition@8 {
427 label = "NAND.kernel";
428 reg = <0x00200000 0x00800000>;
429 };
430 partition@9 {
431 label = "NAND.file-system";
432 reg = <0x00a00000 0x0f600000>;
433 };
434 };
435};
436
437&usb2_phy1 {
438 phy-supply = <&ldousb_reg>;
439};
440
441&usb2_phy2 {
442 phy-supply = <&ldousb_reg>;
443};
444
445&gpio7 {
446 ti,no-reset-on-init;
447 ti,no-idle-on-init;
448};
449
450&mac {
451 status = "okay";
452 dual_emac;
453};
454
455&cpsw_emac0 {
456 phy_id = <&davinci_mdio>, <2>;
457 phy-mode = "rgmii";
458 dual_emac_res_vlan = <1>;
459};
460
461&cpsw_emac1 {
462 phy_id = <&davinci_mdio>, <3>;
463 phy-mode = "rgmii";
464 dual_emac_res_vlan = <2>;
465};
466
467&dcan1 {
468 status = "ok";
469 pinctrl-names = "default", "sleep", "active";
470 pinctrl-0 = <&dcan1_pins_sleep>;
471 pinctrl-1 = <&dcan1_pins_sleep>;
472 pinctrl-2 = <&dcan1_pins_default>;
473};
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/clk/ti-dra7-atl.h>
13#include <dt-bindings/input/input.h>
14
15/ {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 memory {
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
22 };
23
24 evm_3v3_sd: fixedregulator-sd {
25 compatible = "regulator-fixed";
26 regulator-name = "evm_3v3_sd";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 enable-active-high;
30 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
31 };
32
33 evm_3v3_sw: fixedregulator-evm_3v3_sw {
34 compatible = "regulator-fixed";
35 regulator-name = "evm_3v3_sw";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 };
39
40 aic_dvdd: fixedregulator-aic_dvdd {
41 /* TPS77018DBVT */
42 compatible = "regulator-fixed";
43 regulator-name = "aic_dvdd";
44 vin-supply = <&evm_3v3_sw>;
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 };
48
49 extcon_usb1: extcon_usb1 {
50 compatible = "linux,extcon-usb-gpio";
51 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
52 };
53
54 extcon_usb2: extcon_usb2 {
55 compatible = "linux,extcon-usb-gpio";
56 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
57 };
58
59 vtt_fixed: fixedregulator-vtt {
60 compatible = "regulator-fixed";
61 regulator-name = "vtt_fixed";
62 regulator-min-microvolt = <1350000>;
63 regulator-max-microvolt = <1350000>;
64 regulator-always-on;
65 regulator-boot-on;
66 enable-active-high;
67 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
68 };
69
70 sound0: sound@0 {
71 compatible = "simple-audio-card";
72 simple-audio-card,name = "DRA7xx-EVM";
73 simple-audio-card,widgets =
74 "Headphone", "Headphone Jack",
75 "Line", "Line Out",
76 "Microphone", "Mic Jack",
77 "Line", "Line In";
78 simple-audio-card,routing =
79 "Headphone Jack", "HPLOUT",
80 "Headphone Jack", "HPROUT",
81 "Line Out", "LLOUT",
82 "Line Out", "RLOUT",
83 "MIC3L", "Mic Jack",
84 "MIC3R", "Mic Jack",
85 "Mic Jack", "Mic Bias",
86 "LINE1L", "Line In",
87 "LINE1R", "Line In";
88 simple-audio-card,format = "dsp_b";
89 simple-audio-card,bitclock-master = <&sound0_master>;
90 simple-audio-card,frame-master = <&sound0_master>;
91 simple-audio-card,bitclock-inversion;
92
93 sound0_master: simple-audio-card,cpu {
94 sound-dai = <&mcasp3>;
95 system-clock-frequency = <5644800>;
96 };
97
98 simple-audio-card,codec {
99 sound-dai = <&tlv320aic3106>;
100 clocks = <&atl_clkin2_ck>;
101 };
102 };
103
104 leds {
105 compatible = "gpio-leds";
106 led@0 {
107 label = "dra7:usr1";
108 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
109 default-state = "off";
110 };
111
112 led@1 {
113 label = "dra7:usr2";
114 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
115 default-state = "off";
116 };
117
118 led@2 {
119 label = "dra7:usr3";
120 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
121 default-state = "off";
122 };
123
124 led@3 {
125 label = "dra7:usr4";
126 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
130
131 gpio_keys {
132 compatible = "gpio-keys";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 autorepeat;
136
137 USER1 {
138 label = "btnUser1";
139 linux,code = <BTN_0>;
140 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
141 };
142
143 USER2 {
144 label = "btnUser2";
145 linux,code = <BTN_1>;
146 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
147 };
148 };
149};
150
151&dra7_pmx_core {
152 pinctrl-names = "default";
153 pinctrl-0 = <&vtt_pin>;
154
155 vtt_pin: pinmux_vtt_pin {
156 pinctrl-single,pins = <
157 DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
158 >;
159 };
160
161 i2c1_pins: pinmux_i2c1_pins {
162 pinctrl-single,pins = <
163 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
164 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
165 >;
166 };
167
168 i2c2_pins: pinmux_i2c2_pins {
169 pinctrl-single,pins = <
170 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
171 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
172 >;
173 };
174
175 i2c3_pins: pinmux_i2c3_pins {
176 pinctrl-single,pins = <
177 DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
178 DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
179 >;
180 };
181
182 mcspi1_pins: pinmux_mcspi1_pins {
183 pinctrl-single,pins = <
184 DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
185 DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
186 DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
187 DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
188 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
189 DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
190 >;
191 };
192
193 mcspi2_pins: pinmux_mcspi2_pins {
194 pinctrl-single,pins = <
195 DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
196 DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
197 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
198 DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
199 >;
200 };
201
202 uart1_pins: pinmux_uart1_pins {
203 pinctrl-single,pins = <
204 DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
205 DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
206 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
207 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
208 >;
209 };
210
211 uart2_pins: pinmux_uart2_pins {
212 pinctrl-single,pins = <
213 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
214 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
215 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
216 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
217 >;
218 };
219
220 uart3_pins: pinmux_uart3_pins {
221 pinctrl-single,pins = <
222 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
223 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
224 >;
225 };
226
227 qspi1_pins: pinmux_qspi1_pins {
228 pinctrl-single,pins = <
229 DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
230 DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
231 DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
232 DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
233 DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
234 DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
235 DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
236 DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
237 DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
238 DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
239 >;
240 };
241
242 usb1_pins: pinmux_usb1_pins {
243 pinctrl-single,pins = <
244 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
245 >;
246 };
247
248 usb2_pins: pinmux_usb2_pins {
249 pinctrl-single,pins = <
250 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
251 >;
252 };
253
254 nand_flash_x16: nand_flash_x16 {
255 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
256 * So NAND flash requires following switch settings:
257 * SW5.9 (GPMC_WPN) = LOW
258 * SW5.1 (NAND_BOOTn) = HIGH */
259 pinctrl-single,pins = <
260 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
261 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
262 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
263 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
264 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
265 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
266 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
267 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
268 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
269 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
270 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
271 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
272 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
273 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
274 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
275 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
276 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
277 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
278 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
279 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
280 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
281 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
282 >;
283 };
284
285 cpsw_default: cpsw_default {
286 pinctrl-single,pins = <
287 /* Slave 1 */
288 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
289 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
290 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
291 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
292 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
293 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
294 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
295 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
296 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
297 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
298 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
299 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
300
301 /* Slave 2 */
302 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
303 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
304 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
305 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
306 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
307 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
308 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
309 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
310 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
311 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
312 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
313 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
314 >;
315
316 };
317
318 cpsw_sleep: cpsw_sleep {
319 pinctrl-single,pins = <
320 /* Slave 1 */
321 DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
322 DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
323 DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
324 DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
325 DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
326 DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
327 DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
328 DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
329 DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
330 DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
331 DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
332 DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
333
334 /* Slave 2 */
335 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
336 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
337 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
338 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
339 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
340 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
341 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
342 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
343 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
344 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
345 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
346 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
347 >;
348 };
349
350 davinci_mdio_default: davinci_mdio_default {
351 pinctrl-single,pins = <
352 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
353 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
354 >;
355 };
356
357 davinci_mdio_sleep: davinci_mdio_sleep {
358 pinctrl-single,pins = <
359 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
360 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
361 >;
362 };
363
364 dcan1_pins_default: dcan1_pins_default {
365 pinctrl-single,pins = <
366 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
367 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
368 >;
369 };
370
371 dcan1_pins_sleep: dcan1_pins_sleep {
372 pinctrl-single,pins = <
373 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
374 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
375 >;
376 };
377
378 atl_pins: pinmux_atl_pins {
379 pinctrl-single,pins = <
380 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
381 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
382 >;
383 };
384
385 mcasp3_pins: pinmux_mcasp3_pins {
386 pinctrl-single,pins = <
387 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
388 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
389 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
390 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
391 >;
392 };
393
394 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
395 pinctrl-single,pins = <
396 DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
397 DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
398 DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
399 DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
400 >;
401 };
402};
403
404&i2c1 {
405 status = "okay";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c1_pins>;
408 clock-frequency = <400000>;
409
410 tps659038: tps659038@58 {
411 compatible = "ti,tps659038";
412 reg = <0x58>;
413
414 tps659038_pmic {
415 compatible = "ti,tps659038-pmic";
416
417 regulators {
418 smps123_reg: smps123 {
419 /* VDD_MPU */
420 regulator-name = "smps123";
421 regulator-min-microvolt = < 850000>;
422 regulator-max-microvolt = <1250000>;
423 regulator-always-on;
424 regulator-boot-on;
425 };
426
427 smps45_reg: smps45 {
428 /* VDD_DSPEVE */
429 regulator-name = "smps45";
430 regulator-min-microvolt = < 850000>;
431 regulator-max-microvolt = <1150000>;
432 regulator-always-on;
433 regulator-boot-on;
434 };
435
436 smps6_reg: smps6 {
437 /* VDD_GPU - over VDD_SMPS6 */
438 regulator-name = "smps6";
439 regulator-min-microvolt = <850000>;
440 regulator-max-microvolt = <1250000>;
441 regulator-always-on;
442 regulator-boot-on;
443 };
444
445 smps7_reg: smps7 {
446 /* CORE_VDD */
447 regulator-name = "smps7";
448 regulator-min-microvolt = <850000>;
449 regulator-max-microvolt = <1060000>;
450 regulator-always-on;
451 regulator-boot-on;
452 };
453
454 smps8_reg: smps8 {
455 /* VDD_IVAHD */
456 regulator-name = "smps8";
457 regulator-min-microvolt = < 850000>;
458 regulator-max-microvolt = <1250000>;
459 regulator-always-on;
460 regulator-boot-on;
461 };
462
463 smps9_reg: smps9 {
464 /* VDDS1V8 */
465 regulator-name = "smps9";
466 regulator-min-microvolt = <1800000>;
467 regulator-max-microvolt = <1800000>;
468 regulator-always-on;
469 regulator-boot-on;
470 };
471
472 ldo1_reg: ldo1 {
473 /* LDO1_OUT --> SDIO */
474 regulator-name = "ldo1";
475 regulator-min-microvolt = <1800000>;
476 regulator-max-microvolt = <3300000>;
477 regulator-always-on;
478 regulator-boot-on;
479 };
480
481 ldo2_reg: ldo2 {
482 /* VDD_RTCIO */
483 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
484 regulator-name = "ldo2";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 regulator-boot-on;
489 };
490
491 ldo3_reg: ldo3 {
492 /* VDDA_1V8_PHY */
493 regulator-name = "ldo3";
494 regulator-min-microvolt = <1800000>;
495 regulator-max-microvolt = <1800000>;
496 regulator-always-on;
497 regulator-boot-on;
498 };
499
500 ldo9_reg: ldo9 {
501 /* VDD_RTC */
502 regulator-name = "ldo9";
503 regulator-min-microvolt = <1050000>;
504 regulator-max-microvolt = <1050000>;
505 regulator-always-on;
506 regulator-boot-on;
507 regulator-allow-bypass;
508 };
509
510 ldoln_reg: ldoln {
511 /* VDDA_1V8_PLL */
512 regulator-name = "ldoln";
513 regulator-min-microvolt = <1800000>;
514 regulator-max-microvolt = <1800000>;
515 regulator-always-on;
516 regulator-boot-on;
517 };
518
519 ldousb_reg: ldousb {
520 /* VDDA_3V_USB: VDDA_USBHS33 */
521 regulator-name = "ldousb";
522 regulator-min-microvolt = <3300000>;
523 regulator-max-microvolt = <3300000>;
524 regulator-boot-on;
525 };
526 };
527 };
528 };
529
530 pcf_lcd: gpio@20 {
531 compatible = "nxp,pcf8575";
532 reg = <0x20>;
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-parent = <&gpio6>;
536 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
540
541 pcf_gpio_21: gpio@21 {
542 compatible = "ti,pcf8575";
543 reg = <0x21>;
544 lines-initial-states = <0x1408>;
545 gpio-controller;
546 #gpio-cells = <2>;
547 interrupt-parent = <&gpio6>;
548 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
551 };
552
553 tlv320aic3106: tlv320aic3106@19 {
554 #sound-dai-cells = <0>;
555 compatible = "ti,tlv320aic3106";
556 reg = <0x19>;
557 adc-settle-ms = <40>;
558 ai3x-micbias-vg = <1>; /* 2.0V */
559 status = "okay";
560
561 /* Regulators */
562 AVDD-supply = <&evm_3v3_sw>;
563 IOVDD-supply = <&evm_3v3_sw>;
564 DRVDD-supply = <&evm_3v3_sw>;
565 DVDD-supply = <&aic_dvdd>;
566 };
567};
568
569&i2c2 {
570 status = "okay";
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_pins>;
573 clock-frequency = <400000>;
574
575 pcf_hdmi: gpio@26 {
576 compatible = "nxp,pcf8575";
577 reg = <0x26>;
578 gpio-controller;
579 #gpio-cells = <2>;
580 p1 {
581 /* vin6_sel_s0: high: VIN6, low: audio */
582 gpio-hog;
583 gpios = <1 GPIO_ACTIVE_HIGH>;
584 output-low;
585 line-name = "vin6_sel_s0";
586 };
587 };
588};
589
590&i2c3 {
591 status = "okay";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c3_pins>;
594 clock-frequency = <400000>;
595};
596
597&mcspi1 {
598 status = "okay";
599 pinctrl-names = "default";
600 pinctrl-0 = <&mcspi1_pins>;
601};
602
603&mcspi2 {
604 status = "okay";
605 pinctrl-names = "default";
606 pinctrl-0 = <&mcspi2_pins>;
607};
608
609&uart1 {
610 status = "okay";
611 pinctrl-names = "default";
612 pinctrl-0 = <&uart1_pins>;
613 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
614 <&dra7_pmx_core 0x3e0>;
615};
616
617&uart2 {
618 status = "okay";
619 pinctrl-names = "default";
620 pinctrl-0 = <&uart2_pins>;
621};
622
623&uart3 {
624 status = "okay";
625 pinctrl-names = "default";
626 pinctrl-0 = <&uart3_pins>;
627};
628
629&mmc1 {
630 status = "okay";
631 vmmc-supply = <&evm_3v3_sd>;
632 vmmc_aux-supply = <&ldo1_reg>;
633 bus-width = <4>;
634 /*
635 * SDCD signal is not being used here - using the fact that GPIO mode
636 * is always hardwired.
637 */
638 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
639};
640
641&mmc2 {
642 status = "okay";
643 vmmc-supply = <&evm_3v3_sw>;
644 bus-width = <8>;
645};
646
647&cpu0 {
648 cpu0-supply = <&smps123_reg>;
649};
650
651&qspi {
652 status = "okay";
653 pinctrl-names = "default";
654 pinctrl-0 = <&qspi1_pins>;
655
656 spi-max-frequency = <48000000>;
657 m25p80@0 {
658 compatible = "s25fl256s1";
659 spi-max-frequency = <48000000>;
660 reg = <0>;
661 spi-tx-bus-width = <1>;
662 spi-rx-bus-width = <4>;
663 spi-cpol;
664 spi-cpha;
665 #address-cells = <1>;
666 #size-cells = <1>;
667
668 /* MTD partition table.
669 * The ROM checks the first four physical blocks
670 * for a valid file to boot and the flash here is
671 * 64KiB block size.
672 */
673 partition@0 {
674 label = "QSPI.SPL";
675 reg = <0x00000000 0x000010000>;
676 };
677 partition@1 {
678 label = "QSPI.SPL.backup1";
679 reg = <0x00010000 0x00010000>;
680 };
681 partition@2 {
682 label = "QSPI.SPL.backup2";
683 reg = <0x00020000 0x00010000>;
684 };
685 partition@3 {
686 label = "QSPI.SPL.backup3";
687 reg = <0x00030000 0x00010000>;
688 };
689 partition@4 {
690 label = "QSPI.u-boot";
691 reg = <0x00040000 0x00100000>;
692 };
693 partition@5 {
694 label = "QSPI.u-boot-spl-os";
695 reg = <0x00140000 0x00080000>;
696 };
697 partition@6 {
698 label = "QSPI.u-boot-env";
699 reg = <0x001c0000 0x00010000>;
700 };
701 partition@7 {
702 label = "QSPI.u-boot-env.backup1";
703 reg = <0x001d0000 0x0010000>;
704 };
705 partition@8 {
706 label = "QSPI.kernel";
707 reg = <0x001e0000 0x0800000>;
708 };
709 partition@9 {
710 label = "QSPI.file-system";
711 reg = <0x009e0000 0x01620000>;
712 };
713 };
714};
715
716&omap_dwc3_1 {
717 extcon = <&extcon_usb1>;
718};
719
720&omap_dwc3_2 {
721 extcon = <&extcon_usb2>;
722};
723
724&usb1 {
725 dr_mode = "peripheral";
726 pinctrl-names = "default";
727 pinctrl-0 = <&usb1_pins>;
728};
729
730&usb2 {
731 dr_mode = "host";
732 pinctrl-names = "default";
733 pinctrl-0 = <&usb2_pins>;
734};
735
736&elm {
737 status = "okay";
738};
739
740&gpmc {
741 status = "okay";
742 pinctrl-names = "default";
743 pinctrl-0 = <&nand_flash_x16>;
744 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
745 nand@0,0 {
746 compatible = "ti,omap2-nand";
747 reg = <0 0 4>; /* device IO registers */
748 interrupt-parent = <&gpmc>;
749 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
750 <1 IRQ_TYPE_NONE>; /* termcount */
751 ti,nand-ecc-opt = "bch8";
752 ti,elm-id = <&elm>;
753 nand-bus-width = <16>;
754 gpmc,device-width = <2>;
755 gpmc,sync-clk-ps = <0>;
756 gpmc,cs-on-ns = <0>;
757 gpmc,cs-rd-off-ns = <80>;
758 gpmc,cs-wr-off-ns = <80>;
759 gpmc,adv-on-ns = <0>;
760 gpmc,adv-rd-off-ns = <60>;
761 gpmc,adv-wr-off-ns = <60>;
762 gpmc,we-on-ns = <10>;
763 gpmc,we-off-ns = <50>;
764 gpmc,oe-on-ns = <4>;
765 gpmc,oe-off-ns = <40>;
766 gpmc,access-ns = <40>;
767 gpmc,wr-access-ns = <80>;
768 gpmc,rd-cycle-ns = <80>;
769 gpmc,wr-cycle-ns = <80>;
770 gpmc,bus-turnaround-ns = <0>;
771 gpmc,cycle2cycle-delay-ns = <0>;
772 gpmc,clk-activation-ns = <0>;
773 gpmc,wr-data-mux-bus-ns = <0>;
774 /* MTD partition table */
775 /* All SPL-* partitions are sized to minimal length
776 * which can be independently programmable. For
777 * NAND flash this is equal to size of erase-block */
778 #address-cells = <1>;
779 #size-cells = <1>;
780 partition@0 {
781 label = "NAND.SPL";
782 reg = <0x00000000 0x000020000>;
783 };
784 partition@1 {
785 label = "NAND.SPL.backup1";
786 reg = <0x00020000 0x00020000>;
787 };
788 partition@2 {
789 label = "NAND.SPL.backup2";
790 reg = <0x00040000 0x00020000>;
791 };
792 partition@3 {
793 label = "NAND.SPL.backup3";
794 reg = <0x00060000 0x00020000>;
795 };
796 partition@4 {
797 label = "NAND.u-boot-spl-os";
798 reg = <0x00080000 0x00040000>;
799 };
800 partition@5 {
801 label = "NAND.u-boot";
802 reg = <0x000c0000 0x00100000>;
803 };
804 partition@6 {
805 label = "NAND.u-boot-env";
806 reg = <0x001c0000 0x00020000>;
807 };
808 partition@7 {
809 label = "NAND.u-boot-env.backup1";
810 reg = <0x001e0000 0x00020000>;
811 };
812 partition@8 {
813 label = "NAND.kernel";
814 reg = <0x00200000 0x00800000>;
815 };
816 partition@9 {
817 label = "NAND.file-system";
818 reg = <0x00a00000 0x0f600000>;
819 };
820 };
821};
822
823&usb2_phy1 {
824 phy-supply = <&ldousb_reg>;
825};
826
827&usb2_phy2 {
828 phy-supply = <&ldousb_reg>;
829};
830
831&gpio7 {
832 ti,no-reset-on-init;
833 ti,no-idle-on-init;
834};
835
836&mac {
837 status = "okay";
838 pinctrl-names = "default", "sleep";
839 pinctrl-0 = <&cpsw_default>;
840 pinctrl-1 = <&cpsw_sleep>;
841 dual_emac;
842};
843
844&cpsw_emac0 {
845 phy_id = <&davinci_mdio>, <2>;
846 phy-mode = "rgmii";
847 dual_emac_res_vlan = <1>;
848};
849
850&cpsw_emac1 {
851 phy_id = <&davinci_mdio>, <3>;
852 phy-mode = "rgmii";
853 dual_emac_res_vlan = <2>;
854};
855
856&davinci_mdio {
857 pinctrl-names = "default", "sleep";
858 pinctrl-0 = <&davinci_mdio_default>;
859 pinctrl-1 = <&davinci_mdio_sleep>;
860};
861
862&dcan1 {
863 status = "ok";
864 pinctrl-names = "default", "sleep", "active";
865 pinctrl-0 = <&dcan1_pins_sleep>;
866 pinctrl-1 = <&dcan1_pins_sleep>;
867 pinctrl-2 = <&dcan1_pins_default>;
868};
869
870&atl {
871 pinctrl-names = "default";
872 pinctrl-0 = <&atl_pins>;
873
874 assigned-clocks = <&abe_dpll_sys_clk_mux>,
875 <&atl_gfclk_mux>,
876 <&dpll_abe_ck>,
877 <&dpll_abe_m2x2_ck>,
878 <&atl_clkin2_ck>;
879 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
880 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
881
882 status = "okay";
883
884 atl2 {
885 bws = <DRA7_ATL_WS_MCASP2_FSX>;
886 aws = <DRA7_ATL_WS_MCASP3_FSX>;
887 };
888};
889
890&mcasp3 {
891 #sound-dai-cells = <0>;
892 pinctrl-names = "default", "sleep";
893 pinctrl-0 = <&mcasp3_pins>;
894 pinctrl-1 = <&mcasp3_sleep_pins>;
895
896 assigned-clocks = <&mcasp3_ahclkx_mux>;
897 assigned-clock-parents = <&atl_clkin2_ck>;
898
899 status = "okay";
900
901 op-mode = <0>; /* MCASP_IIS_MODE */
902 tdm-slots = <2>;
903 /* 4 serializer */
904 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
905 1 2 0 0
906 >;
907};
908
909&mailbox5 {
910 status = "okay";
911 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
912 status = "okay";
913 };
914 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
915 status = "okay";
916 };
917};
918
919&mailbox6 {
920 status = "okay";
921 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
922 status = "okay";
923 };
924 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
925 status = "okay";
926 };
927};