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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada 388 evaluation board
4 * (DB-88F6820)
5 *
6 * Copyright (C) 2014 Marvell
7 *
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */
10
11/dts-v1/;
12#include "armada-388.dtsi"
13
14/ {
15 model = "Marvell Armada 385 Development Board";
16 compatible = "marvell,a385-db", "marvell,armada388",
17 "marvell,armada385", "marvell,armada380";
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x10000000>; /* 256 MB */
26 };
27
28 soc {
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
34
35 internal-regs {
36 i2c@11000 {
37 status = "okay";
38 clock-frequency = <100000>;
39 };
40
41 i2c@11100 {
42 status = "okay";
43 clock-frequency = <100000>;
44 };
45
46 serial@12000 {
47 status = "okay";
48 };
49
50 ethernet@30000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 buffer-manager = <&bm>;
55 bm,pool-long = <2>;
56 bm,pool-short = <3>;
57 };
58
59 usb@58000 {
60 status = "ok";
61 };
62
63 ethernet@70000 {
64 status = "okay";
65 phy = <&phy0>;
66 phy-mode = "rgmii-id";
67 buffer-manager = <&bm>;
68 bm,pool-long = <0>;
69 bm,pool-short = <1>;
70 };
71
72 mdio@72004 {
73 phy0: ethernet-phy@0 {
74 reg = <0>;
75 };
76
77 phy1: ethernet-phy@1 {
78 reg = <1>;
79 };
80 };
81
82 sata@a8000 {
83 status = "okay";
84 };
85
86 sata@e0000 {
87 status = "okay";
88 };
89
90 bm@c8000 {
91 status = "okay";
92 };
93
94 flash@d0000 {
95 status = "okay";
96 num-cs = <1>;
97 marvell,nand-keep-config;
98 marvell,nand-enable-arbiter;
99 nand-on-flash-bbt;
100 nand-ecc-strength = <4>;
101 nand-ecc-step-size = <512>;
102
103 partition@0 {
104 label = "U-Boot";
105 reg = <0 0x800000>;
106 };
107 partition@800000 {
108 label = "Linux";
109 reg = <0x800000 0x800000>;
110 };
111 partition@1000000 {
112 label = "Filesystem";
113 reg = <0x1000000 0x3f000000>;
114 };
115 };
116
117 sdhci@d8000 {
118 broken-cd;
119 wp-inverted;
120 bus-width = <8>;
121 status = "okay";
122 no-1-8-v;
123 };
124
125 usb3@f0000 {
126 status = "okay";
127 };
128
129 usb3@f8000 {
130 status = "okay";
131 };
132 };
133
134 bm-bppi {
135 status = "okay";
136 };
137
138 pcie {
139 status = "okay";
140 /*
141 * The two PCIe units are accessible through
142 * standard PCIe slots on the board.
143 */
144 pcie@1,0 {
145 /* Port 0, Lane 0 */
146 status = "okay";
147 };
148 pcie@2,0 {
149 /* Port 1, Lane 0 */
150 status = "okay";
151 };
152 };
153 };
154};
155
156&spi0 {
157 status = "okay";
158
159 spi-flash@0 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "w25q32", "jedec,spi-nor";
163 reg = <0>; /* Chip select 0 */
164 spi-max-frequency = <108000000>;
165 };
166};
167
1/*
2 * Device Tree file for Marvell Armada 388 evaluation board
3 * (DB-88F6820)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "armada-388.dtsi"
50
51/ {
52 model = "Marvell Armada 385 Development Board";
53 compatible = "marvell,a385-db", "marvell,armada388",
54 "marvell,armada385", "marvell,armada380";
55
56 chosen {
57 stdout-path = "serial0:115200n8";
58 };
59
60 memory {
61 device_type = "memory";
62 reg = <0x00000000 0x10000000>; /* 256 MB */
63 };
64
65 soc {
66 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
67 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
68 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
69 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
70 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
71
72 internal-regs {
73 spi@10600 {
74 status = "okay";
75
76 spi-flash@0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "w25q32", "jedec,spi-nor";
80 reg = <0>; /* Chip select 0 */
81 spi-max-frequency = <108000000>;
82 };
83 };
84
85 i2c@11000 {
86 status = "okay";
87 clock-frequency = <100000>;
88 };
89
90 i2c@11100 {
91 status = "okay";
92 clock-frequency = <100000>;
93 };
94
95 serial@12000 {
96 status = "okay";
97 };
98
99 ethernet@30000 {
100 status = "okay";
101 phy = <&phy1>;
102 phy-mode = "rgmii-id";
103 buffer-manager = <&bm>;
104 bm,pool-long = <2>;
105 bm,pool-short = <3>;
106 };
107
108 usb@58000 {
109 status = "ok";
110 };
111
112 ethernet@70000 {
113 status = "okay";
114 phy = <&phy0>;
115 phy-mode = "rgmii-id";
116 buffer-manager = <&bm>;
117 bm,pool-long = <0>;
118 bm,pool-short = <1>;
119 };
120
121 mdio@72004 {
122 phy0: ethernet-phy@0 {
123 reg = <0>;
124 };
125
126 phy1: ethernet-phy@1 {
127 reg = <1>;
128 };
129 };
130
131 sata@a8000 {
132 status = "okay";
133 };
134
135 sata@e0000 {
136 status = "okay";
137 };
138
139 bm@c8000 {
140 status = "okay";
141 };
142
143 flash@d0000 {
144 status = "okay";
145 num-cs = <1>;
146 marvell,nand-keep-config;
147 marvell,nand-enable-arbiter;
148 nand-on-flash-bbt;
149 nand-ecc-strength = <4>;
150 nand-ecc-step-size = <512>;
151
152 partition@0 {
153 label = "U-Boot";
154 reg = <0 0x800000>;
155 };
156 partition@800000 {
157 label = "Linux";
158 reg = <0x800000 0x800000>;
159 };
160 partition@1000000 {
161 label = "Filesystem";
162 reg = <0x1000000 0x3f000000>;
163 };
164 };
165
166 sdhci@d8000 {
167 broken-cd;
168 wp-inverted;
169 bus-width = <8>;
170 status = "okay";
171 no-1-8-v;
172 };
173
174 usb3@f0000 {
175 status = "okay";
176 };
177
178 usb3@f8000 {
179 status = "okay";
180 };
181 };
182
183 bm-bppi {
184 status = "okay";
185 };
186
187 pcie-controller {
188 status = "okay";
189 /*
190 * The two PCIe units are accessible through
191 * standard PCIe slots on the board.
192 */
193 pcie@1,0 {
194 /* Port 0, Lane 0 */
195 status = "okay";
196 };
197 pcie@2,0 {
198 /* Port 1, Lane 0 */
199 status = "okay";
200 };
201 };
202 };
203};