1/*
 2 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8/dts-v1/;
 9
10/include/ "skeleton.dtsi"
11
12/ {
13	model = "snps,nsim";
14	compatible = "snps,nsim";
 
15	#address-cells = <1>;
16	#size-cells = <1>;
17	interrupt-parent = <&core_intc>;
18
19	chosen {
20		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
21	};
22
23	aliases {
24		serial0 = &arcuart0;
25	};
26
27	fpga {
28		compatible = "simple-bus";
29		#address-cells = <1>;
30		#size-cells = <1>;
31
32		/* child and parent address space 1:1 mapped */
33		ranges;
34
35		core_clk: core_clk {
36			#clock-cells = <0>;
37			compatible = "fixed-clock";
38			clock-frequency = <80000000>;
39		};
40
41		core_intc: interrupt-controller {
42			compatible = "snps,arc700-intc";
43			interrupt-controller;
44			#interrupt-cells = <1>;
45		};
46
47		arcuart0: serial@c0fc1000 {
48			compatible = "snps,arc-uart";
49			reg = <0xc0fc1000 0x100>;
50			interrupts = <5>;
51			clock-frequency = <80000000>;
52			current-speed = <115200>;
53			status = "okay";
54		};
55
56		ethernet@c0fc2000 {
57			compatible = "snps,arc-emac";
58			reg = <0xc0fc2000 0x3c>;
59			interrupts = <6>;
60			mac-address = [ 00 11 22 33 44 55 ];
61			clock-frequency = <80000000>;
62			max-speed = <100>;
63			phy = <&phy0>;
64
65			#address-cells = <1>;
66			#size-cells = <0>;
67			phy0: ethernet-phy@0 {
68				reg = <1>;
69			};
70		};
71
72		arcpct0: pct {
73			compatible = "snps,arc700-pct";
74		};
75	};
76};

 1/*
 2 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8/dts-v1/;
 9
10/include/ "skeleton.dtsi"
11
12/ {
 
13	compatible = "snps,nsim";
14	clock-frequency = <80000000>;	/* 80 MHZ */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	interrupt-parent = <&intc>;
18
19	chosen {
20		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
21	};
22
23	aliases {
24		serial0 = &arcuart0;
25	};
26
27	fpga {
28		compatible = "simple-bus";
29		#address-cells = <1>;
30		#size-cells = <1>;
31
32		/* child and parent address space 1:1 mapped */
33		ranges;
34
35		intc: interrupt-controller {
 
 
 
 
 
 
36			compatible = "snps,arc700-intc";
37			interrupt-controller;
38			#interrupt-cells = <1>;
39		};
40
41		arcuart0: serial@c0fc1000 {
42			compatible = "snps,arc-uart";
43			reg = <0xc0fc1000 0x100>;
44			interrupts = <5>;
45			clock-frequency = <80000000>;
46			current-speed = <115200>;
47			status = "okay";
48		};
49
50		ethernet@c0fc2000 {
51			compatible = "snps,arc-emac";
52			reg = <0xc0fc2000 0x3c>;
53			interrupts = <6>;
54			mac-address = [ 00 11 22 33 44 55 ];
55			clock-frequency = <80000000>;
56			max-speed = <100>;
57			phy = <&phy0>;
58
59			#address-cells = <1>;
60			#size-cells = <0>;
61			phy0: ethernet-phy@0 {
62				reg = <1>;
63			};
64		};
65
66		arcpmu0: pmu {
67			compatible = "snps,arc700-pct";
68		};
69	};
70};