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1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2016 Krzysztof Kozlowski
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5421 clock controller.
10*/
11
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
14
15/* core clocks */
16#define CLK_FIN_PLL 1
17#define CLK_FOUT_APLL 2
18#define CLK_FOUT_CPLL 3
19#define CLK_FOUT_MPLL 4
20#define CLK_FOUT_BPLL 5
21#define CLK_FOUT_KPLL 6
22#define CLK_FOUT_EPLL 7
23
24/* gate for special clocks (sclk) */
25#define CLK_SCLK_UART0 128
26#define CLK_SCLK_UART1 129
27#define CLK_SCLK_UART2 130
28#define CLK_SCLK_UART3 131
29#define CLK_SCLK_MMC0 132
30#define CLK_SCLK_MMC1 133
31#define CLK_SCLK_MMC2 134
32#define CLK_SCLK_USBD300 150
33#define CLK_SCLK_USBD301 151
34#define CLK_SCLK_USBPHY300 152
35#define CLK_SCLK_USBPHY301 153
36#define CLK_SCLK_PWM 155
37
38/* gate clocks */
39#define CLK_UART0 257
40#define CLK_UART1 258
41#define CLK_UART2 259
42#define CLK_I2C0 261
43#define CLK_I2C1 262
44#define CLK_I2C2 263
45#define CLK_I2C3 264
46#define CLK_USI0 265
47#define CLK_USI1 266
48#define CLK_USI2 267
49#define CLK_USI3 268
50#define CLK_UART3 260
51#define CLK_PWM 279
52#define CLK_MCT 315
53#define CLK_WDT 316
54#define CLK_RTC 317
55#define CLK_TMU 318
56#define CLK_MMC0 351
57#define CLK_MMC1 352
58#define CLK_MMC2 353
59#define CLK_PDMA0 362
60#define CLK_PDMA1 363
61#define CLK_USBH20 365
62#define CLK_USBD300 366
63#define CLK_USBD301 367
64#define CLK_SSS 471
65
66#define CLK_NR_CLKS 512
67
68#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2016 Krzysztof Kozlowski
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5421 clock controller.
10*/
11
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
14
15/* core clocks */
16#define CLK_FIN_PLL 1
17#define CLK_FOUT_APLL 2
18#define CLK_FOUT_CPLL 3
19#define CLK_FOUT_MPLL 4
20#define CLK_FOUT_BPLL 5
21#define CLK_FOUT_KPLL 6
22#define CLK_FOUT_EPLL 7
23
24/* gate for special clocks (sclk) */
25#define CLK_SCLK_UART0 128
26#define CLK_SCLK_UART1 129
27#define CLK_SCLK_UART2 130
28#define CLK_SCLK_UART3 131
29#define CLK_SCLK_MMC0 132
30#define CLK_SCLK_MMC1 133
31#define CLK_SCLK_MMC2 134
32#define CLK_SCLK_USBD300 150
33#define CLK_SCLK_USBD301 151
34#define CLK_SCLK_USBPHY300 152
35#define CLK_SCLK_USBPHY301 153
36#define CLK_SCLK_PWM 155
37
38/* gate clocks */
39#define CLK_UART0 257
40#define CLK_UART1 258
41#define CLK_UART2 259
42#define CLK_I2C0 261
43#define CLK_I2C1 262
44#define CLK_I2C2 263
45#define CLK_I2C3 264
46#define CLK_USI0 265
47#define CLK_USI1 266
48#define CLK_USI2 267
49#define CLK_USI3 268
50#define CLK_UART3 260
51#define CLK_PWM 279
52#define CLK_MCT 315
53#define CLK_WDT 316
54#define CLK_RTC 317
55#define CLK_TMU 318
56#define CLK_MMC0 351
57#define CLK_MMC1 352
58#define CLK_MMC2 353
59#define CLK_PDMA0 362
60#define CLK_PDMA1 363
61#define CLK_USBH20 365
62#define CLK_USBD300 366
63#define CLK_USBD301 367
64#define CLK_SSS 471
65
66#define CLK_NR_CLKS 512
67
68#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */