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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11
12#include <linux/slab.h>
13#include <asm/unaligned.h>
14
15#include "xhci.h"
16#include "xhci-trace.h"
17
18#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
21
22/* USB 3 BOS descriptor and a capability descriptors, combined.
23 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
24 */
25static u8 usb_bos_descriptor [] = {
26 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
27 USB_DT_BOS, /* __u8 bDescriptorType */
28 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
29 0x1, /* __u8 bNumDeviceCaps */
30 /* First device capability, SuperSpeed */
31 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
32 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
33 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
34 0x00, /* bmAttributes, LTM off by default */
35 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
36 0x03, /* bFunctionalitySupport,
37 USB 3.0 speed only */
38 0x00, /* bU1DevExitLat, set later. */
39 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
40 /* Second device capability, SuperSpeedPlus */
41 0x1c, /* bLength 28, will be adjusted later */
42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
43 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
44 0x00, /* bReserved 0 */
45 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
46 0x01, 0x00, /* wFunctionalitySupport */
47 0x00, 0x00, /* wReserved 0 */
48 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
50 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
51 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
53};
54
55static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
56 u16 wLength)
57{
58 int i, ssa_count;
59 u32 temp;
60 u16 desc_size, ssp_cap_size, ssa_size = 0;
61 bool usb3_1 = false;
62
63 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
64 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
65
66 /* does xhci support USB 3.1 Enhanced SuperSpeed */
67 if (xhci->usb3_rhub.min_rev >= 0x01) {
68 /* does xhci provide a PSI table for SSA speed attributes? */
69 if (xhci->usb3_rhub.psi_count) {
70 /* two SSA entries for each unique PSI ID, RX and TX */
71 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
72 ssa_size = ssa_count * sizeof(u32);
73 ssp_cap_size -= 16; /* skip copying the default SSA */
74 }
75 desc_size += ssp_cap_size;
76 usb3_1 = true;
77 }
78 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
79
80 if (usb3_1) {
81 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
82 buf[4] += 1;
83 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
84 }
85
86 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
87 return wLength;
88
89 /* Indicate whether the host has LTM support. */
90 temp = readl(&xhci->cap_regs->hcc_params);
91 if (HCC_LTC(temp))
92 buf[8] |= USB_LTM_SUPPORT;
93
94 /* Set the U1 and U2 exit latencies. */
95 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
96 temp = readl(&xhci->cap_regs->hcs_params3);
97 buf[12] = HCS_U1_LATENCY(temp);
98 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
99 }
100
101 /* If PSI table exists, add the custom speed attributes from it */
102 if (usb3_1 && xhci->usb3_rhub.psi_count) {
103 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
104 int offset;
105
106 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
107
108 if (wLength < desc_size)
109 return wLength;
110 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
111
112 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
113 bm_attrib = (ssa_count - 1) & 0x1f;
114 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
115 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
116
117 if (wLength < desc_size + ssa_size)
118 return wLength;
119 /*
120 * Create the Sublink Speed Attributes (SSA) array.
121 * The xhci PSI field and USB 3.1 SSA fields are very similar,
122 * but link type bits 7:6 differ for values 01b and 10b.
123 * xhci has also only one PSI entry for a symmetric link when
124 * USB 3.1 requires two SSA entries (RX and TX) for every link
125 */
126 offset = desc_size;
127 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
128 psi = xhci->usb3_rhub.psi[i];
129 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
130 psi_exp = XHCI_EXT_PORT_PSIE(psi);
131 psi_mant = XHCI_EXT_PORT_PSIM(psi);
132
133 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
134 for (; psi_exp < 3; psi_exp++)
135 psi_mant /= 1000;
136 if (psi_mant >= 10)
137 psi |= BIT(14);
138
139 if ((psi & PLT_MASK) == PLT_SYM) {
140 /* Symmetric, create SSA RX and TX from one PSI entry */
141 put_unaligned_le32(psi, &buf[offset]);
142 psi |= 1 << 7; /* turn entry to TX */
143 offset += 4;
144 if (offset >= desc_size + ssa_size)
145 return desc_size + ssa_size;
146 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
147 /* Asymetric RX, flip bits 7:6 for SSA */
148 psi ^= PLT_MASK;
149 }
150 put_unaligned_le32(psi, &buf[offset]);
151 offset += 4;
152 if (offset >= desc_size + ssa_size)
153 return desc_size + ssa_size;
154 }
155 }
156 /* ssa_size is 0 for other than usb 3.1 hosts */
157 return desc_size + ssa_size;
158}
159
160static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
161 struct usb_hub_descriptor *desc, int ports)
162{
163 u16 temp;
164
165 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
166 desc->bHubContrCurrent = 0;
167
168 desc->bNbrPorts = ports;
169 temp = 0;
170 /* Bits 1:0 - support per-port power switching, or power always on */
171 if (HCC_PPC(xhci->hcc_params))
172 temp |= HUB_CHAR_INDV_PORT_LPSM;
173 else
174 temp |= HUB_CHAR_NO_LPSM;
175 /* Bit 2 - root hubs are not part of a compound device */
176 /* Bits 4:3 - individual port over current protection */
177 temp |= HUB_CHAR_INDV_PORT_OCPM;
178 /* Bits 6:5 - no TTs in root ports */
179 /* Bit 7 - no port indicators */
180 desc->wHubCharacteristics = cpu_to_le16(temp);
181}
182
183/* Fill in the USB 2.0 roothub descriptor */
184static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
185 struct usb_hub_descriptor *desc)
186{
187 int ports;
188 u16 temp;
189 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
190 u32 portsc;
191 unsigned int i;
192
193 ports = xhci->num_usb2_ports;
194
195 xhci_common_hub_descriptor(xhci, desc, ports);
196 desc->bDescriptorType = USB_DT_HUB;
197 temp = 1 + (ports / 8);
198 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
199
200 /* The Device Removable bits are reported on a byte granularity.
201 * If the port doesn't exist within that byte, the bit is set to 0.
202 */
203 memset(port_removable, 0, sizeof(port_removable));
204 for (i = 0; i < ports; i++) {
205 portsc = readl(xhci->usb2_ports[i]);
206 /* If a device is removable, PORTSC reports a 0, same as in the
207 * hub descriptor DeviceRemovable bits.
208 */
209 if (portsc & PORT_DEV_REMOVE)
210 /* This math is hairy because bit 0 of DeviceRemovable
211 * is reserved, and bit 1 is for port 1, etc.
212 */
213 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
214 }
215
216 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
217 * ports on it. The USB 2.0 specification says that there are two
218 * variable length fields at the end of the hub descriptor:
219 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
220 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
221 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
222 * 0xFF, so we initialize the both arrays (DeviceRemovable and
223 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
224 * set of ports that actually exist.
225 */
226 memset(desc->u.hs.DeviceRemovable, 0xff,
227 sizeof(desc->u.hs.DeviceRemovable));
228 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
229 sizeof(desc->u.hs.PortPwrCtrlMask));
230
231 for (i = 0; i < (ports + 1 + 7) / 8; i++)
232 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
233 sizeof(__u8));
234}
235
236/* Fill in the USB 3.0 roothub descriptor */
237static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
238 struct usb_hub_descriptor *desc)
239{
240 int ports;
241 u16 port_removable;
242 u32 portsc;
243 unsigned int i;
244
245 ports = xhci->num_usb3_ports;
246 xhci_common_hub_descriptor(xhci, desc, ports);
247 desc->bDescriptorType = USB_DT_SS_HUB;
248 desc->bDescLength = USB_DT_SS_HUB_SIZE;
249
250 /* header decode latency should be zero for roothubs,
251 * see section 4.23.5.2.
252 */
253 desc->u.ss.bHubHdrDecLat = 0;
254 desc->u.ss.wHubDelay = 0;
255
256 port_removable = 0;
257 /* bit 0 is reserved, bit 1 is for port 1, etc. */
258 for (i = 0; i < ports; i++) {
259 portsc = readl(xhci->usb3_ports[i]);
260 if (portsc & PORT_DEV_REMOVE)
261 port_removable |= 1 << (i + 1);
262 }
263
264 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
265}
266
267static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
268 struct usb_hub_descriptor *desc)
269{
270
271 if (hcd->speed >= HCD_USB3)
272 xhci_usb3_hub_descriptor(hcd, xhci, desc);
273 else
274 xhci_usb2_hub_descriptor(hcd, xhci, desc);
275
276}
277
278static unsigned int xhci_port_speed(unsigned int port_status)
279{
280 if (DEV_LOWSPEED(port_status))
281 return USB_PORT_STAT_LOW_SPEED;
282 if (DEV_HIGHSPEED(port_status))
283 return USB_PORT_STAT_HIGH_SPEED;
284 /*
285 * FIXME: Yes, we should check for full speed, but the core uses that as
286 * a default in portspeed() in usb/core/hub.c (which is the only place
287 * USB_PORT_STAT_*_SPEED is used).
288 */
289 return 0;
290}
291
292/*
293 * These bits are Read Only (RO) and should be saved and written to the
294 * registers: 0, 3, 10:13, 30
295 * connect status, over-current status, port speed, and device removable.
296 * connect status and port speed are also sticky - meaning they're in
297 * the AUX well and they aren't changed by a hot, warm, or cold reset.
298 */
299#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
300/*
301 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
302 * bits 5:8, 9, 14:15, 25:27
303 * link state, port power, port indicator state, "wake on" enable state
304 */
305#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
306/*
307 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
308 * bit 4 (port reset)
309 */
310#define XHCI_PORT_RW1S ((1<<4))
311/*
312 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
313 * bits 1, 17, 18, 19, 20, 21, 22, 23
314 * port enable/disable, and
315 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
316 * over-current, reset, link state, and L1 change
317 */
318#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
319/*
320 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
321 * latched in
322 */
323#define XHCI_PORT_RW ((1<<16))
324/*
325 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
326 * bits 2, 24, 28:31
327 */
328#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
329
330/*
331 * Given a port state, this function returns a value that would result in the
332 * port being in the same state, if the value was written to the port status
333 * control register.
334 * Save Read Only (RO) bits and save read/write bits where
335 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
336 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
337 */
338u32 xhci_port_state_to_neutral(u32 state)
339{
340 /* Save read-only status and port state */
341 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
342}
343
344/*
345 * find slot id based on port number.
346 * @port: The one-based port number from one of the two split roothubs.
347 */
348int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
349 u16 port)
350{
351 int slot_id;
352 int i;
353 enum usb_device_speed speed;
354
355 slot_id = 0;
356 for (i = 0; i < MAX_HC_SLOTS; i++) {
357 if (!xhci->devs[i] || !xhci->devs[i]->udev)
358 continue;
359 speed = xhci->devs[i]->udev->speed;
360 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
361 && xhci->devs[i]->fake_port == port) {
362 slot_id = i;
363 break;
364 }
365 }
366
367 return slot_id;
368}
369
370/*
371 * Stop device
372 * It issues stop endpoint command for EP 0 to 30. And wait the last command
373 * to complete.
374 * suspend will set to 1, if suspend bit need to set in command.
375 */
376static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
377{
378 struct xhci_virt_device *virt_dev;
379 struct xhci_command *cmd;
380 unsigned long flags;
381 int ret;
382 int i;
383
384 ret = 0;
385 virt_dev = xhci->devs[slot_id];
386 if (!virt_dev)
387 return -ENODEV;
388
389 trace_xhci_stop_device(virt_dev);
390
391 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
392 if (!cmd)
393 return -ENOMEM;
394
395 spin_lock_irqsave(&xhci->lock, flags);
396 for (i = LAST_EP_INDEX; i > 0; i--) {
397 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
398 struct xhci_ep_ctx *ep_ctx;
399 struct xhci_command *command;
400
401 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
402
403 /* Check ep is running, required by AMD SNPS 3.1 xHC */
404 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
405 continue;
406
407 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
408 if (!command) {
409 spin_unlock_irqrestore(&xhci->lock, flags);
410 ret = -ENOMEM;
411 goto cmd_cleanup;
412 }
413
414 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
415 i, suspend);
416 if (ret) {
417 spin_unlock_irqrestore(&xhci->lock, flags);
418 xhci_free_command(xhci, command);
419 goto cmd_cleanup;
420 }
421 }
422 }
423 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
424 if (ret) {
425 spin_unlock_irqrestore(&xhci->lock, flags);
426 goto cmd_cleanup;
427 }
428
429 xhci_ring_cmd_db(xhci);
430 spin_unlock_irqrestore(&xhci->lock, flags);
431
432 /* Wait for last stop endpoint command to finish */
433 wait_for_completion(cmd->completion);
434
435 if (cmd->status == COMP_COMMAND_ABORTED ||
436 cmd->status == COMP_COMMAND_RING_STOPPED) {
437 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
438 ret = -ETIME;
439 }
440
441cmd_cleanup:
442 xhci_free_command(xhci, cmd);
443 return ret;
444}
445
446/*
447 * Ring device, it rings the all doorbells unconditionally.
448 */
449void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
450{
451 int i, s;
452 struct xhci_virt_ep *ep;
453
454 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
455 ep = &xhci->devs[slot_id]->eps[i];
456
457 if (ep->ep_state & EP_HAS_STREAMS) {
458 for (s = 1; s < ep->stream_info->num_streams; s++)
459 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
460 } else if (ep->ring && ep->ring->dequeue) {
461 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
462 }
463 }
464
465 return;
466}
467
468static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
469 u16 wIndex, __le32 __iomem *addr, u32 port_status)
470{
471 /* Don't allow the USB core to disable SuperSpeed ports. */
472 if (hcd->speed >= HCD_USB3) {
473 xhci_dbg(xhci, "Ignoring request to disable "
474 "SuperSpeed port.\n");
475 return;
476 }
477
478 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
479 xhci_dbg(xhci,
480 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
481 return;
482 }
483
484 /* Write 1 to disable the port */
485 writel(port_status | PORT_PE, addr);
486 port_status = readl(addr);
487 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
488 wIndex, port_status);
489}
490
491static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
492 u16 wIndex, __le32 __iomem *addr, u32 port_status)
493{
494 char *port_change_bit;
495 u32 status;
496
497 switch (wValue) {
498 case USB_PORT_FEAT_C_RESET:
499 status = PORT_RC;
500 port_change_bit = "reset";
501 break;
502 case USB_PORT_FEAT_C_BH_PORT_RESET:
503 status = PORT_WRC;
504 port_change_bit = "warm(BH) reset";
505 break;
506 case USB_PORT_FEAT_C_CONNECTION:
507 status = PORT_CSC;
508 port_change_bit = "connect";
509 break;
510 case USB_PORT_FEAT_C_OVER_CURRENT:
511 status = PORT_OCC;
512 port_change_bit = "over-current";
513 break;
514 case USB_PORT_FEAT_C_ENABLE:
515 status = PORT_PEC;
516 port_change_bit = "enable/disable";
517 break;
518 case USB_PORT_FEAT_C_SUSPEND:
519 status = PORT_PLC;
520 port_change_bit = "suspend/resume";
521 break;
522 case USB_PORT_FEAT_C_PORT_LINK_STATE:
523 status = PORT_PLC;
524 port_change_bit = "link state";
525 break;
526 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
527 status = PORT_CEC;
528 port_change_bit = "config error";
529 break;
530 default:
531 /* Should never happen */
532 return;
533 }
534 /* Change bits are all write 1 to clear */
535 writel(port_status | status, addr);
536 port_status = readl(addr);
537 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
538 port_change_bit, wIndex, port_status);
539}
540
541static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
542{
543 int max_ports;
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545
546 if (hcd->speed >= HCD_USB3) {
547 max_ports = xhci->num_usb3_ports;
548 *port_array = xhci->usb3_ports;
549 } else {
550 max_ports = xhci->num_usb2_ports;
551 *port_array = xhci->usb2_ports;
552 }
553
554 return max_ports;
555}
556
557static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
558{
559 __le32 __iomem **port_array;
560
561 xhci_get_ports(hcd, &port_array);
562 return port_array[index];
563}
564
565/*
566 * xhci_set_port_power() must be called with xhci->lock held.
567 * It will release and re-aquire the lock while calling ACPI
568 * method.
569 */
570static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
571 u16 index, bool on, unsigned long *flags)
572{
573 __le32 __iomem *addr;
574 u32 temp;
575
576 addr = xhci_get_port_io_addr(hcd, index);
577 temp = readl(addr);
578 temp = xhci_port_state_to_neutral(temp);
579 if (on) {
580 /* Power on */
581 writel(temp | PORT_POWER, addr);
582 temp = readl(addr);
583 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n",
584 index, temp);
585 } else {
586 /* Power off */
587 writel(temp & ~PORT_POWER, addr);
588 }
589
590 spin_unlock_irqrestore(&xhci->lock, *flags);
591 temp = usb_acpi_power_manageable(hcd->self.root_hub,
592 index);
593 if (temp)
594 usb_acpi_set_power_state(hcd->self.root_hub,
595 index, on);
596 spin_lock_irqsave(&xhci->lock, *flags);
597}
598
599static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
600 u16 test_mode, u16 wIndex)
601{
602 u32 temp;
603 __le32 __iomem *addr;
604
605 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
606 addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
607 temp = readl(addr + PORTPMSC);
608 temp |= test_mode << PORT_TEST_MODE_SHIFT;
609 writel(temp, addr + PORTPMSC);
610 xhci->test_mode = test_mode;
611 if (test_mode == TEST_FORCE_EN)
612 xhci_start(xhci);
613}
614
615static int xhci_enter_test_mode(struct xhci_hcd *xhci,
616 u16 test_mode, u16 wIndex, unsigned long *flags)
617{
618 int i, retval;
619
620 /* Disable all Device Slots */
621 xhci_dbg(xhci, "Disable all slots\n");
622 spin_unlock_irqrestore(&xhci->lock, *flags);
623 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
624 if (!xhci->devs[i])
625 continue;
626
627 retval = xhci_disable_slot(xhci, i);
628 if (retval)
629 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
630 i, retval);
631 }
632 spin_lock_irqsave(&xhci->lock, *flags);
633 /* Put all ports to the Disable state by clear PP */
634 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
635 /* Power off USB3 ports*/
636 for (i = 0; i < xhci->num_usb3_ports; i++)
637 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
638 /* Power off USB2 ports*/
639 for (i = 0; i < xhci->num_usb2_ports; i++)
640 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
641 /* Stop the controller */
642 xhci_dbg(xhci, "Stop controller\n");
643 retval = xhci_halt(xhci);
644 if (retval)
645 return retval;
646 /* Disable runtime PM for test mode */
647 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
648 /* Set PORTPMSC.PTC field to enter selected test mode */
649 /* Port is selected by wIndex. port_id = wIndex + 1 */
650 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
651 test_mode, wIndex + 1);
652 xhci_port_set_test_mode(xhci, test_mode, wIndex);
653 return retval;
654}
655
656static int xhci_exit_test_mode(struct xhci_hcd *xhci)
657{
658 int retval;
659
660 if (!xhci->test_mode) {
661 xhci_err(xhci, "Not in test mode, do nothing.\n");
662 return 0;
663 }
664 if (xhci->test_mode == TEST_FORCE_EN &&
665 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
666 retval = xhci_halt(xhci);
667 if (retval)
668 return retval;
669 }
670 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
671 xhci->test_mode = 0;
672 return xhci_reset(xhci);
673}
674
675void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
676 int port_id, u32 link_state)
677{
678 u32 temp;
679
680 temp = readl(port_array[port_id]);
681 temp = xhci_port_state_to_neutral(temp);
682 temp &= ~PORT_PLS_MASK;
683 temp |= PORT_LINK_STROBE | link_state;
684 writel(temp, port_array[port_id]);
685}
686
687static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
688 __le32 __iomem **port_array, int port_id, u16 wake_mask)
689{
690 u32 temp;
691
692 temp = readl(port_array[port_id]);
693 temp = xhci_port_state_to_neutral(temp);
694
695 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
696 temp |= PORT_WKCONN_E;
697 else
698 temp &= ~PORT_WKCONN_E;
699
700 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
701 temp |= PORT_WKDISC_E;
702 else
703 temp &= ~PORT_WKDISC_E;
704
705 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
706 temp |= PORT_WKOC_E;
707 else
708 temp &= ~PORT_WKOC_E;
709
710 writel(temp, port_array[port_id]);
711}
712
713/* Test and clear port RWC bit */
714void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
715 int port_id, u32 port_bit)
716{
717 u32 temp;
718
719 temp = readl(port_array[port_id]);
720 if (temp & port_bit) {
721 temp = xhci_port_state_to_neutral(temp);
722 temp |= port_bit;
723 writel(temp, port_array[port_id]);
724 }
725}
726
727/* Updates Link Status for USB 2.1 port */
728static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
729{
730 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
731 *status |= USB_PORT_STAT_L1;
732}
733
734/* Updates Link Status for super Speed port */
735static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
736 u32 *status, u32 status_reg)
737{
738 u32 pls = status_reg & PORT_PLS_MASK;
739
740 /* resume state is a xHCI internal state.
741 * Do not report it to usb core, instead, pretend to be U3,
742 * thus usb core knows it's not ready for transfer
743 */
744 if (pls == XDEV_RESUME) {
745 *status |= USB_SS_PORT_LS_U3;
746 return;
747 }
748
749 /* When the CAS bit is set then warm reset
750 * should be performed on port
751 */
752 if (status_reg & PORT_CAS) {
753 /* The CAS bit can be set while the port is
754 * in any link state.
755 * Only roothubs have CAS bit, so we
756 * pretend to be in compliance mode
757 * unless we're already in compliance
758 * or the inactive state.
759 */
760 if (pls != USB_SS_PORT_LS_COMP_MOD &&
761 pls != USB_SS_PORT_LS_SS_INACTIVE) {
762 pls = USB_SS_PORT_LS_COMP_MOD;
763 }
764 /* Return also connection bit -
765 * hub state machine resets port
766 * when this bit is set.
767 */
768 pls |= USB_PORT_STAT_CONNECTION;
769 } else {
770 /*
771 * If CAS bit isn't set but the Port is already at
772 * Compliance Mode, fake a connection so the USB core
773 * notices the Compliance state and resets the port.
774 * This resolves an issue generated by the SN65LVPE502CP
775 * in which sometimes the port enters compliance mode
776 * caused by a delay on the host-device negotiation.
777 */
778 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
779 (pls == USB_SS_PORT_LS_COMP_MOD))
780 pls |= USB_PORT_STAT_CONNECTION;
781 }
782
783 /* update status field */
784 *status |= pls;
785}
786
787/*
788 * Function for Compliance Mode Quirk.
789 *
790 * This Function verifies if all xhc USB3 ports have entered U0, if so,
791 * the compliance mode timer is deleted. A port won't enter
792 * compliance mode if it has previously entered U0.
793 */
794static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
795 u16 wIndex)
796{
797 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
798 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
799
800 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
801 return;
802
803 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
804 xhci->port_status_u0 |= 1 << wIndex;
805 if (xhci->port_status_u0 == all_ports_seen_u0) {
806 del_timer_sync(&xhci->comp_mode_recovery_timer);
807 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
808 "All USB3 ports have entered U0 already!");
809 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
810 "Compliance Mode Recovery Timer Deleted.");
811 }
812 }
813}
814
815static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
816{
817 u32 ext_stat = 0;
818 int speed_id;
819
820 /* only support rx and tx lane counts of 1 in usb3.1 spec */
821 speed_id = DEV_PORT_SPEED(raw_port_status);
822 ext_stat |= speed_id; /* bits 3:0, RX speed id */
823 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
824
825 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
826 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
827
828 return ext_stat;
829}
830
831/*
832 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
833 * 3.0 hubs use.
834 *
835 * Possible side effects:
836 * - Mark a port as being done with device resume,
837 * and ring the endpoint doorbells.
838 * - Stop the Synopsys redriver Compliance Mode polling.
839 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
840 */
841static u32 xhci_get_port_status(struct usb_hcd *hcd,
842 struct xhci_bus_state *bus_state,
843 __le32 __iomem **port_array,
844 u16 wIndex, u32 raw_port_status,
845 unsigned long flags)
846 __releases(&xhci->lock)
847 __acquires(&xhci->lock)
848{
849 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
850 u32 status = 0;
851 int slot_id;
852
853 /* wPortChange bits */
854 if (raw_port_status & PORT_CSC)
855 status |= USB_PORT_STAT_C_CONNECTION << 16;
856 if (raw_port_status & PORT_PEC)
857 status |= USB_PORT_STAT_C_ENABLE << 16;
858 if ((raw_port_status & PORT_OCC))
859 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
860 if ((raw_port_status & PORT_RC))
861 status |= USB_PORT_STAT_C_RESET << 16;
862 /* USB3.0 only */
863 if (hcd->speed >= HCD_USB3) {
864 /* Port link change with port in resume state should not be
865 * reported to usbcore, as this is an internal state to be
866 * handled by xhci driver. Reporting PLC to usbcore may
867 * cause usbcore clearing PLC first and port change event
868 * irq won't be generated.
869 */
870 if ((raw_port_status & PORT_PLC) &&
871 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
872 status |= USB_PORT_STAT_C_LINK_STATE << 16;
873 if ((raw_port_status & PORT_WRC))
874 status |= USB_PORT_STAT_C_BH_RESET << 16;
875 if ((raw_port_status & PORT_CEC))
876 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
877 }
878
879 if (hcd->speed < HCD_USB3) {
880 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
881 && (raw_port_status & PORT_POWER))
882 status |= USB_PORT_STAT_SUSPEND;
883 }
884 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
885 !DEV_SUPERSPEED_ANY(raw_port_status)) {
886 if ((raw_port_status & PORT_RESET) ||
887 !(raw_port_status & PORT_PE))
888 return 0xffffffff;
889 /* did port event handler already start resume timing? */
890 if (!bus_state->resume_done[wIndex]) {
891 /* If not, maybe we are in a host initated resume? */
892 if (test_bit(wIndex, &bus_state->resuming_ports)) {
893 /* Host initated resume doesn't time the resume
894 * signalling using resume_done[].
895 * It manually sets RESUME state, sleeps 20ms
896 * and sets U0 state. This should probably be
897 * changed, but not right now.
898 */
899 } else {
900 /* port resume was discovered now and here,
901 * start resume timing
902 */
903 unsigned long timeout = jiffies +
904 msecs_to_jiffies(USB_RESUME_TIMEOUT);
905
906 set_bit(wIndex, &bus_state->resuming_ports);
907 bus_state->resume_done[wIndex] = timeout;
908 mod_timer(&hcd->rh_timer, timeout);
909 }
910 /* Has resume been signalled for USB_RESUME_TIME yet? */
911 } else if (time_after_eq(jiffies,
912 bus_state->resume_done[wIndex])) {
913 int time_left;
914
915 xhci_dbg(xhci, "Resume USB2 port %d\n",
916 wIndex + 1);
917 bus_state->resume_done[wIndex] = 0;
918 clear_bit(wIndex, &bus_state->resuming_ports);
919
920 set_bit(wIndex, &bus_state->rexit_ports);
921
922 xhci_test_and_clear_bit(xhci, port_array, wIndex,
923 PORT_PLC);
924 xhci_set_link_state(xhci, port_array, wIndex,
925 XDEV_U0);
926
927 spin_unlock_irqrestore(&xhci->lock, flags);
928 time_left = wait_for_completion_timeout(
929 &bus_state->rexit_done[wIndex],
930 msecs_to_jiffies(
931 XHCI_MAX_REXIT_TIMEOUT));
932 spin_lock_irqsave(&xhci->lock, flags);
933
934 if (time_left) {
935 slot_id = xhci_find_slot_id_by_port(hcd,
936 xhci, wIndex + 1);
937 if (!slot_id) {
938 xhci_dbg(xhci, "slot_id is zero\n");
939 return 0xffffffff;
940 }
941 xhci_ring_device(xhci, slot_id);
942 } else {
943 int port_status = readl(port_array[wIndex]);
944 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
945 XHCI_MAX_REXIT_TIMEOUT,
946 port_status);
947 status |= USB_PORT_STAT_SUSPEND;
948 clear_bit(wIndex, &bus_state->rexit_ports);
949 }
950
951 bus_state->port_c_suspend |= 1 << wIndex;
952 bus_state->suspended_ports &= ~(1 << wIndex);
953 } else {
954 /*
955 * The resume has been signaling for less than
956 * USB_RESUME_TIME. Report the port status as SUSPEND,
957 * let the usbcore check port status again and clear
958 * resume signaling later.
959 */
960 status |= USB_PORT_STAT_SUSPEND;
961 }
962 }
963 /*
964 * Clear stale usb2 resume signalling variables in case port changed
965 * state during resume signalling. For example on error
966 */
967 if ((bus_state->resume_done[wIndex] ||
968 test_bit(wIndex, &bus_state->resuming_ports)) &&
969 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
970 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
971 bus_state->resume_done[wIndex] = 0;
972 clear_bit(wIndex, &bus_state->resuming_ports);
973 }
974
975
976 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
977 (raw_port_status & PORT_POWER)) {
978 if (bus_state->suspended_ports & (1 << wIndex)) {
979 bus_state->suspended_ports &= ~(1 << wIndex);
980 if (hcd->speed < HCD_USB3)
981 bus_state->port_c_suspend |= 1 << wIndex;
982 }
983 bus_state->resume_done[wIndex] = 0;
984 clear_bit(wIndex, &bus_state->resuming_ports);
985 }
986 if (raw_port_status & PORT_CONNECT) {
987 status |= USB_PORT_STAT_CONNECTION;
988 status |= xhci_port_speed(raw_port_status);
989 }
990 if (raw_port_status & PORT_PE)
991 status |= USB_PORT_STAT_ENABLE;
992 if (raw_port_status & PORT_OC)
993 status |= USB_PORT_STAT_OVERCURRENT;
994 if (raw_port_status & PORT_RESET)
995 status |= USB_PORT_STAT_RESET;
996 if (raw_port_status & PORT_POWER) {
997 if (hcd->speed >= HCD_USB3)
998 status |= USB_SS_PORT_STAT_POWER;
999 else
1000 status |= USB_PORT_STAT_POWER;
1001 }
1002 /* Update Port Link State */
1003 if (hcd->speed >= HCD_USB3) {
1004 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1005 /*
1006 * Verify if all USB3 Ports Have entered U0 already.
1007 * Delete Compliance Mode Timer if so.
1008 */
1009 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1010 } else {
1011 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1012 }
1013 if (bus_state->port_c_suspend & (1 << wIndex))
1014 status |= USB_PORT_STAT_C_SUSPEND << 16;
1015
1016 return status;
1017}
1018
1019int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1020 u16 wIndex, char *buf, u16 wLength)
1021{
1022 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1023 int max_ports;
1024 unsigned long flags;
1025 u32 temp, status;
1026 int retval = 0;
1027 __le32 __iomem **port_array;
1028 int slot_id;
1029 struct xhci_bus_state *bus_state;
1030 u16 link_state = 0;
1031 u16 wake_mask = 0;
1032 u16 timeout = 0;
1033 u16 test_mode = 0;
1034
1035 max_ports = xhci_get_ports(hcd, &port_array);
1036 bus_state = &xhci->bus_state[hcd_index(hcd)];
1037
1038 spin_lock_irqsave(&xhci->lock, flags);
1039 switch (typeReq) {
1040 case GetHubStatus:
1041 /* No power source, over-current reported per port */
1042 memset(buf, 0, 4);
1043 break;
1044 case GetHubDescriptor:
1045 /* Check to make sure userspace is asking for the USB 3.0 hub
1046 * descriptor for the USB 3.0 roothub. If not, we stall the
1047 * endpoint, like external hubs do.
1048 */
1049 if (hcd->speed >= HCD_USB3 &&
1050 (wLength < USB_DT_SS_HUB_SIZE ||
1051 wValue != (USB_DT_SS_HUB << 8))) {
1052 xhci_dbg(xhci, "Wrong hub descriptor type for "
1053 "USB 3.0 roothub.\n");
1054 goto error;
1055 }
1056 xhci_hub_descriptor(hcd, xhci,
1057 (struct usb_hub_descriptor *) buf);
1058 break;
1059 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1060 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1061 goto error;
1062
1063 if (hcd->speed < HCD_USB3)
1064 goto error;
1065
1066 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1067 spin_unlock_irqrestore(&xhci->lock, flags);
1068 return retval;
1069 case GetPortStatus:
1070 if (!wIndex || wIndex > max_ports)
1071 goto error;
1072 wIndex--;
1073 temp = readl(port_array[wIndex]);
1074 if (temp == ~(u32)0) {
1075 xhci_hc_died(xhci);
1076 retval = -ENODEV;
1077 break;
1078 }
1079 trace_xhci_get_port_status(wIndex, temp);
1080 status = xhci_get_port_status(hcd, bus_state, port_array,
1081 wIndex, temp, flags);
1082 if (status == 0xffffffff)
1083 goto error;
1084
1085 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
1086 wIndex, temp);
1087 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1088
1089 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1090 /* if USB 3.1 extended port status return additional 4 bytes */
1091 if (wValue == 0x02) {
1092 u32 port_li;
1093
1094 if (hcd->speed < HCD_USB31 || wLength != 8) {
1095 xhci_err(xhci, "get ext port status invalid parameter\n");
1096 retval = -EINVAL;
1097 break;
1098 }
1099 port_li = readl(port_array[wIndex] + PORTLI);
1100 status = xhci_get_ext_port_status(temp, port_li);
1101 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1102 }
1103 break;
1104 case SetPortFeature:
1105 if (wValue == USB_PORT_FEAT_LINK_STATE)
1106 link_state = (wIndex & 0xff00) >> 3;
1107 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1108 wake_mask = wIndex & 0xff00;
1109 if (wValue == USB_PORT_FEAT_TEST)
1110 test_mode = (wIndex & 0xff00) >> 8;
1111 /* The MSB of wIndex is the U1/U2 timeout */
1112 timeout = (wIndex & 0xff00) >> 8;
1113 wIndex &= 0xff;
1114 if (!wIndex || wIndex > max_ports)
1115 goto error;
1116 wIndex--;
1117 temp = readl(port_array[wIndex]);
1118 if (temp == ~(u32)0) {
1119 xhci_hc_died(xhci);
1120 retval = -ENODEV;
1121 break;
1122 }
1123 temp = xhci_port_state_to_neutral(temp);
1124 /* FIXME: What new port features do we need to support? */
1125 switch (wValue) {
1126 case USB_PORT_FEAT_SUSPEND:
1127 temp = readl(port_array[wIndex]);
1128 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1129 /* Resume the port to U0 first */
1130 xhci_set_link_state(xhci, port_array, wIndex,
1131 XDEV_U0);
1132 spin_unlock_irqrestore(&xhci->lock, flags);
1133 msleep(10);
1134 spin_lock_irqsave(&xhci->lock, flags);
1135 }
1136 /* In spec software should not attempt to suspend
1137 * a port unless the port reports that it is in the
1138 * enabled (PED = ‘1’,PLS < ‘3’) state.
1139 */
1140 temp = readl(port_array[wIndex]);
1141 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1142 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1143 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1144 goto error;
1145 }
1146
1147 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1148 wIndex + 1);
1149 if (!slot_id) {
1150 xhci_warn(xhci, "slot_id is zero\n");
1151 goto error;
1152 }
1153 /* unlock to execute stop endpoint commands */
1154 spin_unlock_irqrestore(&xhci->lock, flags);
1155 xhci_stop_device(xhci, slot_id, 1);
1156 spin_lock_irqsave(&xhci->lock, flags);
1157
1158 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1159
1160 spin_unlock_irqrestore(&xhci->lock, flags);
1161 msleep(10); /* wait device to enter */
1162 spin_lock_irqsave(&xhci->lock, flags);
1163
1164 temp = readl(port_array[wIndex]);
1165 bus_state->suspended_ports |= 1 << wIndex;
1166 break;
1167 case USB_PORT_FEAT_LINK_STATE:
1168 temp = readl(port_array[wIndex]);
1169
1170 /* Disable port */
1171 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1172 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1173 temp = xhci_port_state_to_neutral(temp);
1174 /*
1175 * Clear all change bits, so that we get a new
1176 * connection event.
1177 */
1178 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1179 PORT_OCC | PORT_RC | PORT_PLC |
1180 PORT_CEC;
1181 writel(temp | PORT_PE, port_array[wIndex]);
1182 temp = readl(port_array[wIndex]);
1183 break;
1184 }
1185
1186 /* Put link in RxDetect (enable port) */
1187 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1188 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1189 xhci_set_link_state(xhci, port_array, wIndex,
1190 link_state);
1191 temp = readl(port_array[wIndex]);
1192 break;
1193 }
1194
1195 /*
1196 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1197 * root hub port's transition to compliance mode upon
1198 * detecting LFPS timeout may be controlled by an
1199 * Compliance Transition Enabled (CTE) flag (not
1200 * software visible). This flag is set by writing 0xA
1201 * to PORTSC PLS field which will allow transition to
1202 * compliance mode the next time LFPS timeout is
1203 * encountered. A warm reset will clear it.
1204 *
1205 * The CTE flag is only supported if the HCCPARAMS2 CTC
1206 * flag is set, otherwise, the compliance substate is
1207 * automatically entered as on 1.0 and prior.
1208 */
1209 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1210 if (!HCC2_CTC(xhci->hcc_params2)) {
1211 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1212 break;
1213 }
1214
1215 if ((temp & PORT_CONNECT)) {
1216 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1217 goto error;
1218 }
1219
1220 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1221 wIndex);
1222 xhci_set_link_state(xhci, port_array, wIndex,
1223 link_state);
1224 temp = readl(port_array[wIndex]);
1225 break;
1226 }
1227 /* Port must be enabled */
1228 if (!(temp & PORT_PE)) {
1229 retval = -ENODEV;
1230 break;
1231 }
1232 /* Can't set port link state above '3' (U3) */
1233 if (link_state > USB_SS_PORT_LS_U3) {
1234 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1235 wIndex, link_state);
1236 goto error;
1237 }
1238 if (link_state == USB_SS_PORT_LS_U3) {
1239 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1240 wIndex + 1);
1241 if (slot_id) {
1242 /* unlock to execute stop endpoint
1243 * commands */
1244 spin_unlock_irqrestore(&xhci->lock,
1245 flags);
1246 xhci_stop_device(xhci, slot_id, 1);
1247 spin_lock_irqsave(&xhci->lock, flags);
1248 }
1249 }
1250
1251 xhci_set_link_state(xhci, port_array, wIndex,
1252 link_state);
1253
1254 spin_unlock_irqrestore(&xhci->lock, flags);
1255 msleep(20); /* wait device to enter */
1256 spin_lock_irqsave(&xhci->lock, flags);
1257
1258 temp = readl(port_array[wIndex]);
1259 if (link_state == USB_SS_PORT_LS_U3)
1260 bus_state->suspended_ports |= 1 << wIndex;
1261 break;
1262 case USB_PORT_FEAT_POWER:
1263 /*
1264 * Turn on ports, even if there isn't per-port switching.
1265 * HC will report connect events even before this is set.
1266 * However, hub_wq will ignore the roothub events until
1267 * the roothub is registered.
1268 */
1269 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1270 break;
1271 case USB_PORT_FEAT_RESET:
1272 temp = (temp | PORT_RESET);
1273 writel(temp, port_array[wIndex]);
1274
1275 temp = readl(port_array[wIndex]);
1276 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1277 break;
1278 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1279 xhci_set_remote_wake_mask(xhci, port_array,
1280 wIndex, wake_mask);
1281 temp = readl(port_array[wIndex]);
1282 xhci_dbg(xhci, "set port remote wake mask, "
1283 "actual port %d status = 0x%x\n",
1284 wIndex, temp);
1285 break;
1286 case USB_PORT_FEAT_BH_PORT_RESET:
1287 temp |= PORT_WR;
1288 writel(temp, port_array[wIndex]);
1289
1290 temp = readl(port_array[wIndex]);
1291 break;
1292 case USB_PORT_FEAT_U1_TIMEOUT:
1293 if (hcd->speed < HCD_USB3)
1294 goto error;
1295 temp = readl(port_array[wIndex] + PORTPMSC);
1296 temp &= ~PORT_U1_TIMEOUT_MASK;
1297 temp |= PORT_U1_TIMEOUT(timeout);
1298 writel(temp, port_array[wIndex] + PORTPMSC);
1299 break;
1300 case USB_PORT_FEAT_U2_TIMEOUT:
1301 if (hcd->speed < HCD_USB3)
1302 goto error;
1303 temp = readl(port_array[wIndex] + PORTPMSC);
1304 temp &= ~PORT_U2_TIMEOUT_MASK;
1305 temp |= PORT_U2_TIMEOUT(timeout);
1306 writel(temp, port_array[wIndex] + PORTPMSC);
1307 break;
1308 case USB_PORT_FEAT_TEST:
1309 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1310 if (hcd->speed != HCD_USB2)
1311 goto error;
1312 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1313 goto error;
1314 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1315 &flags);
1316 break;
1317 default:
1318 goto error;
1319 }
1320 /* unblock any posted writes */
1321 temp = readl(port_array[wIndex]);
1322 break;
1323 case ClearPortFeature:
1324 if (!wIndex || wIndex > max_ports)
1325 goto error;
1326 wIndex--;
1327 temp = readl(port_array[wIndex]);
1328 if (temp == ~(u32)0) {
1329 xhci_hc_died(xhci);
1330 retval = -ENODEV;
1331 break;
1332 }
1333 /* FIXME: What new port features do we need to support? */
1334 temp = xhci_port_state_to_neutral(temp);
1335 switch (wValue) {
1336 case USB_PORT_FEAT_SUSPEND:
1337 temp = readl(port_array[wIndex]);
1338 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1339 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1340 if (temp & PORT_RESET)
1341 goto error;
1342 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1343 if ((temp & PORT_PE) == 0)
1344 goto error;
1345
1346 set_bit(wIndex, &bus_state->resuming_ports);
1347 xhci_set_link_state(xhci, port_array, wIndex,
1348 XDEV_RESUME);
1349 spin_unlock_irqrestore(&xhci->lock, flags);
1350 msleep(USB_RESUME_TIMEOUT);
1351 spin_lock_irqsave(&xhci->lock, flags);
1352 xhci_set_link_state(xhci, port_array, wIndex,
1353 XDEV_U0);
1354 clear_bit(wIndex, &bus_state->resuming_ports);
1355 }
1356 bus_state->port_c_suspend |= 1 << wIndex;
1357
1358 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1359 wIndex + 1);
1360 if (!slot_id) {
1361 xhci_dbg(xhci, "slot_id is zero\n");
1362 goto error;
1363 }
1364 xhci_ring_device(xhci, slot_id);
1365 break;
1366 case USB_PORT_FEAT_C_SUSPEND:
1367 bus_state->port_c_suspend &= ~(1 << wIndex);
1368 /* fall through */
1369 case USB_PORT_FEAT_C_RESET:
1370 case USB_PORT_FEAT_C_BH_PORT_RESET:
1371 case USB_PORT_FEAT_C_CONNECTION:
1372 case USB_PORT_FEAT_C_OVER_CURRENT:
1373 case USB_PORT_FEAT_C_ENABLE:
1374 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1375 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1376 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1377 port_array[wIndex], temp);
1378 break;
1379 case USB_PORT_FEAT_ENABLE:
1380 xhci_disable_port(hcd, xhci, wIndex,
1381 port_array[wIndex], temp);
1382 break;
1383 case USB_PORT_FEAT_POWER:
1384 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1385 break;
1386 case USB_PORT_FEAT_TEST:
1387 retval = xhci_exit_test_mode(xhci);
1388 break;
1389 default:
1390 goto error;
1391 }
1392 break;
1393 default:
1394error:
1395 /* "stall" on error */
1396 retval = -EPIPE;
1397 }
1398 spin_unlock_irqrestore(&xhci->lock, flags);
1399 return retval;
1400}
1401
1402/*
1403 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1404 * Ports are 0-indexed from the HCD point of view,
1405 * and 1-indexed from the USB core pointer of view.
1406 *
1407 * Note that the status change bits will be cleared as soon as a port status
1408 * change event is generated, so we use the saved status from that event.
1409 */
1410int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1411{
1412 unsigned long flags;
1413 u32 temp, status;
1414 u32 mask;
1415 int i, retval;
1416 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1417 int max_ports;
1418 __le32 __iomem **port_array;
1419 struct xhci_bus_state *bus_state;
1420 bool reset_change = false;
1421
1422 max_ports = xhci_get_ports(hcd, &port_array);
1423 bus_state = &xhci->bus_state[hcd_index(hcd)];
1424
1425 /* Initial status is no changes */
1426 retval = (max_ports + 8) / 8;
1427 memset(buf, 0, retval);
1428
1429 /*
1430 * Inform the usbcore about resume-in-progress by returning
1431 * a non-zero value even if there are no status changes.
1432 */
1433 status = bus_state->resuming_ports;
1434
1435 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1436
1437 spin_lock_irqsave(&xhci->lock, flags);
1438 /* For each port, did anything change? If so, set that bit in buf. */
1439 for (i = 0; i < max_ports; i++) {
1440 temp = readl(port_array[i]);
1441 if (temp == ~(u32)0) {
1442 xhci_hc_died(xhci);
1443 retval = -ENODEV;
1444 break;
1445 }
1446 trace_xhci_hub_status_data(i, temp);
1447
1448 if ((temp & mask) != 0 ||
1449 (bus_state->port_c_suspend & 1 << i) ||
1450 (bus_state->resume_done[i] && time_after_eq(
1451 jiffies, bus_state->resume_done[i]))) {
1452 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1453 status = 1;
1454 }
1455 if ((temp & PORT_RC))
1456 reset_change = true;
1457 }
1458 if (!status && !reset_change) {
1459 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1460 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1461 }
1462 spin_unlock_irqrestore(&xhci->lock, flags);
1463 return status ? retval : 0;
1464}
1465
1466#ifdef CONFIG_PM
1467
1468int xhci_bus_suspend(struct usb_hcd *hcd)
1469{
1470 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1471 int max_ports, port_index;
1472 __le32 __iomem **port_array;
1473 struct xhci_bus_state *bus_state;
1474 unsigned long flags;
1475
1476 max_ports = xhci_get_ports(hcd, &port_array);
1477 bus_state = &xhci->bus_state[hcd_index(hcd)];
1478
1479 spin_lock_irqsave(&xhci->lock, flags);
1480
1481 if (hcd->self.root_hub->do_remote_wakeup) {
1482 if (bus_state->resuming_ports || /* USB2 */
1483 bus_state->port_remote_wakeup) { /* USB3 */
1484 spin_unlock_irqrestore(&xhci->lock, flags);
1485 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1486 return -EBUSY;
1487 }
1488 }
1489
1490 port_index = max_ports;
1491 bus_state->bus_suspended = 0;
1492 while (port_index--) {
1493 /* suspend the port if the port is not suspended */
1494 u32 t1, t2;
1495 int slot_id;
1496
1497 t1 = readl(port_array[port_index]);
1498 t2 = xhci_port_state_to_neutral(t1);
1499
1500 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1501 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1502 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1503 port_index + 1);
1504 if (slot_id) {
1505 spin_unlock_irqrestore(&xhci->lock, flags);
1506 xhci_stop_device(xhci, slot_id, 1);
1507 spin_lock_irqsave(&xhci->lock, flags);
1508 }
1509 t2 &= ~PORT_PLS_MASK;
1510 t2 |= PORT_LINK_STROBE | XDEV_U3;
1511 set_bit(port_index, &bus_state->bus_suspended);
1512 }
1513 /* USB core sets remote wake mask for USB 3.0 hubs,
1514 * including the USB 3.0 roothub, but only if CONFIG_PM
1515 * is enabled, so also enable remote wake here.
1516 */
1517 if (hcd->self.root_hub->do_remote_wakeup) {
1518 if (t1 & PORT_CONNECT) {
1519 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1520 t2 &= ~PORT_WKCONN_E;
1521 } else {
1522 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1523 t2 &= ~PORT_WKDISC_E;
1524 }
1525
1526 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1527 (hcd->speed < HCD_USB3)) {
1528 if (usb_amd_pt_check_port(hcd->self.controller,
1529 port_index))
1530 t2 &= ~PORT_WAKE_BITS;
1531 }
1532 } else
1533 t2 &= ~PORT_WAKE_BITS;
1534
1535 t1 = xhci_port_state_to_neutral(t1);
1536 if (t1 != t2)
1537 writel(t2, port_array[port_index]);
1538 }
1539 hcd->state = HC_STATE_SUSPENDED;
1540 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1541 spin_unlock_irqrestore(&xhci->lock, flags);
1542 return 0;
1543}
1544
1545/*
1546 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1547 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1548 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1549 */
1550static bool xhci_port_missing_cas_quirk(int port_index,
1551 __le32 __iomem **port_array)
1552{
1553 u32 portsc;
1554
1555 portsc = readl(port_array[port_index]);
1556
1557 /* if any of these are set we are not stuck */
1558 if (portsc & (PORT_CONNECT | PORT_CAS))
1559 return false;
1560
1561 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1562 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1563 return false;
1564
1565 /* clear wakeup/change bits, and do a warm port reset */
1566 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1567 portsc |= PORT_WR;
1568 writel(portsc, port_array[port_index]);
1569 /* flush write */
1570 readl(port_array[port_index]);
1571 return true;
1572}
1573
1574int xhci_bus_resume(struct usb_hcd *hcd)
1575{
1576 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1577 struct xhci_bus_state *bus_state;
1578 __le32 __iomem **port_array;
1579 unsigned long flags;
1580 int max_ports, port_index;
1581 int slot_id;
1582 int sret;
1583 u32 next_state;
1584 u32 temp, portsc;
1585
1586 max_ports = xhci_get_ports(hcd, &port_array);
1587 bus_state = &xhci->bus_state[hcd_index(hcd)];
1588
1589 if (time_before(jiffies, bus_state->next_statechange))
1590 msleep(5);
1591
1592 spin_lock_irqsave(&xhci->lock, flags);
1593 if (!HCD_HW_ACCESSIBLE(hcd)) {
1594 spin_unlock_irqrestore(&xhci->lock, flags);
1595 return -ESHUTDOWN;
1596 }
1597
1598 /* delay the irqs */
1599 temp = readl(&xhci->op_regs->command);
1600 temp &= ~CMD_EIE;
1601 writel(temp, &xhci->op_regs->command);
1602
1603 /* bus specific resume for ports we suspended at bus_suspend */
1604 if (hcd->speed >= HCD_USB3)
1605 next_state = XDEV_U0;
1606 else
1607 next_state = XDEV_RESUME;
1608
1609 port_index = max_ports;
1610 while (port_index--) {
1611 portsc = readl(port_array[port_index]);
1612
1613 /* warm reset CAS limited ports stuck in polling/compliance */
1614 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1615 (hcd->speed >= HCD_USB3) &&
1616 xhci_port_missing_cas_quirk(port_index, port_array)) {
1617 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1618 clear_bit(port_index, &bus_state->bus_suspended);
1619 continue;
1620 }
1621 /* resume if we suspended the link, and it is still suspended */
1622 if (test_bit(port_index, &bus_state->bus_suspended))
1623 switch (portsc & PORT_PLS_MASK) {
1624 case XDEV_U3:
1625 portsc = xhci_port_state_to_neutral(portsc);
1626 portsc &= ~PORT_PLS_MASK;
1627 portsc |= PORT_LINK_STROBE | next_state;
1628 break;
1629 case XDEV_RESUME:
1630 /* resume already initiated */
1631 break;
1632 default:
1633 /* not in a resumeable state, ignore it */
1634 clear_bit(port_index,
1635 &bus_state->bus_suspended);
1636 break;
1637 }
1638 /* disable wake for all ports, write new link state if needed */
1639 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1640 writel(portsc, port_array[port_index]);
1641 }
1642
1643 /* USB2 specific resume signaling delay and U0 link state transition */
1644 if (hcd->speed < HCD_USB3) {
1645 if (bus_state->bus_suspended) {
1646 spin_unlock_irqrestore(&xhci->lock, flags);
1647 msleep(USB_RESUME_TIMEOUT);
1648 spin_lock_irqsave(&xhci->lock, flags);
1649 }
1650 for_each_set_bit(port_index, &bus_state->bus_suspended,
1651 BITS_PER_LONG) {
1652 /* Clear PLC to poll it later for U0 transition */
1653 xhci_test_and_clear_bit(xhci, port_array, port_index,
1654 PORT_PLC);
1655 xhci_set_link_state(xhci, port_array, port_index,
1656 XDEV_U0);
1657 }
1658 }
1659
1660 /* poll for U0 link state complete, both USB2 and USB3 */
1661 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1662 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1663 PORT_PLC, 10 * 1000);
1664 if (sret) {
1665 xhci_warn(xhci, "port %d resume PLC timeout\n",
1666 port_index);
1667 continue;
1668 }
1669 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1670 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1671 if (slot_id)
1672 xhci_ring_device(xhci, slot_id);
1673 }
1674 (void) readl(&xhci->op_regs->command);
1675
1676 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1677 /* re-enable irqs */
1678 temp = readl(&xhci->op_regs->command);
1679 temp |= CMD_EIE;
1680 writel(temp, &xhci->op_regs->command);
1681 temp = readl(&xhci->op_regs->command);
1682
1683 spin_unlock_irqrestore(&xhci->lock, flags);
1684 return 0;
1685}
1686
1687#endif /* CONFIG_PM */
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23
24#include <linux/slab.h>
25#include <asm/unaligned.h>
26
27#include "xhci.h"
28#include "xhci-trace.h"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
33
34/* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
36 */
37static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
49 USB 3.0 speed only */
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
65};
66
67static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 wLength)
69{
70 int i, ssa_count;
71 u32 temp;
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
73 bool usb3_1 = false;
74
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
77
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
86 }
87 desc_size += ssp_cap_size;
88 usb3_1 = true;
89 }
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
91
92 if (usb3_1) {
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
94 buf[4] += 1;
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
96 }
97
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
99 return wLength;
100
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
103 if (HCC_LTC(temp))
104 buf[8] |= USB_LTM_SUPPORT;
105
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
111 }
112
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi;
116 int offset;
117
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
119
120 if (wLength < desc_size)
121 return wLength;
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
123
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
128
129 if (wLength < desc_size + ssa_size)
130 return wLength;
131 /*
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
137 */
138 offset = desc_size;
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 if ((psi & PLT_MASK) == PLT_SYM) {
143 /* Symmetric, create SSA RX and TX from one PSI entry */
144 put_unaligned_le32(psi, &buf[offset]);
145 psi |= 1 << 7; /* turn entry to TX */
146 offset += 4;
147 if (offset >= desc_size + ssa_size)
148 return desc_size + ssa_size;
149 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
150 /* Asymetric RX, flip bits 7:6 for SSA */
151 psi ^= PLT_MASK;
152 }
153 put_unaligned_le32(psi, &buf[offset]);
154 offset += 4;
155 if (offset >= desc_size + ssa_size)
156 return desc_size + ssa_size;
157 }
158 }
159 /* ssa_size is 0 for other than usb 3.1 hosts */
160 return desc_size + ssa_size;
161}
162
163static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
164 struct usb_hub_descriptor *desc, int ports)
165{
166 u16 temp;
167
168 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
169 desc->bHubContrCurrent = 0;
170
171 desc->bNbrPorts = ports;
172 temp = 0;
173 /* Bits 1:0 - support per-port power switching, or power always on */
174 if (HCC_PPC(xhci->hcc_params))
175 temp |= HUB_CHAR_INDV_PORT_LPSM;
176 else
177 temp |= HUB_CHAR_NO_LPSM;
178 /* Bit 2 - root hubs are not part of a compound device */
179 /* Bits 4:3 - individual port over current protection */
180 temp |= HUB_CHAR_INDV_PORT_OCPM;
181 /* Bits 6:5 - no TTs in root ports */
182 /* Bit 7 - no port indicators */
183 desc->wHubCharacteristics = cpu_to_le16(temp);
184}
185
186/* Fill in the USB 2.0 roothub descriptor */
187static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
188 struct usb_hub_descriptor *desc)
189{
190 int ports;
191 u16 temp;
192 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
193 u32 portsc;
194 unsigned int i;
195
196 ports = xhci->num_usb2_ports;
197
198 xhci_common_hub_descriptor(xhci, desc, ports);
199 desc->bDescriptorType = USB_DT_HUB;
200 temp = 1 + (ports / 8);
201 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
202
203 /* The Device Removable bits are reported on a byte granularity.
204 * If the port doesn't exist within that byte, the bit is set to 0.
205 */
206 memset(port_removable, 0, sizeof(port_removable));
207 for (i = 0; i < ports; i++) {
208 portsc = readl(xhci->usb2_ports[i]);
209 /* If a device is removable, PORTSC reports a 0, same as in the
210 * hub descriptor DeviceRemovable bits.
211 */
212 if (portsc & PORT_DEV_REMOVE)
213 /* This math is hairy because bit 0 of DeviceRemovable
214 * is reserved, and bit 1 is for port 1, etc.
215 */
216 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
217 }
218
219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
220 * ports on it. The USB 2.0 specification says that there are two
221 * variable length fields at the end of the hub descriptor:
222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
225 * 0xFF, so we initialize the both arrays (DeviceRemovable and
226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
227 * set of ports that actually exist.
228 */
229 memset(desc->u.hs.DeviceRemovable, 0xff,
230 sizeof(desc->u.hs.DeviceRemovable));
231 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
232 sizeof(desc->u.hs.PortPwrCtrlMask));
233
234 for (i = 0; i < (ports + 1 + 7) / 8; i++)
235 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
236 sizeof(__u8));
237}
238
239/* Fill in the USB 3.0 roothub descriptor */
240static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 struct usb_hub_descriptor *desc)
242{
243 int ports;
244 u16 port_removable;
245 u32 portsc;
246 unsigned int i;
247
248 ports = xhci->num_usb3_ports;
249 xhci_common_hub_descriptor(xhci, desc, ports);
250 desc->bDescriptorType = USB_DT_SS_HUB;
251 desc->bDescLength = USB_DT_SS_HUB_SIZE;
252
253 /* header decode latency should be zero for roothubs,
254 * see section 4.23.5.2.
255 */
256 desc->u.ss.bHubHdrDecLat = 0;
257 desc->u.ss.wHubDelay = 0;
258
259 port_removable = 0;
260 /* bit 0 is reserved, bit 1 is for port 1, etc. */
261 for (i = 0; i < ports; i++) {
262 portsc = readl(xhci->usb3_ports[i]);
263 if (portsc & PORT_DEV_REMOVE)
264 port_removable |= 1 << (i + 1);
265 }
266
267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
268}
269
270static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271 struct usb_hub_descriptor *desc)
272{
273
274 if (hcd->speed >= HCD_USB3)
275 xhci_usb3_hub_descriptor(hcd, xhci, desc);
276 else
277 xhci_usb2_hub_descriptor(hcd, xhci, desc);
278
279}
280
281static unsigned int xhci_port_speed(unsigned int port_status)
282{
283 if (DEV_LOWSPEED(port_status))
284 return USB_PORT_STAT_LOW_SPEED;
285 if (DEV_HIGHSPEED(port_status))
286 return USB_PORT_STAT_HIGH_SPEED;
287 /*
288 * FIXME: Yes, we should check for full speed, but the core uses that as
289 * a default in portspeed() in usb/core/hub.c (which is the only place
290 * USB_PORT_STAT_*_SPEED is used).
291 */
292 return 0;
293}
294
295/*
296 * These bits are Read Only (RO) and should be saved and written to the
297 * registers: 0, 3, 10:13, 30
298 * connect status, over-current status, port speed, and device removable.
299 * connect status and port speed are also sticky - meaning they're in
300 * the AUX well and they aren't changed by a hot, warm, or cold reset.
301 */
302#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
303/*
304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305 * bits 5:8, 9, 14:15, 25:27
306 * link state, port power, port indicator state, "wake on" enable state
307 */
308#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
309/*
310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
311 * bit 4 (port reset)
312 */
313#define XHCI_PORT_RW1S ((1<<4))
314/*
315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316 * bits 1, 17, 18, 19, 20, 21, 22, 23
317 * port enable/disable, and
318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319 * over-current, reset, link state, and L1 change
320 */
321#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
322/*
323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
324 * latched in
325 */
326#define XHCI_PORT_RW ((1<<16))
327/*
328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
329 * bits 2, 24, 28:31
330 */
331#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
332
333/*
334 * Given a port state, this function returns a value that would result in the
335 * port being in the same state, if the value was written to the port status
336 * control register.
337 * Save Read Only (RO) bits and save read/write bits where
338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
340 */
341u32 xhci_port_state_to_neutral(u32 state)
342{
343 /* Save read-only status and port state */
344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
345}
346
347/*
348 * find slot id based on port number.
349 * @port: The one-based port number from one of the two split roothubs.
350 */
351int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
352 u16 port)
353{
354 int slot_id;
355 int i;
356 enum usb_device_speed speed;
357
358 slot_id = 0;
359 for (i = 0; i < MAX_HC_SLOTS; i++) {
360 if (!xhci->devs[i])
361 continue;
362 speed = xhci->devs[i]->udev->speed;
363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364 && xhci->devs[i]->fake_port == port) {
365 slot_id = i;
366 break;
367 }
368 }
369
370 return slot_id;
371}
372
373/*
374 * Stop device
375 * It issues stop endpoint command for EP 0 to 30. And wait the last command
376 * to complete.
377 * suspend will set to 1, if suspend bit need to set in command.
378 */
379static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
380{
381 struct xhci_virt_device *virt_dev;
382 struct xhci_command *cmd;
383 unsigned long flags;
384 int ret;
385 int i;
386
387 ret = 0;
388 virt_dev = xhci->devs[slot_id];
389 if (!virt_dev)
390 return -ENODEV;
391
392 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
393 if (!cmd) {
394 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
395 return -ENOMEM;
396 }
397
398 spin_lock_irqsave(&xhci->lock, flags);
399 for (i = LAST_EP_INDEX; i > 0; i--) {
400 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
401 struct xhci_command *command;
402 command = xhci_alloc_command(xhci, false, false,
403 GFP_NOWAIT);
404 if (!command) {
405 spin_unlock_irqrestore(&xhci->lock, flags);
406 xhci_free_command(xhci, cmd);
407 return -ENOMEM;
408
409 }
410 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
411 suspend);
412 }
413 }
414 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
415 xhci_ring_cmd_db(xhci);
416 spin_unlock_irqrestore(&xhci->lock, flags);
417
418 /* Wait for last stop endpoint command to finish */
419 wait_for_completion(cmd->completion);
420
421 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
422 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
423 ret = -ETIME;
424 }
425 xhci_free_command(xhci, cmd);
426 return ret;
427}
428
429/*
430 * Ring device, it rings the all doorbells unconditionally.
431 */
432void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
433{
434 int i, s;
435 struct xhci_virt_ep *ep;
436
437 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
438 ep = &xhci->devs[slot_id]->eps[i];
439
440 if (ep->ep_state & EP_HAS_STREAMS) {
441 for (s = 1; s < ep->stream_info->num_streams; s++)
442 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
443 } else if (ep->ring && ep->ring->dequeue) {
444 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
445 }
446 }
447
448 return;
449}
450
451static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
452 u16 wIndex, __le32 __iomem *addr, u32 port_status)
453{
454 /* Don't allow the USB core to disable SuperSpeed ports. */
455 if (hcd->speed >= HCD_USB3) {
456 xhci_dbg(xhci, "Ignoring request to disable "
457 "SuperSpeed port.\n");
458 return;
459 }
460
461 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
462 xhci_dbg(xhci,
463 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
464 return;
465 }
466
467 /* Write 1 to disable the port */
468 writel(port_status | PORT_PE, addr);
469 port_status = readl(addr);
470 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
471 wIndex, port_status);
472}
473
474static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
475 u16 wIndex, __le32 __iomem *addr, u32 port_status)
476{
477 char *port_change_bit;
478 u32 status;
479
480 switch (wValue) {
481 case USB_PORT_FEAT_C_RESET:
482 status = PORT_RC;
483 port_change_bit = "reset";
484 break;
485 case USB_PORT_FEAT_C_BH_PORT_RESET:
486 status = PORT_WRC;
487 port_change_bit = "warm(BH) reset";
488 break;
489 case USB_PORT_FEAT_C_CONNECTION:
490 status = PORT_CSC;
491 port_change_bit = "connect";
492 break;
493 case USB_PORT_FEAT_C_OVER_CURRENT:
494 status = PORT_OCC;
495 port_change_bit = "over-current";
496 break;
497 case USB_PORT_FEAT_C_ENABLE:
498 status = PORT_PEC;
499 port_change_bit = "enable/disable";
500 break;
501 case USB_PORT_FEAT_C_SUSPEND:
502 status = PORT_PLC;
503 port_change_bit = "suspend/resume";
504 break;
505 case USB_PORT_FEAT_C_PORT_LINK_STATE:
506 status = PORT_PLC;
507 port_change_bit = "link state";
508 break;
509 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
510 status = PORT_CEC;
511 port_change_bit = "config error";
512 break;
513 default:
514 /* Should never happen */
515 return;
516 }
517 /* Change bits are all write 1 to clear */
518 writel(port_status | status, addr);
519 port_status = readl(addr);
520 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
521 port_change_bit, wIndex, port_status);
522}
523
524static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
525{
526 int max_ports;
527 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
528
529 if (hcd->speed >= HCD_USB3) {
530 max_ports = xhci->num_usb3_ports;
531 *port_array = xhci->usb3_ports;
532 } else {
533 max_ports = xhci->num_usb2_ports;
534 *port_array = xhci->usb2_ports;
535 }
536
537 return max_ports;
538}
539
540void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
541 int port_id, u32 link_state)
542{
543 u32 temp;
544
545 temp = readl(port_array[port_id]);
546 temp = xhci_port_state_to_neutral(temp);
547 temp &= ~PORT_PLS_MASK;
548 temp |= PORT_LINK_STROBE | link_state;
549 writel(temp, port_array[port_id]);
550}
551
552static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
553 __le32 __iomem **port_array, int port_id, u16 wake_mask)
554{
555 u32 temp;
556
557 temp = readl(port_array[port_id]);
558 temp = xhci_port_state_to_neutral(temp);
559
560 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
561 temp |= PORT_WKCONN_E;
562 else
563 temp &= ~PORT_WKCONN_E;
564
565 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
566 temp |= PORT_WKDISC_E;
567 else
568 temp &= ~PORT_WKDISC_E;
569
570 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
571 temp |= PORT_WKOC_E;
572 else
573 temp &= ~PORT_WKOC_E;
574
575 writel(temp, port_array[port_id]);
576}
577
578/* Test and clear port RWC bit */
579void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
580 int port_id, u32 port_bit)
581{
582 u32 temp;
583
584 temp = readl(port_array[port_id]);
585 if (temp & port_bit) {
586 temp = xhci_port_state_to_neutral(temp);
587 temp |= port_bit;
588 writel(temp, port_array[port_id]);
589 }
590}
591
592/* Updates Link Status for USB 2.1 port */
593static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
594{
595 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
596 *status |= USB_PORT_STAT_L1;
597}
598
599/* Updates Link Status for super Speed port */
600static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
601 u32 *status, u32 status_reg)
602{
603 u32 pls = status_reg & PORT_PLS_MASK;
604
605 /* resume state is a xHCI internal state.
606 * Do not report it to usb core, instead, pretend to be U3,
607 * thus usb core knows it's not ready for transfer
608 */
609 if (pls == XDEV_RESUME) {
610 *status |= USB_SS_PORT_LS_U3;
611 return;
612 }
613
614 /* When the CAS bit is set then warm reset
615 * should be performed on port
616 */
617 if (status_reg & PORT_CAS) {
618 /* The CAS bit can be set while the port is
619 * in any link state.
620 * Only roothubs have CAS bit, so we
621 * pretend to be in compliance mode
622 * unless we're already in compliance
623 * or the inactive state.
624 */
625 if (pls != USB_SS_PORT_LS_COMP_MOD &&
626 pls != USB_SS_PORT_LS_SS_INACTIVE) {
627 pls = USB_SS_PORT_LS_COMP_MOD;
628 }
629 /* Return also connection bit -
630 * hub state machine resets port
631 * when this bit is set.
632 */
633 pls |= USB_PORT_STAT_CONNECTION;
634 } else {
635 /*
636 * If CAS bit isn't set but the Port is already at
637 * Compliance Mode, fake a connection so the USB core
638 * notices the Compliance state and resets the port.
639 * This resolves an issue generated by the SN65LVPE502CP
640 * in which sometimes the port enters compliance mode
641 * caused by a delay on the host-device negotiation.
642 */
643 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
644 (pls == USB_SS_PORT_LS_COMP_MOD))
645 pls |= USB_PORT_STAT_CONNECTION;
646 }
647
648 /* update status field */
649 *status |= pls;
650}
651
652/*
653 * Function for Compliance Mode Quirk.
654 *
655 * This Function verifies if all xhc USB3 ports have entered U0, if so,
656 * the compliance mode timer is deleted. A port won't enter
657 * compliance mode if it has previously entered U0.
658 */
659static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
660 u16 wIndex)
661{
662 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
663 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
664
665 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
666 return;
667
668 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
669 xhci->port_status_u0 |= 1 << wIndex;
670 if (xhci->port_status_u0 == all_ports_seen_u0) {
671 del_timer_sync(&xhci->comp_mode_recovery_timer);
672 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
673 "All USB3 ports have entered U0 already!");
674 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
675 "Compliance Mode Recovery Timer Deleted.");
676 }
677 }
678}
679
680static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
681{
682 u32 ext_stat = 0;
683 int speed_id;
684
685 /* only support rx and tx lane counts of 1 in usb3.1 spec */
686 speed_id = DEV_PORT_SPEED(raw_port_status);
687 ext_stat |= speed_id; /* bits 3:0, RX speed id */
688 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
689
690 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
691 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
692
693 return ext_stat;
694}
695
696/*
697 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
698 * 3.0 hubs use.
699 *
700 * Possible side effects:
701 * - Mark a port as being done with device resume,
702 * and ring the endpoint doorbells.
703 * - Stop the Synopsys redriver Compliance Mode polling.
704 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
705 */
706static u32 xhci_get_port_status(struct usb_hcd *hcd,
707 struct xhci_bus_state *bus_state,
708 __le32 __iomem **port_array,
709 u16 wIndex, u32 raw_port_status,
710 unsigned long flags)
711 __releases(&xhci->lock)
712 __acquires(&xhci->lock)
713{
714 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
715 u32 status = 0;
716 int slot_id;
717
718 /* wPortChange bits */
719 if (raw_port_status & PORT_CSC)
720 status |= USB_PORT_STAT_C_CONNECTION << 16;
721 if (raw_port_status & PORT_PEC)
722 status |= USB_PORT_STAT_C_ENABLE << 16;
723 if ((raw_port_status & PORT_OCC))
724 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
725 if ((raw_port_status & PORT_RC))
726 status |= USB_PORT_STAT_C_RESET << 16;
727 /* USB3.0 only */
728 if (hcd->speed >= HCD_USB3) {
729 /* Port link change with port in resume state should not be
730 * reported to usbcore, as this is an internal state to be
731 * handled by xhci driver. Reporting PLC to usbcore may
732 * cause usbcore clearing PLC first and port change event
733 * irq won't be generated.
734 */
735 if ((raw_port_status & PORT_PLC) &&
736 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
737 status |= USB_PORT_STAT_C_LINK_STATE << 16;
738 if ((raw_port_status & PORT_WRC))
739 status |= USB_PORT_STAT_C_BH_RESET << 16;
740 if ((raw_port_status & PORT_CEC))
741 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
742 }
743
744 if (hcd->speed < HCD_USB3) {
745 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
746 && (raw_port_status & PORT_POWER))
747 status |= USB_PORT_STAT_SUSPEND;
748 }
749 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
750 !DEV_SUPERSPEED_ANY(raw_port_status)) {
751 if ((raw_port_status & PORT_RESET) ||
752 !(raw_port_status & PORT_PE))
753 return 0xffffffff;
754 /* did port event handler already start resume timing? */
755 if (!bus_state->resume_done[wIndex]) {
756 /* If not, maybe we are in a host initated resume? */
757 if (test_bit(wIndex, &bus_state->resuming_ports)) {
758 /* Host initated resume doesn't time the resume
759 * signalling using resume_done[].
760 * It manually sets RESUME state, sleeps 20ms
761 * and sets U0 state. This should probably be
762 * changed, but not right now.
763 */
764 } else {
765 /* port resume was discovered now and here,
766 * start resume timing
767 */
768 unsigned long timeout = jiffies +
769 msecs_to_jiffies(USB_RESUME_TIMEOUT);
770
771 set_bit(wIndex, &bus_state->resuming_ports);
772 bus_state->resume_done[wIndex] = timeout;
773 mod_timer(&hcd->rh_timer, timeout);
774 }
775 /* Has resume been signalled for USB_RESUME_TIME yet? */
776 } else if (time_after_eq(jiffies,
777 bus_state->resume_done[wIndex])) {
778 int time_left;
779
780 xhci_dbg(xhci, "Resume USB2 port %d\n",
781 wIndex + 1);
782 bus_state->resume_done[wIndex] = 0;
783 clear_bit(wIndex, &bus_state->resuming_ports);
784
785 set_bit(wIndex, &bus_state->rexit_ports);
786 xhci_set_link_state(xhci, port_array, wIndex,
787 XDEV_U0);
788
789 spin_unlock_irqrestore(&xhci->lock, flags);
790 time_left = wait_for_completion_timeout(
791 &bus_state->rexit_done[wIndex],
792 msecs_to_jiffies(
793 XHCI_MAX_REXIT_TIMEOUT));
794 spin_lock_irqsave(&xhci->lock, flags);
795
796 if (time_left) {
797 slot_id = xhci_find_slot_id_by_port(hcd,
798 xhci, wIndex + 1);
799 if (!slot_id) {
800 xhci_dbg(xhci, "slot_id is zero\n");
801 return 0xffffffff;
802 }
803 xhci_ring_device(xhci, slot_id);
804 } else {
805 int port_status = readl(port_array[wIndex]);
806 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
807 XHCI_MAX_REXIT_TIMEOUT,
808 port_status);
809 status |= USB_PORT_STAT_SUSPEND;
810 clear_bit(wIndex, &bus_state->rexit_ports);
811 }
812
813 bus_state->port_c_suspend |= 1 << wIndex;
814 bus_state->suspended_ports &= ~(1 << wIndex);
815 } else {
816 /*
817 * The resume has been signaling for less than
818 * USB_RESUME_TIME. Report the port status as SUSPEND,
819 * let the usbcore check port status again and clear
820 * resume signaling later.
821 */
822 status |= USB_PORT_STAT_SUSPEND;
823 }
824 }
825 /*
826 * Clear stale usb2 resume signalling variables in case port changed
827 * state during resume signalling. For example on error
828 */
829 if ((bus_state->resume_done[wIndex] ||
830 test_bit(wIndex, &bus_state->resuming_ports)) &&
831 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
832 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
833 bus_state->resume_done[wIndex] = 0;
834 clear_bit(wIndex, &bus_state->resuming_ports);
835 }
836
837
838 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
839 (raw_port_status & PORT_POWER)) {
840 if (bus_state->suspended_ports & (1 << wIndex)) {
841 bus_state->suspended_ports &= ~(1 << wIndex);
842 if (hcd->speed < HCD_USB3)
843 bus_state->port_c_suspend |= 1 << wIndex;
844 }
845 bus_state->resume_done[wIndex] = 0;
846 clear_bit(wIndex, &bus_state->resuming_ports);
847 }
848 if (raw_port_status & PORT_CONNECT) {
849 status |= USB_PORT_STAT_CONNECTION;
850 status |= xhci_port_speed(raw_port_status);
851 }
852 if (raw_port_status & PORT_PE)
853 status |= USB_PORT_STAT_ENABLE;
854 if (raw_port_status & PORT_OC)
855 status |= USB_PORT_STAT_OVERCURRENT;
856 if (raw_port_status & PORT_RESET)
857 status |= USB_PORT_STAT_RESET;
858 if (raw_port_status & PORT_POWER) {
859 if (hcd->speed >= HCD_USB3)
860 status |= USB_SS_PORT_STAT_POWER;
861 else
862 status |= USB_PORT_STAT_POWER;
863 }
864 /* Update Port Link State */
865 if (hcd->speed >= HCD_USB3) {
866 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
867 /*
868 * Verify if all USB3 Ports Have entered U0 already.
869 * Delete Compliance Mode Timer if so.
870 */
871 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
872 } else {
873 xhci_hub_report_usb2_link_state(&status, raw_port_status);
874 }
875 if (bus_state->port_c_suspend & (1 << wIndex))
876 status |= USB_PORT_STAT_C_SUSPEND << 16;
877
878 return status;
879}
880
881int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
882 u16 wIndex, char *buf, u16 wLength)
883{
884 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
885 int max_ports;
886 unsigned long flags;
887 u32 temp, status;
888 int retval = 0;
889 __le32 __iomem **port_array;
890 int slot_id;
891 struct xhci_bus_state *bus_state;
892 u16 link_state = 0;
893 u16 wake_mask = 0;
894 u16 timeout = 0;
895
896 max_ports = xhci_get_ports(hcd, &port_array);
897 bus_state = &xhci->bus_state[hcd_index(hcd)];
898
899 spin_lock_irqsave(&xhci->lock, flags);
900 switch (typeReq) {
901 case GetHubStatus:
902 /* No power source, over-current reported per port */
903 memset(buf, 0, 4);
904 break;
905 case GetHubDescriptor:
906 /* Check to make sure userspace is asking for the USB 3.0 hub
907 * descriptor for the USB 3.0 roothub. If not, we stall the
908 * endpoint, like external hubs do.
909 */
910 if (hcd->speed >= HCD_USB3 &&
911 (wLength < USB_DT_SS_HUB_SIZE ||
912 wValue != (USB_DT_SS_HUB << 8))) {
913 xhci_dbg(xhci, "Wrong hub descriptor type for "
914 "USB 3.0 roothub.\n");
915 goto error;
916 }
917 xhci_hub_descriptor(hcd, xhci,
918 (struct usb_hub_descriptor *) buf);
919 break;
920 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
921 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
922 goto error;
923
924 if (hcd->speed < HCD_USB3)
925 goto error;
926
927 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
928 spin_unlock_irqrestore(&xhci->lock, flags);
929 return retval;
930 case GetPortStatus:
931 if (!wIndex || wIndex > max_ports)
932 goto error;
933 wIndex--;
934 temp = readl(port_array[wIndex]);
935 if (temp == 0xffffffff) {
936 retval = -ENODEV;
937 break;
938 }
939 status = xhci_get_port_status(hcd, bus_state, port_array,
940 wIndex, temp, flags);
941 if (status == 0xffffffff)
942 goto error;
943
944 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
945 wIndex, temp);
946 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
947
948 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
949 /* if USB 3.1 extended port status return additional 4 bytes */
950 if (wValue == 0x02) {
951 u32 port_li;
952
953 if (hcd->speed < HCD_USB31 || wLength != 8) {
954 xhci_err(xhci, "get ext port status invalid parameter\n");
955 retval = -EINVAL;
956 break;
957 }
958 port_li = readl(port_array[wIndex] + PORTLI);
959 status = xhci_get_ext_port_status(temp, port_li);
960 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
961 }
962 break;
963 case SetPortFeature:
964 if (wValue == USB_PORT_FEAT_LINK_STATE)
965 link_state = (wIndex & 0xff00) >> 3;
966 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
967 wake_mask = wIndex & 0xff00;
968 /* The MSB of wIndex is the U1/U2 timeout */
969 timeout = (wIndex & 0xff00) >> 8;
970 wIndex &= 0xff;
971 if (!wIndex || wIndex > max_ports)
972 goto error;
973 wIndex--;
974 temp = readl(port_array[wIndex]);
975 if (temp == 0xffffffff) {
976 retval = -ENODEV;
977 break;
978 }
979 temp = xhci_port_state_to_neutral(temp);
980 /* FIXME: What new port features do we need to support? */
981 switch (wValue) {
982 case USB_PORT_FEAT_SUSPEND:
983 temp = readl(port_array[wIndex]);
984 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
985 /* Resume the port to U0 first */
986 xhci_set_link_state(xhci, port_array, wIndex,
987 XDEV_U0);
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 msleep(10);
990 spin_lock_irqsave(&xhci->lock, flags);
991 }
992 /* In spec software should not attempt to suspend
993 * a port unless the port reports that it is in the
994 * enabled (PED = ‘1’,PLS < ‘3’) state.
995 */
996 temp = readl(port_array[wIndex]);
997 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
998 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
999 xhci_warn(xhci, "USB core suspending device "
1000 "not in U0/U1/U2.\n");
1001 goto error;
1002 }
1003
1004 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1005 wIndex + 1);
1006 if (!slot_id) {
1007 xhci_warn(xhci, "slot_id is zero\n");
1008 goto error;
1009 }
1010 /* unlock to execute stop endpoint commands */
1011 spin_unlock_irqrestore(&xhci->lock, flags);
1012 xhci_stop_device(xhci, slot_id, 1);
1013 spin_lock_irqsave(&xhci->lock, flags);
1014
1015 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1016
1017 spin_unlock_irqrestore(&xhci->lock, flags);
1018 msleep(10); /* wait device to enter */
1019 spin_lock_irqsave(&xhci->lock, flags);
1020
1021 temp = readl(port_array[wIndex]);
1022 bus_state->suspended_ports |= 1 << wIndex;
1023 break;
1024 case USB_PORT_FEAT_LINK_STATE:
1025 temp = readl(port_array[wIndex]);
1026
1027 /* Disable port */
1028 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1029 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1030 temp = xhci_port_state_to_neutral(temp);
1031 /*
1032 * Clear all change bits, so that we get a new
1033 * connection event.
1034 */
1035 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1036 PORT_OCC | PORT_RC | PORT_PLC |
1037 PORT_CEC;
1038 writel(temp | PORT_PE, port_array[wIndex]);
1039 temp = readl(port_array[wIndex]);
1040 break;
1041 }
1042
1043 /* Put link in RxDetect (enable port) */
1044 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1045 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1046 xhci_set_link_state(xhci, port_array, wIndex,
1047 link_state);
1048 temp = readl(port_array[wIndex]);
1049 break;
1050 }
1051
1052 /* Software should not attempt to set
1053 * port link state above '3' (U3) and the port
1054 * must be enabled.
1055 */
1056 if ((temp & PORT_PE) == 0 ||
1057 (link_state > USB_SS_PORT_LS_U3)) {
1058 xhci_warn(xhci, "Cannot set link state.\n");
1059 goto error;
1060 }
1061
1062 if (link_state == USB_SS_PORT_LS_U3) {
1063 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1064 wIndex + 1);
1065 if (slot_id) {
1066 /* unlock to execute stop endpoint
1067 * commands */
1068 spin_unlock_irqrestore(&xhci->lock,
1069 flags);
1070 xhci_stop_device(xhci, slot_id, 1);
1071 spin_lock_irqsave(&xhci->lock, flags);
1072 }
1073 }
1074
1075 xhci_set_link_state(xhci, port_array, wIndex,
1076 link_state);
1077
1078 spin_unlock_irqrestore(&xhci->lock, flags);
1079 msleep(20); /* wait device to enter */
1080 spin_lock_irqsave(&xhci->lock, flags);
1081
1082 temp = readl(port_array[wIndex]);
1083 if (link_state == USB_SS_PORT_LS_U3)
1084 bus_state->suspended_ports |= 1 << wIndex;
1085 break;
1086 case USB_PORT_FEAT_POWER:
1087 /*
1088 * Turn on ports, even if there isn't per-port switching.
1089 * HC will report connect events even before this is set.
1090 * However, hub_wq will ignore the roothub events until
1091 * the roothub is registered.
1092 */
1093 writel(temp | PORT_POWER, port_array[wIndex]);
1094
1095 temp = readl(port_array[wIndex]);
1096 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1097
1098 spin_unlock_irqrestore(&xhci->lock, flags);
1099 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1100 wIndex);
1101 if (temp)
1102 usb_acpi_set_power_state(hcd->self.root_hub,
1103 wIndex, true);
1104 spin_lock_irqsave(&xhci->lock, flags);
1105 break;
1106 case USB_PORT_FEAT_RESET:
1107 temp = (temp | PORT_RESET);
1108 writel(temp, port_array[wIndex]);
1109
1110 temp = readl(port_array[wIndex]);
1111 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1112 break;
1113 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1114 xhci_set_remote_wake_mask(xhci, port_array,
1115 wIndex, wake_mask);
1116 temp = readl(port_array[wIndex]);
1117 xhci_dbg(xhci, "set port remote wake mask, "
1118 "actual port %d status = 0x%x\n",
1119 wIndex, temp);
1120 break;
1121 case USB_PORT_FEAT_BH_PORT_RESET:
1122 temp |= PORT_WR;
1123 writel(temp, port_array[wIndex]);
1124
1125 temp = readl(port_array[wIndex]);
1126 break;
1127 case USB_PORT_FEAT_U1_TIMEOUT:
1128 if (hcd->speed < HCD_USB3)
1129 goto error;
1130 temp = readl(port_array[wIndex] + PORTPMSC);
1131 temp &= ~PORT_U1_TIMEOUT_MASK;
1132 temp |= PORT_U1_TIMEOUT(timeout);
1133 writel(temp, port_array[wIndex] + PORTPMSC);
1134 break;
1135 case USB_PORT_FEAT_U2_TIMEOUT:
1136 if (hcd->speed < HCD_USB3)
1137 goto error;
1138 temp = readl(port_array[wIndex] + PORTPMSC);
1139 temp &= ~PORT_U2_TIMEOUT_MASK;
1140 temp |= PORT_U2_TIMEOUT(timeout);
1141 writel(temp, port_array[wIndex] + PORTPMSC);
1142 break;
1143 default:
1144 goto error;
1145 }
1146 /* unblock any posted writes */
1147 temp = readl(port_array[wIndex]);
1148 break;
1149 case ClearPortFeature:
1150 if (!wIndex || wIndex > max_ports)
1151 goto error;
1152 wIndex--;
1153 temp = readl(port_array[wIndex]);
1154 if (temp == 0xffffffff) {
1155 retval = -ENODEV;
1156 break;
1157 }
1158 /* FIXME: What new port features do we need to support? */
1159 temp = xhci_port_state_to_neutral(temp);
1160 switch (wValue) {
1161 case USB_PORT_FEAT_SUSPEND:
1162 temp = readl(port_array[wIndex]);
1163 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1164 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1165 if (temp & PORT_RESET)
1166 goto error;
1167 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1168 if ((temp & PORT_PE) == 0)
1169 goto error;
1170
1171 set_bit(wIndex, &bus_state->resuming_ports);
1172 xhci_set_link_state(xhci, port_array, wIndex,
1173 XDEV_RESUME);
1174 spin_unlock_irqrestore(&xhci->lock, flags);
1175 msleep(USB_RESUME_TIMEOUT);
1176 spin_lock_irqsave(&xhci->lock, flags);
1177 xhci_set_link_state(xhci, port_array, wIndex,
1178 XDEV_U0);
1179 clear_bit(wIndex, &bus_state->resuming_ports);
1180 }
1181 bus_state->port_c_suspend |= 1 << wIndex;
1182
1183 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1184 wIndex + 1);
1185 if (!slot_id) {
1186 xhci_dbg(xhci, "slot_id is zero\n");
1187 goto error;
1188 }
1189 xhci_ring_device(xhci, slot_id);
1190 break;
1191 case USB_PORT_FEAT_C_SUSPEND:
1192 bus_state->port_c_suspend &= ~(1 << wIndex);
1193 case USB_PORT_FEAT_C_RESET:
1194 case USB_PORT_FEAT_C_BH_PORT_RESET:
1195 case USB_PORT_FEAT_C_CONNECTION:
1196 case USB_PORT_FEAT_C_OVER_CURRENT:
1197 case USB_PORT_FEAT_C_ENABLE:
1198 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1199 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1200 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1201 port_array[wIndex], temp);
1202 break;
1203 case USB_PORT_FEAT_ENABLE:
1204 xhci_disable_port(hcd, xhci, wIndex,
1205 port_array[wIndex], temp);
1206 break;
1207 case USB_PORT_FEAT_POWER:
1208 writel(temp & ~PORT_POWER, port_array[wIndex]);
1209
1210 spin_unlock_irqrestore(&xhci->lock, flags);
1211 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1212 wIndex);
1213 if (temp)
1214 usb_acpi_set_power_state(hcd->self.root_hub,
1215 wIndex, false);
1216 spin_lock_irqsave(&xhci->lock, flags);
1217 break;
1218 default:
1219 goto error;
1220 }
1221 break;
1222 default:
1223error:
1224 /* "stall" on error */
1225 retval = -EPIPE;
1226 }
1227 spin_unlock_irqrestore(&xhci->lock, flags);
1228 return retval;
1229}
1230
1231/*
1232 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1233 * Ports are 0-indexed from the HCD point of view,
1234 * and 1-indexed from the USB core pointer of view.
1235 *
1236 * Note that the status change bits will be cleared as soon as a port status
1237 * change event is generated, so we use the saved status from that event.
1238 */
1239int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1240{
1241 unsigned long flags;
1242 u32 temp, status;
1243 u32 mask;
1244 int i, retval;
1245 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1246 int max_ports;
1247 __le32 __iomem **port_array;
1248 struct xhci_bus_state *bus_state;
1249 bool reset_change = false;
1250
1251 max_ports = xhci_get_ports(hcd, &port_array);
1252 bus_state = &xhci->bus_state[hcd_index(hcd)];
1253
1254 /* Initial status is no changes */
1255 retval = (max_ports + 8) / 8;
1256 memset(buf, 0, retval);
1257
1258 /*
1259 * Inform the usbcore about resume-in-progress by returning
1260 * a non-zero value even if there are no status changes.
1261 */
1262 status = bus_state->resuming_ports;
1263
1264 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1265
1266 spin_lock_irqsave(&xhci->lock, flags);
1267 /* For each port, did anything change? If so, set that bit in buf. */
1268 for (i = 0; i < max_ports; i++) {
1269 temp = readl(port_array[i]);
1270 if (temp == 0xffffffff) {
1271 retval = -ENODEV;
1272 break;
1273 }
1274 if ((temp & mask) != 0 ||
1275 (bus_state->port_c_suspend & 1 << i) ||
1276 (bus_state->resume_done[i] && time_after_eq(
1277 jiffies, bus_state->resume_done[i]))) {
1278 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1279 status = 1;
1280 }
1281 if ((temp & PORT_RC))
1282 reset_change = true;
1283 }
1284 if (!status && !reset_change) {
1285 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1286 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1287 }
1288 spin_unlock_irqrestore(&xhci->lock, flags);
1289 return status ? retval : 0;
1290}
1291
1292#ifdef CONFIG_PM
1293
1294int xhci_bus_suspend(struct usb_hcd *hcd)
1295{
1296 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1297 int max_ports, port_index;
1298 __le32 __iomem **port_array;
1299 struct xhci_bus_state *bus_state;
1300 unsigned long flags;
1301
1302 max_ports = xhci_get_ports(hcd, &port_array);
1303 bus_state = &xhci->bus_state[hcd_index(hcd)];
1304
1305 spin_lock_irqsave(&xhci->lock, flags);
1306
1307 if (hcd->self.root_hub->do_remote_wakeup) {
1308 if (bus_state->resuming_ports || /* USB2 */
1309 bus_state->port_remote_wakeup) { /* USB3 */
1310 spin_unlock_irqrestore(&xhci->lock, flags);
1311 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1312 return -EBUSY;
1313 }
1314 }
1315
1316 port_index = max_ports;
1317 bus_state->bus_suspended = 0;
1318 while (port_index--) {
1319 /* suspend the port if the port is not suspended */
1320 u32 t1, t2;
1321 int slot_id;
1322
1323 t1 = readl(port_array[port_index]);
1324 t2 = xhci_port_state_to_neutral(t1);
1325
1326 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1327 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1328 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1329 port_index + 1);
1330 if (slot_id) {
1331 spin_unlock_irqrestore(&xhci->lock, flags);
1332 xhci_stop_device(xhci, slot_id, 1);
1333 spin_lock_irqsave(&xhci->lock, flags);
1334 }
1335 t2 &= ~PORT_PLS_MASK;
1336 t2 |= PORT_LINK_STROBE | XDEV_U3;
1337 set_bit(port_index, &bus_state->bus_suspended);
1338 }
1339 /* USB core sets remote wake mask for USB 3.0 hubs,
1340 * including the USB 3.0 roothub, but only if CONFIG_PM
1341 * is enabled, so also enable remote wake here.
1342 */
1343 if (hcd->self.root_hub->do_remote_wakeup) {
1344 if (t1 & PORT_CONNECT) {
1345 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1346 t2 &= ~PORT_WKCONN_E;
1347 } else {
1348 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1349 t2 &= ~PORT_WKDISC_E;
1350 }
1351 } else
1352 t2 &= ~PORT_WAKE_BITS;
1353
1354 t1 = xhci_port_state_to_neutral(t1);
1355 if (t1 != t2)
1356 writel(t2, port_array[port_index]);
1357 }
1358 hcd->state = HC_STATE_SUSPENDED;
1359 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1360 spin_unlock_irqrestore(&xhci->lock, flags);
1361 return 0;
1362}
1363
1364/*
1365 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1366 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1367 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1368 */
1369static bool xhci_port_missing_cas_quirk(int port_index,
1370 __le32 __iomem **port_array)
1371{
1372 u32 portsc;
1373
1374 portsc = readl(port_array[port_index]);
1375
1376 /* if any of these are set we are not stuck */
1377 if (portsc & (PORT_CONNECT | PORT_CAS))
1378 return false;
1379
1380 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1381 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1382 return false;
1383
1384 /* clear wakeup/change bits, and do a warm port reset */
1385 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1386 portsc |= PORT_WR;
1387 writel(portsc, port_array[port_index]);
1388 /* flush write */
1389 readl(port_array[port_index]);
1390 return true;
1391}
1392
1393int xhci_bus_resume(struct usb_hcd *hcd)
1394{
1395 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1396 int max_ports, port_index;
1397 __le32 __iomem **port_array;
1398 struct xhci_bus_state *bus_state;
1399 u32 temp;
1400 unsigned long flags;
1401 unsigned long port_was_suspended = 0;
1402 bool need_usb2_u3_exit = false;
1403 int slot_id;
1404 int sret;
1405
1406 max_ports = xhci_get_ports(hcd, &port_array);
1407 bus_state = &xhci->bus_state[hcd_index(hcd)];
1408
1409 if (time_before(jiffies, bus_state->next_statechange))
1410 msleep(5);
1411
1412 spin_lock_irqsave(&xhci->lock, flags);
1413 if (!HCD_HW_ACCESSIBLE(hcd)) {
1414 spin_unlock_irqrestore(&xhci->lock, flags);
1415 return -ESHUTDOWN;
1416 }
1417
1418 /* delay the irqs */
1419 temp = readl(&xhci->op_regs->command);
1420 temp &= ~CMD_EIE;
1421 writel(temp, &xhci->op_regs->command);
1422
1423 port_index = max_ports;
1424 while (port_index--) {
1425 /* Check whether need resume ports. If needed
1426 resume port and disable remote wakeup */
1427 u32 temp;
1428
1429 temp = readl(port_array[port_index]);
1430
1431 /* warm reset CAS limited ports stuck in polling/compliance */
1432 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1433 (hcd->speed >= HCD_USB3) &&
1434 xhci_port_missing_cas_quirk(port_index, port_array)) {
1435 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1436 continue;
1437 }
1438 if (DEV_SUPERSPEED_ANY(temp))
1439 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1440 else
1441 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1442 if (test_bit(port_index, &bus_state->bus_suspended) &&
1443 (temp & PORT_PLS_MASK)) {
1444 set_bit(port_index, &port_was_suspended);
1445 if (!DEV_SUPERSPEED_ANY(temp)) {
1446 xhci_set_link_state(xhci, port_array,
1447 port_index, XDEV_RESUME);
1448 need_usb2_u3_exit = true;
1449 }
1450 } else
1451 writel(temp, port_array[port_index]);
1452 }
1453
1454 if (need_usb2_u3_exit) {
1455 spin_unlock_irqrestore(&xhci->lock, flags);
1456 msleep(USB_RESUME_TIMEOUT);
1457 spin_lock_irqsave(&xhci->lock, flags);
1458 }
1459
1460 port_index = max_ports;
1461 while (port_index--) {
1462 if (!(port_was_suspended & BIT(port_index)))
1463 continue;
1464 /* Clear PLC to poll it later after XDEV_U0 */
1465 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1466 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1467 }
1468
1469 port_index = max_ports;
1470 while (port_index--) {
1471 if (!(port_was_suspended & BIT(port_index)))
1472 continue;
1473 /* Poll and Clear PLC */
1474 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1475 PORT_PLC, 10 * 1000);
1476 if (sret)
1477 xhci_warn(xhci, "port %d resume PLC timeout\n",
1478 port_index);
1479 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1480 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1481 if (slot_id)
1482 xhci_ring_device(xhci, slot_id);
1483 }
1484
1485 (void) readl(&xhci->op_regs->command);
1486
1487 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1488 /* re-enable irqs */
1489 temp = readl(&xhci->op_regs->command);
1490 temp |= CMD_EIE;
1491 writel(temp, &xhci->op_regs->command);
1492 temp = readl(&xhci->op_regs->command);
1493
1494 spin_unlock_irqrestore(&xhci->lock, flags);
1495 return 0;
1496}
1497
1498#endif /* CONFIG_PM */