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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11# define SUPPORT_SYSRQ
12#endif
13
14#include <linux/kernel.h>
15#include <linux/atomic.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmaengine.h>
18#include <linux/module.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/interrupt.h>
22#include <linux/init.h>
23#include <linux/console.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial_core.h>
27#include <linux/slab.h>
28#include <linux/clk.h>
29#include <linux/platform_device.h>
30#include <linux/delay.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/wait.h>
34
35#define UART_MR1 0x0000
36
37#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
38#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
39#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
40#define UART_MR1_RX_RDY_CTL BIT(7)
41#define UART_MR1_CTS_CTL BIT(6)
42
43#define UART_MR2 0x0004
44#define UART_MR2_ERROR_MODE BIT(6)
45#define UART_MR2_BITS_PER_CHAR 0x30
46#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
47#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
48#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
49#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
50#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
51#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
52#define UART_MR2_PARITY_MODE_NONE 0x0
53#define UART_MR2_PARITY_MODE_ODD 0x1
54#define UART_MR2_PARITY_MODE_EVEN 0x2
55#define UART_MR2_PARITY_MODE_SPACE 0x3
56#define UART_MR2_PARITY_MODE 0x3
57
58#define UART_CSR 0x0008
59
60#define UART_TF 0x000C
61#define UARTDM_TF 0x0070
62
63#define UART_CR 0x0010
64#define UART_CR_CMD_NULL (0 << 4)
65#define UART_CR_CMD_RESET_RX (1 << 4)
66#define UART_CR_CMD_RESET_TX (2 << 4)
67#define UART_CR_CMD_RESET_ERR (3 << 4)
68#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
69#define UART_CR_CMD_START_BREAK (5 << 4)
70#define UART_CR_CMD_STOP_BREAK (6 << 4)
71#define UART_CR_CMD_RESET_CTS (7 << 4)
72#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
73#define UART_CR_CMD_PACKET_MODE (9 << 4)
74#define UART_CR_CMD_MODE_RESET (12 << 4)
75#define UART_CR_CMD_SET_RFR (13 << 4)
76#define UART_CR_CMD_RESET_RFR (14 << 4)
77#define UART_CR_CMD_PROTECTION_EN (16 << 4)
78#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
79#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
80#define UART_CR_CMD_FORCE_STALE (4 << 8)
81#define UART_CR_CMD_RESET_TX_READY (3 << 8)
82#define UART_CR_TX_DISABLE BIT(3)
83#define UART_CR_TX_ENABLE BIT(2)
84#define UART_CR_RX_DISABLE BIT(1)
85#define UART_CR_RX_ENABLE BIT(0)
86#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
87
88#define UART_IMR 0x0014
89#define UART_IMR_TXLEV BIT(0)
90#define UART_IMR_RXSTALE BIT(3)
91#define UART_IMR_RXLEV BIT(4)
92#define UART_IMR_DELTA_CTS BIT(5)
93#define UART_IMR_CURRENT_CTS BIT(6)
94#define UART_IMR_RXBREAK_START BIT(10)
95
96#define UART_IPR_RXSTALE_LAST 0x20
97#define UART_IPR_STALE_LSB 0x1F
98#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
99#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
100
101#define UART_IPR 0x0018
102#define UART_TFWR 0x001C
103#define UART_RFWR 0x0020
104#define UART_HCR 0x0024
105
106#define UART_MREG 0x0028
107#define UART_NREG 0x002C
108#define UART_DREG 0x0030
109#define UART_MNDREG 0x0034
110#define UART_IRDA 0x0038
111#define UART_MISR_MODE 0x0040
112#define UART_MISR_RESET 0x0044
113#define UART_MISR_EXPORT 0x0048
114#define UART_MISR_VAL 0x004C
115#define UART_TEST_CTRL 0x0050
116
117#define UART_SR 0x0008
118#define UART_SR_HUNT_CHAR BIT(7)
119#define UART_SR_RX_BREAK BIT(6)
120#define UART_SR_PAR_FRAME_ERR BIT(5)
121#define UART_SR_OVERRUN BIT(4)
122#define UART_SR_TX_EMPTY BIT(3)
123#define UART_SR_TX_READY BIT(2)
124#define UART_SR_RX_FULL BIT(1)
125#define UART_SR_RX_READY BIT(0)
126
127#define UART_RF 0x000C
128#define UARTDM_RF 0x0070
129#define UART_MISR 0x0010
130#define UART_ISR 0x0014
131#define UART_ISR_TX_READY BIT(7)
132
133#define UARTDM_RXFS 0x50
134#define UARTDM_RXFS_BUF_SHIFT 0x7
135#define UARTDM_RXFS_BUF_MASK 0x7
136
137#define UARTDM_DMEN 0x3C
138#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
139#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
140
141#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
142#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
143
144#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
145#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
146
147#define UARTDM_DMRX 0x34
148#define UARTDM_NCF_TX 0x40
149#define UARTDM_RX_TOTAL_SNAP 0x38
150
151#define UARTDM_BURST_SIZE 16 /* in bytes */
152#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
153#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
154#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
155
156enum {
157 UARTDM_1P1 = 1,
158 UARTDM_1P2,
159 UARTDM_1P3,
160 UARTDM_1P4,
161};
162
163struct msm_dma {
164 struct dma_chan *chan;
165 enum dma_data_direction dir;
166 dma_addr_t phys;
167 unsigned char *virt;
168 dma_cookie_t cookie;
169 u32 enable_bit;
170 unsigned int count;
171 struct dma_async_tx_descriptor *desc;
172};
173
174struct msm_port {
175 struct uart_port uart;
176 char name[16];
177 struct clk *clk;
178 struct clk *pclk;
179 unsigned int imr;
180 int is_uartdm;
181 unsigned int old_snap_state;
182 bool break_detected;
183 struct msm_dma tx_dma;
184 struct msm_dma rx_dma;
185};
186
187#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
188
189static
190void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
191{
192 writel_relaxed(val, port->membase + off);
193}
194
195static
196unsigned int msm_read(struct uart_port *port, unsigned int off)
197{
198 return readl_relaxed(port->membase + off);
199}
200
201/*
202 * Setup the MND registers to use the TCXO clock.
203 */
204static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
205{
206 msm_write(port, 0x06, UART_MREG);
207 msm_write(port, 0xF1, UART_NREG);
208 msm_write(port, 0x0F, UART_DREG);
209 msm_write(port, 0x1A, UART_MNDREG);
210 port->uartclk = 1843200;
211}
212
213/*
214 * Setup the MND registers to use the TCXO clock divided by 4.
215 */
216static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
217{
218 msm_write(port, 0x18, UART_MREG);
219 msm_write(port, 0xF6, UART_NREG);
220 msm_write(port, 0x0F, UART_DREG);
221 msm_write(port, 0x0A, UART_MNDREG);
222 port->uartclk = 1843200;
223}
224
225static void msm_serial_set_mnd_regs(struct uart_port *port)
226{
227 struct msm_port *msm_port = UART_TO_MSM(port);
228
229 /*
230 * These registers don't exist so we change the clk input rate
231 * on uartdm hardware instead
232 */
233 if (msm_port->is_uartdm)
234 return;
235
236 if (port->uartclk == 19200000)
237 msm_serial_set_mnd_regs_tcxo(port);
238 else if (port->uartclk == 4800000)
239 msm_serial_set_mnd_regs_tcxoby4(port);
240}
241
242static void msm_handle_tx(struct uart_port *port);
243static void msm_start_rx_dma(struct msm_port *msm_port);
244
245static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
246{
247 struct device *dev = port->dev;
248 unsigned int mapped;
249 u32 val;
250
251 mapped = dma->count;
252 dma->count = 0;
253
254 dmaengine_terminate_all(dma->chan);
255
256 /*
257 * DMA Stall happens if enqueue and flush command happens concurrently.
258 * For example before changing the baud rate/protocol configuration and
259 * sending flush command to ADM, disable the channel of UARTDM.
260 * Note: should not reset the receiver here immediately as it is not
261 * suggested to do disable/reset or reset/disable at the same time.
262 */
263 val = msm_read(port, UARTDM_DMEN);
264 val &= ~dma->enable_bit;
265 msm_write(port, val, UARTDM_DMEN);
266
267 if (mapped)
268 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
269}
270
271static void msm_release_dma(struct msm_port *msm_port)
272{
273 struct msm_dma *dma;
274
275 dma = &msm_port->tx_dma;
276 if (dma->chan) {
277 msm_stop_dma(&msm_port->uart, dma);
278 dma_release_channel(dma->chan);
279 }
280
281 memset(dma, 0, sizeof(*dma));
282
283 dma = &msm_port->rx_dma;
284 if (dma->chan) {
285 msm_stop_dma(&msm_port->uart, dma);
286 dma_release_channel(dma->chan);
287 kfree(dma->virt);
288 }
289
290 memset(dma, 0, sizeof(*dma));
291}
292
293static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
294{
295 struct device *dev = msm_port->uart.dev;
296 struct dma_slave_config conf;
297 struct msm_dma *dma;
298 u32 crci = 0;
299 int ret;
300
301 dma = &msm_port->tx_dma;
302
303 /* allocate DMA resources, if available */
304 dma->chan = dma_request_slave_channel_reason(dev, "tx");
305 if (IS_ERR(dma->chan))
306 goto no_tx;
307
308 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
309
310 memset(&conf, 0, sizeof(conf));
311 conf.direction = DMA_MEM_TO_DEV;
312 conf.device_fc = true;
313 conf.dst_addr = base + UARTDM_TF;
314 conf.dst_maxburst = UARTDM_BURST_SIZE;
315 conf.slave_id = crci;
316
317 ret = dmaengine_slave_config(dma->chan, &conf);
318 if (ret)
319 goto rel_tx;
320
321 dma->dir = DMA_TO_DEVICE;
322
323 if (msm_port->is_uartdm < UARTDM_1P4)
324 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
325 else
326 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
327
328 return;
329
330rel_tx:
331 dma_release_channel(dma->chan);
332no_tx:
333 memset(dma, 0, sizeof(*dma));
334}
335
336static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
337{
338 struct device *dev = msm_port->uart.dev;
339 struct dma_slave_config conf;
340 struct msm_dma *dma;
341 u32 crci = 0;
342 int ret;
343
344 dma = &msm_port->rx_dma;
345
346 /* allocate DMA resources, if available */
347 dma->chan = dma_request_slave_channel_reason(dev, "rx");
348 if (IS_ERR(dma->chan))
349 goto no_rx;
350
351 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
352
353 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
354 if (!dma->virt)
355 goto rel_rx;
356
357 memset(&conf, 0, sizeof(conf));
358 conf.direction = DMA_DEV_TO_MEM;
359 conf.device_fc = true;
360 conf.src_addr = base + UARTDM_RF;
361 conf.src_maxburst = UARTDM_BURST_SIZE;
362 conf.slave_id = crci;
363
364 ret = dmaengine_slave_config(dma->chan, &conf);
365 if (ret)
366 goto err;
367
368 dma->dir = DMA_FROM_DEVICE;
369
370 if (msm_port->is_uartdm < UARTDM_1P4)
371 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
372 else
373 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
374
375 return;
376err:
377 kfree(dma->virt);
378rel_rx:
379 dma_release_channel(dma->chan);
380no_rx:
381 memset(dma, 0, sizeof(*dma));
382}
383
384static inline void msm_wait_for_xmitr(struct uart_port *port)
385{
386 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
387 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
388 break;
389 udelay(1);
390 }
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
392}
393
394static void msm_stop_tx(struct uart_port *port)
395{
396 struct msm_port *msm_port = UART_TO_MSM(port);
397
398 msm_port->imr &= ~UART_IMR_TXLEV;
399 msm_write(port, msm_port->imr, UART_IMR);
400}
401
402static void msm_start_tx(struct uart_port *port)
403{
404 struct msm_port *msm_port = UART_TO_MSM(port);
405 struct msm_dma *dma = &msm_port->tx_dma;
406
407 /* Already started in DMA mode */
408 if (dma->count)
409 return;
410
411 msm_port->imr |= UART_IMR_TXLEV;
412 msm_write(port, msm_port->imr, UART_IMR);
413}
414
415static void msm_reset_dm_count(struct uart_port *port, int count)
416{
417 msm_wait_for_xmitr(port);
418 msm_write(port, count, UARTDM_NCF_TX);
419 msm_read(port, UARTDM_NCF_TX);
420}
421
422static void msm_complete_tx_dma(void *args)
423{
424 struct msm_port *msm_port = args;
425 struct uart_port *port = &msm_port->uart;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct msm_dma *dma = &msm_port->tx_dma;
428 struct dma_tx_state state;
429 enum dma_status status;
430 unsigned long flags;
431 unsigned int count;
432 u32 val;
433
434 spin_lock_irqsave(&port->lock, flags);
435
436 /* Already stopped */
437 if (!dma->count)
438 goto done;
439
440 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
441
442 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
443
444 val = msm_read(port, UARTDM_DMEN);
445 val &= ~dma->enable_bit;
446 msm_write(port, val, UARTDM_DMEN);
447
448 if (msm_port->is_uartdm > UARTDM_1P3) {
449 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
450 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
451 }
452
453 count = dma->count - state.residue;
454 port->icount.tx += count;
455 dma->count = 0;
456
457 xmit->tail += count;
458 xmit->tail &= UART_XMIT_SIZE - 1;
459
460 /* Restore "Tx FIFO below watermark" interrupt */
461 msm_port->imr |= UART_IMR_TXLEV;
462 msm_write(port, msm_port->imr, UART_IMR);
463
464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
465 uart_write_wakeup(port);
466
467 msm_handle_tx(port);
468done:
469 spin_unlock_irqrestore(&port->lock, flags);
470}
471
472static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
473{
474 struct circ_buf *xmit = &msm_port->uart.state->xmit;
475 struct uart_port *port = &msm_port->uart;
476 struct msm_dma *dma = &msm_port->tx_dma;
477 void *cpu_addr;
478 int ret;
479 u32 val;
480
481 cpu_addr = &xmit->buf[xmit->tail];
482
483 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
484 ret = dma_mapping_error(port->dev, dma->phys);
485 if (ret)
486 return ret;
487
488 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
489 count, DMA_MEM_TO_DEV,
490 DMA_PREP_INTERRUPT |
491 DMA_PREP_FENCE);
492 if (!dma->desc) {
493 ret = -EIO;
494 goto unmap;
495 }
496
497 dma->desc->callback = msm_complete_tx_dma;
498 dma->desc->callback_param = msm_port;
499
500 dma->cookie = dmaengine_submit(dma->desc);
501 ret = dma_submit_error(dma->cookie);
502 if (ret)
503 goto unmap;
504
505 /*
506 * Using DMA complete for Tx FIFO reload, no need for
507 * "Tx FIFO below watermark" one, disable it
508 */
509 msm_port->imr &= ~UART_IMR_TXLEV;
510 msm_write(port, msm_port->imr, UART_IMR);
511
512 dma->count = count;
513
514 val = msm_read(port, UARTDM_DMEN);
515 val |= dma->enable_bit;
516
517 if (msm_port->is_uartdm < UARTDM_1P4)
518 msm_write(port, val, UARTDM_DMEN);
519
520 msm_reset_dm_count(port, count);
521
522 if (msm_port->is_uartdm > UARTDM_1P3)
523 msm_write(port, val, UARTDM_DMEN);
524
525 dma_async_issue_pending(dma->chan);
526 return 0;
527unmap:
528 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
529 return ret;
530}
531
532static void msm_complete_rx_dma(void *args)
533{
534 struct msm_port *msm_port = args;
535 struct uart_port *port = &msm_port->uart;
536 struct tty_port *tport = &port->state->port;
537 struct msm_dma *dma = &msm_port->rx_dma;
538 int count = 0, i, sysrq;
539 unsigned long flags;
540 u32 val;
541
542 spin_lock_irqsave(&port->lock, flags);
543
544 /* Already stopped */
545 if (!dma->count)
546 goto done;
547
548 val = msm_read(port, UARTDM_DMEN);
549 val &= ~dma->enable_bit;
550 msm_write(port, val, UARTDM_DMEN);
551
552 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
553 port->icount.overrun++;
554 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
555 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
556 }
557
558 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
559
560 port->icount.rx += count;
561
562 dma->count = 0;
563
564 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
565
566 for (i = 0; i < count; i++) {
567 char flag = TTY_NORMAL;
568
569 if (msm_port->break_detected && dma->virt[i] == 0) {
570 port->icount.brk++;
571 flag = TTY_BREAK;
572 msm_port->break_detected = false;
573 if (uart_handle_break(port))
574 continue;
575 }
576
577 if (!(port->read_status_mask & UART_SR_RX_BREAK))
578 flag = TTY_NORMAL;
579
580 spin_unlock_irqrestore(&port->lock, flags);
581 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
582 spin_lock_irqsave(&port->lock, flags);
583 if (!sysrq)
584 tty_insert_flip_char(tport, dma->virt[i], flag);
585 }
586
587 msm_start_rx_dma(msm_port);
588done:
589 spin_unlock_irqrestore(&port->lock, flags);
590
591 if (count)
592 tty_flip_buffer_push(tport);
593}
594
595static void msm_start_rx_dma(struct msm_port *msm_port)
596{
597 struct msm_dma *dma = &msm_port->rx_dma;
598 struct uart_port *uart = &msm_port->uart;
599 u32 val;
600 int ret;
601
602 if (!dma->chan)
603 return;
604
605 dma->phys = dma_map_single(uart->dev, dma->virt,
606 UARTDM_RX_SIZE, dma->dir);
607 ret = dma_mapping_error(uart->dev, dma->phys);
608 if (ret)
609 return;
610
611 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
612 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
613 DMA_PREP_INTERRUPT);
614 if (!dma->desc)
615 goto unmap;
616
617 dma->desc->callback = msm_complete_rx_dma;
618 dma->desc->callback_param = msm_port;
619
620 dma->cookie = dmaengine_submit(dma->desc);
621 ret = dma_submit_error(dma->cookie);
622 if (ret)
623 goto unmap;
624 /*
625 * Using DMA for FIFO off-load, no need for "Rx FIFO over
626 * watermark" or "stale" interrupts, disable them
627 */
628 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
629
630 /*
631 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
632 * we need RXSTALE to flush input DMA fifo to memory
633 */
634 if (msm_port->is_uartdm < UARTDM_1P4)
635 msm_port->imr |= UART_IMR_RXSTALE;
636
637 msm_write(uart, msm_port->imr, UART_IMR);
638
639 dma->count = UARTDM_RX_SIZE;
640
641 dma_async_issue_pending(dma->chan);
642
643 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
644 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
645
646 val = msm_read(uart, UARTDM_DMEN);
647 val |= dma->enable_bit;
648
649 if (msm_port->is_uartdm < UARTDM_1P4)
650 msm_write(uart, val, UARTDM_DMEN);
651
652 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
653
654 if (msm_port->is_uartdm > UARTDM_1P3)
655 msm_write(uart, val, UARTDM_DMEN);
656
657 return;
658unmap:
659 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
660}
661
662static void msm_stop_rx(struct uart_port *port)
663{
664 struct msm_port *msm_port = UART_TO_MSM(port);
665 struct msm_dma *dma = &msm_port->rx_dma;
666
667 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
668 msm_write(port, msm_port->imr, UART_IMR);
669
670 if (dma->chan)
671 msm_stop_dma(port, dma);
672}
673
674static void msm_enable_ms(struct uart_port *port)
675{
676 struct msm_port *msm_port = UART_TO_MSM(port);
677
678 msm_port->imr |= UART_IMR_DELTA_CTS;
679 msm_write(port, msm_port->imr, UART_IMR);
680}
681
682static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
683{
684 struct tty_port *tport = &port->state->port;
685 unsigned int sr;
686 int count = 0;
687 struct msm_port *msm_port = UART_TO_MSM(port);
688
689 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
690 port->icount.overrun++;
691 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
692 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
693 }
694
695 if (misr & UART_IMR_RXSTALE) {
696 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
697 msm_port->old_snap_state;
698 msm_port->old_snap_state = 0;
699 } else {
700 count = 4 * (msm_read(port, UART_RFWR));
701 msm_port->old_snap_state += count;
702 }
703
704 /* TODO: Precise error reporting */
705
706 port->icount.rx += count;
707
708 while (count > 0) {
709 unsigned char buf[4];
710 int sysrq, r_count, i;
711
712 sr = msm_read(port, UART_SR);
713 if ((sr & UART_SR_RX_READY) == 0) {
714 msm_port->old_snap_state -= count;
715 break;
716 }
717
718 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
719 r_count = min_t(int, count, sizeof(buf));
720
721 for (i = 0; i < r_count; i++) {
722 char flag = TTY_NORMAL;
723
724 if (msm_port->break_detected && buf[i] == 0) {
725 port->icount.brk++;
726 flag = TTY_BREAK;
727 msm_port->break_detected = false;
728 if (uart_handle_break(port))
729 continue;
730 }
731
732 if (!(port->read_status_mask & UART_SR_RX_BREAK))
733 flag = TTY_NORMAL;
734
735 spin_unlock(&port->lock);
736 sysrq = uart_handle_sysrq_char(port, buf[i]);
737 spin_lock(&port->lock);
738 if (!sysrq)
739 tty_insert_flip_char(tport, buf[i], flag);
740 }
741 count -= r_count;
742 }
743
744 spin_unlock(&port->lock);
745 tty_flip_buffer_push(tport);
746 spin_lock(&port->lock);
747
748 if (misr & (UART_IMR_RXSTALE))
749 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
750 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
751 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
752
753 /* Try to use DMA */
754 msm_start_rx_dma(msm_port);
755}
756
757static void msm_handle_rx(struct uart_port *port)
758{
759 struct tty_port *tport = &port->state->port;
760 unsigned int sr;
761
762 /*
763 * Handle overrun. My understanding of the hardware is that overrun
764 * is not tied to the RX buffer, so we handle the case out of band.
765 */
766 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
767 port->icount.overrun++;
768 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
769 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
770 }
771
772 /* and now the main RX loop */
773 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
774 unsigned int c;
775 char flag = TTY_NORMAL;
776 int sysrq;
777
778 c = msm_read(port, UART_RF);
779
780 if (sr & UART_SR_RX_BREAK) {
781 port->icount.brk++;
782 if (uart_handle_break(port))
783 continue;
784 } else if (sr & UART_SR_PAR_FRAME_ERR) {
785 port->icount.frame++;
786 } else {
787 port->icount.rx++;
788 }
789
790 /* Mask conditions we're ignorning. */
791 sr &= port->read_status_mask;
792
793 if (sr & UART_SR_RX_BREAK)
794 flag = TTY_BREAK;
795 else if (sr & UART_SR_PAR_FRAME_ERR)
796 flag = TTY_FRAME;
797
798 spin_unlock(&port->lock);
799 sysrq = uart_handle_sysrq_char(port, c);
800 spin_lock(&port->lock);
801 if (!sysrq)
802 tty_insert_flip_char(tport, c, flag);
803 }
804
805 spin_unlock(&port->lock);
806 tty_flip_buffer_push(tport);
807 spin_lock(&port->lock);
808}
809
810static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
811{
812 struct circ_buf *xmit = &port->state->xmit;
813 struct msm_port *msm_port = UART_TO_MSM(port);
814 unsigned int num_chars;
815 unsigned int tf_pointer = 0;
816 void __iomem *tf;
817
818 if (msm_port->is_uartdm)
819 tf = port->membase + UARTDM_TF;
820 else
821 tf = port->membase + UART_TF;
822
823 if (tx_count && msm_port->is_uartdm)
824 msm_reset_dm_count(port, tx_count);
825
826 while (tf_pointer < tx_count) {
827 int i;
828 char buf[4] = { 0 };
829
830 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
831 break;
832
833 if (msm_port->is_uartdm)
834 num_chars = min(tx_count - tf_pointer,
835 (unsigned int)sizeof(buf));
836 else
837 num_chars = 1;
838
839 for (i = 0; i < num_chars; i++) {
840 buf[i] = xmit->buf[xmit->tail + i];
841 port->icount.tx++;
842 }
843
844 iowrite32_rep(tf, buf, 1);
845 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
846 tf_pointer += num_chars;
847 }
848
849 /* disable tx interrupts if nothing more to send */
850 if (uart_circ_empty(xmit))
851 msm_stop_tx(port);
852
853 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
854 uart_write_wakeup(port);
855}
856
857static void msm_handle_tx(struct uart_port *port)
858{
859 struct msm_port *msm_port = UART_TO_MSM(port);
860 struct circ_buf *xmit = &msm_port->uart.state->xmit;
861 struct msm_dma *dma = &msm_port->tx_dma;
862 unsigned int pio_count, dma_count, dma_min;
863 void __iomem *tf;
864 int err = 0;
865
866 if (port->x_char) {
867 if (msm_port->is_uartdm)
868 tf = port->membase + UARTDM_TF;
869 else
870 tf = port->membase + UART_TF;
871
872 if (msm_port->is_uartdm)
873 msm_reset_dm_count(port, 1);
874
875 iowrite8_rep(tf, &port->x_char, 1);
876 port->icount.tx++;
877 port->x_char = 0;
878 return;
879 }
880
881 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
882 msm_stop_tx(port);
883 return;
884 }
885
886 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
887 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
888
889 dma_min = 1; /* Always DMA */
890 if (msm_port->is_uartdm > UARTDM_1P3) {
891 dma_count = UARTDM_TX_AIGN(dma_count);
892 dma_min = UARTDM_BURST_SIZE;
893 } else {
894 if (dma_count > UARTDM_TX_MAX)
895 dma_count = UARTDM_TX_MAX;
896 }
897
898 if (pio_count > port->fifosize)
899 pio_count = port->fifosize;
900
901 if (!dma->chan || dma_count < dma_min)
902 msm_handle_tx_pio(port, pio_count);
903 else
904 err = msm_handle_tx_dma(msm_port, dma_count);
905
906 if (err) /* fall back to PIO mode */
907 msm_handle_tx_pio(port, pio_count);
908}
909
910static void msm_handle_delta_cts(struct uart_port *port)
911{
912 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
913 port->icount.cts++;
914 wake_up_interruptible(&port->state->port.delta_msr_wait);
915}
916
917static irqreturn_t msm_uart_irq(int irq, void *dev_id)
918{
919 struct uart_port *port = dev_id;
920 struct msm_port *msm_port = UART_TO_MSM(port);
921 struct msm_dma *dma = &msm_port->rx_dma;
922 unsigned long flags;
923 unsigned int misr;
924 u32 val;
925
926 spin_lock_irqsave(&port->lock, flags);
927 misr = msm_read(port, UART_MISR);
928 msm_write(port, 0, UART_IMR); /* disable interrupt */
929
930 if (misr & UART_IMR_RXBREAK_START) {
931 msm_port->break_detected = true;
932 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
933 }
934
935 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
936 if (dma->count) {
937 val = UART_CR_CMD_STALE_EVENT_DISABLE;
938 msm_write(port, val, UART_CR);
939 val = UART_CR_CMD_RESET_STALE_INT;
940 msm_write(port, val, UART_CR);
941 /*
942 * Flush DMA input fifo to memory, this will also
943 * trigger DMA RX completion
944 */
945 dmaengine_terminate_all(dma->chan);
946 } else if (msm_port->is_uartdm) {
947 msm_handle_rx_dm(port, misr);
948 } else {
949 msm_handle_rx(port);
950 }
951 }
952 if (misr & UART_IMR_TXLEV)
953 msm_handle_tx(port);
954 if (misr & UART_IMR_DELTA_CTS)
955 msm_handle_delta_cts(port);
956
957 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
958 spin_unlock_irqrestore(&port->lock, flags);
959
960 return IRQ_HANDLED;
961}
962
963static unsigned int msm_tx_empty(struct uart_port *port)
964{
965 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
966}
967
968static unsigned int msm_get_mctrl(struct uart_port *port)
969{
970 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
971}
972
973static void msm_reset(struct uart_port *port)
974{
975 struct msm_port *msm_port = UART_TO_MSM(port);
976
977 /* reset everything */
978 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
979 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
980 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
981 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
982 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
983 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
984
985 /* Disable DM modes */
986 if (msm_port->is_uartdm)
987 msm_write(port, 0, UARTDM_DMEN);
988}
989
990static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
991{
992 unsigned int mr;
993
994 mr = msm_read(port, UART_MR1);
995
996 if (!(mctrl & TIOCM_RTS)) {
997 mr &= ~UART_MR1_RX_RDY_CTL;
998 msm_write(port, mr, UART_MR1);
999 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1000 } else {
1001 mr |= UART_MR1_RX_RDY_CTL;
1002 msm_write(port, mr, UART_MR1);
1003 }
1004}
1005
1006static void msm_break_ctl(struct uart_port *port, int break_ctl)
1007{
1008 if (break_ctl)
1009 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1010 else
1011 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1012}
1013
1014struct msm_baud_map {
1015 u16 divisor;
1016 u8 code;
1017 u8 rxstale;
1018};
1019
1020static const struct msm_baud_map *
1021msm_find_best_baud(struct uart_port *port, unsigned int baud,
1022 unsigned long *rate)
1023{
1024 struct msm_port *msm_port = UART_TO_MSM(port);
1025 unsigned int divisor, result;
1026 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1027 const struct msm_baud_map *entry, *end, *best;
1028 static const struct msm_baud_map table[] = {
1029 { 1, 0xff, 31 },
1030 { 2, 0xee, 16 },
1031 { 3, 0xdd, 8 },
1032 { 4, 0xcc, 6 },
1033 { 6, 0xbb, 6 },
1034 { 8, 0xaa, 6 },
1035 { 12, 0x99, 6 },
1036 { 16, 0x88, 1 },
1037 { 24, 0x77, 1 },
1038 { 32, 0x66, 1 },
1039 { 48, 0x55, 1 },
1040 { 96, 0x44, 1 },
1041 { 192, 0x33, 1 },
1042 { 384, 0x22, 1 },
1043 { 768, 0x11, 1 },
1044 { 1536, 0x00, 1 },
1045 };
1046
1047 best = table; /* Default to smallest divider */
1048 target = clk_round_rate(msm_port->clk, 16 * baud);
1049 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1050
1051 end = table + ARRAY_SIZE(table);
1052 entry = table;
1053 while (entry < end) {
1054 if (entry->divisor <= divisor) {
1055 result = target / entry->divisor / 16;
1056 diff = abs(result - baud);
1057
1058 /* Keep track of best entry */
1059 if (diff < best_diff) {
1060 best_diff = diff;
1061 best = entry;
1062 best_rate = target;
1063 }
1064
1065 if (result == baud)
1066 break;
1067 } else if (entry->divisor > divisor) {
1068 old = target;
1069 target = clk_round_rate(msm_port->clk, old + 1);
1070 /*
1071 * The rate didn't get any faster so we can't do
1072 * better at dividing it down
1073 */
1074 if (target == old)
1075 break;
1076
1077 /* Start the divisor search over at this new rate */
1078 entry = table;
1079 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1080 continue;
1081 }
1082 entry++;
1083 }
1084
1085 *rate = best_rate;
1086 return best;
1087}
1088
1089static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1090 unsigned long *saved_flags)
1091{
1092 unsigned int rxstale, watermark, mask;
1093 struct msm_port *msm_port = UART_TO_MSM(port);
1094 const struct msm_baud_map *entry;
1095 unsigned long flags, rate;
1096
1097 flags = *saved_flags;
1098 spin_unlock_irqrestore(&port->lock, flags);
1099
1100 entry = msm_find_best_baud(port, baud, &rate);
1101 clk_set_rate(msm_port->clk, rate);
1102 baud = rate / 16 / entry->divisor;
1103
1104 spin_lock_irqsave(&port->lock, flags);
1105 *saved_flags = flags;
1106 port->uartclk = rate;
1107
1108 msm_write(port, entry->code, UART_CSR);
1109
1110 /* RX stale watermark */
1111 rxstale = entry->rxstale;
1112 watermark = UART_IPR_STALE_LSB & rxstale;
1113 if (msm_port->is_uartdm) {
1114 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1115 } else {
1116 watermark |= UART_IPR_RXSTALE_LAST;
1117 mask = UART_IPR_STALE_TIMEOUT_MSB;
1118 }
1119
1120 watermark |= mask & (rxstale << 2);
1121
1122 msm_write(port, watermark, UART_IPR);
1123
1124 /* set RX watermark */
1125 watermark = (port->fifosize * 3) / 4;
1126 msm_write(port, watermark, UART_RFWR);
1127
1128 /* set TX watermark */
1129 msm_write(port, 10, UART_TFWR);
1130
1131 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1132 msm_reset(port);
1133
1134 /* Enable RX and TX */
1135 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1136
1137 /* turn on RX and CTS interrupts */
1138 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1139 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1140
1141 msm_write(port, msm_port->imr, UART_IMR);
1142
1143 if (msm_port->is_uartdm) {
1144 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1145 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1146 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1147 }
1148
1149 return baud;
1150}
1151
1152static void msm_init_clock(struct uart_port *port)
1153{
1154 struct msm_port *msm_port = UART_TO_MSM(port);
1155
1156 clk_prepare_enable(msm_port->clk);
1157 clk_prepare_enable(msm_port->pclk);
1158 msm_serial_set_mnd_regs(port);
1159}
1160
1161static int msm_startup(struct uart_port *port)
1162{
1163 struct msm_port *msm_port = UART_TO_MSM(port);
1164 unsigned int data, rfr_level, mask;
1165 int ret;
1166
1167 snprintf(msm_port->name, sizeof(msm_port->name),
1168 "msm_serial%d", port->line);
1169
1170 msm_init_clock(port);
1171
1172 if (likely(port->fifosize > 12))
1173 rfr_level = port->fifosize - 12;
1174 else
1175 rfr_level = port->fifosize;
1176
1177 /* set automatic RFR level */
1178 data = msm_read(port, UART_MR1);
1179
1180 if (msm_port->is_uartdm)
1181 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1182 else
1183 mask = UART_MR1_AUTO_RFR_LEVEL1;
1184
1185 data &= ~mask;
1186 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1187 data |= mask & (rfr_level << 2);
1188 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1189 msm_write(port, data, UART_MR1);
1190
1191 if (msm_port->is_uartdm) {
1192 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1193 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1194 }
1195
1196 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1197 msm_port->name, port);
1198 if (unlikely(ret))
1199 goto err_irq;
1200
1201 return 0;
1202
1203err_irq:
1204 if (msm_port->is_uartdm)
1205 msm_release_dma(msm_port);
1206
1207 clk_disable_unprepare(msm_port->pclk);
1208 clk_disable_unprepare(msm_port->clk);
1209
1210 return ret;
1211}
1212
1213static void msm_shutdown(struct uart_port *port)
1214{
1215 struct msm_port *msm_port = UART_TO_MSM(port);
1216
1217 msm_port->imr = 0;
1218 msm_write(port, 0, UART_IMR); /* disable interrupts */
1219
1220 if (msm_port->is_uartdm)
1221 msm_release_dma(msm_port);
1222
1223 clk_disable_unprepare(msm_port->clk);
1224
1225 free_irq(port->irq, port);
1226}
1227
1228static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1229 struct ktermios *old)
1230{
1231 struct msm_port *msm_port = UART_TO_MSM(port);
1232 struct msm_dma *dma = &msm_port->rx_dma;
1233 unsigned long flags;
1234 unsigned int baud, mr;
1235
1236 spin_lock_irqsave(&port->lock, flags);
1237
1238 if (dma->chan) /* Terminate if any */
1239 msm_stop_dma(port, dma);
1240
1241 /* calculate and set baud rate */
1242 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1243 baud = msm_set_baud_rate(port, baud, &flags);
1244 if (tty_termios_baud_rate(termios))
1245 tty_termios_encode_baud_rate(termios, baud, baud);
1246
1247 /* calculate parity */
1248 mr = msm_read(port, UART_MR2);
1249 mr &= ~UART_MR2_PARITY_MODE;
1250 if (termios->c_cflag & PARENB) {
1251 if (termios->c_cflag & PARODD)
1252 mr |= UART_MR2_PARITY_MODE_ODD;
1253 else if (termios->c_cflag & CMSPAR)
1254 mr |= UART_MR2_PARITY_MODE_SPACE;
1255 else
1256 mr |= UART_MR2_PARITY_MODE_EVEN;
1257 }
1258
1259 /* calculate bits per char */
1260 mr &= ~UART_MR2_BITS_PER_CHAR;
1261 switch (termios->c_cflag & CSIZE) {
1262 case CS5:
1263 mr |= UART_MR2_BITS_PER_CHAR_5;
1264 break;
1265 case CS6:
1266 mr |= UART_MR2_BITS_PER_CHAR_6;
1267 break;
1268 case CS7:
1269 mr |= UART_MR2_BITS_PER_CHAR_7;
1270 break;
1271 case CS8:
1272 default:
1273 mr |= UART_MR2_BITS_PER_CHAR_8;
1274 break;
1275 }
1276
1277 /* calculate stop bits */
1278 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1279 if (termios->c_cflag & CSTOPB)
1280 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1281 else
1282 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1283
1284 /* set parity, bits per char, and stop bit */
1285 msm_write(port, mr, UART_MR2);
1286
1287 /* calculate and set hardware flow control */
1288 mr = msm_read(port, UART_MR1);
1289 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1290 if (termios->c_cflag & CRTSCTS) {
1291 mr |= UART_MR1_CTS_CTL;
1292 mr |= UART_MR1_RX_RDY_CTL;
1293 }
1294 msm_write(port, mr, UART_MR1);
1295
1296 /* Configure status bits to ignore based on termio flags. */
1297 port->read_status_mask = 0;
1298 if (termios->c_iflag & INPCK)
1299 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1300 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1301 port->read_status_mask |= UART_SR_RX_BREAK;
1302
1303 uart_update_timeout(port, termios->c_cflag, baud);
1304
1305 /* Try to use DMA */
1306 msm_start_rx_dma(msm_port);
1307
1308 spin_unlock_irqrestore(&port->lock, flags);
1309}
1310
1311static const char *msm_type(struct uart_port *port)
1312{
1313 return "MSM";
1314}
1315
1316static void msm_release_port(struct uart_port *port)
1317{
1318 struct platform_device *pdev = to_platform_device(port->dev);
1319 struct resource *uart_resource;
1320 resource_size_t size;
1321
1322 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1323 if (unlikely(!uart_resource))
1324 return;
1325 size = resource_size(uart_resource);
1326
1327 release_mem_region(port->mapbase, size);
1328 iounmap(port->membase);
1329 port->membase = NULL;
1330}
1331
1332static int msm_request_port(struct uart_port *port)
1333{
1334 struct platform_device *pdev = to_platform_device(port->dev);
1335 struct resource *uart_resource;
1336 resource_size_t size;
1337 int ret;
1338
1339 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1340 if (unlikely(!uart_resource))
1341 return -ENXIO;
1342
1343 size = resource_size(uart_resource);
1344
1345 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1346 return -EBUSY;
1347
1348 port->membase = ioremap(port->mapbase, size);
1349 if (!port->membase) {
1350 ret = -EBUSY;
1351 goto fail_release_port;
1352 }
1353
1354 return 0;
1355
1356fail_release_port:
1357 release_mem_region(port->mapbase, size);
1358 return ret;
1359}
1360
1361static void msm_config_port(struct uart_port *port, int flags)
1362{
1363 int ret;
1364
1365 if (flags & UART_CONFIG_TYPE) {
1366 port->type = PORT_MSM;
1367 ret = msm_request_port(port);
1368 if (ret)
1369 return;
1370 }
1371}
1372
1373static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1374{
1375 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1376 return -EINVAL;
1377 if (unlikely(port->irq != ser->irq))
1378 return -EINVAL;
1379 return 0;
1380}
1381
1382static void msm_power(struct uart_port *port, unsigned int state,
1383 unsigned int oldstate)
1384{
1385 struct msm_port *msm_port = UART_TO_MSM(port);
1386
1387 switch (state) {
1388 case 0:
1389 clk_prepare_enable(msm_port->clk);
1390 clk_prepare_enable(msm_port->pclk);
1391 break;
1392 case 3:
1393 clk_disable_unprepare(msm_port->clk);
1394 clk_disable_unprepare(msm_port->pclk);
1395 break;
1396 default:
1397 pr_err("msm_serial: Unknown PM state %d\n", state);
1398 }
1399}
1400
1401#ifdef CONFIG_CONSOLE_POLL
1402static int msm_poll_get_char_single(struct uart_port *port)
1403{
1404 struct msm_port *msm_port = UART_TO_MSM(port);
1405 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1406
1407 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1408 return NO_POLL_CHAR;
1409
1410 return msm_read(port, rf_reg) & 0xff;
1411}
1412
1413static int msm_poll_get_char_dm(struct uart_port *port)
1414{
1415 int c;
1416 static u32 slop;
1417 static int count;
1418 unsigned char *sp = (unsigned char *)&slop;
1419
1420 /* Check if a previous read had more than one char */
1421 if (count) {
1422 c = sp[sizeof(slop) - count];
1423 count--;
1424 /* Or if FIFO is empty */
1425 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1426 /*
1427 * If RX packing buffer has less than a word, force stale to
1428 * push contents into RX FIFO
1429 */
1430 count = msm_read(port, UARTDM_RXFS);
1431 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1432 if (count) {
1433 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1434 slop = msm_read(port, UARTDM_RF);
1435 c = sp[0];
1436 count--;
1437 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1438 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1439 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1440 UART_CR);
1441 } else {
1442 c = NO_POLL_CHAR;
1443 }
1444 /* FIFO has a word */
1445 } else {
1446 slop = msm_read(port, UARTDM_RF);
1447 c = sp[0];
1448 count = sizeof(slop) - 1;
1449 }
1450
1451 return c;
1452}
1453
1454static int msm_poll_get_char(struct uart_port *port)
1455{
1456 u32 imr;
1457 int c;
1458 struct msm_port *msm_port = UART_TO_MSM(port);
1459
1460 /* Disable all interrupts */
1461 imr = msm_read(port, UART_IMR);
1462 msm_write(port, 0, UART_IMR);
1463
1464 if (msm_port->is_uartdm)
1465 c = msm_poll_get_char_dm(port);
1466 else
1467 c = msm_poll_get_char_single(port);
1468
1469 /* Enable interrupts */
1470 msm_write(port, imr, UART_IMR);
1471
1472 return c;
1473}
1474
1475static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1476{
1477 u32 imr;
1478 struct msm_port *msm_port = UART_TO_MSM(port);
1479
1480 /* Disable all interrupts */
1481 imr = msm_read(port, UART_IMR);
1482 msm_write(port, 0, UART_IMR);
1483
1484 if (msm_port->is_uartdm)
1485 msm_reset_dm_count(port, 1);
1486
1487 /* Wait until FIFO is empty */
1488 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1489 cpu_relax();
1490
1491 /* Write a character */
1492 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1493
1494 /* Wait until FIFO is empty */
1495 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1496 cpu_relax();
1497
1498 /* Enable interrupts */
1499 msm_write(port, imr, UART_IMR);
1500}
1501#endif
1502
1503static struct uart_ops msm_uart_pops = {
1504 .tx_empty = msm_tx_empty,
1505 .set_mctrl = msm_set_mctrl,
1506 .get_mctrl = msm_get_mctrl,
1507 .stop_tx = msm_stop_tx,
1508 .start_tx = msm_start_tx,
1509 .stop_rx = msm_stop_rx,
1510 .enable_ms = msm_enable_ms,
1511 .break_ctl = msm_break_ctl,
1512 .startup = msm_startup,
1513 .shutdown = msm_shutdown,
1514 .set_termios = msm_set_termios,
1515 .type = msm_type,
1516 .release_port = msm_release_port,
1517 .request_port = msm_request_port,
1518 .config_port = msm_config_port,
1519 .verify_port = msm_verify_port,
1520 .pm = msm_power,
1521#ifdef CONFIG_CONSOLE_POLL
1522 .poll_get_char = msm_poll_get_char,
1523 .poll_put_char = msm_poll_put_char,
1524#endif
1525};
1526
1527static struct msm_port msm_uart_ports[] = {
1528 {
1529 .uart = {
1530 .iotype = UPIO_MEM,
1531 .ops = &msm_uart_pops,
1532 .flags = UPF_BOOT_AUTOCONF,
1533 .fifosize = 64,
1534 .line = 0,
1535 },
1536 },
1537 {
1538 .uart = {
1539 .iotype = UPIO_MEM,
1540 .ops = &msm_uart_pops,
1541 .flags = UPF_BOOT_AUTOCONF,
1542 .fifosize = 64,
1543 .line = 1,
1544 },
1545 },
1546 {
1547 .uart = {
1548 .iotype = UPIO_MEM,
1549 .ops = &msm_uart_pops,
1550 .flags = UPF_BOOT_AUTOCONF,
1551 .fifosize = 64,
1552 .line = 2,
1553 },
1554 },
1555};
1556
1557#define UART_NR ARRAY_SIZE(msm_uart_ports)
1558
1559static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1560{
1561 return &msm_uart_ports[line].uart;
1562}
1563
1564#ifdef CONFIG_SERIAL_MSM_CONSOLE
1565static void __msm_console_write(struct uart_port *port, const char *s,
1566 unsigned int count, bool is_uartdm)
1567{
1568 int i;
1569 int num_newlines = 0;
1570 bool replaced = false;
1571 void __iomem *tf;
1572
1573 if (is_uartdm)
1574 tf = port->membase + UARTDM_TF;
1575 else
1576 tf = port->membase + UART_TF;
1577
1578 /* Account for newlines that will get a carriage return added */
1579 for (i = 0; i < count; i++)
1580 if (s[i] == '\n')
1581 num_newlines++;
1582 count += num_newlines;
1583
1584 spin_lock(&port->lock);
1585 if (is_uartdm)
1586 msm_reset_dm_count(port, count);
1587
1588 i = 0;
1589 while (i < count) {
1590 int j;
1591 unsigned int num_chars;
1592 char buf[4] = { 0 };
1593
1594 if (is_uartdm)
1595 num_chars = min(count - i, (unsigned int)sizeof(buf));
1596 else
1597 num_chars = 1;
1598
1599 for (j = 0; j < num_chars; j++) {
1600 char c = *s;
1601
1602 if (c == '\n' && !replaced) {
1603 buf[j] = '\r';
1604 j++;
1605 replaced = true;
1606 }
1607 if (j < num_chars) {
1608 buf[j] = c;
1609 s++;
1610 replaced = false;
1611 }
1612 }
1613
1614 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1615 cpu_relax();
1616
1617 iowrite32_rep(tf, buf, 1);
1618 i += num_chars;
1619 }
1620 spin_unlock(&port->lock);
1621}
1622
1623static void msm_console_write(struct console *co, const char *s,
1624 unsigned int count)
1625{
1626 struct uart_port *port;
1627 struct msm_port *msm_port;
1628
1629 BUG_ON(co->index < 0 || co->index >= UART_NR);
1630
1631 port = msm_get_port_from_line(co->index);
1632 msm_port = UART_TO_MSM(port);
1633
1634 __msm_console_write(port, s, count, msm_port->is_uartdm);
1635}
1636
1637static int __init msm_console_setup(struct console *co, char *options)
1638{
1639 struct uart_port *port;
1640 int baud = 115200;
1641 int bits = 8;
1642 int parity = 'n';
1643 int flow = 'n';
1644
1645 if (unlikely(co->index >= UART_NR || co->index < 0))
1646 return -ENXIO;
1647
1648 port = msm_get_port_from_line(co->index);
1649
1650 if (unlikely(!port->membase))
1651 return -ENXIO;
1652
1653 msm_init_clock(port);
1654
1655 if (options)
1656 uart_parse_options(options, &baud, &parity, &bits, &flow);
1657
1658 pr_info("msm_serial: console setup on port #%d\n", port->line);
1659
1660 return uart_set_options(port, co, baud, parity, bits, flow);
1661}
1662
1663static void
1664msm_serial_early_write(struct console *con, const char *s, unsigned n)
1665{
1666 struct earlycon_device *dev = con->data;
1667
1668 __msm_console_write(&dev->port, s, n, false);
1669}
1670
1671static int __init
1672msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1673{
1674 if (!device->port.membase)
1675 return -ENODEV;
1676
1677 device->con->write = msm_serial_early_write;
1678 return 0;
1679}
1680OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1681 msm_serial_early_console_setup);
1682
1683static void
1684msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1685{
1686 struct earlycon_device *dev = con->data;
1687
1688 __msm_console_write(&dev->port, s, n, true);
1689}
1690
1691static int __init
1692msm_serial_early_console_setup_dm(struct earlycon_device *device,
1693 const char *opt)
1694{
1695 if (!device->port.membase)
1696 return -ENODEV;
1697
1698 device->con->write = msm_serial_early_write_dm;
1699 return 0;
1700}
1701OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1702 msm_serial_early_console_setup_dm);
1703
1704static struct uart_driver msm_uart_driver;
1705
1706static struct console msm_console = {
1707 .name = "ttyMSM",
1708 .write = msm_console_write,
1709 .device = uart_console_device,
1710 .setup = msm_console_setup,
1711 .flags = CON_PRINTBUFFER,
1712 .index = -1,
1713 .data = &msm_uart_driver,
1714};
1715
1716#define MSM_CONSOLE (&msm_console)
1717
1718#else
1719#define MSM_CONSOLE NULL
1720#endif
1721
1722static struct uart_driver msm_uart_driver = {
1723 .owner = THIS_MODULE,
1724 .driver_name = "msm_serial",
1725 .dev_name = "ttyMSM",
1726 .nr = UART_NR,
1727 .cons = MSM_CONSOLE,
1728};
1729
1730static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1731
1732static const struct of_device_id msm_uartdm_table[] = {
1733 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1734 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1735 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1736 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1737 { }
1738};
1739
1740static int msm_serial_probe(struct platform_device *pdev)
1741{
1742 struct msm_port *msm_port;
1743 struct resource *resource;
1744 struct uart_port *port;
1745 const struct of_device_id *id;
1746 int irq, line;
1747
1748 if (pdev->dev.of_node)
1749 line = of_alias_get_id(pdev->dev.of_node, "serial");
1750 else
1751 line = pdev->id;
1752
1753 if (line < 0)
1754 line = atomic_inc_return(&msm_uart_next_id) - 1;
1755
1756 if (unlikely(line < 0 || line >= UART_NR))
1757 return -ENXIO;
1758
1759 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1760
1761 port = msm_get_port_from_line(line);
1762 port->dev = &pdev->dev;
1763 msm_port = UART_TO_MSM(port);
1764
1765 id = of_match_device(msm_uartdm_table, &pdev->dev);
1766 if (id)
1767 msm_port->is_uartdm = (unsigned long)id->data;
1768 else
1769 msm_port->is_uartdm = 0;
1770
1771 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1772 if (IS_ERR(msm_port->clk))
1773 return PTR_ERR(msm_port->clk);
1774
1775 if (msm_port->is_uartdm) {
1776 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1777 if (IS_ERR(msm_port->pclk))
1778 return PTR_ERR(msm_port->pclk);
1779 }
1780
1781 port->uartclk = clk_get_rate(msm_port->clk);
1782 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1783
1784 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1785 if (unlikely(!resource))
1786 return -ENXIO;
1787 port->mapbase = resource->start;
1788
1789 irq = platform_get_irq(pdev, 0);
1790 if (unlikely(irq < 0))
1791 return -ENXIO;
1792 port->irq = irq;
1793
1794 platform_set_drvdata(pdev, port);
1795
1796 return uart_add_one_port(&msm_uart_driver, port);
1797}
1798
1799static int msm_serial_remove(struct platform_device *pdev)
1800{
1801 struct uart_port *port = platform_get_drvdata(pdev);
1802
1803 uart_remove_one_port(&msm_uart_driver, port);
1804
1805 return 0;
1806}
1807
1808static const struct of_device_id msm_match_table[] = {
1809 { .compatible = "qcom,msm-uart" },
1810 { .compatible = "qcom,msm-uartdm" },
1811 {}
1812};
1813MODULE_DEVICE_TABLE(of, msm_match_table);
1814
1815static struct platform_driver msm_platform_driver = {
1816 .remove = msm_serial_remove,
1817 .probe = msm_serial_probe,
1818 .driver = {
1819 .name = "msm_serial",
1820 .of_match_table = msm_match_table,
1821 },
1822};
1823
1824static int __init msm_serial_init(void)
1825{
1826 int ret;
1827
1828 ret = uart_register_driver(&msm_uart_driver);
1829 if (unlikely(ret))
1830 return ret;
1831
1832 ret = platform_driver_register(&msm_platform_driver);
1833 if (unlikely(ret))
1834 uart_unregister_driver(&msm_uart_driver);
1835
1836 pr_info("msm_serial: driver initialized\n");
1837
1838 return ret;
1839}
1840
1841static void __exit msm_serial_exit(void)
1842{
1843 platform_driver_unregister(&msm_platform_driver);
1844 uart_unregister_driver(&msm_uart_driver);
1845}
1846
1847module_init(msm_serial_init);
1848module_exit(msm_serial_exit);
1849
1850MODULE_AUTHOR("Robert Love <rlove@google.com>");
1851MODULE_DESCRIPTION("Driver for msm7x serial device");
1852MODULE_LICENSE("GPL");
1/*
2 * Driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
22#include <linux/kernel.h>
23#include <linux/atomic.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/module.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_core.h>
35#include <linux/slab.h>
36#include <linux/clk.h>
37#include <linux/platform_device.h>
38#include <linux/delay.h>
39#include <linux/of.h>
40#include <linux/of_device.h>
41#include <linux/wait.h>
42
43#define UART_MR1 0x0000
44
45#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
46#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
47#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
48#define UART_MR1_RX_RDY_CTL BIT(7)
49#define UART_MR1_CTS_CTL BIT(6)
50
51#define UART_MR2 0x0004
52#define UART_MR2_ERROR_MODE BIT(6)
53#define UART_MR2_BITS_PER_CHAR 0x30
54#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
55#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
56#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
57#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
58#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
59#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
60#define UART_MR2_PARITY_MODE_NONE 0x0
61#define UART_MR2_PARITY_MODE_ODD 0x1
62#define UART_MR2_PARITY_MODE_EVEN 0x2
63#define UART_MR2_PARITY_MODE_SPACE 0x3
64#define UART_MR2_PARITY_MODE 0x3
65
66#define UART_CSR 0x0008
67
68#define UART_TF 0x000C
69#define UARTDM_TF 0x0070
70
71#define UART_CR 0x0010
72#define UART_CR_CMD_NULL (0 << 4)
73#define UART_CR_CMD_RESET_RX (1 << 4)
74#define UART_CR_CMD_RESET_TX (2 << 4)
75#define UART_CR_CMD_RESET_ERR (3 << 4)
76#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
77#define UART_CR_CMD_START_BREAK (5 << 4)
78#define UART_CR_CMD_STOP_BREAK (6 << 4)
79#define UART_CR_CMD_RESET_CTS (7 << 4)
80#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
81#define UART_CR_CMD_PACKET_MODE (9 << 4)
82#define UART_CR_CMD_MODE_RESET (12 << 4)
83#define UART_CR_CMD_SET_RFR (13 << 4)
84#define UART_CR_CMD_RESET_RFR (14 << 4)
85#define UART_CR_CMD_PROTECTION_EN (16 << 4)
86#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
87#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
88#define UART_CR_CMD_FORCE_STALE (4 << 8)
89#define UART_CR_CMD_RESET_TX_READY (3 << 8)
90#define UART_CR_TX_DISABLE BIT(3)
91#define UART_CR_TX_ENABLE BIT(2)
92#define UART_CR_RX_DISABLE BIT(1)
93#define UART_CR_RX_ENABLE BIT(0)
94#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
95
96#define UART_IMR 0x0014
97#define UART_IMR_TXLEV BIT(0)
98#define UART_IMR_RXSTALE BIT(3)
99#define UART_IMR_RXLEV BIT(4)
100#define UART_IMR_DELTA_CTS BIT(5)
101#define UART_IMR_CURRENT_CTS BIT(6)
102#define UART_IMR_RXBREAK_START BIT(10)
103
104#define UART_IPR_RXSTALE_LAST 0x20
105#define UART_IPR_STALE_LSB 0x1F
106#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
107#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
108
109#define UART_IPR 0x0018
110#define UART_TFWR 0x001C
111#define UART_RFWR 0x0020
112#define UART_HCR 0x0024
113
114#define UART_MREG 0x0028
115#define UART_NREG 0x002C
116#define UART_DREG 0x0030
117#define UART_MNDREG 0x0034
118#define UART_IRDA 0x0038
119#define UART_MISR_MODE 0x0040
120#define UART_MISR_RESET 0x0044
121#define UART_MISR_EXPORT 0x0048
122#define UART_MISR_VAL 0x004C
123#define UART_TEST_CTRL 0x0050
124
125#define UART_SR 0x0008
126#define UART_SR_HUNT_CHAR BIT(7)
127#define UART_SR_RX_BREAK BIT(6)
128#define UART_SR_PAR_FRAME_ERR BIT(5)
129#define UART_SR_OVERRUN BIT(4)
130#define UART_SR_TX_EMPTY BIT(3)
131#define UART_SR_TX_READY BIT(2)
132#define UART_SR_RX_FULL BIT(1)
133#define UART_SR_RX_READY BIT(0)
134
135#define UART_RF 0x000C
136#define UARTDM_RF 0x0070
137#define UART_MISR 0x0010
138#define UART_ISR 0x0014
139#define UART_ISR_TX_READY BIT(7)
140
141#define UARTDM_RXFS 0x50
142#define UARTDM_RXFS_BUF_SHIFT 0x7
143#define UARTDM_RXFS_BUF_MASK 0x7
144
145#define UARTDM_DMEN 0x3C
146#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
147#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
148
149#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
150#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
151
152#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
153#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
154
155#define UARTDM_DMRX 0x34
156#define UARTDM_NCF_TX 0x40
157#define UARTDM_RX_TOTAL_SNAP 0x38
158
159#define UARTDM_BURST_SIZE 16 /* in bytes */
160#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
161#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
162#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
163
164enum {
165 UARTDM_1P1 = 1,
166 UARTDM_1P2,
167 UARTDM_1P3,
168 UARTDM_1P4,
169};
170
171struct msm_dma {
172 struct dma_chan *chan;
173 enum dma_data_direction dir;
174 dma_addr_t phys;
175 unsigned char *virt;
176 dma_cookie_t cookie;
177 u32 enable_bit;
178 unsigned int count;
179 struct dma_async_tx_descriptor *desc;
180};
181
182struct msm_port {
183 struct uart_port uart;
184 char name[16];
185 struct clk *clk;
186 struct clk *pclk;
187 unsigned int imr;
188 int is_uartdm;
189 unsigned int old_snap_state;
190 bool break_detected;
191 struct msm_dma tx_dma;
192 struct msm_dma rx_dma;
193};
194
195#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
196
197static
198void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
199{
200 writel_relaxed(val, port->membase + off);
201}
202
203static
204unsigned int msm_read(struct uart_port *port, unsigned int off)
205{
206 return readl_relaxed(port->membase + off);
207}
208
209/*
210 * Setup the MND registers to use the TCXO clock.
211 */
212static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
213{
214 msm_write(port, 0x06, UART_MREG);
215 msm_write(port, 0xF1, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x1A, UART_MNDREG);
218 port->uartclk = 1843200;
219}
220
221/*
222 * Setup the MND registers to use the TCXO clock divided by 4.
223 */
224static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
225{
226 msm_write(port, 0x18, UART_MREG);
227 msm_write(port, 0xF6, UART_NREG);
228 msm_write(port, 0x0F, UART_DREG);
229 msm_write(port, 0x0A, UART_MNDREG);
230 port->uartclk = 1843200;
231}
232
233static void msm_serial_set_mnd_regs(struct uart_port *port)
234{
235 struct msm_port *msm_port = UART_TO_MSM(port);
236
237 /*
238 * These registers don't exist so we change the clk input rate
239 * on uartdm hardware instead
240 */
241 if (msm_port->is_uartdm)
242 return;
243
244 if (port->uartclk == 19200000)
245 msm_serial_set_mnd_regs_tcxo(port);
246 else if (port->uartclk == 4800000)
247 msm_serial_set_mnd_regs_tcxoby4(port);
248}
249
250static void msm_handle_tx(struct uart_port *port);
251static void msm_start_rx_dma(struct msm_port *msm_port);
252
253static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
254{
255 struct device *dev = port->dev;
256 unsigned int mapped;
257 u32 val;
258
259 mapped = dma->count;
260 dma->count = 0;
261
262 dmaengine_terminate_all(dma->chan);
263
264 /*
265 * DMA Stall happens if enqueue and flush command happens concurrently.
266 * For example before changing the baud rate/protocol configuration and
267 * sending flush command to ADM, disable the channel of UARTDM.
268 * Note: should not reset the receiver here immediately as it is not
269 * suggested to do disable/reset or reset/disable at the same time.
270 */
271 val = msm_read(port, UARTDM_DMEN);
272 val &= ~dma->enable_bit;
273 msm_write(port, val, UARTDM_DMEN);
274
275 if (mapped)
276 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
277}
278
279static void msm_release_dma(struct msm_port *msm_port)
280{
281 struct msm_dma *dma;
282
283 dma = &msm_port->tx_dma;
284 if (dma->chan) {
285 msm_stop_dma(&msm_port->uart, dma);
286 dma_release_channel(dma->chan);
287 }
288
289 memset(dma, 0, sizeof(*dma));
290
291 dma = &msm_port->rx_dma;
292 if (dma->chan) {
293 msm_stop_dma(&msm_port->uart, dma);
294 dma_release_channel(dma->chan);
295 kfree(dma->virt);
296 }
297
298 memset(dma, 0, sizeof(*dma));
299}
300
301static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
302{
303 struct device *dev = msm_port->uart.dev;
304 struct dma_slave_config conf;
305 struct msm_dma *dma;
306 u32 crci = 0;
307 int ret;
308
309 dma = &msm_port->tx_dma;
310
311 /* allocate DMA resources, if available */
312 dma->chan = dma_request_slave_channel_reason(dev, "tx");
313 if (IS_ERR(dma->chan))
314 goto no_tx;
315
316 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
317
318 memset(&conf, 0, sizeof(conf));
319 conf.direction = DMA_MEM_TO_DEV;
320 conf.device_fc = true;
321 conf.dst_addr = base + UARTDM_TF;
322 conf.dst_maxburst = UARTDM_BURST_SIZE;
323 conf.slave_id = crci;
324
325 ret = dmaengine_slave_config(dma->chan, &conf);
326 if (ret)
327 goto rel_tx;
328
329 dma->dir = DMA_TO_DEVICE;
330
331 if (msm_port->is_uartdm < UARTDM_1P4)
332 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
333 else
334 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
335
336 return;
337
338rel_tx:
339 dma_release_channel(dma->chan);
340no_tx:
341 memset(dma, 0, sizeof(*dma));
342}
343
344static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
345{
346 struct device *dev = msm_port->uart.dev;
347 struct dma_slave_config conf;
348 struct msm_dma *dma;
349 u32 crci = 0;
350 int ret;
351
352 dma = &msm_port->rx_dma;
353
354 /* allocate DMA resources, if available */
355 dma->chan = dma_request_slave_channel_reason(dev, "rx");
356 if (IS_ERR(dma->chan))
357 goto no_rx;
358
359 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
360
361 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
362 if (!dma->virt)
363 goto rel_rx;
364
365 memset(&conf, 0, sizeof(conf));
366 conf.direction = DMA_DEV_TO_MEM;
367 conf.device_fc = true;
368 conf.src_addr = base + UARTDM_RF;
369 conf.src_maxburst = UARTDM_BURST_SIZE;
370 conf.slave_id = crci;
371
372 ret = dmaengine_slave_config(dma->chan, &conf);
373 if (ret)
374 goto err;
375
376 dma->dir = DMA_FROM_DEVICE;
377
378 if (msm_port->is_uartdm < UARTDM_1P4)
379 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
380 else
381 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
382
383 return;
384err:
385 kfree(dma->virt);
386rel_rx:
387 dma_release_channel(dma->chan);
388no_rx:
389 memset(dma, 0, sizeof(*dma));
390}
391
392static inline void msm_wait_for_xmitr(struct uart_port *port)
393{
394 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
395 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
396 break;
397 udelay(1);
398 }
399 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
400}
401
402static void msm_stop_tx(struct uart_port *port)
403{
404 struct msm_port *msm_port = UART_TO_MSM(port);
405
406 msm_port->imr &= ~UART_IMR_TXLEV;
407 msm_write(port, msm_port->imr, UART_IMR);
408}
409
410static void msm_start_tx(struct uart_port *port)
411{
412 struct msm_port *msm_port = UART_TO_MSM(port);
413 struct msm_dma *dma = &msm_port->tx_dma;
414
415 /* Already started in DMA mode */
416 if (dma->count)
417 return;
418
419 msm_port->imr |= UART_IMR_TXLEV;
420 msm_write(port, msm_port->imr, UART_IMR);
421}
422
423static void msm_reset_dm_count(struct uart_port *port, int count)
424{
425 msm_wait_for_xmitr(port);
426 msm_write(port, count, UARTDM_NCF_TX);
427 msm_read(port, UARTDM_NCF_TX);
428}
429
430static void msm_complete_tx_dma(void *args)
431{
432 struct msm_port *msm_port = args;
433 struct uart_port *port = &msm_port->uart;
434 struct circ_buf *xmit = &port->state->xmit;
435 struct msm_dma *dma = &msm_port->tx_dma;
436 struct dma_tx_state state;
437 enum dma_status status;
438 unsigned long flags;
439 unsigned int count;
440 u32 val;
441
442 spin_lock_irqsave(&port->lock, flags);
443
444 /* Already stopped */
445 if (!dma->count)
446 goto done;
447
448 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
449
450 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
451
452 val = msm_read(port, UARTDM_DMEN);
453 val &= ~dma->enable_bit;
454 msm_write(port, val, UARTDM_DMEN);
455
456 if (msm_port->is_uartdm > UARTDM_1P3) {
457 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
458 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
459 }
460
461 count = dma->count - state.residue;
462 port->icount.tx += count;
463 dma->count = 0;
464
465 xmit->tail += count;
466 xmit->tail &= UART_XMIT_SIZE - 1;
467
468 /* Restore "Tx FIFO below watermark" interrupt */
469 msm_port->imr |= UART_IMR_TXLEV;
470 msm_write(port, msm_port->imr, UART_IMR);
471
472 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
473 uart_write_wakeup(port);
474
475 msm_handle_tx(port);
476done:
477 spin_unlock_irqrestore(&port->lock, flags);
478}
479
480static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
481{
482 struct circ_buf *xmit = &msm_port->uart.state->xmit;
483 struct uart_port *port = &msm_port->uart;
484 struct msm_dma *dma = &msm_port->tx_dma;
485 void *cpu_addr;
486 int ret;
487 u32 val;
488
489 cpu_addr = &xmit->buf[xmit->tail];
490
491 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
492 ret = dma_mapping_error(port->dev, dma->phys);
493 if (ret)
494 return ret;
495
496 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
497 count, DMA_MEM_TO_DEV,
498 DMA_PREP_INTERRUPT |
499 DMA_PREP_FENCE);
500 if (!dma->desc) {
501 ret = -EIO;
502 goto unmap;
503 }
504
505 dma->desc->callback = msm_complete_tx_dma;
506 dma->desc->callback_param = msm_port;
507
508 dma->cookie = dmaengine_submit(dma->desc);
509 ret = dma_submit_error(dma->cookie);
510 if (ret)
511 goto unmap;
512
513 /*
514 * Using DMA complete for Tx FIFO reload, no need for
515 * "Tx FIFO below watermark" one, disable it
516 */
517 msm_port->imr &= ~UART_IMR_TXLEV;
518 msm_write(port, msm_port->imr, UART_IMR);
519
520 dma->count = count;
521
522 val = msm_read(port, UARTDM_DMEN);
523 val |= dma->enable_bit;
524
525 if (msm_port->is_uartdm < UARTDM_1P4)
526 msm_write(port, val, UARTDM_DMEN);
527
528 msm_reset_dm_count(port, count);
529
530 if (msm_port->is_uartdm > UARTDM_1P3)
531 msm_write(port, val, UARTDM_DMEN);
532
533 dma_async_issue_pending(dma->chan);
534 return 0;
535unmap:
536 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
537 return ret;
538}
539
540static void msm_complete_rx_dma(void *args)
541{
542 struct msm_port *msm_port = args;
543 struct uart_port *port = &msm_port->uart;
544 struct tty_port *tport = &port->state->port;
545 struct msm_dma *dma = &msm_port->rx_dma;
546 int count = 0, i, sysrq;
547 unsigned long flags;
548 u32 val;
549
550 spin_lock_irqsave(&port->lock, flags);
551
552 /* Already stopped */
553 if (!dma->count)
554 goto done;
555
556 val = msm_read(port, UARTDM_DMEN);
557 val &= ~dma->enable_bit;
558 msm_write(port, val, UARTDM_DMEN);
559
560 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
561 port->icount.overrun++;
562 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
563 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
564 }
565
566 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
567
568 port->icount.rx += count;
569
570 dma->count = 0;
571
572 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
573
574 for (i = 0; i < count; i++) {
575 char flag = TTY_NORMAL;
576
577 if (msm_port->break_detected && dma->virt[i] == 0) {
578 port->icount.brk++;
579 flag = TTY_BREAK;
580 msm_port->break_detected = false;
581 if (uart_handle_break(port))
582 continue;
583 }
584
585 if (!(port->read_status_mask & UART_SR_RX_BREAK))
586 flag = TTY_NORMAL;
587
588 spin_unlock_irqrestore(&port->lock, flags);
589 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
590 spin_lock_irqsave(&port->lock, flags);
591 if (!sysrq)
592 tty_insert_flip_char(tport, dma->virt[i], flag);
593 }
594
595 msm_start_rx_dma(msm_port);
596done:
597 spin_unlock_irqrestore(&port->lock, flags);
598
599 if (count)
600 tty_flip_buffer_push(tport);
601}
602
603static void msm_start_rx_dma(struct msm_port *msm_port)
604{
605 struct msm_dma *dma = &msm_port->rx_dma;
606 struct uart_port *uart = &msm_port->uart;
607 u32 val;
608 int ret;
609
610 if (!dma->chan)
611 return;
612
613 dma->phys = dma_map_single(uart->dev, dma->virt,
614 UARTDM_RX_SIZE, dma->dir);
615 ret = dma_mapping_error(uart->dev, dma->phys);
616 if (ret)
617 return;
618
619 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
620 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
621 DMA_PREP_INTERRUPT);
622 if (!dma->desc)
623 goto unmap;
624
625 dma->desc->callback = msm_complete_rx_dma;
626 dma->desc->callback_param = msm_port;
627
628 dma->cookie = dmaengine_submit(dma->desc);
629 ret = dma_submit_error(dma->cookie);
630 if (ret)
631 goto unmap;
632 /*
633 * Using DMA for FIFO off-load, no need for "Rx FIFO over
634 * watermark" or "stale" interrupts, disable them
635 */
636 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
637
638 /*
639 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
640 * we need RXSTALE to flush input DMA fifo to memory
641 */
642 if (msm_port->is_uartdm < UARTDM_1P4)
643 msm_port->imr |= UART_IMR_RXSTALE;
644
645 msm_write(uart, msm_port->imr, UART_IMR);
646
647 dma->count = UARTDM_RX_SIZE;
648
649 dma_async_issue_pending(dma->chan);
650
651 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
652 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
653
654 val = msm_read(uart, UARTDM_DMEN);
655 val |= dma->enable_bit;
656
657 if (msm_port->is_uartdm < UARTDM_1P4)
658 msm_write(uart, val, UARTDM_DMEN);
659
660 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
661
662 if (msm_port->is_uartdm > UARTDM_1P3)
663 msm_write(uart, val, UARTDM_DMEN);
664
665 return;
666unmap:
667 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
668}
669
670static void msm_stop_rx(struct uart_port *port)
671{
672 struct msm_port *msm_port = UART_TO_MSM(port);
673 struct msm_dma *dma = &msm_port->rx_dma;
674
675 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
676 msm_write(port, msm_port->imr, UART_IMR);
677
678 if (dma->chan)
679 msm_stop_dma(port, dma);
680}
681
682static void msm_enable_ms(struct uart_port *port)
683{
684 struct msm_port *msm_port = UART_TO_MSM(port);
685
686 msm_port->imr |= UART_IMR_DELTA_CTS;
687 msm_write(port, msm_port->imr, UART_IMR);
688}
689
690static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
691{
692 struct tty_port *tport = &port->state->port;
693 unsigned int sr;
694 int count = 0;
695 struct msm_port *msm_port = UART_TO_MSM(port);
696
697 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
698 port->icount.overrun++;
699 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
700 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
701 }
702
703 if (misr & UART_IMR_RXSTALE) {
704 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
705 msm_port->old_snap_state;
706 msm_port->old_snap_state = 0;
707 } else {
708 count = 4 * (msm_read(port, UART_RFWR));
709 msm_port->old_snap_state += count;
710 }
711
712 /* TODO: Precise error reporting */
713
714 port->icount.rx += count;
715
716 while (count > 0) {
717 unsigned char buf[4];
718 int sysrq, r_count, i;
719
720 sr = msm_read(port, UART_SR);
721 if ((sr & UART_SR_RX_READY) == 0) {
722 msm_port->old_snap_state -= count;
723 break;
724 }
725
726 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
727 r_count = min_t(int, count, sizeof(buf));
728
729 for (i = 0; i < r_count; i++) {
730 char flag = TTY_NORMAL;
731
732 if (msm_port->break_detected && buf[i] == 0) {
733 port->icount.brk++;
734 flag = TTY_BREAK;
735 msm_port->break_detected = false;
736 if (uart_handle_break(port))
737 continue;
738 }
739
740 if (!(port->read_status_mask & UART_SR_RX_BREAK))
741 flag = TTY_NORMAL;
742
743 spin_unlock(&port->lock);
744 sysrq = uart_handle_sysrq_char(port, buf[i]);
745 spin_lock(&port->lock);
746 if (!sysrq)
747 tty_insert_flip_char(tport, buf[i], flag);
748 }
749 count -= r_count;
750 }
751
752 spin_unlock(&port->lock);
753 tty_flip_buffer_push(tport);
754 spin_lock(&port->lock);
755
756 if (misr & (UART_IMR_RXSTALE))
757 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
758 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
759 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
760
761 /* Try to use DMA */
762 msm_start_rx_dma(msm_port);
763}
764
765static void msm_handle_rx(struct uart_port *port)
766{
767 struct tty_port *tport = &port->state->port;
768 unsigned int sr;
769
770 /*
771 * Handle overrun. My understanding of the hardware is that overrun
772 * is not tied to the RX buffer, so we handle the case out of band.
773 */
774 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
775 port->icount.overrun++;
776 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
777 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
778 }
779
780 /* and now the main RX loop */
781 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
782 unsigned int c;
783 char flag = TTY_NORMAL;
784 int sysrq;
785
786 c = msm_read(port, UART_RF);
787
788 if (sr & UART_SR_RX_BREAK) {
789 port->icount.brk++;
790 if (uart_handle_break(port))
791 continue;
792 } else if (sr & UART_SR_PAR_FRAME_ERR) {
793 port->icount.frame++;
794 } else {
795 port->icount.rx++;
796 }
797
798 /* Mask conditions we're ignorning. */
799 sr &= port->read_status_mask;
800
801 if (sr & UART_SR_RX_BREAK)
802 flag = TTY_BREAK;
803 else if (sr & UART_SR_PAR_FRAME_ERR)
804 flag = TTY_FRAME;
805
806 spin_unlock(&port->lock);
807 sysrq = uart_handle_sysrq_char(port, c);
808 spin_lock(&port->lock);
809 if (!sysrq)
810 tty_insert_flip_char(tport, c, flag);
811 }
812
813 spin_unlock(&port->lock);
814 tty_flip_buffer_push(tport);
815 spin_lock(&port->lock);
816}
817
818static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
819{
820 struct circ_buf *xmit = &port->state->xmit;
821 struct msm_port *msm_port = UART_TO_MSM(port);
822 unsigned int num_chars;
823 unsigned int tf_pointer = 0;
824 void __iomem *tf;
825
826 if (msm_port->is_uartdm)
827 tf = port->membase + UARTDM_TF;
828 else
829 tf = port->membase + UART_TF;
830
831 if (tx_count && msm_port->is_uartdm)
832 msm_reset_dm_count(port, tx_count);
833
834 while (tf_pointer < tx_count) {
835 int i;
836 char buf[4] = { 0 };
837
838 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
839 break;
840
841 if (msm_port->is_uartdm)
842 num_chars = min(tx_count - tf_pointer,
843 (unsigned int)sizeof(buf));
844 else
845 num_chars = 1;
846
847 for (i = 0; i < num_chars; i++) {
848 buf[i] = xmit->buf[xmit->tail + i];
849 port->icount.tx++;
850 }
851
852 iowrite32_rep(tf, buf, 1);
853 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
854 tf_pointer += num_chars;
855 }
856
857 /* disable tx interrupts if nothing more to send */
858 if (uart_circ_empty(xmit))
859 msm_stop_tx(port);
860
861 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
862 uart_write_wakeup(port);
863}
864
865static void msm_handle_tx(struct uart_port *port)
866{
867 struct msm_port *msm_port = UART_TO_MSM(port);
868 struct circ_buf *xmit = &msm_port->uart.state->xmit;
869 struct msm_dma *dma = &msm_port->tx_dma;
870 unsigned int pio_count, dma_count, dma_min;
871 void __iomem *tf;
872 int err = 0;
873
874 if (port->x_char) {
875 if (msm_port->is_uartdm)
876 tf = port->membase + UARTDM_TF;
877 else
878 tf = port->membase + UART_TF;
879
880 if (msm_port->is_uartdm)
881 msm_reset_dm_count(port, 1);
882
883 iowrite8_rep(tf, &port->x_char, 1);
884 port->icount.tx++;
885 port->x_char = 0;
886 return;
887 }
888
889 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
890 msm_stop_tx(port);
891 return;
892 }
893
894 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
895 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
896
897 dma_min = 1; /* Always DMA */
898 if (msm_port->is_uartdm > UARTDM_1P3) {
899 dma_count = UARTDM_TX_AIGN(dma_count);
900 dma_min = UARTDM_BURST_SIZE;
901 } else {
902 if (dma_count > UARTDM_TX_MAX)
903 dma_count = UARTDM_TX_MAX;
904 }
905
906 if (pio_count > port->fifosize)
907 pio_count = port->fifosize;
908
909 if (!dma->chan || dma_count < dma_min)
910 msm_handle_tx_pio(port, pio_count);
911 else
912 err = msm_handle_tx_dma(msm_port, dma_count);
913
914 if (err) /* fall back to PIO mode */
915 msm_handle_tx_pio(port, pio_count);
916}
917
918static void msm_handle_delta_cts(struct uart_port *port)
919{
920 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
921 port->icount.cts++;
922 wake_up_interruptible(&port->state->port.delta_msr_wait);
923}
924
925static irqreturn_t msm_uart_irq(int irq, void *dev_id)
926{
927 struct uart_port *port = dev_id;
928 struct msm_port *msm_port = UART_TO_MSM(port);
929 struct msm_dma *dma = &msm_port->rx_dma;
930 unsigned long flags;
931 unsigned int misr;
932 u32 val;
933
934 spin_lock_irqsave(&port->lock, flags);
935 misr = msm_read(port, UART_MISR);
936 msm_write(port, 0, UART_IMR); /* disable interrupt */
937
938 if (misr & UART_IMR_RXBREAK_START) {
939 msm_port->break_detected = true;
940 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
941 }
942
943 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
944 if (dma->count) {
945 val = UART_CR_CMD_STALE_EVENT_DISABLE;
946 msm_write(port, val, UART_CR);
947 val = UART_CR_CMD_RESET_STALE_INT;
948 msm_write(port, val, UART_CR);
949 /*
950 * Flush DMA input fifo to memory, this will also
951 * trigger DMA RX completion
952 */
953 dmaengine_terminate_all(dma->chan);
954 } else if (msm_port->is_uartdm) {
955 msm_handle_rx_dm(port, misr);
956 } else {
957 msm_handle_rx(port);
958 }
959 }
960 if (misr & UART_IMR_TXLEV)
961 msm_handle_tx(port);
962 if (misr & UART_IMR_DELTA_CTS)
963 msm_handle_delta_cts(port);
964
965 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
966 spin_unlock_irqrestore(&port->lock, flags);
967
968 return IRQ_HANDLED;
969}
970
971static unsigned int msm_tx_empty(struct uart_port *port)
972{
973 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
974}
975
976static unsigned int msm_get_mctrl(struct uart_port *port)
977{
978 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
979}
980
981static void msm_reset(struct uart_port *port)
982{
983 struct msm_port *msm_port = UART_TO_MSM(port);
984
985 /* reset everything */
986 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
987 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
988 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
989 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
990 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
991 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
992
993 /* Disable DM modes */
994 if (msm_port->is_uartdm)
995 msm_write(port, 0, UARTDM_DMEN);
996}
997
998static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
999{
1000 unsigned int mr;
1001
1002 mr = msm_read(port, UART_MR1);
1003
1004 if (!(mctrl & TIOCM_RTS)) {
1005 mr &= ~UART_MR1_RX_RDY_CTL;
1006 msm_write(port, mr, UART_MR1);
1007 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1008 } else {
1009 mr |= UART_MR1_RX_RDY_CTL;
1010 msm_write(port, mr, UART_MR1);
1011 }
1012}
1013
1014static void msm_break_ctl(struct uart_port *port, int break_ctl)
1015{
1016 if (break_ctl)
1017 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1018 else
1019 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1020}
1021
1022struct msm_baud_map {
1023 u16 divisor;
1024 u8 code;
1025 u8 rxstale;
1026};
1027
1028static const struct msm_baud_map *
1029msm_find_best_baud(struct uart_port *port, unsigned int baud,
1030 unsigned long *rate)
1031{
1032 struct msm_port *msm_port = UART_TO_MSM(port);
1033 unsigned int divisor, result;
1034 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1035 const struct msm_baud_map *entry, *end, *best;
1036 static const struct msm_baud_map table[] = {
1037 { 1, 0xff, 31 },
1038 { 2, 0xee, 16 },
1039 { 3, 0xdd, 8 },
1040 { 4, 0xcc, 6 },
1041 { 6, 0xbb, 6 },
1042 { 8, 0xaa, 6 },
1043 { 12, 0x99, 6 },
1044 { 16, 0x88, 1 },
1045 { 24, 0x77, 1 },
1046 { 32, 0x66, 1 },
1047 { 48, 0x55, 1 },
1048 { 96, 0x44, 1 },
1049 { 192, 0x33, 1 },
1050 { 384, 0x22, 1 },
1051 { 768, 0x11, 1 },
1052 { 1536, 0x00, 1 },
1053 };
1054
1055 best = table; /* Default to smallest divider */
1056 target = clk_round_rate(msm_port->clk, 16 * baud);
1057 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1058
1059 end = table + ARRAY_SIZE(table);
1060 entry = table;
1061 while (entry < end) {
1062 if (entry->divisor <= divisor) {
1063 result = target / entry->divisor / 16;
1064 diff = abs(result - baud);
1065
1066 /* Keep track of best entry */
1067 if (diff < best_diff) {
1068 best_diff = diff;
1069 best = entry;
1070 best_rate = target;
1071 }
1072
1073 if (result == baud)
1074 break;
1075 } else if (entry->divisor > divisor) {
1076 old = target;
1077 target = clk_round_rate(msm_port->clk, old + 1);
1078 /*
1079 * The rate didn't get any faster so we can't do
1080 * better at dividing it down
1081 */
1082 if (target == old)
1083 break;
1084
1085 /* Start the divisor search over at this new rate */
1086 entry = table;
1087 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1088 continue;
1089 }
1090 entry++;
1091 }
1092
1093 *rate = best_rate;
1094 return best;
1095}
1096
1097static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1098 unsigned long *saved_flags)
1099{
1100 unsigned int rxstale, watermark, mask;
1101 struct msm_port *msm_port = UART_TO_MSM(port);
1102 const struct msm_baud_map *entry;
1103 unsigned long flags, rate;
1104
1105 flags = *saved_flags;
1106 spin_unlock_irqrestore(&port->lock, flags);
1107
1108 entry = msm_find_best_baud(port, baud, &rate);
1109 clk_set_rate(msm_port->clk, rate);
1110 baud = rate / 16 / entry->divisor;
1111
1112 spin_lock_irqsave(&port->lock, flags);
1113 *saved_flags = flags;
1114 port->uartclk = rate;
1115
1116 msm_write(port, entry->code, UART_CSR);
1117
1118 /* RX stale watermark */
1119 rxstale = entry->rxstale;
1120 watermark = UART_IPR_STALE_LSB & rxstale;
1121 if (msm_port->is_uartdm) {
1122 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1123 } else {
1124 watermark |= UART_IPR_RXSTALE_LAST;
1125 mask = UART_IPR_STALE_TIMEOUT_MSB;
1126 }
1127
1128 watermark |= mask & (rxstale << 2);
1129
1130 msm_write(port, watermark, UART_IPR);
1131
1132 /* set RX watermark */
1133 watermark = (port->fifosize * 3) / 4;
1134 msm_write(port, watermark, UART_RFWR);
1135
1136 /* set TX watermark */
1137 msm_write(port, 10, UART_TFWR);
1138
1139 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1140 msm_reset(port);
1141
1142 /* Enable RX and TX */
1143 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1144
1145 /* turn on RX and CTS interrupts */
1146 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1147 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1148
1149 msm_write(port, msm_port->imr, UART_IMR);
1150
1151 if (msm_port->is_uartdm) {
1152 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1153 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1154 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1155 }
1156
1157 return baud;
1158}
1159
1160static void msm_init_clock(struct uart_port *port)
1161{
1162 struct msm_port *msm_port = UART_TO_MSM(port);
1163
1164 clk_prepare_enable(msm_port->clk);
1165 clk_prepare_enable(msm_port->pclk);
1166 msm_serial_set_mnd_regs(port);
1167}
1168
1169static int msm_startup(struct uart_port *port)
1170{
1171 struct msm_port *msm_port = UART_TO_MSM(port);
1172 unsigned int data, rfr_level, mask;
1173 int ret;
1174
1175 snprintf(msm_port->name, sizeof(msm_port->name),
1176 "msm_serial%d", port->line);
1177
1178 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1179 msm_port->name, port);
1180 if (unlikely(ret))
1181 return ret;
1182
1183 msm_init_clock(port);
1184
1185 if (likely(port->fifosize > 12))
1186 rfr_level = port->fifosize - 12;
1187 else
1188 rfr_level = port->fifosize;
1189
1190 /* set automatic RFR level */
1191 data = msm_read(port, UART_MR1);
1192
1193 if (msm_port->is_uartdm)
1194 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1195 else
1196 mask = UART_MR1_AUTO_RFR_LEVEL1;
1197
1198 data &= ~mask;
1199 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1200 data |= mask & (rfr_level << 2);
1201 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1202 msm_write(port, data, UART_MR1);
1203
1204 if (msm_port->is_uartdm) {
1205 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1206 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1207 }
1208
1209 return 0;
1210}
1211
1212static void msm_shutdown(struct uart_port *port)
1213{
1214 struct msm_port *msm_port = UART_TO_MSM(port);
1215
1216 msm_port->imr = 0;
1217 msm_write(port, 0, UART_IMR); /* disable interrupts */
1218
1219 if (msm_port->is_uartdm)
1220 msm_release_dma(msm_port);
1221
1222 clk_disable_unprepare(msm_port->clk);
1223
1224 free_irq(port->irq, port);
1225}
1226
1227static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1228 struct ktermios *old)
1229{
1230 struct msm_port *msm_port = UART_TO_MSM(port);
1231 struct msm_dma *dma = &msm_port->rx_dma;
1232 unsigned long flags;
1233 unsigned int baud, mr;
1234
1235 spin_lock_irqsave(&port->lock, flags);
1236
1237 if (dma->chan) /* Terminate if any */
1238 msm_stop_dma(port, dma);
1239
1240 /* calculate and set baud rate */
1241 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1242 baud = msm_set_baud_rate(port, baud, &flags);
1243 if (tty_termios_baud_rate(termios))
1244 tty_termios_encode_baud_rate(termios, baud, baud);
1245
1246 /* calculate parity */
1247 mr = msm_read(port, UART_MR2);
1248 mr &= ~UART_MR2_PARITY_MODE;
1249 if (termios->c_cflag & PARENB) {
1250 if (termios->c_cflag & PARODD)
1251 mr |= UART_MR2_PARITY_MODE_ODD;
1252 else if (termios->c_cflag & CMSPAR)
1253 mr |= UART_MR2_PARITY_MODE_SPACE;
1254 else
1255 mr |= UART_MR2_PARITY_MODE_EVEN;
1256 }
1257
1258 /* calculate bits per char */
1259 mr &= ~UART_MR2_BITS_PER_CHAR;
1260 switch (termios->c_cflag & CSIZE) {
1261 case CS5:
1262 mr |= UART_MR2_BITS_PER_CHAR_5;
1263 break;
1264 case CS6:
1265 mr |= UART_MR2_BITS_PER_CHAR_6;
1266 break;
1267 case CS7:
1268 mr |= UART_MR2_BITS_PER_CHAR_7;
1269 break;
1270 case CS8:
1271 default:
1272 mr |= UART_MR2_BITS_PER_CHAR_8;
1273 break;
1274 }
1275
1276 /* calculate stop bits */
1277 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1278 if (termios->c_cflag & CSTOPB)
1279 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1280 else
1281 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1282
1283 /* set parity, bits per char, and stop bit */
1284 msm_write(port, mr, UART_MR2);
1285
1286 /* calculate and set hardware flow control */
1287 mr = msm_read(port, UART_MR1);
1288 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1289 if (termios->c_cflag & CRTSCTS) {
1290 mr |= UART_MR1_CTS_CTL;
1291 mr |= UART_MR1_RX_RDY_CTL;
1292 }
1293 msm_write(port, mr, UART_MR1);
1294
1295 /* Configure status bits to ignore based on termio flags. */
1296 port->read_status_mask = 0;
1297 if (termios->c_iflag & INPCK)
1298 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1299 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1300 port->read_status_mask |= UART_SR_RX_BREAK;
1301
1302 uart_update_timeout(port, termios->c_cflag, baud);
1303
1304 /* Try to use DMA */
1305 msm_start_rx_dma(msm_port);
1306
1307 spin_unlock_irqrestore(&port->lock, flags);
1308}
1309
1310static const char *msm_type(struct uart_port *port)
1311{
1312 return "MSM";
1313}
1314
1315static void msm_release_port(struct uart_port *port)
1316{
1317 struct platform_device *pdev = to_platform_device(port->dev);
1318 struct resource *uart_resource;
1319 resource_size_t size;
1320
1321 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322 if (unlikely(!uart_resource))
1323 return;
1324 size = resource_size(uart_resource);
1325
1326 release_mem_region(port->mapbase, size);
1327 iounmap(port->membase);
1328 port->membase = NULL;
1329}
1330
1331static int msm_request_port(struct uart_port *port)
1332{
1333 struct platform_device *pdev = to_platform_device(port->dev);
1334 struct resource *uart_resource;
1335 resource_size_t size;
1336 int ret;
1337
1338 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339 if (unlikely(!uart_resource))
1340 return -ENXIO;
1341
1342 size = resource_size(uart_resource);
1343
1344 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1345 return -EBUSY;
1346
1347 port->membase = ioremap(port->mapbase, size);
1348 if (!port->membase) {
1349 ret = -EBUSY;
1350 goto fail_release_port;
1351 }
1352
1353 return 0;
1354
1355fail_release_port:
1356 release_mem_region(port->mapbase, size);
1357 return ret;
1358}
1359
1360static void msm_config_port(struct uart_port *port, int flags)
1361{
1362 int ret;
1363
1364 if (flags & UART_CONFIG_TYPE) {
1365 port->type = PORT_MSM;
1366 ret = msm_request_port(port);
1367 if (ret)
1368 return;
1369 }
1370}
1371
1372static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1373{
1374 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1375 return -EINVAL;
1376 if (unlikely(port->irq != ser->irq))
1377 return -EINVAL;
1378 return 0;
1379}
1380
1381static void msm_power(struct uart_port *port, unsigned int state,
1382 unsigned int oldstate)
1383{
1384 struct msm_port *msm_port = UART_TO_MSM(port);
1385
1386 switch (state) {
1387 case 0:
1388 clk_prepare_enable(msm_port->clk);
1389 clk_prepare_enable(msm_port->pclk);
1390 break;
1391 case 3:
1392 clk_disable_unprepare(msm_port->clk);
1393 clk_disable_unprepare(msm_port->pclk);
1394 break;
1395 default:
1396 pr_err("msm_serial: Unknown PM state %d\n", state);
1397 }
1398}
1399
1400#ifdef CONFIG_CONSOLE_POLL
1401static int msm_poll_get_char_single(struct uart_port *port)
1402{
1403 struct msm_port *msm_port = UART_TO_MSM(port);
1404 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1405
1406 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1407 return NO_POLL_CHAR;
1408
1409 return msm_read(port, rf_reg) & 0xff;
1410}
1411
1412static int msm_poll_get_char_dm(struct uart_port *port)
1413{
1414 int c;
1415 static u32 slop;
1416 static int count;
1417 unsigned char *sp = (unsigned char *)&slop;
1418
1419 /* Check if a previous read had more than one char */
1420 if (count) {
1421 c = sp[sizeof(slop) - count];
1422 count--;
1423 /* Or if FIFO is empty */
1424 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1425 /*
1426 * If RX packing buffer has less than a word, force stale to
1427 * push contents into RX FIFO
1428 */
1429 count = msm_read(port, UARTDM_RXFS);
1430 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1431 if (count) {
1432 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1433 slop = msm_read(port, UARTDM_RF);
1434 c = sp[0];
1435 count--;
1436 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1437 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1438 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1439 UART_CR);
1440 } else {
1441 c = NO_POLL_CHAR;
1442 }
1443 /* FIFO has a word */
1444 } else {
1445 slop = msm_read(port, UARTDM_RF);
1446 c = sp[0];
1447 count = sizeof(slop) - 1;
1448 }
1449
1450 return c;
1451}
1452
1453static int msm_poll_get_char(struct uart_port *port)
1454{
1455 u32 imr;
1456 int c;
1457 struct msm_port *msm_port = UART_TO_MSM(port);
1458
1459 /* Disable all interrupts */
1460 imr = msm_read(port, UART_IMR);
1461 msm_write(port, 0, UART_IMR);
1462
1463 if (msm_port->is_uartdm)
1464 c = msm_poll_get_char_dm(port);
1465 else
1466 c = msm_poll_get_char_single(port);
1467
1468 /* Enable interrupts */
1469 msm_write(port, imr, UART_IMR);
1470
1471 return c;
1472}
1473
1474static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1475{
1476 u32 imr;
1477 struct msm_port *msm_port = UART_TO_MSM(port);
1478
1479 /* Disable all interrupts */
1480 imr = msm_read(port, UART_IMR);
1481 msm_write(port, 0, UART_IMR);
1482
1483 if (msm_port->is_uartdm)
1484 msm_reset_dm_count(port, 1);
1485
1486 /* Wait until FIFO is empty */
1487 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1488 cpu_relax();
1489
1490 /* Write a character */
1491 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1492
1493 /* Wait until FIFO is empty */
1494 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1495 cpu_relax();
1496
1497 /* Enable interrupts */
1498 msm_write(port, imr, UART_IMR);
1499}
1500#endif
1501
1502static struct uart_ops msm_uart_pops = {
1503 .tx_empty = msm_tx_empty,
1504 .set_mctrl = msm_set_mctrl,
1505 .get_mctrl = msm_get_mctrl,
1506 .stop_tx = msm_stop_tx,
1507 .start_tx = msm_start_tx,
1508 .stop_rx = msm_stop_rx,
1509 .enable_ms = msm_enable_ms,
1510 .break_ctl = msm_break_ctl,
1511 .startup = msm_startup,
1512 .shutdown = msm_shutdown,
1513 .set_termios = msm_set_termios,
1514 .type = msm_type,
1515 .release_port = msm_release_port,
1516 .request_port = msm_request_port,
1517 .config_port = msm_config_port,
1518 .verify_port = msm_verify_port,
1519 .pm = msm_power,
1520#ifdef CONFIG_CONSOLE_POLL
1521 .poll_get_char = msm_poll_get_char,
1522 .poll_put_char = msm_poll_put_char,
1523#endif
1524};
1525
1526static struct msm_port msm_uart_ports[] = {
1527 {
1528 .uart = {
1529 .iotype = UPIO_MEM,
1530 .ops = &msm_uart_pops,
1531 .flags = UPF_BOOT_AUTOCONF,
1532 .fifosize = 64,
1533 .line = 0,
1534 },
1535 },
1536 {
1537 .uart = {
1538 .iotype = UPIO_MEM,
1539 .ops = &msm_uart_pops,
1540 .flags = UPF_BOOT_AUTOCONF,
1541 .fifosize = 64,
1542 .line = 1,
1543 },
1544 },
1545 {
1546 .uart = {
1547 .iotype = UPIO_MEM,
1548 .ops = &msm_uart_pops,
1549 .flags = UPF_BOOT_AUTOCONF,
1550 .fifosize = 64,
1551 .line = 2,
1552 },
1553 },
1554};
1555
1556#define UART_NR ARRAY_SIZE(msm_uart_ports)
1557
1558static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1559{
1560 return &msm_uart_ports[line].uart;
1561}
1562
1563#ifdef CONFIG_SERIAL_MSM_CONSOLE
1564static void __msm_console_write(struct uart_port *port, const char *s,
1565 unsigned int count, bool is_uartdm)
1566{
1567 int i;
1568 int num_newlines = 0;
1569 bool replaced = false;
1570 void __iomem *tf;
1571
1572 if (is_uartdm)
1573 tf = port->membase + UARTDM_TF;
1574 else
1575 tf = port->membase + UART_TF;
1576
1577 /* Account for newlines that will get a carriage return added */
1578 for (i = 0; i < count; i++)
1579 if (s[i] == '\n')
1580 num_newlines++;
1581 count += num_newlines;
1582
1583 spin_lock(&port->lock);
1584 if (is_uartdm)
1585 msm_reset_dm_count(port, count);
1586
1587 i = 0;
1588 while (i < count) {
1589 int j;
1590 unsigned int num_chars;
1591 char buf[4] = { 0 };
1592
1593 if (is_uartdm)
1594 num_chars = min(count - i, (unsigned int)sizeof(buf));
1595 else
1596 num_chars = 1;
1597
1598 for (j = 0; j < num_chars; j++) {
1599 char c = *s;
1600
1601 if (c == '\n' && !replaced) {
1602 buf[j] = '\r';
1603 j++;
1604 replaced = true;
1605 }
1606 if (j < num_chars) {
1607 buf[j] = c;
1608 s++;
1609 replaced = false;
1610 }
1611 }
1612
1613 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1614 cpu_relax();
1615
1616 iowrite32_rep(tf, buf, 1);
1617 i += num_chars;
1618 }
1619 spin_unlock(&port->lock);
1620}
1621
1622static void msm_console_write(struct console *co, const char *s,
1623 unsigned int count)
1624{
1625 struct uart_port *port;
1626 struct msm_port *msm_port;
1627
1628 BUG_ON(co->index < 0 || co->index >= UART_NR);
1629
1630 port = msm_get_port_from_line(co->index);
1631 msm_port = UART_TO_MSM(port);
1632
1633 __msm_console_write(port, s, count, msm_port->is_uartdm);
1634}
1635
1636static int __init msm_console_setup(struct console *co, char *options)
1637{
1638 struct uart_port *port;
1639 int baud = 115200;
1640 int bits = 8;
1641 int parity = 'n';
1642 int flow = 'n';
1643
1644 if (unlikely(co->index >= UART_NR || co->index < 0))
1645 return -ENXIO;
1646
1647 port = msm_get_port_from_line(co->index);
1648
1649 if (unlikely(!port->membase))
1650 return -ENXIO;
1651
1652 msm_init_clock(port);
1653
1654 if (options)
1655 uart_parse_options(options, &baud, &parity, &bits, &flow);
1656
1657 pr_info("msm_serial: console setup on port #%d\n", port->line);
1658
1659 return uart_set_options(port, co, baud, parity, bits, flow);
1660}
1661
1662static void
1663msm_serial_early_write(struct console *con, const char *s, unsigned n)
1664{
1665 struct earlycon_device *dev = con->data;
1666
1667 __msm_console_write(&dev->port, s, n, false);
1668}
1669
1670static int __init
1671msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1672{
1673 if (!device->port.membase)
1674 return -ENODEV;
1675
1676 device->con->write = msm_serial_early_write;
1677 return 0;
1678}
1679OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1680 msm_serial_early_console_setup);
1681
1682static void
1683msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1684{
1685 struct earlycon_device *dev = con->data;
1686
1687 __msm_console_write(&dev->port, s, n, true);
1688}
1689
1690static int __init
1691msm_serial_early_console_setup_dm(struct earlycon_device *device,
1692 const char *opt)
1693{
1694 if (!device->port.membase)
1695 return -ENODEV;
1696
1697 device->con->write = msm_serial_early_write_dm;
1698 return 0;
1699}
1700OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1701 msm_serial_early_console_setup_dm);
1702
1703static struct uart_driver msm_uart_driver;
1704
1705static struct console msm_console = {
1706 .name = "ttyMSM",
1707 .write = msm_console_write,
1708 .device = uart_console_device,
1709 .setup = msm_console_setup,
1710 .flags = CON_PRINTBUFFER,
1711 .index = -1,
1712 .data = &msm_uart_driver,
1713};
1714
1715#define MSM_CONSOLE (&msm_console)
1716
1717#else
1718#define MSM_CONSOLE NULL
1719#endif
1720
1721static struct uart_driver msm_uart_driver = {
1722 .owner = THIS_MODULE,
1723 .driver_name = "msm_serial",
1724 .dev_name = "ttyMSM",
1725 .nr = UART_NR,
1726 .cons = MSM_CONSOLE,
1727};
1728
1729static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1730
1731static const struct of_device_id msm_uartdm_table[] = {
1732 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1733 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1734 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1735 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1736 { }
1737};
1738
1739static int msm_serial_probe(struct platform_device *pdev)
1740{
1741 struct msm_port *msm_port;
1742 struct resource *resource;
1743 struct uart_port *port;
1744 const struct of_device_id *id;
1745 int irq, line;
1746
1747 if (pdev->dev.of_node)
1748 line = of_alias_get_id(pdev->dev.of_node, "serial");
1749 else
1750 line = pdev->id;
1751
1752 if (line < 0)
1753 line = atomic_inc_return(&msm_uart_next_id) - 1;
1754
1755 if (unlikely(line < 0 || line >= UART_NR))
1756 return -ENXIO;
1757
1758 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1759
1760 port = msm_get_port_from_line(line);
1761 port->dev = &pdev->dev;
1762 msm_port = UART_TO_MSM(port);
1763
1764 id = of_match_device(msm_uartdm_table, &pdev->dev);
1765 if (id)
1766 msm_port->is_uartdm = (unsigned long)id->data;
1767 else
1768 msm_port->is_uartdm = 0;
1769
1770 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1771 if (IS_ERR(msm_port->clk))
1772 return PTR_ERR(msm_port->clk);
1773
1774 if (msm_port->is_uartdm) {
1775 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1776 if (IS_ERR(msm_port->pclk))
1777 return PTR_ERR(msm_port->pclk);
1778 }
1779
1780 port->uartclk = clk_get_rate(msm_port->clk);
1781 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1782
1783 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1784 if (unlikely(!resource))
1785 return -ENXIO;
1786 port->mapbase = resource->start;
1787
1788 irq = platform_get_irq(pdev, 0);
1789 if (unlikely(irq < 0))
1790 return -ENXIO;
1791 port->irq = irq;
1792
1793 platform_set_drvdata(pdev, port);
1794
1795 return uart_add_one_port(&msm_uart_driver, port);
1796}
1797
1798static int msm_serial_remove(struct platform_device *pdev)
1799{
1800 struct uart_port *port = platform_get_drvdata(pdev);
1801
1802 uart_remove_one_port(&msm_uart_driver, port);
1803
1804 return 0;
1805}
1806
1807static const struct of_device_id msm_match_table[] = {
1808 { .compatible = "qcom,msm-uart" },
1809 { .compatible = "qcom,msm-uartdm" },
1810 {}
1811};
1812MODULE_DEVICE_TABLE(of, msm_match_table);
1813
1814static struct platform_driver msm_platform_driver = {
1815 .remove = msm_serial_remove,
1816 .probe = msm_serial_probe,
1817 .driver = {
1818 .name = "msm_serial",
1819 .of_match_table = msm_match_table,
1820 },
1821};
1822
1823static int __init msm_serial_init(void)
1824{
1825 int ret;
1826
1827 ret = uart_register_driver(&msm_uart_driver);
1828 if (unlikely(ret))
1829 return ret;
1830
1831 ret = platform_driver_register(&msm_platform_driver);
1832 if (unlikely(ret))
1833 uart_unregister_driver(&msm_uart_driver);
1834
1835 pr_info("msm_serial: driver initialized\n");
1836
1837 return ret;
1838}
1839
1840static void __exit msm_serial_exit(void)
1841{
1842 platform_driver_unregister(&msm_platform_driver);
1843 uart_unregister_driver(&msm_uart_driver);
1844}
1845
1846module_init(msm_serial_init);
1847module_exit(msm_serial_exit);
1848
1849MODULE_AUTHOR("Robert Love <rlove@google.com>");
1850MODULE_DESCRIPTION("Driver for msm7x serial device");
1851MODULE_LICENSE("GPL");