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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_device.h>
11#include <linux/of_pci.h>
12#include <linux/pci_hotplug.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/cpumask.h>
16#include <linux/pci-aspm.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68static int find_anything(struct device *dev, void *data)
69{
70 return 1;
71}
72
73/*
74 * Some device drivers need know if PCI is initiated.
75 * Basically, we think PCI is not initiated when there
76 * is no device to be found on the pci_bus_type.
77 */
78int no_pci_devices(void)
79{
80 struct device *dev;
81 int no_devices;
82
83 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
84 no_devices = (dev == NULL);
85 put_device(dev);
86 return no_devices;
87}
88EXPORT_SYMBOL(no_pci_devices);
89
90/*
91 * PCI Bus Class
92 */
93static void release_pcibus_dev(struct device *dev)
94{
95 struct pci_bus *pci_bus = to_pci_bus(dev);
96
97 put_device(pci_bus->bridge);
98 pci_bus_remove_resources(pci_bus);
99 pci_release_bus_of_node(pci_bus);
100 kfree(pci_bus);
101}
102
103static struct class pcibus_class = {
104 .name = "pci_bus",
105 .dev_release = &release_pcibus_dev,
106 .dev_groups = pcibus_groups,
107};
108
109static int __init pcibus_class_init(void)
110{
111 return class_register(&pcibus_class);
112}
113postcore_initcall(pcibus_class_init);
114
115static u64 pci_size(u64 base, u64 maxbase, u64 mask)
116{
117 u64 size = mask & maxbase; /* Find the significant bits */
118 if (!size)
119 return 0;
120
121 /*
122 * Get the lowest of them to find the decode size, and from that
123 * the extent.
124 */
125 size = (size & ~(size-1)) - 1;
126
127 /*
128 * base == maxbase can be valid only if the BAR has already been
129 * programmed with all 1s.
130 */
131 if (base == maxbase && ((base | size) & mask) != mask)
132 return 0;
133
134 return size;
135}
136
137static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
138{
139 u32 mem_type;
140 unsigned long flags;
141
142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
143 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
144 flags |= IORESOURCE_IO;
145 return flags;
146 }
147
148 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
149 flags |= IORESOURCE_MEM;
150 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
151 flags |= IORESOURCE_PREFETCH;
152
153 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
154 switch (mem_type) {
155 case PCI_BASE_ADDRESS_MEM_TYPE_32:
156 break;
157 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
158 /* 1M mem BAR treated as 32-bit BAR */
159 break;
160 case PCI_BASE_ADDRESS_MEM_TYPE_64:
161 flags |= IORESOURCE_MEM_64;
162 break;
163 default:
164 /* mem unknown type treated as 32-bit BAR */
165 break;
166 }
167 return flags;
168}
169
170#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
171
172/**
173 * pci_read_base - Read a PCI BAR
174 * @dev: the PCI device
175 * @type: type of the BAR
176 * @res: resource buffer to be filled in
177 * @pos: BAR position in the config space
178 *
179 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
180 */
181int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
182 struct resource *res, unsigned int pos)
183{
184 u32 l = 0, sz = 0, mask;
185 u64 l64, sz64, mask64;
186 u16 orig_cmd;
187 struct pci_bus_region region, inverted_region;
188
189 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
190
191 /* No printks while decoding is disabled! */
192 if (!dev->mmio_always_on) {
193 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
194 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
195 pci_write_config_word(dev, PCI_COMMAND,
196 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
197 }
198 }
199
200 res->name = pci_name(dev);
201
202 pci_read_config_dword(dev, pos, &l);
203 pci_write_config_dword(dev, pos, l | mask);
204 pci_read_config_dword(dev, pos, &sz);
205 pci_write_config_dword(dev, pos, l);
206
207 /*
208 * All bits set in sz means the device isn't working properly.
209 * If the BAR isn't implemented, all bits must be 0. If it's a
210 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
211 * 1 must be clear.
212 */
213 if (sz == 0xffffffff)
214 sz = 0;
215
216 /*
217 * I don't know how l can have all bits set. Copied from old code.
218 * Maybe it fixes a bug on some ancient platform.
219 */
220 if (l == 0xffffffff)
221 l = 0;
222
223 if (type == pci_bar_unknown) {
224 res->flags = decode_bar(dev, l);
225 res->flags |= IORESOURCE_SIZEALIGN;
226 if (res->flags & IORESOURCE_IO) {
227 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
229 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
230 } else {
231 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
232 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
233 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
234 }
235 } else {
236 if (l & PCI_ROM_ADDRESS_ENABLE)
237 res->flags |= IORESOURCE_ROM_ENABLE;
238 l64 = l & PCI_ROM_ADDRESS_MASK;
239 sz64 = sz & PCI_ROM_ADDRESS_MASK;
240 mask64 = PCI_ROM_ADDRESS_MASK;
241 }
242
243 if (res->flags & IORESOURCE_MEM_64) {
244 pci_read_config_dword(dev, pos + 4, &l);
245 pci_write_config_dword(dev, pos + 4, ~0);
246 pci_read_config_dword(dev, pos + 4, &sz);
247 pci_write_config_dword(dev, pos + 4, l);
248
249 l64 |= ((u64)l << 32);
250 sz64 |= ((u64)sz << 32);
251 mask64 |= ((u64)~0 << 32);
252 }
253
254 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
255 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
256
257 if (!sz64)
258 goto fail;
259
260 sz64 = pci_size(l64, sz64, mask64);
261 if (!sz64) {
262 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
263 pos);
264 goto fail;
265 }
266
267 if (res->flags & IORESOURCE_MEM_64) {
268 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
269 && sz64 > 0x100000000ULL) {
270 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
271 res->start = 0;
272 res->end = 0;
273 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
274 pos, (unsigned long long)sz64);
275 goto out;
276 }
277
278 if ((sizeof(pci_bus_addr_t) < 8) && l) {
279 /* Above 32-bit boundary; try to reallocate */
280 res->flags |= IORESOURCE_UNSET;
281 res->start = 0;
282 res->end = sz64;
283 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
284 pos, (unsigned long long)l64);
285 goto out;
286 }
287 }
288
289 region.start = l64;
290 region.end = l64 + sz64;
291
292 pcibios_bus_to_resource(dev->bus, res, ®ion);
293 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
294
295 /*
296 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
297 * the corresponding resource address (the physical address used by
298 * the CPU. Converting that resource address back to a bus address
299 * should yield the original BAR value:
300 *
301 * resource_to_bus(bus_to_resource(A)) == A
302 *
303 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
304 * be claimed by the device.
305 */
306 if (inverted_region.start != region.start) {
307 res->flags |= IORESOURCE_UNSET;
308 res->start = 0;
309 res->end = region.end - region.start;
310 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
311 pos, (unsigned long long)region.start);
312 }
313
314 goto out;
315
316
317fail:
318 res->flags = 0;
319out:
320 if (res->flags)
321 pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
322
323 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
324}
325
326static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
327{
328 unsigned int pos, reg;
329
330 if (dev->non_compliant_bars)
331 return;
332
333 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
334 if (dev->is_virtfn)
335 return;
336
337 for (pos = 0; pos < howmany; pos++) {
338 struct resource *res = &dev->resource[pos];
339 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
340 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
341 }
342
343 if (rom) {
344 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
345 dev->rom_base_reg = rom;
346 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
347 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
348 __pci_read_base(dev, pci_bar_mem32, res, rom);
349 }
350}
351
352static void pci_read_bridge_io(struct pci_bus *child)
353{
354 struct pci_dev *dev = child->self;
355 u8 io_base_lo, io_limit_lo;
356 unsigned long io_mask, io_granularity, base, limit;
357 struct pci_bus_region region;
358 struct resource *res;
359
360 io_mask = PCI_IO_RANGE_MASK;
361 io_granularity = 0x1000;
362 if (dev->io_window_1k) {
363 /* Support 1K I/O space granularity */
364 io_mask = PCI_IO_1K_RANGE_MASK;
365 io_granularity = 0x400;
366 }
367
368 res = child->resource[0];
369 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
370 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
371 base = (io_base_lo & io_mask) << 8;
372 limit = (io_limit_lo & io_mask) << 8;
373
374 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
375 u16 io_base_hi, io_limit_hi;
376
377 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
378 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
379 base |= ((unsigned long) io_base_hi << 16);
380 limit |= ((unsigned long) io_limit_hi << 16);
381 }
382
383 if (base <= limit) {
384 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
385 region.start = base;
386 region.end = limit + io_granularity - 1;
387 pcibios_bus_to_resource(dev->bus, res, ®ion);
388 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
389 }
390}
391
392static void pci_read_bridge_mmio(struct pci_bus *child)
393{
394 struct pci_dev *dev = child->self;
395 u16 mem_base_lo, mem_limit_lo;
396 unsigned long base, limit;
397 struct pci_bus_region region;
398 struct resource *res;
399
400 res = child->resource[1];
401 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
402 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
403 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
404 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
405 if (base <= limit) {
406 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
407 region.start = base;
408 region.end = limit + 0xfffff;
409 pcibios_bus_to_resource(dev->bus, res, ®ion);
410 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
411 }
412}
413
414static void pci_read_bridge_mmio_pref(struct pci_bus *child)
415{
416 struct pci_dev *dev = child->self;
417 u16 mem_base_lo, mem_limit_lo;
418 u64 base64, limit64;
419 pci_bus_addr_t base, limit;
420 struct pci_bus_region region;
421 struct resource *res;
422
423 res = child->resource[2];
424 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
425 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
426 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
427 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
428
429 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
430 u32 mem_base_hi, mem_limit_hi;
431
432 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
433 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
434
435 /*
436 * Some bridges set the base > limit by default, and some
437 * (broken) BIOSes do not initialize them. If we find
438 * this, just assume they are not being used.
439 */
440 if (mem_base_hi <= mem_limit_hi) {
441 base64 |= (u64) mem_base_hi << 32;
442 limit64 |= (u64) mem_limit_hi << 32;
443 }
444 }
445
446 base = (pci_bus_addr_t) base64;
447 limit = (pci_bus_addr_t) limit64;
448
449 if (base != base64) {
450 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
451 (unsigned long long) base64);
452 return;
453 }
454
455 if (base <= limit) {
456 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
457 IORESOURCE_MEM | IORESOURCE_PREFETCH;
458 if (res->flags & PCI_PREF_RANGE_TYPE_64)
459 res->flags |= IORESOURCE_MEM_64;
460 region.start = base;
461 region.end = limit + 0xfffff;
462 pcibios_bus_to_resource(dev->bus, res, ®ion);
463 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
464 }
465}
466
467void pci_read_bridge_bases(struct pci_bus *child)
468{
469 struct pci_dev *dev = child->self;
470 struct resource *res;
471 int i;
472
473 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
474 return;
475
476 pci_info(dev, "PCI bridge to %pR%s\n",
477 &child->busn_res,
478 dev->transparent ? " (subtractive decode)" : "");
479
480 pci_bus_remove_resources(child);
481 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
482 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
483
484 pci_read_bridge_io(child);
485 pci_read_bridge_mmio(child);
486 pci_read_bridge_mmio_pref(child);
487
488 if (dev->transparent) {
489 pci_bus_for_each_resource(child->parent, res, i) {
490 if (res && res->flags) {
491 pci_bus_add_resource(child, res,
492 PCI_SUBTRACTIVE_DECODE);
493 pci_printk(KERN_DEBUG, dev,
494 " bridge window %pR (subtractive decode)\n",
495 res);
496 }
497 }
498 }
499}
500
501static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
502{
503 struct pci_bus *b;
504
505 b = kzalloc(sizeof(*b), GFP_KERNEL);
506 if (!b)
507 return NULL;
508
509 INIT_LIST_HEAD(&b->node);
510 INIT_LIST_HEAD(&b->children);
511 INIT_LIST_HEAD(&b->devices);
512 INIT_LIST_HEAD(&b->slots);
513 INIT_LIST_HEAD(&b->resources);
514 b->max_bus_speed = PCI_SPEED_UNKNOWN;
515 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
516#ifdef CONFIG_PCI_DOMAINS_GENERIC
517 if (parent)
518 b->domain_nr = parent->domain_nr;
519#endif
520 return b;
521}
522
523static void devm_pci_release_host_bridge_dev(struct device *dev)
524{
525 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
526
527 if (bridge->release_fn)
528 bridge->release_fn(bridge);
529}
530
531static void pci_release_host_bridge_dev(struct device *dev)
532{
533 devm_pci_release_host_bridge_dev(dev);
534 pci_free_host_bridge(to_pci_host_bridge(dev));
535}
536
537struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
538{
539 struct pci_host_bridge *bridge;
540
541 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
542 if (!bridge)
543 return NULL;
544
545 INIT_LIST_HEAD(&bridge->windows);
546 bridge->dev.release = pci_release_host_bridge_dev;
547
548 /*
549 * We assume we can manage these PCIe features. Some systems may
550 * reserve these for use by the platform itself, e.g., an ACPI BIOS
551 * may implement its own AER handling and use _OSC to prevent the
552 * OS from interfering.
553 */
554 bridge->native_aer = 1;
555 bridge->native_hotplug = 1;
556 bridge->native_pme = 1;
557
558 return bridge;
559}
560EXPORT_SYMBOL(pci_alloc_host_bridge);
561
562struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
563 size_t priv)
564{
565 struct pci_host_bridge *bridge;
566
567 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
568 if (!bridge)
569 return NULL;
570
571 INIT_LIST_HEAD(&bridge->windows);
572 bridge->dev.release = devm_pci_release_host_bridge_dev;
573
574 return bridge;
575}
576EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
577
578void pci_free_host_bridge(struct pci_host_bridge *bridge)
579{
580 pci_free_resource_list(&bridge->windows);
581
582 kfree(bridge);
583}
584EXPORT_SYMBOL(pci_free_host_bridge);
585
586static const unsigned char pcix_bus_speed[] = {
587 PCI_SPEED_UNKNOWN, /* 0 */
588 PCI_SPEED_66MHz_PCIX, /* 1 */
589 PCI_SPEED_100MHz_PCIX, /* 2 */
590 PCI_SPEED_133MHz_PCIX, /* 3 */
591 PCI_SPEED_UNKNOWN, /* 4 */
592 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
593 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
594 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
595 PCI_SPEED_UNKNOWN, /* 8 */
596 PCI_SPEED_66MHz_PCIX_266, /* 9 */
597 PCI_SPEED_100MHz_PCIX_266, /* A */
598 PCI_SPEED_133MHz_PCIX_266, /* B */
599 PCI_SPEED_UNKNOWN, /* C */
600 PCI_SPEED_66MHz_PCIX_533, /* D */
601 PCI_SPEED_100MHz_PCIX_533, /* E */
602 PCI_SPEED_133MHz_PCIX_533 /* F */
603};
604
605const unsigned char pcie_link_speed[] = {
606 PCI_SPEED_UNKNOWN, /* 0 */
607 PCIE_SPEED_2_5GT, /* 1 */
608 PCIE_SPEED_5_0GT, /* 2 */
609 PCIE_SPEED_8_0GT, /* 3 */
610 PCIE_SPEED_16_0GT, /* 4 */
611 PCI_SPEED_UNKNOWN, /* 5 */
612 PCI_SPEED_UNKNOWN, /* 6 */
613 PCI_SPEED_UNKNOWN, /* 7 */
614 PCI_SPEED_UNKNOWN, /* 8 */
615 PCI_SPEED_UNKNOWN, /* 9 */
616 PCI_SPEED_UNKNOWN, /* A */
617 PCI_SPEED_UNKNOWN, /* B */
618 PCI_SPEED_UNKNOWN, /* C */
619 PCI_SPEED_UNKNOWN, /* D */
620 PCI_SPEED_UNKNOWN, /* E */
621 PCI_SPEED_UNKNOWN /* F */
622};
623
624void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
625{
626 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
627}
628EXPORT_SYMBOL_GPL(pcie_update_link_speed);
629
630static unsigned char agp_speeds[] = {
631 AGP_UNKNOWN,
632 AGP_1X,
633 AGP_2X,
634 AGP_4X,
635 AGP_8X
636};
637
638static enum pci_bus_speed agp_speed(int agp3, int agpstat)
639{
640 int index = 0;
641
642 if (agpstat & 4)
643 index = 3;
644 else if (agpstat & 2)
645 index = 2;
646 else if (agpstat & 1)
647 index = 1;
648 else
649 goto out;
650
651 if (agp3) {
652 index += 2;
653 if (index == 5)
654 index = 0;
655 }
656
657 out:
658 return agp_speeds[index];
659}
660
661static void pci_set_bus_speed(struct pci_bus *bus)
662{
663 struct pci_dev *bridge = bus->self;
664 int pos;
665
666 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
667 if (!pos)
668 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
669 if (pos) {
670 u32 agpstat, agpcmd;
671
672 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
673 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
674
675 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
676 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
677 }
678
679 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
680 if (pos) {
681 u16 status;
682 enum pci_bus_speed max;
683
684 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
685 &status);
686
687 if (status & PCI_X_SSTATUS_533MHZ) {
688 max = PCI_SPEED_133MHz_PCIX_533;
689 } else if (status & PCI_X_SSTATUS_266MHZ) {
690 max = PCI_SPEED_133MHz_PCIX_266;
691 } else if (status & PCI_X_SSTATUS_133MHZ) {
692 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
693 max = PCI_SPEED_133MHz_PCIX_ECC;
694 else
695 max = PCI_SPEED_133MHz_PCIX;
696 } else {
697 max = PCI_SPEED_66MHz_PCIX;
698 }
699
700 bus->max_bus_speed = max;
701 bus->cur_bus_speed = pcix_bus_speed[
702 (status & PCI_X_SSTATUS_FREQ) >> 6];
703
704 return;
705 }
706
707 if (pci_is_pcie(bridge)) {
708 u32 linkcap;
709 u16 linksta;
710
711 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
712 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
713
714 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
715 pcie_update_link_speed(bus, linksta);
716 }
717}
718
719static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
720{
721 struct irq_domain *d;
722
723 /*
724 * Any firmware interface that can resolve the msi_domain
725 * should be called from here.
726 */
727 d = pci_host_bridge_of_msi_domain(bus);
728 if (!d)
729 d = pci_host_bridge_acpi_msi_domain(bus);
730
731#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
732 /*
733 * If no IRQ domain was found via the OF tree, try looking it up
734 * directly through the fwnode_handle.
735 */
736 if (!d) {
737 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
738
739 if (fwnode)
740 d = irq_find_matching_fwnode(fwnode,
741 DOMAIN_BUS_PCI_MSI);
742 }
743#endif
744
745 return d;
746}
747
748static void pci_set_bus_msi_domain(struct pci_bus *bus)
749{
750 struct irq_domain *d;
751 struct pci_bus *b;
752
753 /*
754 * The bus can be a root bus, a subordinate bus, or a virtual bus
755 * created by an SR-IOV device. Walk up to the first bridge device
756 * found or derive the domain from the host bridge.
757 */
758 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
759 if (b->self)
760 d = dev_get_msi_domain(&b->self->dev);
761 }
762
763 if (!d)
764 d = pci_host_bridge_msi_domain(b);
765
766 dev_set_msi_domain(&bus->dev, d);
767}
768
769static int pci_register_host_bridge(struct pci_host_bridge *bridge)
770{
771 struct device *parent = bridge->dev.parent;
772 struct resource_entry *window, *n;
773 struct pci_bus *bus, *b;
774 resource_size_t offset;
775 LIST_HEAD(resources);
776 struct resource *res;
777 char addr[64], *fmt;
778 const char *name;
779 int err;
780
781 bus = pci_alloc_bus(NULL);
782 if (!bus)
783 return -ENOMEM;
784
785 bridge->bus = bus;
786
787 /* Temporarily move resources off the list */
788 list_splice_init(&bridge->windows, &resources);
789 bus->sysdata = bridge->sysdata;
790 bus->msi = bridge->msi;
791 bus->ops = bridge->ops;
792 bus->number = bus->busn_res.start = bridge->busnr;
793#ifdef CONFIG_PCI_DOMAINS_GENERIC
794 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
795#endif
796
797 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
798 if (b) {
799 /* Ignore it if we already got here via a different bridge */
800 dev_dbg(&b->dev, "bus already known\n");
801 err = -EEXIST;
802 goto free;
803 }
804
805 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
806 bridge->busnr);
807
808 err = pcibios_root_bridge_prepare(bridge);
809 if (err)
810 goto free;
811
812 err = device_register(&bridge->dev);
813 if (err)
814 put_device(&bridge->dev);
815
816 bus->bridge = get_device(&bridge->dev);
817 device_enable_async_suspend(bus->bridge);
818 pci_set_bus_of_node(bus);
819 pci_set_bus_msi_domain(bus);
820
821 if (!parent)
822 set_dev_node(bus->bridge, pcibus_to_node(bus));
823
824 bus->dev.class = &pcibus_class;
825 bus->dev.parent = bus->bridge;
826
827 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
828 name = dev_name(&bus->dev);
829
830 err = device_register(&bus->dev);
831 if (err)
832 goto unregister;
833
834 pcibios_add_bus(bus);
835
836 /* Create legacy_io and legacy_mem files for this bus */
837 pci_create_legacy_files(bus);
838
839 if (parent)
840 dev_info(parent, "PCI host bridge to bus %s\n", name);
841 else
842 pr_info("PCI host bridge to bus %s\n", name);
843
844 /* Add initial resources to the bus */
845 resource_list_for_each_entry_safe(window, n, &resources) {
846 list_move_tail(&window->node, &bridge->windows);
847 offset = window->offset;
848 res = window->res;
849
850 if (res->flags & IORESOURCE_BUS)
851 pci_bus_insert_busn_res(bus, bus->number, res->end);
852 else
853 pci_bus_add_resource(bus, res, 0);
854
855 if (offset) {
856 if (resource_type(res) == IORESOURCE_IO)
857 fmt = " (bus address [%#06llx-%#06llx])";
858 else
859 fmt = " (bus address [%#010llx-%#010llx])";
860
861 snprintf(addr, sizeof(addr), fmt,
862 (unsigned long long)(res->start - offset),
863 (unsigned long long)(res->end - offset));
864 } else
865 addr[0] = '\0';
866
867 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
868 }
869
870 down_write(&pci_bus_sem);
871 list_add_tail(&bus->node, &pci_root_buses);
872 up_write(&pci_bus_sem);
873
874 return 0;
875
876unregister:
877 put_device(&bridge->dev);
878 device_unregister(&bridge->dev);
879
880free:
881 kfree(bus);
882 return err;
883}
884
885static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
886 struct pci_dev *bridge, int busnr)
887{
888 struct pci_bus *child;
889 int i;
890 int ret;
891
892 /* Allocate a new bus and inherit stuff from the parent */
893 child = pci_alloc_bus(parent);
894 if (!child)
895 return NULL;
896
897 child->parent = parent;
898 child->ops = parent->ops;
899 child->msi = parent->msi;
900 child->sysdata = parent->sysdata;
901 child->bus_flags = parent->bus_flags;
902
903 /*
904 * Initialize some portions of the bus device, but don't register
905 * it now as the parent is not properly set up yet.
906 */
907 child->dev.class = &pcibus_class;
908 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
909
910 /* Set up the primary, secondary and subordinate bus numbers */
911 child->number = child->busn_res.start = busnr;
912 child->primary = parent->busn_res.start;
913 child->busn_res.end = 0xff;
914
915 if (!bridge) {
916 child->dev.parent = parent->bridge;
917 goto add_dev;
918 }
919
920 child->self = bridge;
921 child->bridge = get_device(&bridge->dev);
922 child->dev.parent = child->bridge;
923 pci_set_bus_of_node(child);
924 pci_set_bus_speed(child);
925
926 /* Set up default resource pointers and names */
927 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
928 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
929 child->resource[i]->name = child->name;
930 }
931 bridge->subordinate = child;
932
933add_dev:
934 pci_set_bus_msi_domain(child);
935 ret = device_register(&child->dev);
936 WARN_ON(ret < 0);
937
938 pcibios_add_bus(child);
939
940 if (child->ops->add_bus) {
941 ret = child->ops->add_bus(child);
942 if (WARN_ON(ret < 0))
943 dev_err(&child->dev, "failed to add bus: %d\n", ret);
944 }
945
946 /* Create legacy_io and legacy_mem files for this bus */
947 pci_create_legacy_files(child);
948
949 return child;
950}
951
952struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
953 int busnr)
954{
955 struct pci_bus *child;
956
957 child = pci_alloc_child_bus(parent, dev, busnr);
958 if (child) {
959 down_write(&pci_bus_sem);
960 list_add_tail(&child->node, &parent->children);
961 up_write(&pci_bus_sem);
962 }
963 return child;
964}
965EXPORT_SYMBOL(pci_add_new_bus);
966
967static void pci_enable_crs(struct pci_dev *pdev)
968{
969 u16 root_cap = 0;
970
971 /* Enable CRS Software Visibility if supported */
972 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
973 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
974 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
975 PCI_EXP_RTCTL_CRSSVE);
976}
977
978static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
979 unsigned int available_buses);
980
981/*
982 * pci_scan_bridge_extend() - Scan buses behind a bridge
983 * @bus: Parent bus the bridge is on
984 * @dev: Bridge itself
985 * @max: Starting subordinate number of buses behind this bridge
986 * @available_buses: Total number of buses available for this bridge and
987 * the devices below. After the minimal bus space has
988 * been allocated the remaining buses will be
989 * distributed equally between hotplug-capable bridges.
990 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
991 * that need to be reconfigured.
992 *
993 * If it's a bridge, configure it and scan the bus behind it.
994 * For CardBus bridges, we don't scan behind as the devices will
995 * be handled by the bridge driver itself.
996 *
997 * We need to process bridges in two passes -- first we scan those
998 * already configured by the BIOS and after we are done with all of
999 * them, we proceed to assigning numbers to the remaining buses in
1000 * order to avoid overlaps between old and new bus numbers.
1001 */
1002static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1003 int max, unsigned int available_buses,
1004 int pass)
1005{
1006 struct pci_bus *child;
1007 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1008 u32 buses, i, j = 0;
1009 u16 bctl;
1010 u8 primary, secondary, subordinate;
1011 int broken = 0;
1012
1013 /*
1014 * Make sure the bridge is powered on to be able to access config
1015 * space of devices below it.
1016 */
1017 pm_runtime_get_sync(&dev->dev);
1018
1019 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1020 primary = buses & 0xFF;
1021 secondary = (buses >> 8) & 0xFF;
1022 subordinate = (buses >> 16) & 0xFF;
1023
1024 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1025 secondary, subordinate, pass);
1026
1027 if (!primary && (primary != bus->number) && secondary && subordinate) {
1028 pci_warn(dev, "Primary bus is hard wired to 0\n");
1029 primary = bus->number;
1030 }
1031
1032 /* Check if setup is sensible at all */
1033 if (!pass &&
1034 (primary != bus->number || secondary <= bus->number ||
1035 secondary > subordinate)) {
1036 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1037 secondary, subordinate);
1038 broken = 1;
1039 }
1040
1041 /*
1042 * Disable Master-Abort Mode during probing to avoid reporting of
1043 * bus errors in some architectures.
1044 */
1045 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1046 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1047 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1048
1049 pci_enable_crs(dev);
1050
1051 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1052 !is_cardbus && !broken) {
1053 unsigned int cmax;
1054
1055 /*
1056 * Bus already configured by firmware, process it in the
1057 * first pass and just note the configuration.
1058 */
1059 if (pass)
1060 goto out;
1061
1062 /*
1063 * The bus might already exist for two reasons: Either we
1064 * are rescanning the bus or the bus is reachable through
1065 * more than one bridge. The second case can happen with
1066 * the i450NX chipset.
1067 */
1068 child = pci_find_bus(pci_domain_nr(bus), secondary);
1069 if (!child) {
1070 child = pci_add_new_bus(bus, dev, secondary);
1071 if (!child)
1072 goto out;
1073 child->primary = primary;
1074 pci_bus_insert_busn_res(child, secondary, subordinate);
1075 child->bridge_ctl = bctl;
1076 }
1077
1078 cmax = pci_scan_child_bus(child);
1079 if (cmax > subordinate)
1080 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1081 subordinate, cmax);
1082
1083 /* Subordinate should equal child->busn_res.end */
1084 if (subordinate > max)
1085 max = subordinate;
1086 } else {
1087
1088 /*
1089 * We need to assign a number to this bus which we always
1090 * do in the second pass.
1091 */
1092 if (!pass) {
1093 if (pcibios_assign_all_busses() || broken || is_cardbus)
1094
1095 /*
1096 * Temporarily disable forwarding of the
1097 * configuration cycles on all bridges in
1098 * this bus segment to avoid possible
1099 * conflicts in the second pass between two
1100 * bridges programmed with overlapping bus
1101 * ranges.
1102 */
1103 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1104 buses & ~0xffffff);
1105 goto out;
1106 }
1107
1108 /* Clear errors */
1109 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1110
1111 /*
1112 * Prevent assigning a bus number that already exists.
1113 * This can happen when a bridge is hot-plugged, so in this
1114 * case we only re-scan this bus.
1115 */
1116 child = pci_find_bus(pci_domain_nr(bus), max+1);
1117 if (!child) {
1118 child = pci_add_new_bus(bus, dev, max+1);
1119 if (!child)
1120 goto out;
1121 pci_bus_insert_busn_res(child, max+1,
1122 bus->busn_res.end);
1123 }
1124 max++;
1125 if (available_buses)
1126 available_buses--;
1127
1128 buses = (buses & 0xff000000)
1129 | ((unsigned int)(child->primary) << 0)
1130 | ((unsigned int)(child->busn_res.start) << 8)
1131 | ((unsigned int)(child->busn_res.end) << 16);
1132
1133 /*
1134 * yenta.c forces a secondary latency timer of 176.
1135 * Copy that behaviour here.
1136 */
1137 if (is_cardbus) {
1138 buses &= ~0xff000000;
1139 buses |= CARDBUS_LATENCY_TIMER << 24;
1140 }
1141
1142 /* We need to blast all three values with a single write */
1143 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1144
1145 if (!is_cardbus) {
1146 child->bridge_ctl = bctl;
1147 max = pci_scan_child_bus_extend(child, available_buses);
1148 } else {
1149
1150 /*
1151 * For CardBus bridges, we leave 4 bus numbers as
1152 * cards with a PCI-to-PCI bridge can be inserted
1153 * later.
1154 */
1155 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1156 struct pci_bus *parent = bus;
1157 if (pci_find_bus(pci_domain_nr(bus),
1158 max+i+1))
1159 break;
1160 while (parent->parent) {
1161 if ((!pcibios_assign_all_busses()) &&
1162 (parent->busn_res.end > max) &&
1163 (parent->busn_res.end <= max+i)) {
1164 j = 1;
1165 }
1166 parent = parent->parent;
1167 }
1168 if (j) {
1169
1170 /*
1171 * Often, there are two CardBus
1172 * bridges -- try to leave one
1173 * valid bus number for each one.
1174 */
1175 i /= 2;
1176 break;
1177 }
1178 }
1179 max += i;
1180 }
1181
1182 /* Set subordinate bus number to its real value */
1183 pci_bus_update_busn_res_end(child, max);
1184 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1185 }
1186
1187 sprintf(child->name,
1188 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1189 pci_domain_nr(bus), child->number);
1190
1191 /* Has only triggered on CardBus, fixup is in yenta_socket */
1192 while (bus->parent) {
1193 if ((child->busn_res.end > bus->busn_res.end) ||
1194 (child->number > bus->busn_res.end) ||
1195 (child->number < bus->number) ||
1196 (child->busn_res.end < bus->number)) {
1197 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1198 &child->busn_res,
1199 (bus->number > child->busn_res.end &&
1200 bus->busn_res.end < child->number) ?
1201 "wholly" : "partially",
1202 bus->self->transparent ? " transparent" : "",
1203 dev_name(&bus->dev),
1204 &bus->busn_res);
1205 }
1206 bus = bus->parent;
1207 }
1208
1209out:
1210 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1211
1212 pm_runtime_put(&dev->dev);
1213
1214 return max;
1215}
1216
1217/*
1218 * pci_scan_bridge() - Scan buses behind a bridge
1219 * @bus: Parent bus the bridge is on
1220 * @dev: Bridge itself
1221 * @max: Starting subordinate number of buses behind this bridge
1222 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1223 * that need to be reconfigured.
1224 *
1225 * If it's a bridge, configure it and scan the bus behind it.
1226 * For CardBus bridges, we don't scan behind as the devices will
1227 * be handled by the bridge driver itself.
1228 *
1229 * We need to process bridges in two passes -- first we scan those
1230 * already configured by the BIOS and after we are done with all of
1231 * them, we proceed to assigning numbers to the remaining buses in
1232 * order to avoid overlaps between old and new bus numbers.
1233 */
1234int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1235{
1236 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1237}
1238EXPORT_SYMBOL(pci_scan_bridge);
1239
1240/*
1241 * Read interrupt line and base address registers.
1242 * The architecture-dependent code can tweak these, of course.
1243 */
1244static void pci_read_irq(struct pci_dev *dev)
1245{
1246 unsigned char irq;
1247
1248 /* VFs are not allowed to use INTx, so skip the config reads */
1249 if (dev->is_virtfn) {
1250 dev->pin = 0;
1251 dev->irq = 0;
1252 return;
1253 }
1254
1255 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1256 dev->pin = irq;
1257 if (irq)
1258 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1259 dev->irq = irq;
1260}
1261
1262void set_pcie_port_type(struct pci_dev *pdev)
1263{
1264 int pos;
1265 u16 reg16;
1266 int type;
1267 struct pci_dev *parent;
1268
1269 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1270 if (!pos)
1271 return;
1272
1273 pdev->pcie_cap = pos;
1274 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1275 pdev->pcie_flags_reg = reg16;
1276 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1277 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1278
1279 /*
1280 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1281 * of a Link. No PCIe component has two Links. Two Links are
1282 * connected by a Switch that has a Port on each Link and internal
1283 * logic to connect the two Ports.
1284 */
1285 type = pci_pcie_type(pdev);
1286 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1287 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1288 pdev->has_secondary_link = 1;
1289 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1290 type == PCI_EXP_TYPE_DOWNSTREAM) {
1291 parent = pci_upstream_bridge(pdev);
1292
1293 /*
1294 * Usually there's an upstream device (Root Port or Switch
1295 * Downstream Port), but we can't assume one exists.
1296 */
1297 if (parent && !parent->has_secondary_link)
1298 pdev->has_secondary_link = 1;
1299 }
1300}
1301
1302void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1303{
1304 u32 reg32;
1305
1306 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1307 if (reg32 & PCI_EXP_SLTCAP_HPC)
1308 pdev->is_hotplug_bridge = 1;
1309}
1310
1311static void set_pcie_thunderbolt(struct pci_dev *dev)
1312{
1313 int vsec = 0;
1314 u32 header;
1315
1316 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1317 PCI_EXT_CAP_ID_VNDR))) {
1318 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1319
1320 /* Is the device part of a Thunderbolt controller? */
1321 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1322 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1323 dev->is_thunderbolt = 1;
1324 return;
1325 }
1326 }
1327}
1328
1329/**
1330 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1331 * @dev: PCI device
1332 *
1333 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1334 * when forwarding a type1 configuration request the bridge must check that
1335 * the extended register address field is zero. The bridge is not permitted
1336 * to forward the transactions and must handle it as an Unsupported Request.
1337 * Some bridges do not follow this rule and simply drop the extended register
1338 * bits, resulting in the standard config space being aliased, every 256
1339 * bytes across the entire configuration space. Test for this condition by
1340 * comparing the first dword of each potential alias to the vendor/device ID.
1341 * Known offenders:
1342 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1343 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1344 */
1345static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1346{
1347#ifdef CONFIG_PCI_QUIRKS
1348 int pos;
1349 u32 header, tmp;
1350
1351 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1352
1353 for (pos = PCI_CFG_SPACE_SIZE;
1354 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1355 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1356 || header != tmp)
1357 return false;
1358 }
1359
1360 return true;
1361#else
1362 return false;
1363#endif
1364}
1365
1366/**
1367 * pci_cfg_space_size - Get the configuration space size of the PCI device
1368 * @dev: PCI device
1369 *
1370 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1371 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1372 * access it. Maybe we don't have a way to generate extended config space
1373 * accesses, or the device is behind a reverse Express bridge. So we try
1374 * reading the dword at 0x100 which must either be 0 or a valid extended
1375 * capability header.
1376 */
1377static int pci_cfg_space_size_ext(struct pci_dev *dev)
1378{
1379 u32 status;
1380 int pos = PCI_CFG_SPACE_SIZE;
1381
1382 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1383 return PCI_CFG_SPACE_SIZE;
1384 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1385 return PCI_CFG_SPACE_SIZE;
1386
1387 return PCI_CFG_SPACE_EXP_SIZE;
1388}
1389
1390int pci_cfg_space_size(struct pci_dev *dev)
1391{
1392 int pos;
1393 u32 status;
1394 u16 class;
1395
1396 class = dev->class >> 8;
1397 if (class == PCI_CLASS_BRIDGE_HOST)
1398 return pci_cfg_space_size_ext(dev);
1399
1400 if (pci_is_pcie(dev))
1401 return pci_cfg_space_size_ext(dev);
1402
1403 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1404 if (!pos)
1405 return PCI_CFG_SPACE_SIZE;
1406
1407 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1408 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1409 return pci_cfg_space_size_ext(dev);
1410
1411 return PCI_CFG_SPACE_SIZE;
1412}
1413
1414static u32 pci_class(struct pci_dev *dev)
1415{
1416 u32 class;
1417
1418#ifdef CONFIG_PCI_IOV
1419 if (dev->is_virtfn)
1420 return dev->physfn->sriov->class;
1421#endif
1422 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1423 return class;
1424}
1425
1426static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1427{
1428#ifdef CONFIG_PCI_IOV
1429 if (dev->is_virtfn) {
1430 *vendor = dev->physfn->sriov->subsystem_vendor;
1431 *device = dev->physfn->sriov->subsystem_device;
1432 return;
1433 }
1434#endif
1435 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1436 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1437}
1438
1439static u8 pci_hdr_type(struct pci_dev *dev)
1440{
1441 u8 hdr_type;
1442
1443#ifdef CONFIG_PCI_IOV
1444 if (dev->is_virtfn)
1445 return dev->physfn->sriov->hdr_type;
1446#endif
1447 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1448 return hdr_type;
1449}
1450
1451#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1452
1453static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1454{
1455 /*
1456 * Disable the MSI hardware to avoid screaming interrupts
1457 * during boot. This is the power on reset default so
1458 * usually this should be a noop.
1459 */
1460 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1461 if (dev->msi_cap)
1462 pci_msi_set_enable(dev, 0);
1463
1464 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1465 if (dev->msix_cap)
1466 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1467}
1468
1469/**
1470 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1471 * @dev: PCI device
1472 *
1473 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1474 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1475 */
1476static int pci_intx_mask_broken(struct pci_dev *dev)
1477{
1478 u16 orig, toggle, new;
1479
1480 pci_read_config_word(dev, PCI_COMMAND, &orig);
1481 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1482 pci_write_config_word(dev, PCI_COMMAND, toggle);
1483 pci_read_config_word(dev, PCI_COMMAND, &new);
1484
1485 pci_write_config_word(dev, PCI_COMMAND, orig);
1486
1487 /*
1488 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1489 * r2.3, so strictly speaking, a device is not *broken* if it's not
1490 * writable. But we'll live with the misnomer for now.
1491 */
1492 if (new != toggle)
1493 return 1;
1494 return 0;
1495}
1496
1497/**
1498 * pci_setup_device - Fill in class and map information of a device
1499 * @dev: the device structure to fill
1500 *
1501 * Initialize the device structure with information about the device's
1502 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1503 * Called at initialisation of the PCI subsystem and by CardBus services.
1504 * Returns 0 on success and negative if unknown type of device (not normal,
1505 * bridge or CardBus).
1506 */
1507int pci_setup_device(struct pci_dev *dev)
1508{
1509 u32 class;
1510 u16 cmd;
1511 u8 hdr_type;
1512 int pos = 0;
1513 struct pci_bus_region region;
1514 struct resource *res;
1515
1516 hdr_type = pci_hdr_type(dev);
1517
1518 dev->sysdata = dev->bus->sysdata;
1519 dev->dev.parent = dev->bus->bridge;
1520 dev->dev.bus = &pci_bus_type;
1521 dev->hdr_type = hdr_type & 0x7f;
1522 dev->multifunction = !!(hdr_type & 0x80);
1523 dev->error_state = pci_channel_io_normal;
1524 set_pcie_port_type(dev);
1525
1526 pci_dev_assign_slot(dev);
1527
1528 /*
1529 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1530 * set this higher, assuming the system even supports it.
1531 */
1532 dev->dma_mask = 0xffffffff;
1533
1534 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1535 dev->bus->number, PCI_SLOT(dev->devfn),
1536 PCI_FUNC(dev->devfn));
1537
1538 class = pci_class(dev);
1539
1540 dev->revision = class & 0xff;
1541 dev->class = class >> 8; /* upper 3 bytes */
1542
1543 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1544 dev->vendor, dev->device, dev->hdr_type, dev->class);
1545
1546 /* Need to have dev->class ready */
1547 dev->cfg_size = pci_cfg_space_size(dev);
1548
1549 /* Need to have dev->cfg_size ready */
1550 set_pcie_thunderbolt(dev);
1551
1552 /* "Unknown power state" */
1553 dev->current_state = PCI_UNKNOWN;
1554
1555 /* Early fixups, before probing the BARs */
1556 pci_fixup_device(pci_fixup_early, dev);
1557
1558 /* Device class may be changed after fixup */
1559 class = dev->class >> 8;
1560
1561 if (dev->non_compliant_bars) {
1562 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1563 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1564 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1565 cmd &= ~PCI_COMMAND_IO;
1566 cmd &= ~PCI_COMMAND_MEMORY;
1567 pci_write_config_word(dev, PCI_COMMAND, cmd);
1568 }
1569 }
1570
1571 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1572
1573 switch (dev->hdr_type) { /* header type */
1574 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1575 if (class == PCI_CLASS_BRIDGE_PCI)
1576 goto bad;
1577 pci_read_irq(dev);
1578 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1579
1580 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1581
1582 /*
1583 * Do the ugly legacy mode stuff here rather than broken chip
1584 * quirk code. Legacy mode ATA controllers have fixed
1585 * addresses. These are not always echoed in BAR0-3, and
1586 * BAR0-3 in a few cases contain junk!
1587 */
1588 if (class == PCI_CLASS_STORAGE_IDE) {
1589 u8 progif;
1590 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1591 if ((progif & 1) == 0) {
1592 region.start = 0x1F0;
1593 region.end = 0x1F7;
1594 res = &dev->resource[0];
1595 res->flags = LEGACY_IO_RESOURCE;
1596 pcibios_bus_to_resource(dev->bus, res, ®ion);
1597 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1598 res);
1599 region.start = 0x3F6;
1600 region.end = 0x3F6;
1601 res = &dev->resource[1];
1602 res->flags = LEGACY_IO_RESOURCE;
1603 pcibios_bus_to_resource(dev->bus, res, ®ion);
1604 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1605 res);
1606 }
1607 if ((progif & 4) == 0) {
1608 region.start = 0x170;
1609 region.end = 0x177;
1610 res = &dev->resource[2];
1611 res->flags = LEGACY_IO_RESOURCE;
1612 pcibios_bus_to_resource(dev->bus, res, ®ion);
1613 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1614 res);
1615 region.start = 0x376;
1616 region.end = 0x376;
1617 res = &dev->resource[3];
1618 res->flags = LEGACY_IO_RESOURCE;
1619 pcibios_bus_to_resource(dev->bus, res, ®ion);
1620 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1621 res);
1622 }
1623 }
1624 break;
1625
1626 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1627 if (class != PCI_CLASS_BRIDGE_PCI)
1628 goto bad;
1629
1630 /*
1631 * The PCI-to-PCI bridge spec requires that subtractive
1632 * decoding (i.e. transparent) bridge must have programming
1633 * interface code of 0x01.
1634 */
1635 pci_read_irq(dev);
1636 dev->transparent = ((dev->class & 0xff) == 1);
1637 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1638 set_pcie_hotplug_bridge(dev);
1639 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1640 if (pos) {
1641 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1642 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1643 }
1644 break;
1645
1646 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1647 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1648 goto bad;
1649 pci_read_irq(dev);
1650 pci_read_bases(dev, 1, 0);
1651 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1652 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1653 break;
1654
1655 default: /* unknown header */
1656 pci_err(dev, "unknown header type %02x, ignoring device\n",
1657 dev->hdr_type);
1658 return -EIO;
1659
1660 bad:
1661 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1662 dev->class, dev->hdr_type);
1663 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1664 }
1665
1666 /* We found a fine healthy device, go go go... */
1667 return 0;
1668}
1669
1670static void pci_configure_mps(struct pci_dev *dev)
1671{
1672 struct pci_dev *bridge = pci_upstream_bridge(dev);
1673 int mps, p_mps, rc;
1674
1675 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1676 return;
1677
1678 mps = pcie_get_mps(dev);
1679 p_mps = pcie_get_mps(bridge);
1680
1681 if (mps == p_mps)
1682 return;
1683
1684 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1685 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1686 mps, pci_name(bridge), p_mps);
1687 return;
1688 }
1689
1690 /*
1691 * Fancier MPS configuration is done later by
1692 * pcie_bus_configure_settings()
1693 */
1694 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1695 return;
1696
1697 rc = pcie_set_mps(dev, p_mps);
1698 if (rc) {
1699 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1700 p_mps);
1701 return;
1702 }
1703
1704 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1705 p_mps, mps, 128 << dev->pcie_mpss);
1706}
1707
1708static struct hpp_type0 pci_default_type0 = {
1709 .revision = 1,
1710 .cache_line_size = 8,
1711 .latency_timer = 0x40,
1712 .enable_serr = 0,
1713 .enable_perr = 0,
1714};
1715
1716static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1717{
1718 u16 pci_cmd, pci_bctl;
1719
1720 if (!hpp)
1721 hpp = &pci_default_type0;
1722
1723 if (hpp->revision > 1) {
1724 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1725 hpp->revision);
1726 hpp = &pci_default_type0;
1727 }
1728
1729 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1730 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1731 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1732 if (hpp->enable_serr)
1733 pci_cmd |= PCI_COMMAND_SERR;
1734 if (hpp->enable_perr)
1735 pci_cmd |= PCI_COMMAND_PARITY;
1736 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1737
1738 /* Program bridge control value */
1739 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1740 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1741 hpp->latency_timer);
1742 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1743 if (hpp->enable_serr)
1744 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1745 if (hpp->enable_perr)
1746 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1747 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1748 }
1749}
1750
1751static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1752{
1753 int pos;
1754
1755 if (!hpp)
1756 return;
1757
1758 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1759 if (!pos)
1760 return;
1761
1762 pci_warn(dev, "PCI-X settings not supported\n");
1763}
1764
1765static bool pcie_root_rcb_set(struct pci_dev *dev)
1766{
1767 struct pci_dev *rp = pcie_find_root_port(dev);
1768 u16 lnkctl;
1769
1770 if (!rp)
1771 return false;
1772
1773 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1774 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1775 return true;
1776
1777 return false;
1778}
1779
1780static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1781{
1782 int pos;
1783 u32 reg32;
1784
1785 if (!hpp)
1786 return;
1787
1788 if (!pci_is_pcie(dev))
1789 return;
1790
1791 if (hpp->revision > 1) {
1792 pci_warn(dev, "PCIe settings rev %d not supported\n",
1793 hpp->revision);
1794 return;
1795 }
1796
1797 /*
1798 * Don't allow _HPX to change MPS or MRRS settings. We manage
1799 * those to make sure they're consistent with the rest of the
1800 * platform.
1801 */
1802 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1803 PCI_EXP_DEVCTL_READRQ;
1804 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1805 PCI_EXP_DEVCTL_READRQ);
1806
1807 /* Initialize Device Control Register */
1808 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1809 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1810
1811 /* Initialize Link Control Register */
1812 if (pcie_cap_has_lnkctl(dev)) {
1813
1814 /*
1815 * If the Root Port supports Read Completion Boundary of
1816 * 128, set RCB to 128. Otherwise, clear it.
1817 */
1818 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1819 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1820 if (pcie_root_rcb_set(dev))
1821 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1822
1823 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1824 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1825 }
1826
1827 /* Find Advanced Error Reporting Enhanced Capability */
1828 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1829 if (!pos)
1830 return;
1831
1832 /* Initialize Uncorrectable Error Mask Register */
1833 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1834 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1835 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1836
1837 /* Initialize Uncorrectable Error Severity Register */
1838 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1839 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1840 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1841
1842 /* Initialize Correctable Error Mask Register */
1843 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1844 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1845 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1846
1847 /* Initialize Advanced Error Capabilities and Control Register */
1848 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1849 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1850
1851 /* Don't enable ECRC generation or checking if unsupported */
1852 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1853 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1854 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1855 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1856 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1857
1858 /*
1859 * FIXME: The following two registers are not supported yet.
1860 *
1861 * o Secondary Uncorrectable Error Severity Register
1862 * o Secondary Uncorrectable Error Mask Register
1863 */
1864}
1865
1866int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1867{
1868 struct pci_host_bridge *host;
1869 u32 cap;
1870 u16 ctl;
1871 int ret;
1872
1873 if (!pci_is_pcie(dev))
1874 return 0;
1875
1876 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1877 if (ret)
1878 return 0;
1879
1880 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1881 return 0;
1882
1883 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1884 if (ret)
1885 return 0;
1886
1887 host = pci_find_host_bridge(dev->bus);
1888 if (!host)
1889 return 0;
1890
1891 /*
1892 * If some device in the hierarchy doesn't handle Extended Tags
1893 * correctly, make sure they're disabled.
1894 */
1895 if (host->no_ext_tags) {
1896 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1897 pci_info(dev, "disabling Extended Tags\n");
1898 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1899 PCI_EXP_DEVCTL_EXT_TAG);
1900 }
1901 return 0;
1902 }
1903
1904 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1905 pci_info(dev, "enabling Extended Tags\n");
1906 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1907 PCI_EXP_DEVCTL_EXT_TAG);
1908 }
1909 return 0;
1910}
1911
1912/**
1913 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1914 * @dev: PCI device to query
1915 *
1916 * Returns true if the device has enabled relaxed ordering attribute.
1917 */
1918bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1919{
1920 u16 v;
1921
1922 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1923
1924 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1925}
1926EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1927
1928static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1929{
1930 struct pci_dev *root;
1931
1932 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1933 if (dev->is_virtfn)
1934 return;
1935
1936 if (!pcie_relaxed_ordering_enabled(dev))
1937 return;
1938
1939 /*
1940 * For now, we only deal with Relaxed Ordering issues with Root
1941 * Ports. Peer-to-Peer DMA is another can of worms.
1942 */
1943 root = pci_find_pcie_root_port(dev);
1944 if (!root)
1945 return;
1946
1947 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1948 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1949 PCI_EXP_DEVCTL_RELAX_EN);
1950 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
1951 }
1952}
1953
1954static void pci_configure_ltr(struct pci_dev *dev)
1955{
1956#ifdef CONFIG_PCIEASPM
1957 u32 cap;
1958 struct pci_dev *bridge;
1959
1960 if (!pci_is_pcie(dev))
1961 return;
1962
1963 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
1964 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1965 return;
1966
1967 /*
1968 * Software must not enable LTR in an Endpoint unless the Root
1969 * Complex and all intermediate Switches indicate support for LTR.
1970 * PCIe r3.1, sec 6.18.
1971 */
1972 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1973 dev->ltr_path = 1;
1974 else {
1975 bridge = pci_upstream_bridge(dev);
1976 if (bridge && bridge->ltr_path)
1977 dev->ltr_path = 1;
1978 }
1979
1980 if (dev->ltr_path)
1981 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
1982 PCI_EXP_DEVCTL2_LTR_EN);
1983#endif
1984}
1985
1986static void pci_configure_device(struct pci_dev *dev)
1987{
1988 struct hotplug_params hpp;
1989 int ret;
1990
1991 pci_configure_mps(dev);
1992 pci_configure_extended_tags(dev, NULL);
1993 pci_configure_relaxed_ordering(dev);
1994 pci_configure_ltr(dev);
1995
1996 memset(&hpp, 0, sizeof(hpp));
1997 ret = pci_get_hp_params(dev, &hpp);
1998 if (ret)
1999 return;
2000
2001 program_hpp_type2(dev, hpp.t2);
2002 program_hpp_type1(dev, hpp.t1);
2003 program_hpp_type0(dev, hpp.t0);
2004}
2005
2006static void pci_release_capabilities(struct pci_dev *dev)
2007{
2008 pci_vpd_release(dev);
2009 pci_iov_release(dev);
2010 pci_free_cap_save_buffers(dev);
2011}
2012
2013/**
2014 * pci_release_dev - Free a PCI device structure when all users of it are
2015 * finished
2016 * @dev: device that's been disconnected
2017 *
2018 * Will be called only by the device core when all users of this PCI device are
2019 * done.
2020 */
2021static void pci_release_dev(struct device *dev)
2022{
2023 struct pci_dev *pci_dev;
2024
2025 pci_dev = to_pci_dev(dev);
2026 pci_release_capabilities(pci_dev);
2027 pci_release_of_node(pci_dev);
2028 pcibios_release_device(pci_dev);
2029 pci_bus_put(pci_dev->bus);
2030 kfree(pci_dev->driver_override);
2031 kfree(pci_dev->dma_alias_mask);
2032 kfree(pci_dev);
2033}
2034
2035struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2036{
2037 struct pci_dev *dev;
2038
2039 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2040 if (!dev)
2041 return NULL;
2042
2043 INIT_LIST_HEAD(&dev->bus_list);
2044 dev->dev.type = &pci_dev_type;
2045 dev->bus = pci_bus_get(bus);
2046
2047 return dev;
2048}
2049EXPORT_SYMBOL(pci_alloc_dev);
2050
2051static bool pci_bus_crs_vendor_id(u32 l)
2052{
2053 return (l & 0xffff) == 0x0001;
2054}
2055
2056static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2057 int timeout)
2058{
2059 int delay = 1;
2060
2061 if (!pci_bus_crs_vendor_id(*l))
2062 return true; /* not a CRS completion */
2063
2064 if (!timeout)
2065 return false; /* CRS, but caller doesn't want to wait */
2066
2067 /*
2068 * We got the reserved Vendor ID that indicates a completion with
2069 * Configuration Request Retry Status (CRS). Retry until we get a
2070 * valid Vendor ID or we time out.
2071 */
2072 while (pci_bus_crs_vendor_id(*l)) {
2073 if (delay > timeout) {
2074 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2075 pci_domain_nr(bus), bus->number,
2076 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2077
2078 return false;
2079 }
2080 if (delay >= 1000)
2081 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2082 pci_domain_nr(bus), bus->number,
2083 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2084
2085 msleep(delay);
2086 delay *= 2;
2087
2088 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2089 return false;
2090 }
2091
2092 if (delay >= 1000)
2093 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2094 pci_domain_nr(bus), bus->number,
2095 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2096
2097 return true;
2098}
2099
2100bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2101 int timeout)
2102{
2103 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2104 return false;
2105
2106 /* Some broken boards return 0 or ~0 if a slot is empty: */
2107 if (*l == 0xffffffff || *l == 0x00000000 ||
2108 *l == 0x0000ffff || *l == 0xffff0000)
2109 return false;
2110
2111 if (pci_bus_crs_vendor_id(*l))
2112 return pci_bus_wait_crs(bus, devfn, l, timeout);
2113
2114 return true;
2115}
2116EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2117
2118/*
2119 * Read the config data for a PCI device, sanity-check it,
2120 * and fill in the dev structure.
2121 */
2122static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2123{
2124 struct pci_dev *dev;
2125 u32 l;
2126
2127 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2128 return NULL;
2129
2130 dev = pci_alloc_dev(bus);
2131 if (!dev)
2132 return NULL;
2133
2134 dev->devfn = devfn;
2135 dev->vendor = l & 0xffff;
2136 dev->device = (l >> 16) & 0xffff;
2137
2138 pci_set_of_node(dev);
2139
2140 if (pci_setup_device(dev)) {
2141 pci_bus_put(dev->bus);
2142 kfree(dev);
2143 return NULL;
2144 }
2145
2146 return dev;
2147}
2148
2149static void pci_init_capabilities(struct pci_dev *dev)
2150{
2151 /* Enhanced Allocation */
2152 pci_ea_init(dev);
2153
2154 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2155 pci_msi_setup_pci_dev(dev);
2156
2157 /* Buffers for saving PCIe and PCI-X capabilities */
2158 pci_allocate_cap_save_buffers(dev);
2159
2160 /* Power Management */
2161 pci_pm_init(dev);
2162
2163 /* Vital Product Data */
2164 pci_vpd_init(dev);
2165
2166 /* Alternative Routing-ID Forwarding */
2167 pci_configure_ari(dev);
2168
2169 /* Single Root I/O Virtualization */
2170 pci_iov_init(dev);
2171
2172 /* Address Translation Services */
2173 pci_ats_init(dev);
2174
2175 /* Enable ACS P2P upstream forwarding */
2176 pci_enable_acs(dev);
2177
2178 /* Precision Time Measurement */
2179 pci_ptm_init(dev);
2180
2181 /* Advanced Error Reporting */
2182 pci_aer_init(dev);
2183
2184 if (pci_probe_reset_function(dev) == 0)
2185 dev->reset_fn = 1;
2186}
2187
2188/*
2189 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2190 * devices. Firmware interfaces that can select the MSI domain on a
2191 * per-device basis should be called from here.
2192 */
2193static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2194{
2195 struct irq_domain *d;
2196
2197 /*
2198 * If a domain has been set through the pcibios_add_device()
2199 * callback, then this is the one (platform code knows best).
2200 */
2201 d = dev_get_msi_domain(&dev->dev);
2202 if (d)
2203 return d;
2204
2205 /*
2206 * Let's see if we have a firmware interface able to provide
2207 * the domain.
2208 */
2209 d = pci_msi_get_device_domain(dev);
2210 if (d)
2211 return d;
2212
2213 return NULL;
2214}
2215
2216static void pci_set_msi_domain(struct pci_dev *dev)
2217{
2218 struct irq_domain *d;
2219
2220 /*
2221 * If the platform or firmware interfaces cannot supply a
2222 * device-specific MSI domain, then inherit the default domain
2223 * from the host bridge itself.
2224 */
2225 d = pci_dev_msi_domain(dev);
2226 if (!d)
2227 d = dev_get_msi_domain(&dev->bus->dev);
2228
2229 dev_set_msi_domain(&dev->dev, d);
2230}
2231
2232void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2233{
2234 int ret;
2235
2236 pci_configure_device(dev);
2237
2238 device_initialize(&dev->dev);
2239 dev->dev.release = pci_release_dev;
2240
2241 set_dev_node(&dev->dev, pcibus_to_node(bus));
2242 dev->dev.dma_mask = &dev->dma_mask;
2243 dev->dev.dma_parms = &dev->dma_parms;
2244 dev->dev.coherent_dma_mask = 0xffffffffull;
2245
2246 pci_set_dma_max_seg_size(dev, 65536);
2247 pci_set_dma_seg_boundary(dev, 0xffffffff);
2248
2249 /* Fix up broken headers */
2250 pci_fixup_device(pci_fixup_header, dev);
2251
2252 /* Moved out from quirk header fixup code */
2253 pci_reassigndev_resource_alignment(dev);
2254
2255 /* Clear the state_saved flag */
2256 dev->state_saved = false;
2257
2258 /* Initialize various capabilities */
2259 pci_init_capabilities(dev);
2260
2261 /*
2262 * Add the device to our list of discovered devices
2263 * and the bus list for fixup functions, etc.
2264 */
2265 down_write(&pci_bus_sem);
2266 list_add_tail(&dev->bus_list, &bus->devices);
2267 up_write(&pci_bus_sem);
2268
2269 ret = pcibios_add_device(dev);
2270 WARN_ON(ret < 0);
2271
2272 /* Set up MSI IRQ domain */
2273 pci_set_msi_domain(dev);
2274
2275 /* Notifier could use PCI capabilities */
2276 dev->match_driver = false;
2277 ret = device_add(&dev->dev);
2278 WARN_ON(ret < 0);
2279}
2280
2281struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2282{
2283 struct pci_dev *dev;
2284
2285 dev = pci_get_slot(bus, devfn);
2286 if (dev) {
2287 pci_dev_put(dev);
2288 return dev;
2289 }
2290
2291 dev = pci_scan_device(bus, devfn);
2292 if (!dev)
2293 return NULL;
2294
2295 pci_device_add(dev, bus);
2296
2297 return dev;
2298}
2299EXPORT_SYMBOL(pci_scan_single_device);
2300
2301static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2302{
2303 int pos;
2304 u16 cap = 0;
2305 unsigned next_fn;
2306
2307 if (pci_ari_enabled(bus)) {
2308 if (!dev)
2309 return 0;
2310 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2311 if (!pos)
2312 return 0;
2313
2314 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2315 next_fn = PCI_ARI_CAP_NFN(cap);
2316 if (next_fn <= fn)
2317 return 0; /* protect against malformed list */
2318
2319 return next_fn;
2320 }
2321
2322 /* dev may be NULL for non-contiguous multifunction devices */
2323 if (!dev || dev->multifunction)
2324 return (fn + 1) % 8;
2325
2326 return 0;
2327}
2328
2329static int only_one_child(struct pci_bus *bus)
2330{
2331 struct pci_dev *bridge = bus->self;
2332
2333 /*
2334 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2335 * we scan for all possible devices, not just Device 0.
2336 */
2337 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2338 return 0;
2339
2340 /*
2341 * A PCIe Downstream Port normally leads to a Link with only Device
2342 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2343 * only for Device 0 in that situation.
2344 *
2345 * Checking has_secondary_link is a hack to identify Downstream
2346 * Ports because sometimes Switches are configured such that the
2347 * PCIe Port Type labels are backwards.
2348 */
2349 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2350 return 1;
2351
2352 return 0;
2353}
2354
2355/**
2356 * pci_scan_slot - Scan a PCI slot on a bus for devices
2357 * @bus: PCI bus to scan
2358 * @devfn: slot number to scan (must have zero function)
2359 *
2360 * Scan a PCI slot on the specified PCI bus for devices, adding
2361 * discovered devices to the @bus->devices list. New devices
2362 * will not have is_added set.
2363 *
2364 * Returns the number of new devices found.
2365 */
2366int pci_scan_slot(struct pci_bus *bus, int devfn)
2367{
2368 unsigned fn, nr = 0;
2369 struct pci_dev *dev;
2370
2371 if (only_one_child(bus) && (devfn > 0))
2372 return 0; /* Already scanned the entire slot */
2373
2374 dev = pci_scan_single_device(bus, devfn);
2375 if (!dev)
2376 return 0;
2377 if (!dev->is_added)
2378 nr++;
2379
2380 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2381 dev = pci_scan_single_device(bus, devfn + fn);
2382 if (dev) {
2383 if (!dev->is_added)
2384 nr++;
2385 dev->multifunction = 1;
2386 }
2387 }
2388
2389 /* Only one slot has PCIe device */
2390 if (bus->self && nr)
2391 pcie_aspm_init_link_state(bus->self);
2392
2393 return nr;
2394}
2395EXPORT_SYMBOL(pci_scan_slot);
2396
2397static int pcie_find_smpss(struct pci_dev *dev, void *data)
2398{
2399 u8 *smpss = data;
2400
2401 if (!pci_is_pcie(dev))
2402 return 0;
2403
2404 /*
2405 * We don't have a way to change MPS settings on devices that have
2406 * drivers attached. A hot-added device might support only the minimum
2407 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2408 * where devices may be hot-added, we limit the fabric MPS to 128 so
2409 * hot-added devices will work correctly.
2410 *
2411 * However, if we hot-add a device to a slot directly below a Root
2412 * Port, it's impossible for there to be other existing devices below
2413 * the port. We don't limit the MPS in this case because we can
2414 * reconfigure MPS on both the Root Port and the hot-added device,
2415 * and there are no other devices involved.
2416 *
2417 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2418 */
2419 if (dev->is_hotplug_bridge &&
2420 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2421 *smpss = 0;
2422
2423 if (*smpss > dev->pcie_mpss)
2424 *smpss = dev->pcie_mpss;
2425
2426 return 0;
2427}
2428
2429static void pcie_write_mps(struct pci_dev *dev, int mps)
2430{
2431 int rc;
2432
2433 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2434 mps = 128 << dev->pcie_mpss;
2435
2436 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2437 dev->bus->self)
2438
2439 /*
2440 * For "Performance", the assumption is made that
2441 * downstream communication will never be larger than
2442 * the MRRS. So, the MPS only needs to be configured
2443 * for the upstream communication. This being the case,
2444 * walk from the top down and set the MPS of the child
2445 * to that of the parent bus.
2446 *
2447 * Configure the device MPS with the smaller of the
2448 * device MPSS or the bridge MPS (which is assumed to be
2449 * properly configured at this point to the largest
2450 * allowable MPS based on its parent bus).
2451 */
2452 mps = min(mps, pcie_get_mps(dev->bus->self));
2453 }
2454
2455 rc = pcie_set_mps(dev, mps);
2456 if (rc)
2457 pci_err(dev, "Failed attempting to set the MPS\n");
2458}
2459
2460static void pcie_write_mrrs(struct pci_dev *dev)
2461{
2462 int rc, mrrs;
2463
2464 /*
2465 * In the "safe" case, do not configure the MRRS. There appear to be
2466 * issues with setting MRRS to 0 on a number of devices.
2467 */
2468 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2469 return;
2470
2471 /*
2472 * For max performance, the MRRS must be set to the largest supported
2473 * value. However, it cannot be configured larger than the MPS the
2474 * device or the bus can support. This should already be properly
2475 * configured by a prior call to pcie_write_mps().
2476 */
2477 mrrs = pcie_get_mps(dev);
2478
2479 /*
2480 * MRRS is a R/W register. Invalid values can be written, but a
2481 * subsequent read will verify if the value is acceptable or not.
2482 * If the MRRS value provided is not acceptable (e.g., too large),
2483 * shrink the value until it is acceptable to the HW.
2484 */
2485 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2486 rc = pcie_set_readrq(dev, mrrs);
2487 if (!rc)
2488 break;
2489
2490 pci_warn(dev, "Failed attempting to set the MRRS\n");
2491 mrrs /= 2;
2492 }
2493
2494 if (mrrs < 128)
2495 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2496}
2497
2498static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2499{
2500 int mps, orig_mps;
2501
2502 if (!pci_is_pcie(dev))
2503 return 0;
2504
2505 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2506 pcie_bus_config == PCIE_BUS_DEFAULT)
2507 return 0;
2508
2509 mps = 128 << *(u8 *)data;
2510 orig_mps = pcie_get_mps(dev);
2511
2512 pcie_write_mps(dev, mps);
2513 pcie_write_mrrs(dev);
2514
2515 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2516 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2517 orig_mps, pcie_get_readrq(dev));
2518
2519 return 0;
2520}
2521
2522/*
2523 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2524 * parents then children fashion. If this changes, then this code will not
2525 * work as designed.
2526 */
2527void pcie_bus_configure_settings(struct pci_bus *bus)
2528{
2529 u8 smpss = 0;
2530
2531 if (!bus->self)
2532 return;
2533
2534 if (!pci_is_pcie(bus->self))
2535 return;
2536
2537 /*
2538 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2539 * to be aware of the MPS of the destination. To work around this,
2540 * simply force the MPS of the entire system to the smallest possible.
2541 */
2542 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2543 smpss = 0;
2544
2545 if (pcie_bus_config == PCIE_BUS_SAFE) {
2546 smpss = bus->self->pcie_mpss;
2547
2548 pcie_find_smpss(bus->self, &smpss);
2549 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2550 }
2551
2552 pcie_bus_configure_set(bus->self, &smpss);
2553 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2554}
2555EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2556
2557/*
2558 * Called after each bus is probed, but before its children are examined. This
2559 * is marked as __weak because multiple architectures define it.
2560 */
2561void __weak pcibios_fixup_bus(struct pci_bus *bus)
2562{
2563 /* nothing to do, expected to be removed in the future */
2564}
2565
2566/**
2567 * pci_scan_child_bus_extend() - Scan devices below a bus
2568 * @bus: Bus to scan for devices
2569 * @available_buses: Total number of buses available (%0 does not try to
2570 * extend beyond the minimal)
2571 *
2572 * Scans devices below @bus including subordinate buses. Returns new
2573 * subordinate number including all the found devices. Passing
2574 * @available_buses causes the remaining bus space to be distributed
2575 * equally between hotplug-capable bridges to allow future extension of the
2576 * hierarchy.
2577 */
2578static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2579 unsigned int available_buses)
2580{
2581 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2582 unsigned int start = bus->busn_res.start;
2583 unsigned int devfn, fn, cmax, max = start;
2584 struct pci_dev *dev;
2585 int nr_devs;
2586
2587 dev_dbg(&bus->dev, "scanning bus\n");
2588
2589 /* Go find them, Rover! */
2590 for (devfn = 0; devfn < 256; devfn += 8) {
2591 nr_devs = pci_scan_slot(bus, devfn);
2592
2593 /*
2594 * The Jailhouse hypervisor may pass individual functions of a
2595 * multi-function device to a guest without passing function 0.
2596 * Look for them as well.
2597 */
2598 if (jailhouse_paravirt() && nr_devs == 0) {
2599 for (fn = 1; fn < 8; fn++) {
2600 dev = pci_scan_single_device(bus, devfn + fn);
2601 if (dev)
2602 dev->multifunction = 1;
2603 }
2604 }
2605 }
2606
2607 /* Reserve buses for SR-IOV capability */
2608 used_buses = pci_iov_bus_range(bus);
2609 max += used_buses;
2610
2611 /*
2612 * After performing arch-dependent fixup of the bus, look behind
2613 * all PCI-to-PCI bridges on this bus.
2614 */
2615 if (!bus->is_added) {
2616 dev_dbg(&bus->dev, "fixups for bus\n");
2617 pcibios_fixup_bus(bus);
2618 bus->is_added = 1;
2619 }
2620
2621 /*
2622 * Calculate how many hotplug bridges and normal bridges there
2623 * are on this bus. We will distribute the additional available
2624 * buses between hotplug bridges.
2625 */
2626 for_each_pci_bridge(dev, bus) {
2627 if (dev->is_hotplug_bridge)
2628 hotplug_bridges++;
2629 else
2630 normal_bridges++;
2631 }
2632
2633 /*
2634 * Scan bridges that are already configured. We don't touch them
2635 * unless they are misconfigured (which will be done in the second
2636 * scan below).
2637 */
2638 for_each_pci_bridge(dev, bus) {
2639 cmax = max;
2640 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2641 used_buses += cmax - max;
2642 }
2643
2644 /* Scan bridges that need to be reconfigured */
2645 for_each_pci_bridge(dev, bus) {
2646 unsigned int buses = 0;
2647
2648 if (!hotplug_bridges && normal_bridges == 1) {
2649
2650 /*
2651 * There is only one bridge on the bus (upstream
2652 * port) so it gets all available buses which it
2653 * can then distribute to the possible hotplug
2654 * bridges below.
2655 */
2656 buses = available_buses;
2657 } else if (dev->is_hotplug_bridge) {
2658
2659 /*
2660 * Distribute the extra buses between hotplug
2661 * bridges if any.
2662 */
2663 buses = available_buses / hotplug_bridges;
2664 buses = min(buses, available_buses - used_buses);
2665 }
2666
2667 cmax = max;
2668 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2669 used_buses += max - cmax;
2670 }
2671
2672 /*
2673 * Make sure a hotplug bridge has at least the minimum requested
2674 * number of buses but allow it to grow up to the maximum available
2675 * bus number of there is room.
2676 */
2677 if (bus->self && bus->self->is_hotplug_bridge) {
2678 used_buses = max_t(unsigned int, available_buses,
2679 pci_hotplug_bus_size - 1);
2680 if (max - start < used_buses) {
2681 max = start + used_buses;
2682
2683 /* Do not allocate more buses than we have room left */
2684 if (max > bus->busn_res.end)
2685 max = bus->busn_res.end;
2686
2687 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2688 &bus->busn_res, max - start);
2689 }
2690 }
2691
2692 /*
2693 * We've scanned the bus and so we know all about what's on
2694 * the other side of any bridges that may be on this bus plus
2695 * any devices.
2696 *
2697 * Return how far we've got finding sub-buses.
2698 */
2699 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2700 return max;
2701}
2702
2703/**
2704 * pci_scan_child_bus() - Scan devices below a bus
2705 * @bus: Bus to scan for devices
2706 *
2707 * Scans devices below @bus including subordinate buses. Returns new
2708 * subordinate number including all the found devices.
2709 */
2710unsigned int pci_scan_child_bus(struct pci_bus *bus)
2711{
2712 return pci_scan_child_bus_extend(bus, 0);
2713}
2714EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2715
2716/**
2717 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2718 * @bridge: Host bridge to set up
2719 *
2720 * Default empty implementation. Replace with an architecture-specific setup
2721 * routine, if necessary.
2722 */
2723int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2724{
2725 return 0;
2726}
2727
2728void __weak pcibios_add_bus(struct pci_bus *bus)
2729{
2730}
2731
2732void __weak pcibios_remove_bus(struct pci_bus *bus)
2733{
2734}
2735
2736struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2737 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2738{
2739 int error;
2740 struct pci_host_bridge *bridge;
2741
2742 bridge = pci_alloc_host_bridge(0);
2743 if (!bridge)
2744 return NULL;
2745
2746 bridge->dev.parent = parent;
2747
2748 list_splice_init(resources, &bridge->windows);
2749 bridge->sysdata = sysdata;
2750 bridge->busnr = bus;
2751 bridge->ops = ops;
2752
2753 error = pci_register_host_bridge(bridge);
2754 if (error < 0)
2755 goto err_out;
2756
2757 return bridge->bus;
2758
2759err_out:
2760 kfree(bridge);
2761 return NULL;
2762}
2763EXPORT_SYMBOL_GPL(pci_create_root_bus);
2764
2765int pci_host_probe(struct pci_host_bridge *bridge)
2766{
2767 struct pci_bus *bus, *child;
2768 int ret;
2769
2770 ret = pci_scan_root_bus_bridge(bridge);
2771 if (ret < 0) {
2772 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2773 return ret;
2774 }
2775
2776 bus = bridge->bus;
2777
2778 /*
2779 * We insert PCI resources into the iomem_resource and
2780 * ioport_resource trees in either pci_bus_claim_resources()
2781 * or pci_bus_assign_resources().
2782 */
2783 if (pci_has_flag(PCI_PROBE_ONLY)) {
2784 pci_bus_claim_resources(bus);
2785 } else {
2786 pci_bus_size_bridges(bus);
2787 pci_bus_assign_resources(bus);
2788
2789 list_for_each_entry(child, &bus->children, node)
2790 pcie_bus_configure_settings(child);
2791 }
2792
2793 pci_bus_add_devices(bus);
2794 return 0;
2795}
2796EXPORT_SYMBOL_GPL(pci_host_probe);
2797
2798int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2799{
2800 struct resource *res = &b->busn_res;
2801 struct resource *parent_res, *conflict;
2802
2803 res->start = bus;
2804 res->end = bus_max;
2805 res->flags = IORESOURCE_BUS;
2806
2807 if (!pci_is_root_bus(b))
2808 parent_res = &b->parent->busn_res;
2809 else {
2810 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2811 res->flags |= IORESOURCE_PCI_FIXED;
2812 }
2813
2814 conflict = request_resource_conflict(parent_res, res);
2815
2816 if (conflict)
2817 dev_printk(KERN_DEBUG, &b->dev,
2818 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2819 res, pci_is_root_bus(b) ? "domain " : "",
2820 parent_res, conflict->name, conflict);
2821
2822 return conflict == NULL;
2823}
2824
2825int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2826{
2827 struct resource *res = &b->busn_res;
2828 struct resource old_res = *res;
2829 resource_size_t size;
2830 int ret;
2831
2832 if (res->start > bus_max)
2833 return -EINVAL;
2834
2835 size = bus_max - res->start + 1;
2836 ret = adjust_resource(res, res->start, size);
2837 dev_printk(KERN_DEBUG, &b->dev,
2838 "busn_res: %pR end %s updated to %02x\n",
2839 &old_res, ret ? "can not be" : "is", bus_max);
2840
2841 if (!ret && !res->parent)
2842 pci_bus_insert_busn_res(b, res->start, res->end);
2843
2844 return ret;
2845}
2846
2847void pci_bus_release_busn_res(struct pci_bus *b)
2848{
2849 struct resource *res = &b->busn_res;
2850 int ret;
2851
2852 if (!res->flags || !res->parent)
2853 return;
2854
2855 ret = release_resource(res);
2856 dev_printk(KERN_DEBUG, &b->dev,
2857 "busn_res: %pR %s released\n",
2858 res, ret ? "can not be" : "is");
2859}
2860
2861int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2862{
2863 struct resource_entry *window;
2864 bool found = false;
2865 struct pci_bus *b;
2866 int max, bus, ret;
2867
2868 if (!bridge)
2869 return -EINVAL;
2870
2871 resource_list_for_each_entry(window, &bridge->windows)
2872 if (window->res->flags & IORESOURCE_BUS) {
2873 found = true;
2874 break;
2875 }
2876
2877 ret = pci_register_host_bridge(bridge);
2878 if (ret < 0)
2879 return ret;
2880
2881 b = bridge->bus;
2882 bus = bridge->busnr;
2883
2884 if (!found) {
2885 dev_info(&b->dev,
2886 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2887 bus);
2888 pci_bus_insert_busn_res(b, bus, 255);
2889 }
2890
2891 max = pci_scan_child_bus(b);
2892
2893 if (!found)
2894 pci_bus_update_busn_res_end(b, max);
2895
2896 return 0;
2897}
2898EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2899
2900struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2901 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2902{
2903 struct resource_entry *window;
2904 bool found = false;
2905 struct pci_bus *b;
2906 int max;
2907
2908 resource_list_for_each_entry(window, resources)
2909 if (window->res->flags & IORESOURCE_BUS) {
2910 found = true;
2911 break;
2912 }
2913
2914 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2915 if (!b)
2916 return NULL;
2917
2918 if (!found) {
2919 dev_info(&b->dev,
2920 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2921 bus);
2922 pci_bus_insert_busn_res(b, bus, 255);
2923 }
2924
2925 max = pci_scan_child_bus(b);
2926
2927 if (!found)
2928 pci_bus_update_busn_res_end(b, max);
2929
2930 return b;
2931}
2932EXPORT_SYMBOL(pci_scan_root_bus);
2933
2934struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2935 void *sysdata)
2936{
2937 LIST_HEAD(resources);
2938 struct pci_bus *b;
2939
2940 pci_add_resource(&resources, &ioport_resource);
2941 pci_add_resource(&resources, &iomem_resource);
2942 pci_add_resource(&resources, &busn_resource);
2943 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2944 if (b) {
2945 pci_scan_child_bus(b);
2946 } else {
2947 pci_free_resource_list(&resources);
2948 }
2949 return b;
2950}
2951EXPORT_SYMBOL(pci_scan_bus);
2952
2953/**
2954 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
2955 * @bridge: PCI bridge for the bus to scan
2956 *
2957 * Scan a PCI bus and child buses for new devices, add them,
2958 * and enable them, resizing bridge mmio/io resource if necessary
2959 * and possible. The caller must ensure the child devices are already
2960 * removed for resizing to occur.
2961 *
2962 * Returns the max number of subordinate bus discovered.
2963 */
2964unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2965{
2966 unsigned int max;
2967 struct pci_bus *bus = bridge->subordinate;
2968
2969 max = pci_scan_child_bus(bus);
2970
2971 pci_assign_unassigned_bridge_resources(bridge);
2972
2973 pci_bus_add_devices(bus);
2974
2975 return max;
2976}
2977
2978/**
2979 * pci_rescan_bus - Scan a PCI bus for devices
2980 * @bus: PCI bus to scan
2981 *
2982 * Scan a PCI bus and child buses for new devices, add them,
2983 * and enable them.
2984 *
2985 * Returns the max number of subordinate bus discovered.
2986 */
2987unsigned int pci_rescan_bus(struct pci_bus *bus)
2988{
2989 unsigned int max;
2990
2991 max = pci_scan_child_bus(bus);
2992 pci_assign_unassigned_bus_resources(bus);
2993 pci_bus_add_devices(bus);
2994
2995 return max;
2996}
2997EXPORT_SYMBOL_GPL(pci_rescan_bus);
2998
2999/*
3000 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3001 * routines should always be executed under this mutex.
3002 */
3003static DEFINE_MUTEX(pci_rescan_remove_lock);
3004
3005void pci_lock_rescan_remove(void)
3006{
3007 mutex_lock(&pci_rescan_remove_lock);
3008}
3009EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3010
3011void pci_unlock_rescan_remove(void)
3012{
3013 mutex_unlock(&pci_rescan_remove_lock);
3014}
3015EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3016
3017static int __init pci_sort_bf_cmp(const struct device *d_a,
3018 const struct device *d_b)
3019{
3020 const struct pci_dev *a = to_pci_dev(d_a);
3021 const struct pci_dev *b = to_pci_dev(d_b);
3022
3023 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3024 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3025
3026 if (a->bus->number < b->bus->number) return -1;
3027 else if (a->bus->number > b->bus->number) return 1;
3028
3029 if (a->devfn < b->devfn) return -1;
3030 else if (a->devfn > b->devfn) return 1;
3031
3032 return 0;
3033}
3034
3035void __init pci_sort_breadthfirst(void)
3036{
3037 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3038}
3039
3040int pci_hp_add_bridge(struct pci_dev *dev)
3041{
3042 struct pci_bus *parent = dev->bus;
3043 int busnr, start = parent->busn_res.start;
3044 unsigned int available_buses = 0;
3045 int end = parent->busn_res.end;
3046
3047 for (busnr = start; busnr <= end; busnr++) {
3048 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3049 break;
3050 }
3051 if (busnr-- > end) {
3052 pci_err(dev, "No bus number available for hot-added bridge\n");
3053 return -1;
3054 }
3055
3056 /* Scan bridges that are already configured */
3057 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3058
3059 /*
3060 * Distribute the available bus numbers between hotplug-capable
3061 * bridges to make extending the chain later possible.
3062 */
3063 available_buses = end - busnr;
3064
3065 /* Scan bridges that need to be reconfigured */
3066 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3067
3068 if (!dev->subordinate)
3069 return -1;
3070
3071 return 0;
3072}
3073EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/of_device.h>
10#include <linux/of_pci.h>
11#include <linux/pci_hotplug.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
15#include <linux/pci-aspm.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/irqdomain.h>
19#include <linux/pm_runtime.h>
20#include "pci.h"
21
22#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23#define CARDBUS_RESERVE_BUSNR 3
24
25static struct resource busn_resource = {
26 .name = "PCI busn",
27 .start = 0,
28 .end = 255,
29 .flags = IORESOURCE_BUS,
30};
31
32/* Ugh. Need to stop exporting this to modules. */
33LIST_HEAD(pci_root_buses);
34EXPORT_SYMBOL(pci_root_buses);
35
36static LIST_HEAD(pci_domain_busn_res_list);
37
38struct pci_domain_busn_res {
39 struct list_head list;
40 struct resource res;
41 int domain_nr;
42};
43
44static struct resource *get_pci_domain_busn_res(int domain_nr)
45{
46 struct pci_domain_busn_res *r;
47
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
50 return &r->res;
51
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
53 if (!r)
54 return NULL;
55
56 r->domain_nr = domain_nr;
57 r->res.start = 0;
58 r->res.end = 0xff;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
62
63 return &r->res;
64}
65
66static int find_anything(struct device *dev, void *data)
67{
68 return 1;
69}
70
71/*
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
75 */
76int no_pci_devices(void)
77{
78 struct device *dev;
79 int no_devices;
80
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
83 put_device(dev);
84 return no_devices;
85}
86EXPORT_SYMBOL(no_pci_devices);
87
88/*
89 * PCI Bus Class
90 */
91static void release_pcibus_dev(struct device *dev)
92{
93 struct pci_bus *pci_bus = to_pci_bus(dev);
94
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
98 kfree(pci_bus);
99}
100
101static struct class pcibus_class = {
102 .name = "pci_bus",
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
105};
106
107static int __init pcibus_class_init(void)
108{
109 return class_register(&pcibus_class);
110}
111postcore_initcall(pcibus_class_init);
112
113static u64 pci_size(u64 base, u64 maxbase, u64 mask)
114{
115 u64 size = mask & maxbase; /* Find the significant bits */
116 if (!size)
117 return 0;
118
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
122
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
126 return 0;
127
128 return size;
129}
130
131static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132{
133 u32 mem_type;
134 unsigned long flags;
135
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
140 }
141
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
146
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
156 break;
157 default:
158 /* mem unknown type treated as 32-bit BAR */
159 break;
160 }
161 return flags;
162}
163
164#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
166/**
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
172 *
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 */
175int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
177{
178 u32 l, sz, mask;
179 u64 l64, sz64, mask64;
180 u16 orig_cmd;
181 struct pci_bus_region region, inverted_region;
182
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
192 }
193
194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201 /*
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 * 1 must be clear.
206 */
207 if (sz == 0xffffffff)
208 sz = 0;
209
210 /*
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
213 */
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 } else {
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 }
229 } else {
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
235 }
236
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
246 }
247
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
250
251 if (!sz64)
252 goto fail;
253
254 sz64 = pci_size(l64, sz64, mask64);
255 if (!sz64) {
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
258 goto fail;
259 }
260
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
269 goto out;
270 }
271
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
275 res->start = 0;
276 res->end = sz64;
277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
279 goto out;
280 }
281 }
282
283 region.start = l64;
284 region.end = l64 + sz64;
285
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288
289 /*
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
294 *
295 * resource_to_bus(bus_to_resource(A)) == A
296 *
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
299 */
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
302 res->start = 0;
303 res->end = region.end - region.start;
304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
306 }
307
308 goto out;
309
310
311fail:
312 res->flags = 0;
313out:
314 if (res->flags)
315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
316
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318}
319
320static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321{
322 unsigned int pos, reg;
323
324 if (dev->non_compliant_bars)
325 return;
326
327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
331 }
332
333 if (rom) {
334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
335 dev->rom_base_reg = rom;
336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
338 __pci_read_base(dev, pci_bar_mem32, res, rom);
339 }
340}
341
342static void pci_read_bridge_io(struct pci_bus *child)
343{
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
346 unsigned long io_mask, io_granularity, base, limit;
347 struct pci_bus_region region;
348 struct resource *res;
349
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
356 }
357
358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
363
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
366
367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
371 }
372
373 if (base <= limit) {
374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
375 region.start = base;
376 region.end = limit + io_granularity - 1;
377 pcibios_bus_to_resource(dev->bus, res, ®ion);
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
379 }
380}
381
382static void pci_read_bridge_mmio(struct pci_bus *child)
383{
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
389
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 if (base <= limit) {
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.start = base;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
401 }
402}
403
404static void pci_read_bridge_mmio_pref(struct pci_bus *child)
405{
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
408 u64 base64, limit64;
409 pci_bus_addr_t base, limit;
410 struct pci_bus_region region;
411 struct resource *res;
412
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
418
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
421
422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
424
425 /*
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
429 */
430 if (mem_base_hi <= mem_limit_hi) {
431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
433 }
434 }
435
436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
438
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
442 return;
443 }
444
445 if (base <= limit) {
446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
450 region.start = base;
451 region.end = limit + 0xfffff;
452 pcibios_bus_to_resource(dev->bus, res, ®ion);
453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
454 }
455}
456
457void pci_read_bridge_bases(struct pci_bus *child)
458{
459 struct pci_dev *dev = child->self;
460 struct resource *res;
461 int i;
462
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 return;
465
466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 &child->busn_res,
468 dev->transparent ? " (subtractive decode)" : "");
469
470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473
474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
477
478 if (dev->transparent) {
479 pci_bus_for_each_resource(child->parent, res, i) {
480 if (res && res->flags) {
481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
485 res);
486 }
487 }
488 }
489}
490
491static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
492{
493 struct pci_bus *b;
494
495 b = kzalloc(sizeof(*b), GFP_KERNEL);
496 if (!b)
497 return NULL;
498
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
506#ifdef CONFIG_PCI_DOMAINS_GENERIC
507 if (parent)
508 b->domain_nr = parent->domain_nr;
509#endif
510 return b;
511}
512
513static void pci_release_host_bridge_dev(struct device *dev)
514{
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
519
520 pci_free_resource_list(&bridge->windows);
521
522 kfree(bridge);
523}
524
525struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
526{
527 struct pci_host_bridge *bridge;
528
529 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
530 if (!bridge)
531 return NULL;
532
533 INIT_LIST_HEAD(&bridge->windows);
534
535 return bridge;
536}
537EXPORT_SYMBOL(pci_alloc_host_bridge);
538
539static const unsigned char pcix_bus_speed[] = {
540 PCI_SPEED_UNKNOWN, /* 0 */
541 PCI_SPEED_66MHz_PCIX, /* 1 */
542 PCI_SPEED_100MHz_PCIX, /* 2 */
543 PCI_SPEED_133MHz_PCIX, /* 3 */
544 PCI_SPEED_UNKNOWN, /* 4 */
545 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
546 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
547 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
548 PCI_SPEED_UNKNOWN, /* 8 */
549 PCI_SPEED_66MHz_PCIX_266, /* 9 */
550 PCI_SPEED_100MHz_PCIX_266, /* A */
551 PCI_SPEED_133MHz_PCIX_266, /* B */
552 PCI_SPEED_UNKNOWN, /* C */
553 PCI_SPEED_66MHz_PCIX_533, /* D */
554 PCI_SPEED_100MHz_PCIX_533, /* E */
555 PCI_SPEED_133MHz_PCIX_533 /* F */
556};
557
558const unsigned char pcie_link_speed[] = {
559 PCI_SPEED_UNKNOWN, /* 0 */
560 PCIE_SPEED_2_5GT, /* 1 */
561 PCIE_SPEED_5_0GT, /* 2 */
562 PCIE_SPEED_8_0GT, /* 3 */
563 PCI_SPEED_UNKNOWN, /* 4 */
564 PCI_SPEED_UNKNOWN, /* 5 */
565 PCI_SPEED_UNKNOWN, /* 6 */
566 PCI_SPEED_UNKNOWN, /* 7 */
567 PCI_SPEED_UNKNOWN, /* 8 */
568 PCI_SPEED_UNKNOWN, /* 9 */
569 PCI_SPEED_UNKNOWN, /* A */
570 PCI_SPEED_UNKNOWN, /* B */
571 PCI_SPEED_UNKNOWN, /* C */
572 PCI_SPEED_UNKNOWN, /* D */
573 PCI_SPEED_UNKNOWN, /* E */
574 PCI_SPEED_UNKNOWN /* F */
575};
576
577void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
578{
579 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
580}
581EXPORT_SYMBOL_GPL(pcie_update_link_speed);
582
583static unsigned char agp_speeds[] = {
584 AGP_UNKNOWN,
585 AGP_1X,
586 AGP_2X,
587 AGP_4X,
588 AGP_8X
589};
590
591static enum pci_bus_speed agp_speed(int agp3, int agpstat)
592{
593 int index = 0;
594
595 if (agpstat & 4)
596 index = 3;
597 else if (agpstat & 2)
598 index = 2;
599 else if (agpstat & 1)
600 index = 1;
601 else
602 goto out;
603
604 if (agp3) {
605 index += 2;
606 if (index == 5)
607 index = 0;
608 }
609
610 out:
611 return agp_speeds[index];
612}
613
614static void pci_set_bus_speed(struct pci_bus *bus)
615{
616 struct pci_dev *bridge = bus->self;
617 int pos;
618
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
620 if (!pos)
621 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
622 if (pos) {
623 u32 agpstat, agpcmd;
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
626 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
627
628 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
629 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
630 }
631
632 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
633 if (pos) {
634 u16 status;
635 enum pci_bus_speed max;
636
637 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
638 &status);
639
640 if (status & PCI_X_SSTATUS_533MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_533;
642 } else if (status & PCI_X_SSTATUS_266MHZ) {
643 max = PCI_SPEED_133MHz_PCIX_266;
644 } else if (status & PCI_X_SSTATUS_133MHZ) {
645 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
646 max = PCI_SPEED_133MHz_PCIX_ECC;
647 else
648 max = PCI_SPEED_133MHz_PCIX;
649 } else {
650 max = PCI_SPEED_66MHz_PCIX;
651 }
652
653 bus->max_bus_speed = max;
654 bus->cur_bus_speed = pcix_bus_speed[
655 (status & PCI_X_SSTATUS_FREQ) >> 6];
656
657 return;
658 }
659
660 if (pci_is_pcie(bridge)) {
661 u32 linkcap;
662 u16 linksta;
663
664 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
665 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
666
667 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
668 pcie_update_link_speed(bus, linksta);
669 }
670}
671
672static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
673{
674 struct irq_domain *d;
675
676 /*
677 * Any firmware interface that can resolve the msi_domain
678 * should be called from here.
679 */
680 d = pci_host_bridge_of_msi_domain(bus);
681 if (!d)
682 d = pci_host_bridge_acpi_msi_domain(bus);
683
684#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
685 /*
686 * If no IRQ domain was found via the OF tree, try looking it up
687 * directly through the fwnode_handle.
688 */
689 if (!d) {
690 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
691
692 if (fwnode)
693 d = irq_find_matching_fwnode(fwnode,
694 DOMAIN_BUS_PCI_MSI);
695 }
696#endif
697
698 return d;
699}
700
701static void pci_set_bus_msi_domain(struct pci_bus *bus)
702{
703 struct irq_domain *d;
704 struct pci_bus *b;
705
706 /*
707 * The bus can be a root bus, a subordinate bus, or a virtual bus
708 * created by an SR-IOV device. Walk up to the first bridge device
709 * found or derive the domain from the host bridge.
710 */
711 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
712 if (b->self)
713 d = dev_get_msi_domain(&b->self->dev);
714 }
715
716 if (!d)
717 d = pci_host_bridge_msi_domain(b);
718
719 dev_set_msi_domain(&bus->dev, d);
720}
721
722int pci_register_host_bridge(struct pci_host_bridge *bridge)
723{
724 struct device *parent = bridge->dev.parent;
725 struct resource_entry *window, *n;
726 struct pci_bus *bus, *b;
727 resource_size_t offset;
728 LIST_HEAD(resources);
729 struct resource *res;
730 char addr[64], *fmt;
731 const char *name;
732 int err;
733
734 bus = pci_alloc_bus(NULL);
735 if (!bus)
736 return -ENOMEM;
737
738 bridge->bus = bus;
739
740 /* temporarily move resources off the list */
741 list_splice_init(&bridge->windows, &resources);
742 bus->sysdata = bridge->sysdata;
743 bus->msi = bridge->msi;
744 bus->ops = bridge->ops;
745 bus->number = bus->busn_res.start = bridge->busnr;
746#ifdef CONFIG_PCI_DOMAINS_GENERIC
747 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
748#endif
749
750 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
751 if (b) {
752 /* If we already got to this bus through a different bridge, ignore it */
753 dev_dbg(&b->dev, "bus already known\n");
754 err = -EEXIST;
755 goto free;
756 }
757
758 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
759 bridge->busnr);
760
761 err = pcibios_root_bridge_prepare(bridge);
762 if (err)
763 goto free;
764
765 err = device_register(&bridge->dev);
766 if (err)
767 put_device(&bridge->dev);
768
769 bus->bridge = get_device(&bridge->dev);
770 device_enable_async_suspend(bus->bridge);
771 pci_set_bus_of_node(bus);
772 pci_set_bus_msi_domain(bus);
773
774 if (!parent)
775 set_dev_node(bus->bridge, pcibus_to_node(bus));
776
777 bus->dev.class = &pcibus_class;
778 bus->dev.parent = bus->bridge;
779
780 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
781 name = dev_name(&bus->dev);
782
783 err = device_register(&bus->dev);
784 if (err)
785 goto unregister;
786
787 pcibios_add_bus(bus);
788
789 /* Create legacy_io and legacy_mem files for this bus */
790 pci_create_legacy_files(bus);
791
792 if (parent)
793 dev_info(parent, "PCI host bridge to bus %s\n", name);
794 else
795 pr_info("PCI host bridge to bus %s\n", name);
796
797 /* Add initial resources to the bus */
798 resource_list_for_each_entry_safe(window, n, &resources) {
799 list_move_tail(&window->node, &bridge->windows);
800 offset = window->offset;
801 res = window->res;
802
803 if (res->flags & IORESOURCE_BUS)
804 pci_bus_insert_busn_res(bus, bus->number, res->end);
805 else
806 pci_bus_add_resource(bus, res, 0);
807
808 if (offset) {
809 if (resource_type(res) == IORESOURCE_IO)
810 fmt = " (bus address [%#06llx-%#06llx])";
811 else
812 fmt = " (bus address [%#010llx-%#010llx])";
813
814 snprintf(addr, sizeof(addr), fmt,
815 (unsigned long long)(res->start - offset),
816 (unsigned long long)(res->end - offset));
817 } else
818 addr[0] = '\0';
819
820 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
821 }
822
823 down_write(&pci_bus_sem);
824 list_add_tail(&bus->node, &pci_root_buses);
825 up_write(&pci_bus_sem);
826
827 return 0;
828
829unregister:
830 put_device(&bridge->dev);
831 device_unregister(&bridge->dev);
832
833free:
834 kfree(bus);
835 return err;
836}
837EXPORT_SYMBOL(pci_register_host_bridge);
838
839static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
840 struct pci_dev *bridge, int busnr)
841{
842 struct pci_bus *child;
843 int i;
844 int ret;
845
846 /*
847 * Allocate a new bus, and inherit stuff from the parent..
848 */
849 child = pci_alloc_bus(parent);
850 if (!child)
851 return NULL;
852
853 child->parent = parent;
854 child->ops = parent->ops;
855 child->msi = parent->msi;
856 child->sysdata = parent->sysdata;
857 child->bus_flags = parent->bus_flags;
858
859 /* initialize some portions of the bus device, but don't register it
860 * now as the parent is not properly set up yet.
861 */
862 child->dev.class = &pcibus_class;
863 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
864
865 /*
866 * Set up the primary, secondary and subordinate
867 * bus numbers.
868 */
869 child->number = child->busn_res.start = busnr;
870 child->primary = parent->busn_res.start;
871 child->busn_res.end = 0xff;
872
873 if (!bridge) {
874 child->dev.parent = parent->bridge;
875 goto add_dev;
876 }
877
878 child->self = bridge;
879 child->bridge = get_device(&bridge->dev);
880 child->dev.parent = child->bridge;
881 pci_set_bus_of_node(child);
882 pci_set_bus_speed(child);
883
884 /* Set up default resource pointers and names.. */
885 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
886 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
887 child->resource[i]->name = child->name;
888 }
889 bridge->subordinate = child;
890
891add_dev:
892 pci_set_bus_msi_domain(child);
893 ret = device_register(&child->dev);
894 WARN_ON(ret < 0);
895
896 pcibios_add_bus(child);
897
898 if (child->ops->add_bus) {
899 ret = child->ops->add_bus(child);
900 if (WARN_ON(ret < 0))
901 dev_err(&child->dev, "failed to add bus: %d\n", ret);
902 }
903
904 /* Create legacy_io and legacy_mem files for this bus */
905 pci_create_legacy_files(child);
906
907 return child;
908}
909
910struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
911 int busnr)
912{
913 struct pci_bus *child;
914
915 child = pci_alloc_child_bus(parent, dev, busnr);
916 if (child) {
917 down_write(&pci_bus_sem);
918 list_add_tail(&child->node, &parent->children);
919 up_write(&pci_bus_sem);
920 }
921 return child;
922}
923EXPORT_SYMBOL(pci_add_new_bus);
924
925static void pci_enable_crs(struct pci_dev *pdev)
926{
927 u16 root_cap = 0;
928
929 /* Enable CRS Software Visibility if supported */
930 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
931 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
932 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
933 PCI_EXP_RTCTL_CRSSVE);
934}
935
936/*
937 * If it's a bridge, configure it and scan the bus behind it.
938 * For CardBus bridges, we don't scan behind as the devices will
939 * be handled by the bridge driver itself.
940 *
941 * We need to process bridges in two passes -- first we scan those
942 * already configured by the BIOS and after we are done with all of
943 * them, we proceed to assigning numbers to the remaining buses in
944 * order to avoid overlaps between old and new bus numbers.
945 */
946int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
947{
948 struct pci_bus *child;
949 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
950 u32 buses, i, j = 0;
951 u16 bctl;
952 u8 primary, secondary, subordinate;
953 int broken = 0;
954
955 /*
956 * Make sure the bridge is powered on to be able to access config
957 * space of devices below it.
958 */
959 pm_runtime_get_sync(&dev->dev);
960
961 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
962 primary = buses & 0xFF;
963 secondary = (buses >> 8) & 0xFF;
964 subordinate = (buses >> 16) & 0xFF;
965
966 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
967 secondary, subordinate, pass);
968
969 if (!primary && (primary != bus->number) && secondary && subordinate) {
970 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
971 primary = bus->number;
972 }
973
974 /* Check if setup is sensible at all */
975 if (!pass &&
976 (primary != bus->number || secondary <= bus->number ||
977 secondary > subordinate)) {
978 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
979 secondary, subordinate);
980 broken = 1;
981 }
982
983 /* Disable MasterAbortMode during probing to avoid reporting
984 of bus errors (in some architectures) */
985 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
986 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
987 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
988
989 pci_enable_crs(dev);
990
991 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
992 !is_cardbus && !broken) {
993 unsigned int cmax;
994 /*
995 * Bus already configured by firmware, process it in the first
996 * pass and just note the configuration.
997 */
998 if (pass)
999 goto out;
1000
1001 /*
1002 * The bus might already exist for two reasons: Either we are
1003 * rescanning the bus or the bus is reachable through more than
1004 * one bridge. The second case can happen with the i450NX
1005 * chipset.
1006 */
1007 child = pci_find_bus(pci_domain_nr(bus), secondary);
1008 if (!child) {
1009 child = pci_add_new_bus(bus, dev, secondary);
1010 if (!child)
1011 goto out;
1012 child->primary = primary;
1013 pci_bus_insert_busn_res(child, secondary, subordinate);
1014 child->bridge_ctl = bctl;
1015 }
1016
1017 cmax = pci_scan_child_bus(child);
1018 if (cmax > subordinate)
1019 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1020 subordinate, cmax);
1021 /* subordinate should equal child->busn_res.end */
1022 if (subordinate > max)
1023 max = subordinate;
1024 } else {
1025 /*
1026 * We need to assign a number to this bus which we always
1027 * do in the second pass.
1028 */
1029 if (!pass) {
1030 if (pcibios_assign_all_busses() || broken || is_cardbus)
1031 /* Temporarily disable forwarding of the
1032 configuration cycles on all bridges in
1033 this bus segment to avoid possible
1034 conflicts in the second pass between two
1035 bridges programmed with overlapping
1036 bus ranges. */
1037 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1038 buses & ~0xffffff);
1039 goto out;
1040 }
1041
1042 /* Clear errors */
1043 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1044
1045 /* Prevent assigning a bus number that already exists.
1046 * This can happen when a bridge is hot-plugged, so in
1047 * this case we only re-scan this bus. */
1048 child = pci_find_bus(pci_domain_nr(bus), max+1);
1049 if (!child) {
1050 child = pci_add_new_bus(bus, dev, max+1);
1051 if (!child)
1052 goto out;
1053 pci_bus_insert_busn_res(child, max+1, 0xff);
1054 }
1055 max++;
1056 buses = (buses & 0xff000000)
1057 | ((unsigned int)(child->primary) << 0)
1058 | ((unsigned int)(child->busn_res.start) << 8)
1059 | ((unsigned int)(child->busn_res.end) << 16);
1060
1061 /*
1062 * yenta.c forces a secondary latency timer of 176.
1063 * Copy that behaviour here.
1064 */
1065 if (is_cardbus) {
1066 buses &= ~0xff000000;
1067 buses |= CARDBUS_LATENCY_TIMER << 24;
1068 }
1069
1070 /*
1071 * We need to blast all three values with a single write.
1072 */
1073 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1074
1075 if (!is_cardbus) {
1076 child->bridge_ctl = bctl;
1077 max = pci_scan_child_bus(child);
1078 } else {
1079 /*
1080 * For CardBus bridges, we leave 4 bus numbers
1081 * as cards with a PCI-to-PCI bridge can be
1082 * inserted later.
1083 */
1084 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1085 struct pci_bus *parent = bus;
1086 if (pci_find_bus(pci_domain_nr(bus),
1087 max+i+1))
1088 break;
1089 while (parent->parent) {
1090 if ((!pcibios_assign_all_busses()) &&
1091 (parent->busn_res.end > max) &&
1092 (parent->busn_res.end <= max+i)) {
1093 j = 1;
1094 }
1095 parent = parent->parent;
1096 }
1097 if (j) {
1098 /*
1099 * Often, there are two cardbus bridges
1100 * -- try to leave one valid bus number
1101 * for each one.
1102 */
1103 i /= 2;
1104 break;
1105 }
1106 }
1107 max += i;
1108 }
1109 /*
1110 * Set the subordinate bus number to its real value.
1111 */
1112 pci_bus_update_busn_res_end(child, max);
1113 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1114 }
1115
1116 sprintf(child->name,
1117 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1118 pci_domain_nr(bus), child->number);
1119
1120 /* Has only triggered on CardBus, fixup is in yenta_socket */
1121 while (bus->parent) {
1122 if ((child->busn_res.end > bus->busn_res.end) ||
1123 (child->number > bus->busn_res.end) ||
1124 (child->number < bus->number) ||
1125 (child->busn_res.end < bus->number)) {
1126 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1127 &child->busn_res,
1128 (bus->number > child->busn_res.end &&
1129 bus->busn_res.end < child->number) ?
1130 "wholly" : "partially",
1131 bus->self->transparent ? " transparent" : "",
1132 dev_name(&bus->dev),
1133 &bus->busn_res);
1134 }
1135 bus = bus->parent;
1136 }
1137
1138out:
1139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1140
1141 pm_runtime_put(&dev->dev);
1142
1143 return max;
1144}
1145EXPORT_SYMBOL(pci_scan_bridge);
1146
1147/*
1148 * Read interrupt line and base address registers.
1149 * The architecture-dependent code can tweak these, of course.
1150 */
1151static void pci_read_irq(struct pci_dev *dev)
1152{
1153 unsigned char irq;
1154
1155 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1156 dev->pin = irq;
1157 if (irq)
1158 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1159 dev->irq = irq;
1160}
1161
1162void set_pcie_port_type(struct pci_dev *pdev)
1163{
1164 int pos;
1165 u16 reg16;
1166 int type;
1167 struct pci_dev *parent;
1168
1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1170 if (!pos)
1171 return;
1172
1173 pdev->pcie_cap = pos;
1174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1175 pdev->pcie_flags_reg = reg16;
1176 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1177 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1178
1179 /*
1180 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1181 * of a Link. No PCIe component has two Links. Two Links are
1182 * connected by a Switch that has a Port on each Link and internal
1183 * logic to connect the two Ports.
1184 */
1185 type = pci_pcie_type(pdev);
1186 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1187 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1188 pdev->has_secondary_link = 1;
1189 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1190 type == PCI_EXP_TYPE_DOWNSTREAM) {
1191 parent = pci_upstream_bridge(pdev);
1192
1193 /*
1194 * Usually there's an upstream device (Root Port or Switch
1195 * Downstream Port), but we can't assume one exists.
1196 */
1197 if (parent && !parent->has_secondary_link)
1198 pdev->has_secondary_link = 1;
1199 }
1200}
1201
1202void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1203{
1204 u32 reg32;
1205
1206 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1207 if (reg32 & PCI_EXP_SLTCAP_HPC)
1208 pdev->is_hotplug_bridge = 1;
1209}
1210
1211/**
1212 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1213 * @dev: PCI device
1214 *
1215 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1216 * when forwarding a type1 configuration request the bridge must check that
1217 * the extended register address field is zero. The bridge is not permitted
1218 * to forward the transactions and must handle it as an Unsupported Request.
1219 * Some bridges do not follow this rule and simply drop the extended register
1220 * bits, resulting in the standard config space being aliased, every 256
1221 * bytes across the entire configuration space. Test for this condition by
1222 * comparing the first dword of each potential alias to the vendor/device ID.
1223 * Known offenders:
1224 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1225 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1226 */
1227static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1228{
1229#ifdef CONFIG_PCI_QUIRKS
1230 int pos;
1231 u32 header, tmp;
1232
1233 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1234
1235 for (pos = PCI_CFG_SPACE_SIZE;
1236 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1237 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1238 || header != tmp)
1239 return false;
1240 }
1241
1242 return true;
1243#else
1244 return false;
1245#endif
1246}
1247
1248/**
1249 * pci_cfg_space_size - get the configuration space size of the PCI device.
1250 * @dev: PCI device
1251 *
1252 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1253 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1254 * access it. Maybe we don't have a way to generate extended config space
1255 * accesses, or the device is behind a reverse Express bridge. So we try
1256 * reading the dword at 0x100 which must either be 0 or a valid extended
1257 * capability header.
1258 */
1259static int pci_cfg_space_size_ext(struct pci_dev *dev)
1260{
1261 u32 status;
1262 int pos = PCI_CFG_SPACE_SIZE;
1263
1264 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1265 return PCI_CFG_SPACE_SIZE;
1266 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1267 return PCI_CFG_SPACE_SIZE;
1268
1269 return PCI_CFG_SPACE_EXP_SIZE;
1270}
1271
1272int pci_cfg_space_size(struct pci_dev *dev)
1273{
1274 int pos;
1275 u32 status;
1276 u16 class;
1277
1278 class = dev->class >> 8;
1279 if (class == PCI_CLASS_BRIDGE_HOST)
1280 return pci_cfg_space_size_ext(dev);
1281
1282 if (pci_is_pcie(dev))
1283 return pci_cfg_space_size_ext(dev);
1284
1285 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1286 if (!pos)
1287 return PCI_CFG_SPACE_SIZE;
1288
1289 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1290 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1291 return pci_cfg_space_size_ext(dev);
1292
1293 return PCI_CFG_SPACE_SIZE;
1294}
1295
1296#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1297
1298static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1299{
1300 /*
1301 * Disable the MSI hardware to avoid screaming interrupts
1302 * during boot. This is the power on reset default so
1303 * usually this should be a noop.
1304 */
1305 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1306 if (dev->msi_cap)
1307 pci_msi_set_enable(dev, 0);
1308
1309 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1310 if (dev->msix_cap)
1311 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1312}
1313
1314/**
1315 * pci_setup_device - fill in class and map information of a device
1316 * @dev: the device structure to fill
1317 *
1318 * Initialize the device structure with information about the device's
1319 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1320 * Called at initialisation of the PCI subsystem and by CardBus services.
1321 * Returns 0 on success and negative if unknown type of device (not normal,
1322 * bridge or CardBus).
1323 */
1324int pci_setup_device(struct pci_dev *dev)
1325{
1326 u32 class;
1327 u16 cmd;
1328 u8 hdr_type;
1329 int pos = 0;
1330 struct pci_bus_region region;
1331 struct resource *res;
1332
1333 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1334 return -EIO;
1335
1336 dev->sysdata = dev->bus->sysdata;
1337 dev->dev.parent = dev->bus->bridge;
1338 dev->dev.bus = &pci_bus_type;
1339 dev->hdr_type = hdr_type & 0x7f;
1340 dev->multifunction = !!(hdr_type & 0x80);
1341 dev->error_state = pci_channel_io_normal;
1342 set_pcie_port_type(dev);
1343
1344 pci_dev_assign_slot(dev);
1345 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1346 set this higher, assuming the system even supports it. */
1347 dev->dma_mask = 0xffffffff;
1348
1349 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1350 dev->bus->number, PCI_SLOT(dev->devfn),
1351 PCI_FUNC(dev->devfn));
1352
1353 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1354 dev->revision = class & 0xff;
1355 dev->class = class >> 8; /* upper 3 bytes */
1356
1357 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1358 dev->vendor, dev->device, dev->hdr_type, dev->class);
1359
1360 /* need to have dev->class ready */
1361 dev->cfg_size = pci_cfg_space_size(dev);
1362
1363 /* "Unknown power state" */
1364 dev->current_state = PCI_UNKNOWN;
1365
1366 /* Early fixups, before probing the BARs */
1367 pci_fixup_device(pci_fixup_early, dev);
1368 /* device class may be changed after fixup */
1369 class = dev->class >> 8;
1370
1371 if (dev->non_compliant_bars) {
1372 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1373 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1374 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1375 cmd &= ~PCI_COMMAND_IO;
1376 cmd &= ~PCI_COMMAND_MEMORY;
1377 pci_write_config_word(dev, PCI_COMMAND, cmd);
1378 }
1379 }
1380
1381 switch (dev->hdr_type) { /* header type */
1382 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1383 if (class == PCI_CLASS_BRIDGE_PCI)
1384 goto bad;
1385 pci_read_irq(dev);
1386 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1387 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1388 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1389
1390 /*
1391 * Do the ugly legacy mode stuff here rather than broken chip
1392 * quirk code. Legacy mode ATA controllers have fixed
1393 * addresses. These are not always echoed in BAR0-3, and
1394 * BAR0-3 in a few cases contain junk!
1395 */
1396 if (class == PCI_CLASS_STORAGE_IDE) {
1397 u8 progif;
1398 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1399 if ((progif & 1) == 0) {
1400 region.start = 0x1F0;
1401 region.end = 0x1F7;
1402 res = &dev->resource[0];
1403 res->flags = LEGACY_IO_RESOURCE;
1404 pcibios_bus_to_resource(dev->bus, res, ®ion);
1405 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1406 res);
1407 region.start = 0x3F6;
1408 region.end = 0x3F6;
1409 res = &dev->resource[1];
1410 res->flags = LEGACY_IO_RESOURCE;
1411 pcibios_bus_to_resource(dev->bus, res, ®ion);
1412 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1413 res);
1414 }
1415 if ((progif & 4) == 0) {
1416 region.start = 0x170;
1417 region.end = 0x177;
1418 res = &dev->resource[2];
1419 res->flags = LEGACY_IO_RESOURCE;
1420 pcibios_bus_to_resource(dev->bus, res, ®ion);
1421 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1422 res);
1423 region.start = 0x376;
1424 region.end = 0x376;
1425 res = &dev->resource[3];
1426 res->flags = LEGACY_IO_RESOURCE;
1427 pcibios_bus_to_resource(dev->bus, res, ®ion);
1428 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1429 res);
1430 }
1431 }
1432 break;
1433
1434 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1435 if (class != PCI_CLASS_BRIDGE_PCI)
1436 goto bad;
1437 /* The PCI-to-PCI bridge spec requires that subtractive
1438 decoding (i.e. transparent) bridge must have programming
1439 interface code of 0x01. */
1440 pci_read_irq(dev);
1441 dev->transparent = ((dev->class & 0xff) == 1);
1442 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1443 set_pcie_hotplug_bridge(dev);
1444 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1445 if (pos) {
1446 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1447 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1448 }
1449 break;
1450
1451 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1452 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1453 goto bad;
1454 pci_read_irq(dev);
1455 pci_read_bases(dev, 1, 0);
1456 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1457 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1458 break;
1459
1460 default: /* unknown header */
1461 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1462 dev->hdr_type);
1463 return -EIO;
1464
1465 bad:
1466 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1467 dev->class, dev->hdr_type);
1468 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1469 }
1470
1471 /* We found a fine healthy device, go go go... */
1472 return 0;
1473}
1474
1475static void pci_configure_mps(struct pci_dev *dev)
1476{
1477 struct pci_dev *bridge = pci_upstream_bridge(dev);
1478 int mps, p_mps, rc;
1479
1480 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1481 return;
1482
1483 mps = pcie_get_mps(dev);
1484 p_mps = pcie_get_mps(bridge);
1485
1486 if (mps == p_mps)
1487 return;
1488
1489 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1490 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1491 mps, pci_name(bridge), p_mps);
1492 return;
1493 }
1494
1495 /*
1496 * Fancier MPS configuration is done later by
1497 * pcie_bus_configure_settings()
1498 */
1499 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1500 return;
1501
1502 rc = pcie_set_mps(dev, p_mps);
1503 if (rc) {
1504 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1505 p_mps);
1506 return;
1507 }
1508
1509 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1510 p_mps, mps, 128 << dev->pcie_mpss);
1511}
1512
1513static struct hpp_type0 pci_default_type0 = {
1514 .revision = 1,
1515 .cache_line_size = 8,
1516 .latency_timer = 0x40,
1517 .enable_serr = 0,
1518 .enable_perr = 0,
1519};
1520
1521static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1522{
1523 u16 pci_cmd, pci_bctl;
1524
1525 if (!hpp)
1526 hpp = &pci_default_type0;
1527
1528 if (hpp->revision > 1) {
1529 dev_warn(&dev->dev,
1530 "PCI settings rev %d not supported; using defaults\n",
1531 hpp->revision);
1532 hpp = &pci_default_type0;
1533 }
1534
1535 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1536 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1537 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1538 if (hpp->enable_serr)
1539 pci_cmd |= PCI_COMMAND_SERR;
1540 if (hpp->enable_perr)
1541 pci_cmd |= PCI_COMMAND_PARITY;
1542 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1543
1544 /* Program bridge control value */
1545 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1546 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1547 hpp->latency_timer);
1548 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1549 if (hpp->enable_serr)
1550 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1551 if (hpp->enable_perr)
1552 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1553 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1554 }
1555}
1556
1557static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1558{
1559 if (hpp)
1560 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1561}
1562
1563static bool pcie_root_rcb_set(struct pci_dev *dev)
1564{
1565 struct pci_dev *rp = pcie_find_root_port(dev);
1566 u16 lnkctl;
1567
1568 if (!rp)
1569 return false;
1570
1571 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1572 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1573 return true;
1574
1575 return false;
1576}
1577
1578static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1579{
1580 int pos;
1581 u32 reg32;
1582
1583 if (!hpp)
1584 return;
1585
1586 if (hpp->revision > 1) {
1587 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1588 hpp->revision);
1589 return;
1590 }
1591
1592 /*
1593 * Don't allow _HPX to change MPS or MRRS settings. We manage
1594 * those to make sure they're consistent with the rest of the
1595 * platform.
1596 */
1597 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1598 PCI_EXP_DEVCTL_READRQ;
1599 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1600 PCI_EXP_DEVCTL_READRQ);
1601
1602 /* Initialize Device Control Register */
1603 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1604 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1605
1606 /* Initialize Link Control Register */
1607 if (pcie_cap_has_lnkctl(dev)) {
1608
1609 /*
1610 * If the Root Port supports Read Completion Boundary of
1611 * 128, set RCB to 128. Otherwise, clear it.
1612 */
1613 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1614 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1615 if (pcie_root_rcb_set(dev))
1616 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1617
1618 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1619 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1620 }
1621
1622 /* Find Advanced Error Reporting Enhanced Capability */
1623 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1624 if (!pos)
1625 return;
1626
1627 /* Initialize Uncorrectable Error Mask Register */
1628 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1629 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1630 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1631
1632 /* Initialize Uncorrectable Error Severity Register */
1633 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1634 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1635 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1636
1637 /* Initialize Correctable Error Mask Register */
1638 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1639 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1640 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1641
1642 /* Initialize Advanced Error Capabilities and Control Register */
1643 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1644 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1645 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1646
1647 /*
1648 * FIXME: The following two registers are not supported yet.
1649 *
1650 * o Secondary Uncorrectable Error Severity Register
1651 * o Secondary Uncorrectable Error Mask Register
1652 */
1653}
1654
1655static void pci_configure_device(struct pci_dev *dev)
1656{
1657 struct hotplug_params hpp;
1658 int ret;
1659
1660 pci_configure_mps(dev);
1661
1662 memset(&hpp, 0, sizeof(hpp));
1663 ret = pci_get_hp_params(dev, &hpp);
1664 if (ret)
1665 return;
1666
1667 program_hpp_type2(dev, hpp.t2);
1668 program_hpp_type1(dev, hpp.t1);
1669 program_hpp_type0(dev, hpp.t0);
1670}
1671
1672static void pci_release_capabilities(struct pci_dev *dev)
1673{
1674 pci_vpd_release(dev);
1675 pci_iov_release(dev);
1676 pci_free_cap_save_buffers(dev);
1677}
1678
1679/**
1680 * pci_release_dev - free a pci device structure when all users of it are finished.
1681 * @dev: device that's been disconnected
1682 *
1683 * Will be called only by the device core when all users of this pci device are
1684 * done.
1685 */
1686static void pci_release_dev(struct device *dev)
1687{
1688 struct pci_dev *pci_dev;
1689
1690 pci_dev = to_pci_dev(dev);
1691 pci_release_capabilities(pci_dev);
1692 pci_release_of_node(pci_dev);
1693 pcibios_release_device(pci_dev);
1694 pci_bus_put(pci_dev->bus);
1695 kfree(pci_dev->driver_override);
1696 kfree(pci_dev->dma_alias_mask);
1697 kfree(pci_dev);
1698}
1699
1700struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1701{
1702 struct pci_dev *dev;
1703
1704 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1705 if (!dev)
1706 return NULL;
1707
1708 INIT_LIST_HEAD(&dev->bus_list);
1709 dev->dev.type = &pci_dev_type;
1710 dev->bus = pci_bus_get(bus);
1711
1712 return dev;
1713}
1714EXPORT_SYMBOL(pci_alloc_dev);
1715
1716bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1717 int crs_timeout)
1718{
1719 int delay = 1;
1720
1721 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1722 return false;
1723
1724 /* some broken boards return 0 or ~0 if a slot is empty: */
1725 if (*l == 0xffffffff || *l == 0x00000000 ||
1726 *l == 0x0000ffff || *l == 0xffff0000)
1727 return false;
1728
1729 /*
1730 * Configuration Request Retry Status. Some root ports return the
1731 * actual device ID instead of the synthetic ID (0xFFFF) required
1732 * by the PCIe spec. Ignore the device ID and only check for
1733 * (vendor id == 1).
1734 */
1735 while ((*l & 0xffff) == 0x0001) {
1736 if (!crs_timeout)
1737 return false;
1738
1739 msleep(delay);
1740 delay *= 2;
1741 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1742 return false;
1743 /* Card hasn't responded in 60 seconds? Must be stuck. */
1744 if (delay > crs_timeout) {
1745 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1746 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1747 PCI_FUNC(devfn));
1748 return false;
1749 }
1750 }
1751
1752 return true;
1753}
1754EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1755
1756/*
1757 * Read the config data for a PCI device, sanity-check it
1758 * and fill in the dev structure...
1759 */
1760static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1761{
1762 struct pci_dev *dev;
1763 u32 l;
1764
1765 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1766 return NULL;
1767
1768 dev = pci_alloc_dev(bus);
1769 if (!dev)
1770 return NULL;
1771
1772 dev->devfn = devfn;
1773 dev->vendor = l & 0xffff;
1774 dev->device = (l >> 16) & 0xffff;
1775
1776 pci_set_of_node(dev);
1777
1778 if (pci_setup_device(dev)) {
1779 pci_bus_put(dev->bus);
1780 kfree(dev);
1781 return NULL;
1782 }
1783
1784 return dev;
1785}
1786
1787static void pci_init_capabilities(struct pci_dev *dev)
1788{
1789 /* Enhanced Allocation */
1790 pci_ea_init(dev);
1791
1792 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1793 pci_msi_setup_pci_dev(dev);
1794
1795 /* Buffers for saving PCIe and PCI-X capabilities */
1796 pci_allocate_cap_save_buffers(dev);
1797
1798 /* Power Management */
1799 pci_pm_init(dev);
1800
1801 /* Vital Product Data */
1802 pci_vpd_init(dev);
1803
1804 /* Alternative Routing-ID Forwarding */
1805 pci_configure_ari(dev);
1806
1807 /* Single Root I/O Virtualization */
1808 pci_iov_init(dev);
1809
1810 /* Address Translation Services */
1811 pci_ats_init(dev);
1812
1813 /* Enable ACS P2P upstream forwarding */
1814 pci_enable_acs(dev);
1815
1816 /* Precision Time Measurement */
1817 pci_ptm_init(dev);
1818
1819 /* Advanced Error Reporting */
1820 pci_aer_init(dev);
1821}
1822
1823/*
1824 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1825 * devices. Firmware interfaces that can select the MSI domain on a
1826 * per-device basis should be called from here.
1827 */
1828static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1829{
1830 struct irq_domain *d;
1831
1832 /*
1833 * If a domain has been set through the pcibios_add_device
1834 * callback, then this is the one (platform code knows best).
1835 */
1836 d = dev_get_msi_domain(&dev->dev);
1837 if (d)
1838 return d;
1839
1840 /*
1841 * Let's see if we have a firmware interface able to provide
1842 * the domain.
1843 */
1844 d = pci_msi_get_device_domain(dev);
1845 if (d)
1846 return d;
1847
1848 return NULL;
1849}
1850
1851static void pci_set_msi_domain(struct pci_dev *dev)
1852{
1853 struct irq_domain *d;
1854
1855 /*
1856 * If the platform or firmware interfaces cannot supply a
1857 * device-specific MSI domain, then inherit the default domain
1858 * from the host bridge itself.
1859 */
1860 d = pci_dev_msi_domain(dev);
1861 if (!d)
1862 d = dev_get_msi_domain(&dev->bus->dev);
1863
1864 dev_set_msi_domain(&dev->dev, d);
1865}
1866
1867/**
1868 * pci_dma_configure - Setup DMA configuration
1869 * @dev: ptr to pci_dev struct of the PCI device
1870 *
1871 * Function to update PCI devices's DMA configuration using the same
1872 * info from the OF node or ACPI node of host bridge's parent (if any).
1873 */
1874static void pci_dma_configure(struct pci_dev *dev)
1875{
1876 struct device *bridge = pci_get_host_bridge_device(dev);
1877
1878 if (IS_ENABLED(CONFIG_OF) &&
1879 bridge->parent && bridge->parent->of_node) {
1880 of_dma_configure(&dev->dev, bridge->parent->of_node);
1881 } else if (has_acpi_companion(bridge)) {
1882 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1883 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1884
1885 if (attr == DEV_DMA_NOT_SUPPORTED)
1886 dev_warn(&dev->dev, "DMA not supported.\n");
1887 else
1888 acpi_dma_configure(&dev->dev, attr);
1889 }
1890
1891 pci_put_host_bridge_device(bridge);
1892}
1893
1894void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1895{
1896 int ret;
1897
1898 pci_configure_device(dev);
1899
1900 device_initialize(&dev->dev);
1901 dev->dev.release = pci_release_dev;
1902
1903 set_dev_node(&dev->dev, pcibus_to_node(bus));
1904 dev->dev.dma_mask = &dev->dma_mask;
1905 dev->dev.dma_parms = &dev->dma_parms;
1906 dev->dev.coherent_dma_mask = 0xffffffffull;
1907 pci_dma_configure(dev);
1908
1909 pci_set_dma_max_seg_size(dev, 65536);
1910 pci_set_dma_seg_boundary(dev, 0xffffffff);
1911
1912 /* Fix up broken headers */
1913 pci_fixup_device(pci_fixup_header, dev);
1914
1915 /* moved out from quirk header fixup code */
1916 pci_reassigndev_resource_alignment(dev);
1917
1918 /* Clear the state_saved flag. */
1919 dev->state_saved = false;
1920
1921 /* Initialize various capabilities */
1922 pci_init_capabilities(dev);
1923
1924 /*
1925 * Add the device to our list of discovered devices
1926 * and the bus list for fixup functions, etc.
1927 */
1928 down_write(&pci_bus_sem);
1929 list_add_tail(&dev->bus_list, &bus->devices);
1930 up_write(&pci_bus_sem);
1931
1932 ret = pcibios_add_device(dev);
1933 WARN_ON(ret < 0);
1934
1935 /* Setup MSI irq domain */
1936 pci_set_msi_domain(dev);
1937
1938 /* Notifier could use PCI capabilities */
1939 dev->match_driver = false;
1940 ret = device_add(&dev->dev);
1941 WARN_ON(ret < 0);
1942}
1943
1944struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1945{
1946 struct pci_dev *dev;
1947
1948 dev = pci_get_slot(bus, devfn);
1949 if (dev) {
1950 pci_dev_put(dev);
1951 return dev;
1952 }
1953
1954 dev = pci_scan_device(bus, devfn);
1955 if (!dev)
1956 return NULL;
1957
1958 pci_device_add(dev, bus);
1959
1960 return dev;
1961}
1962EXPORT_SYMBOL(pci_scan_single_device);
1963
1964static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1965{
1966 int pos;
1967 u16 cap = 0;
1968 unsigned next_fn;
1969
1970 if (pci_ari_enabled(bus)) {
1971 if (!dev)
1972 return 0;
1973 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1974 if (!pos)
1975 return 0;
1976
1977 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1978 next_fn = PCI_ARI_CAP_NFN(cap);
1979 if (next_fn <= fn)
1980 return 0; /* protect against malformed list */
1981
1982 return next_fn;
1983 }
1984
1985 /* dev may be NULL for non-contiguous multifunction devices */
1986 if (!dev || dev->multifunction)
1987 return (fn + 1) % 8;
1988
1989 return 0;
1990}
1991
1992static int only_one_child(struct pci_bus *bus)
1993{
1994 struct pci_dev *parent = bus->self;
1995
1996 if (!parent || !pci_is_pcie(parent))
1997 return 0;
1998 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1999 return 1;
2000
2001 /*
2002 * PCIe downstream ports are bridges that normally lead to only a
2003 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2004 * possible devices, not just device 0. See PCIe spec r3.0,
2005 * sec 7.3.1.
2006 */
2007 if (parent->has_secondary_link &&
2008 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2009 return 1;
2010 return 0;
2011}
2012
2013/**
2014 * pci_scan_slot - scan a PCI slot on a bus for devices.
2015 * @bus: PCI bus to scan
2016 * @devfn: slot number to scan (must have zero function.)
2017 *
2018 * Scan a PCI slot on the specified PCI bus for devices, adding
2019 * discovered devices to the @bus->devices list. New devices
2020 * will not have is_added set.
2021 *
2022 * Returns the number of new devices found.
2023 */
2024int pci_scan_slot(struct pci_bus *bus, int devfn)
2025{
2026 unsigned fn, nr = 0;
2027 struct pci_dev *dev;
2028
2029 if (only_one_child(bus) && (devfn > 0))
2030 return 0; /* Already scanned the entire slot */
2031
2032 dev = pci_scan_single_device(bus, devfn);
2033 if (!dev)
2034 return 0;
2035 if (!dev->is_added)
2036 nr++;
2037
2038 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2039 dev = pci_scan_single_device(bus, devfn + fn);
2040 if (dev) {
2041 if (!dev->is_added)
2042 nr++;
2043 dev->multifunction = 1;
2044 }
2045 }
2046
2047 /* only one slot has pcie device */
2048 if (bus->self && nr)
2049 pcie_aspm_init_link_state(bus->self);
2050
2051 return nr;
2052}
2053EXPORT_SYMBOL(pci_scan_slot);
2054
2055static int pcie_find_smpss(struct pci_dev *dev, void *data)
2056{
2057 u8 *smpss = data;
2058
2059 if (!pci_is_pcie(dev))
2060 return 0;
2061
2062 /*
2063 * We don't have a way to change MPS settings on devices that have
2064 * drivers attached. A hot-added device might support only the minimum
2065 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2066 * where devices may be hot-added, we limit the fabric MPS to 128 so
2067 * hot-added devices will work correctly.
2068 *
2069 * However, if we hot-add a device to a slot directly below a Root
2070 * Port, it's impossible for there to be other existing devices below
2071 * the port. We don't limit the MPS in this case because we can
2072 * reconfigure MPS on both the Root Port and the hot-added device,
2073 * and there are no other devices involved.
2074 *
2075 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2076 */
2077 if (dev->is_hotplug_bridge &&
2078 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2079 *smpss = 0;
2080
2081 if (*smpss > dev->pcie_mpss)
2082 *smpss = dev->pcie_mpss;
2083
2084 return 0;
2085}
2086
2087static void pcie_write_mps(struct pci_dev *dev, int mps)
2088{
2089 int rc;
2090
2091 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2092 mps = 128 << dev->pcie_mpss;
2093
2094 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2095 dev->bus->self)
2096 /* For "Performance", the assumption is made that
2097 * downstream communication will never be larger than
2098 * the MRRS. So, the MPS only needs to be configured
2099 * for the upstream communication. This being the case,
2100 * walk from the top down and set the MPS of the child
2101 * to that of the parent bus.
2102 *
2103 * Configure the device MPS with the smaller of the
2104 * device MPSS or the bridge MPS (which is assumed to be
2105 * properly configured at this point to the largest
2106 * allowable MPS based on its parent bus).
2107 */
2108 mps = min(mps, pcie_get_mps(dev->bus->self));
2109 }
2110
2111 rc = pcie_set_mps(dev, mps);
2112 if (rc)
2113 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2114}
2115
2116static void pcie_write_mrrs(struct pci_dev *dev)
2117{
2118 int rc, mrrs;
2119
2120 /* In the "safe" case, do not configure the MRRS. There appear to be
2121 * issues with setting MRRS to 0 on a number of devices.
2122 */
2123 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2124 return;
2125
2126 /* For Max performance, the MRRS must be set to the largest supported
2127 * value. However, it cannot be configured larger than the MPS the
2128 * device or the bus can support. This should already be properly
2129 * configured by a prior call to pcie_write_mps.
2130 */
2131 mrrs = pcie_get_mps(dev);
2132
2133 /* MRRS is a R/W register. Invalid values can be written, but a
2134 * subsequent read will verify if the value is acceptable or not.
2135 * If the MRRS value provided is not acceptable (e.g., too large),
2136 * shrink the value until it is acceptable to the HW.
2137 */
2138 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2139 rc = pcie_set_readrq(dev, mrrs);
2140 if (!rc)
2141 break;
2142
2143 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2144 mrrs /= 2;
2145 }
2146
2147 if (mrrs < 128)
2148 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2149}
2150
2151static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2152{
2153 int mps, orig_mps;
2154
2155 if (!pci_is_pcie(dev))
2156 return 0;
2157
2158 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2159 pcie_bus_config == PCIE_BUS_DEFAULT)
2160 return 0;
2161
2162 mps = 128 << *(u8 *)data;
2163 orig_mps = pcie_get_mps(dev);
2164
2165 pcie_write_mps(dev, mps);
2166 pcie_write_mrrs(dev);
2167
2168 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2169 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2170 orig_mps, pcie_get_readrq(dev));
2171
2172 return 0;
2173}
2174
2175/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2176 * parents then children fashion. If this changes, then this code will not
2177 * work as designed.
2178 */
2179void pcie_bus_configure_settings(struct pci_bus *bus)
2180{
2181 u8 smpss = 0;
2182
2183 if (!bus->self)
2184 return;
2185
2186 if (!pci_is_pcie(bus->self))
2187 return;
2188
2189 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2190 * to be aware of the MPS of the destination. To work around this,
2191 * simply force the MPS of the entire system to the smallest possible.
2192 */
2193 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2194 smpss = 0;
2195
2196 if (pcie_bus_config == PCIE_BUS_SAFE) {
2197 smpss = bus->self->pcie_mpss;
2198
2199 pcie_find_smpss(bus->self, &smpss);
2200 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2201 }
2202
2203 pcie_bus_configure_set(bus->self, &smpss);
2204 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2205}
2206EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2207
2208unsigned int pci_scan_child_bus(struct pci_bus *bus)
2209{
2210 unsigned int devfn, pass, max = bus->busn_res.start;
2211 struct pci_dev *dev;
2212
2213 dev_dbg(&bus->dev, "scanning bus\n");
2214
2215 /* Go find them, Rover! */
2216 for (devfn = 0; devfn < 0x100; devfn += 8)
2217 pci_scan_slot(bus, devfn);
2218
2219 /* Reserve buses for SR-IOV capability. */
2220 max += pci_iov_bus_range(bus);
2221
2222 /*
2223 * After performing arch-dependent fixup of the bus, look behind
2224 * all PCI-to-PCI bridges on this bus.
2225 */
2226 if (!bus->is_added) {
2227 dev_dbg(&bus->dev, "fixups for bus\n");
2228 pcibios_fixup_bus(bus);
2229 bus->is_added = 1;
2230 }
2231
2232 for (pass = 0; pass < 2; pass++)
2233 list_for_each_entry(dev, &bus->devices, bus_list) {
2234 if (pci_is_bridge(dev))
2235 max = pci_scan_bridge(bus, dev, max, pass);
2236 }
2237
2238 /*
2239 * Make sure a hotplug bridge has at least the minimum requested
2240 * number of buses.
2241 */
2242 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2243 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2244 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2245 }
2246
2247 /*
2248 * We've scanned the bus and so we know all about what's on
2249 * the other side of any bridges that may be on this bus plus
2250 * any devices.
2251 *
2252 * Return how far we've got finding sub-buses.
2253 */
2254 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2255 return max;
2256}
2257EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2258
2259/**
2260 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2261 * @bridge: Host bridge to set up.
2262 *
2263 * Default empty implementation. Replace with an architecture-specific setup
2264 * routine, if necessary.
2265 */
2266int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2267{
2268 return 0;
2269}
2270
2271void __weak pcibios_add_bus(struct pci_bus *bus)
2272{
2273}
2274
2275void __weak pcibios_remove_bus(struct pci_bus *bus)
2276{
2277}
2278
2279static struct pci_bus *pci_create_root_bus_msi(struct device *parent,
2280 int bus, struct pci_ops *ops, void *sysdata,
2281 struct list_head *resources, struct msi_controller *msi)
2282{
2283 int error;
2284 struct pci_host_bridge *bridge;
2285
2286 bridge = pci_alloc_host_bridge(0);
2287 if (!bridge)
2288 return NULL;
2289
2290 bridge->dev.parent = parent;
2291 bridge->dev.release = pci_release_host_bridge_dev;
2292
2293 list_splice_init(resources, &bridge->windows);
2294 bridge->sysdata = sysdata;
2295 bridge->busnr = bus;
2296 bridge->ops = ops;
2297 bridge->msi = msi;
2298
2299 error = pci_register_host_bridge(bridge);
2300 if (error < 0)
2301 goto err_out;
2302
2303 return bridge->bus;
2304
2305err_out:
2306 kfree(bridge);
2307 return NULL;
2308}
2309
2310struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2311 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2312{
2313 return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources,
2314 NULL);
2315}
2316EXPORT_SYMBOL_GPL(pci_create_root_bus);
2317
2318int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2319{
2320 struct resource *res = &b->busn_res;
2321 struct resource *parent_res, *conflict;
2322
2323 res->start = bus;
2324 res->end = bus_max;
2325 res->flags = IORESOURCE_BUS;
2326
2327 if (!pci_is_root_bus(b))
2328 parent_res = &b->parent->busn_res;
2329 else {
2330 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2331 res->flags |= IORESOURCE_PCI_FIXED;
2332 }
2333
2334 conflict = request_resource_conflict(parent_res, res);
2335
2336 if (conflict)
2337 dev_printk(KERN_DEBUG, &b->dev,
2338 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2339 res, pci_is_root_bus(b) ? "domain " : "",
2340 parent_res, conflict->name, conflict);
2341
2342 return conflict == NULL;
2343}
2344
2345int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2346{
2347 struct resource *res = &b->busn_res;
2348 struct resource old_res = *res;
2349 resource_size_t size;
2350 int ret;
2351
2352 if (res->start > bus_max)
2353 return -EINVAL;
2354
2355 size = bus_max - res->start + 1;
2356 ret = adjust_resource(res, res->start, size);
2357 dev_printk(KERN_DEBUG, &b->dev,
2358 "busn_res: %pR end %s updated to %02x\n",
2359 &old_res, ret ? "can not be" : "is", bus_max);
2360
2361 if (!ret && !res->parent)
2362 pci_bus_insert_busn_res(b, res->start, res->end);
2363
2364 return ret;
2365}
2366
2367void pci_bus_release_busn_res(struct pci_bus *b)
2368{
2369 struct resource *res = &b->busn_res;
2370 int ret;
2371
2372 if (!res->flags || !res->parent)
2373 return;
2374
2375 ret = release_resource(res);
2376 dev_printk(KERN_DEBUG, &b->dev,
2377 "busn_res: %pR %s released\n",
2378 res, ret ? "can not be" : "is");
2379}
2380
2381struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2382 struct pci_ops *ops, void *sysdata,
2383 struct list_head *resources, struct msi_controller *msi)
2384{
2385 struct resource_entry *window;
2386 bool found = false;
2387 struct pci_bus *b;
2388 int max;
2389
2390 resource_list_for_each_entry(window, resources)
2391 if (window->res->flags & IORESOURCE_BUS) {
2392 found = true;
2393 break;
2394 }
2395
2396 b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi);
2397 if (!b)
2398 return NULL;
2399
2400 if (!found) {
2401 dev_info(&b->dev,
2402 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2403 bus);
2404 pci_bus_insert_busn_res(b, bus, 255);
2405 }
2406
2407 max = pci_scan_child_bus(b);
2408
2409 if (!found)
2410 pci_bus_update_busn_res_end(b, max);
2411
2412 return b;
2413}
2414
2415struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2416 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2417{
2418 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2419 NULL);
2420}
2421EXPORT_SYMBOL(pci_scan_root_bus);
2422
2423struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2424 void *sysdata)
2425{
2426 LIST_HEAD(resources);
2427 struct pci_bus *b;
2428
2429 pci_add_resource(&resources, &ioport_resource);
2430 pci_add_resource(&resources, &iomem_resource);
2431 pci_add_resource(&resources, &busn_resource);
2432 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2433 if (b) {
2434 pci_scan_child_bus(b);
2435 } else {
2436 pci_free_resource_list(&resources);
2437 }
2438 return b;
2439}
2440EXPORT_SYMBOL(pci_scan_bus);
2441
2442/**
2443 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2444 * @bridge: PCI bridge for the bus to scan
2445 *
2446 * Scan a PCI bus and child buses for new devices, add them,
2447 * and enable them, resizing bridge mmio/io resource if necessary
2448 * and possible. The caller must ensure the child devices are already
2449 * removed for resizing to occur.
2450 *
2451 * Returns the max number of subordinate bus discovered.
2452 */
2453unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2454{
2455 unsigned int max;
2456 struct pci_bus *bus = bridge->subordinate;
2457
2458 max = pci_scan_child_bus(bus);
2459
2460 pci_assign_unassigned_bridge_resources(bridge);
2461
2462 pci_bus_add_devices(bus);
2463
2464 return max;
2465}
2466
2467/**
2468 * pci_rescan_bus - scan a PCI bus for devices.
2469 * @bus: PCI bus to scan
2470 *
2471 * Scan a PCI bus and child buses for new devices, adds them,
2472 * and enables them.
2473 *
2474 * Returns the max number of subordinate bus discovered.
2475 */
2476unsigned int pci_rescan_bus(struct pci_bus *bus)
2477{
2478 unsigned int max;
2479
2480 max = pci_scan_child_bus(bus);
2481 pci_assign_unassigned_bus_resources(bus);
2482 pci_bus_add_devices(bus);
2483
2484 return max;
2485}
2486EXPORT_SYMBOL_GPL(pci_rescan_bus);
2487
2488/*
2489 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2490 * routines should always be executed under this mutex.
2491 */
2492static DEFINE_MUTEX(pci_rescan_remove_lock);
2493
2494void pci_lock_rescan_remove(void)
2495{
2496 mutex_lock(&pci_rescan_remove_lock);
2497}
2498EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2499
2500void pci_unlock_rescan_remove(void)
2501{
2502 mutex_unlock(&pci_rescan_remove_lock);
2503}
2504EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2505
2506static int __init pci_sort_bf_cmp(const struct device *d_a,
2507 const struct device *d_b)
2508{
2509 const struct pci_dev *a = to_pci_dev(d_a);
2510 const struct pci_dev *b = to_pci_dev(d_b);
2511
2512 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2513 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2514
2515 if (a->bus->number < b->bus->number) return -1;
2516 else if (a->bus->number > b->bus->number) return 1;
2517
2518 if (a->devfn < b->devfn) return -1;
2519 else if (a->devfn > b->devfn) return 1;
2520
2521 return 0;
2522}
2523
2524void __init pci_sort_breadthfirst(void)
2525{
2526 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2527}