1/*
  2 * Marvell 88E6xxx Address Translation Unit (ATU) support
  3 *
  4 * Copyright (c) 2008 Marvell Semiconductor
  5 * Copyright (c) 2017 Savoir-faire Linux, Inc.
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License as published by
  9 * the Free Software Foundation; either version 2 of the License, or
 10 * (at your option) any later version.
 11 */
 12#include <linux/interrupt.h>
 13#include <linux/irqdomain.h>
 14
 15#include "chip.h"
 16#include "global1.h"
 17
 18/* Offset 0x01: ATU FID Register */
 19
 20static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
 21{
 22	return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
 23}
 24
 25/* Offset 0x0A: ATU Control Register */
 26
 27int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
 28{
 29	u16 val;
 30	int err;
 31
 32	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
 33	if (err)
 34		return err;
 35
 36	if (learn2all)
 37		val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
 38	else
 39		val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
 40
 41	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
 42}
 43
 44int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
 45				  unsigned int msecs)
 46{
 47	const unsigned int coeff = chip->info->age_time_coeff;
 48	const unsigned int min = 0x01 * coeff;
 49	const unsigned int max = 0xff * coeff;
 50	u8 age_time;
 51	u16 val;
 52	int err;
 53
 54	if (msecs < min || msecs > max)
 55		return -ERANGE;
 56
 57	/* Round to nearest multiple of coeff */
 58	age_time = (msecs + coeff / 2) / coeff;
 59
 60	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
 61	if (err)
 62		return err;
 63
 64	/* AgeTime is 11:4 bits */
 65	val &= ~0xff0;
 66	val |= age_time << 4;
 67
 68	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
 69	if (err)
 70		return err;
 71
 72	dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
 73		age_time * coeff);
 74
 75	return 0;
 76}
 77
 78/* Offset 0x0B: ATU Operation Register */
 79
 80static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
 81{
 82	return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP,
 83				 MV88E6XXX_G1_ATU_OP_BUSY);
 84}
 85
 86static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
 87{
 88	u16 val;
 89	int err;
 90
 91	/* FID bits are dispatched all around gradually as more are supported */
 92	if (mv88e6xxx_num_databases(chip) > 256) {
 93		err = mv88e6xxx_g1_atu_fid_write(chip, fid);
 94		if (err)
 95			return err;
 96	} else {
 97		if (mv88e6xxx_num_databases(chip) > 16) {
 98			/* ATU DBNum[7:4] are located in ATU Control 15:12 */
 99			err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
100						&val);
101			if (err)
102				return err;
103
104			val = (val & 0x0fff) | ((fid << 8) & 0xf000);
105			err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
106						 val);
107			if (err)
108				return err;
109		}
110
111		/* ATU DBNum[3:0] are located in ATU Operation 3:0 */
112		op |= fid & 0xf;
113	}
114
115	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
116				 MV88E6XXX_G1_ATU_OP_BUSY | op);
117	if (err)
118		return err;
119
120	return mv88e6xxx_g1_atu_op_wait(chip);
121}
122
123/* Offset 0x0C: ATU Data Register */
124
125static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
126				      struct mv88e6xxx_atu_entry *entry)
127{
128	u16 val;
129	int err;
130
131	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
132	if (err)
133		return err;
134
135	entry->state = val & 0xf;
136	if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
137		entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK);
138		entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
139	}
140
141	return 0;
142}
143
144static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
145				       struct mv88e6xxx_atu_entry *entry)
146{
147	u16 data = entry->state & 0xf;
148
149	if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
150		if (entry->trunk)
151			data |= MV88E6XXX_G1_ATU_DATA_TRUNK;
152
153		data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
154	}
155
156	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
157}
158
159/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
160 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
161 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
162 */
163
164static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
165				     struct mv88e6xxx_atu_entry *entry)
166{
167	u16 val;
168	int i, err;
169
170	for (i = 0; i < 3; i++) {
171		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
172		if (err)
173			return err;
174
175		entry->mac[i * 2] = val >> 8;
176		entry->mac[i * 2 + 1] = val & 0xff;
177	}
178
179	return 0;
180}
181
182static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
183				      struct mv88e6xxx_atu_entry *entry)
184{
185	u16 val;
186	int i, err;
187
188	for (i = 0; i < 3; i++) {
189		val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1];
190		err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
191		if (err)
192			return err;
193	}
194
195	return 0;
196}
197
198/* Address Translation Unit operations */
199
200int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
201			     struct mv88e6xxx_atu_entry *entry)
202{
203	int err;
204
205	err = mv88e6xxx_g1_atu_op_wait(chip);
206	if (err)
207		return err;
208
209	/* Write the MAC address to iterate from only once */
210	if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
211		err = mv88e6xxx_g1_atu_mac_write(chip, entry);
212		if (err)
213			return err;
214	}
215
216	err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
217	if (err)
218		return err;
219
220	err = mv88e6xxx_g1_atu_data_read(chip, entry);
221	if (err)
222		return err;
223
224	return mv88e6xxx_g1_atu_mac_read(chip, entry);
225}
226
227int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
228			       struct mv88e6xxx_atu_entry *entry)
229{
230	int err;
231
232	err = mv88e6xxx_g1_atu_op_wait(chip);
233	if (err)
234		return err;
235
236	err = mv88e6xxx_g1_atu_mac_write(chip, entry);
237	if (err)
238		return err;
239
240	err = mv88e6xxx_g1_atu_data_write(chip, entry);
241	if (err)
242		return err;
243
244	return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
245}
246
247static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
248				      struct mv88e6xxx_atu_entry *entry,
249				      bool all)
250{
251	u16 op;
252	int err;
253
254	err = mv88e6xxx_g1_atu_op_wait(chip);
255	if (err)
256		return err;
257
258	err = mv88e6xxx_g1_atu_data_write(chip, entry);
259	if (err)
260		return err;
261
262	/* Flush/Move all or non-static entries from all or a given database */
263	if (all && fid)
264		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB;
265	else if (fid)
266		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
267	else if (all)
268		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL;
269	else
270		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC;
271
272	return mv88e6xxx_g1_atu_op(chip, fid, op);
273}
274
275int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
276{
277	struct mv88e6xxx_atu_entry entry = {
278		.state = 0, /* Null EntryState means Flush */
279	};
280
281	return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
282}
283
284static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
285				 int from_port, int to_port, bool all)
286{
287	struct mv88e6xxx_atu_entry entry = { 0 };
288	unsigned long mask;
289	int shift;
290
291	if (!chip->info->atu_move_port_mask)
292		return -EOPNOTSUPP;
293
294	mask = chip->info->atu_move_port_mask;
295	shift = bitmap_weight(&mask, 16);
296
297	entry.state = 0xf, /* Full EntryState means Move */
298	entry.portvec = from_port & mask;
299	entry.portvec |= (to_port & mask) << shift;
300
301	return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
302}
303
304int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
305			    bool all)
306{
307	int from_port = port;
308	int to_port = chip->info->atu_move_port_mask;
309
310	return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
311}
312
313static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id)
314{
315	struct mv88e6xxx_chip *chip = dev_id;
316	struct mv88e6xxx_atu_entry entry;
317	int err;
318	u16 val;
319
320	mutex_lock(&chip->reg_lock);
321
322	err = mv88e6xxx_g1_atu_op(chip, 0,
323				  MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION);
324	if (err)
325		goto out;
326
327	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val);
328	if (err)
329		goto out;
330
331	err = mv88e6xxx_g1_atu_data_read(chip, &entry);
332	if (err)
333		goto out;
334
335	err = mv88e6xxx_g1_atu_mac_read(chip, &entry);
336	if (err)
337		goto out;
338
339	if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) {
340		dev_err_ratelimited(chip->dev,
341				    "ATU age out violation for %pM\n",
342				    entry.mac);
343	}
344
345	if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) {
346		dev_err_ratelimited(chip->dev,
347				    "ATU member violation for %pM portvec %x\n",
348				    entry.mac, entry.portvec);
349		chip->ports[entry.portvec].atu_member_violation++;
350	}
351
352	if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) {
353		dev_err_ratelimited(chip->dev,
354				    "ATU miss violation for %pM portvec %x\n",
355				    entry.mac, entry.portvec);
356		chip->ports[entry.portvec].atu_miss_violation++;
357	}
358
359	if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) {
360		dev_err_ratelimited(chip->dev,
361				    "ATU full violation for %pM portvec %x\n",
362				    entry.mac, entry.portvec);
363		chip->ports[entry.portvec].atu_full_violation++;
364	}
365	mutex_unlock(&chip->reg_lock);
366
367	return IRQ_HANDLED;
368
369out:
370	mutex_unlock(&chip->reg_lock);
371
372	dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
373		err);
374	return IRQ_HANDLED;
375}
376
377int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip)
378{
379	int err;
380
381	chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
382					      MV88E6XXX_G1_STS_IRQ_ATU_PROB);
383	if (chip->atu_prob_irq < 0)
384		return chip->atu_prob_irq;
385
386	err = request_threaded_irq(chip->atu_prob_irq, NULL,
387				   mv88e6xxx_g1_atu_prob_irq_thread_fn,
388				   IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob",
389				   chip);
390	if (err)
391		irq_dispose_mapping(chip->atu_prob_irq);
392
393	return err;
394}
395
396void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip)
397{
398	free_irq(chip->atu_prob_irq, chip);
399	irq_dispose_mapping(chip->atu_prob_irq);
400}