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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34#include "dce_v11_0.h"
35
36#include "dce/dce_11_0_d.h"
37#include "dce/dce_11_0_sh_mask.h"
38#include "dce/dce_11_0_enum.h"
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "gmc/gmc_8_1_sh_mask.h"
43
44static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46
47static const u32 crtc_offsets[] =
48{
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56};
57
58static const u32 hpd_offsets[] =
59{
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66};
67
68static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET,
76 DIG7_REGISTER_OFFSET,
77 DIG8_REGISTER_OFFSET
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static const u32 cz_golden_settings_a11[] =
119{
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
122};
123
124static const u32 cz_mgcg_cgcg_init[] =
125{
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128};
129
130static const u32 stoney_golden_settings_a11[] =
131{
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
134};
135
136static const u32 polaris11_golden_settings_a11[] =
137{
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
143};
144
145static const u32 polaris10_golden_settings_a11[] =
146{
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
151};
152
153static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154{
155 switch (adev->asic_type) {
156 case CHIP_CARRIZO:
157 amdgpu_device_program_register_sequence(adev,
158 cz_mgcg_cgcg_init,
159 ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_device_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 ARRAY_SIZE(cz_golden_settings_a11));
163 break;
164 case CHIP_STONEY:
165 amdgpu_device_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 ARRAY_SIZE(stoney_golden_settings_a11));
168 break;
169 case CHIP_POLARIS11:
170 case CHIP_POLARIS12:
171 amdgpu_device_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 ARRAY_SIZE(polaris11_golden_settings_a11));
174 break;
175 case CHIP_POLARIS10:
176 amdgpu_device_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 ARRAY_SIZE(polaris10_golden_settings_a11));
179 break;
180 default:
181 break;
182 }
183}
184
185static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
187{
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195
196 return r;
197}
198
199static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
201{
202 unsigned long flags;
203
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208}
209
210static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
211{
212 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
213 return 0;
214 else
215 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
216}
217
218static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
219{
220 unsigned i;
221
222 /* Enable pflip interrupts */
223 for (i = 0; i < adev->mode_info.num_crtc; i++)
224 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
225}
226
227static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
228{
229 unsigned i;
230
231 /* Disable pflip interrupts */
232 for (i = 0; i < adev->mode_info.num_crtc; i++)
233 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
234}
235
236/**
237 * dce_v11_0_page_flip - pageflip callback.
238 *
239 * @adev: amdgpu_device pointer
240 * @crtc_id: crtc to cleanup pageflip on
241 * @crtc_base: new address of the crtc (GPU MC address)
242 *
243 * Triggers the actual pageflip by updating the primary
244 * surface base address.
245 */
246static void dce_v11_0_page_flip(struct amdgpu_device *adev,
247 int crtc_id, u64 crtc_base, bool async)
248{
249 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
250 u32 tmp;
251
252 /* flip immediate for async, default is vsync */
253 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
254 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
255 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
256 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
257 /* update the scanout addresses */
258 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
259 upper_32_bits(crtc_base));
260 /* writing to the low address triggers the update */
261 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
262 lower_32_bits(crtc_base));
263 /* post the write */
264 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
265}
266
267static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
268 u32 *vbl, u32 *position)
269{
270 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 return -EINVAL;
272
273 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
274 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
275
276 return 0;
277}
278
279/**
280 * dce_v11_0_hpd_sense - hpd sense callback.
281 *
282 * @adev: amdgpu_device pointer
283 * @hpd: hpd (hotplug detect) pin
284 *
285 * Checks if a digital monitor is connected (evergreen+).
286 * Returns true if connected, false if not connected.
287 */
288static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
289 enum amdgpu_hpd_id hpd)
290{
291 bool connected = false;
292
293 if (hpd >= adev->mode_info.num_hpd)
294 return connected;
295
296 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
297 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
298 connected = true;
299
300 return connected;
301}
302
303/**
304 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
305 *
306 * @adev: amdgpu_device pointer
307 * @hpd: hpd (hotplug detect) pin
308 *
309 * Set the polarity of the hpd pin (evergreen+).
310 */
311static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
312 enum amdgpu_hpd_id hpd)
313{
314 u32 tmp;
315 bool connected = dce_v11_0_hpd_sense(adev, hpd);
316
317 if (hpd >= adev->mode_info.num_hpd)
318 return;
319
320 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
321 if (connected)
322 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
323 else
324 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
326}
327
328/**
329 * dce_v11_0_hpd_init - hpd setup callback.
330 *
331 * @adev: amdgpu_device pointer
332 *
333 * Setup the hpd pins used by the card (evergreen+).
334 * Enable the pin, set the polarity, and enable the hpd interrupts.
335 */
336static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
337{
338 struct drm_device *dev = adev->ddev;
339 struct drm_connector *connector;
340 u32 tmp;
341
342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
343 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
344
345 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
346 continue;
347
348 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
349 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
350 /* don't try to enable hpd on eDP or LVDS avoid breaking the
351 * aux dp channel on imac and help (but not completely fix)
352 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
353 * also avoid interrupt storms during dpms.
354 */
355 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
357 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358 continue;
359 }
360
361 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
362 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
363 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
364
365 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
366 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
367 DC_HPD_CONNECT_INT_DELAY,
368 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
369 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
370 DC_HPD_DISCONNECT_INT_DELAY,
371 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
372 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
373
374 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
375 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
376 }
377}
378
379/**
380 * dce_v11_0_hpd_fini - hpd tear down callback.
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Tear down the hpd pins used by the card (evergreen+).
385 * Disable the hpd interrupts.
386 */
387static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
388{
389 struct drm_device *dev = adev->ddev;
390 struct drm_connector *connector;
391 u32 tmp;
392
393 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
394 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
395
396 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
397 continue;
398
399 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
400 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
401 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
402
403 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
404 }
405}
406
407static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
408{
409 return mmDC_GPIO_HPD_A;
410}
411
412static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
413{
414 u32 crtc_hung = 0;
415 u32 crtc_status[6];
416 u32 i, j, tmp;
417
418 for (i = 0; i < adev->mode_info.num_crtc; i++) {
419 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
420 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
421 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
422 crtc_hung |= (1 << i);
423 }
424 }
425
426 for (j = 0; j < 10; j++) {
427 for (i = 0; i < adev->mode_info.num_crtc; i++) {
428 if (crtc_hung & (1 << i)) {
429 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
430 if (tmp != crtc_status[i])
431 crtc_hung &= ~(1 << i);
432 }
433 }
434 if (crtc_hung == 0)
435 return false;
436 udelay(100);
437 }
438
439 return true;
440}
441
442static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
443 bool render)
444{
445 u32 tmp;
446
447 /* Lockout access through VGA aperture*/
448 tmp = RREG32(mmVGA_HDP_CONTROL);
449 if (render)
450 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
451 else
452 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
453 WREG32(mmVGA_HDP_CONTROL, tmp);
454
455 /* disable VGA render */
456 tmp = RREG32(mmVGA_RENDER_CONTROL);
457 if (render)
458 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
459 else
460 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
461 WREG32(mmVGA_RENDER_CONTROL, tmp);
462}
463
464static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
465{
466 int num_crtc = 0;
467
468 switch (adev->asic_type) {
469 case CHIP_CARRIZO:
470 num_crtc = 3;
471 break;
472 case CHIP_STONEY:
473 num_crtc = 2;
474 break;
475 case CHIP_POLARIS10:
476 num_crtc = 6;
477 break;
478 case CHIP_POLARIS11:
479 case CHIP_POLARIS12:
480 num_crtc = 5;
481 break;
482 default:
483 num_crtc = 0;
484 }
485 return num_crtc;
486}
487
488void dce_v11_0_disable_dce(struct amdgpu_device *adev)
489{
490 /*Disable VGA render and enabled crtc, if has DCE engine*/
491 if (amdgpu_atombios_has_dce_engine_info(adev)) {
492 u32 tmp;
493 int crtc_enabled, i;
494
495 dce_v11_0_set_vga_render_state(adev, false);
496
497 /*Disable crtc*/
498 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
499 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
500 CRTC_CONTROL, CRTC_MASTER_EN);
501 if (crtc_enabled) {
502 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
503 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
504 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
505 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
506 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
507 }
508 }
509 }
510}
511
512static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
513{
514 struct drm_device *dev = encoder->dev;
515 struct amdgpu_device *adev = dev->dev_private;
516 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
518 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
519 int bpc = 0;
520 u32 tmp = 0;
521 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
522
523 if (connector) {
524 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
525 bpc = amdgpu_connector_get_monitor_bpc(connector);
526 dither = amdgpu_connector->dither;
527 }
528
529 /* LVDS/eDP FMT is set up by atom */
530 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
531 return;
532
533 /* not needed for analog */
534 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
535 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
536 return;
537
538 if (bpc == 0)
539 return;
540
541 switch (bpc) {
542 case 6:
543 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
544 /* XXX sort out optimal dither settings */
545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
546 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
549 } else {
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
552 }
553 break;
554 case 8:
555 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
556 /* XXX sort out optimal dither settings */
557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
559 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
561 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
562 } else {
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
565 }
566 break;
567 case 10:
568 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
569 /* XXX sort out optimal dither settings */
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
575 } else {
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
578 }
579 break;
580 default:
581 /* not needed */
582 break;
583 }
584
585 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
586}
587
588
589/* display watermark setup */
590/**
591 * dce_v11_0_line_buffer_adjust - Set up the line buffer
592 *
593 * @adev: amdgpu_device pointer
594 * @amdgpu_crtc: the selected display controller
595 * @mode: the current display mode on the selected display
596 * controller
597 *
598 * Setup up the line buffer allocation for
599 * the selected display controller (CIK).
600 * Returns the line buffer size in pixels.
601 */
602static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
603 struct amdgpu_crtc *amdgpu_crtc,
604 struct drm_display_mode *mode)
605{
606 u32 tmp, buffer_alloc, i, mem_cfg;
607 u32 pipe_offset = amdgpu_crtc->crtc_id;
608 /*
609 * Line Buffer Setup
610 * There are 6 line buffers, one for each display controllers.
611 * There are 3 partitions per LB. Select the number of partitions
612 * to enable based on the display width. For display widths larger
613 * than 4096, you need use to use 2 display controllers and combine
614 * them using the stereo blender.
615 */
616 if (amdgpu_crtc->base.enabled && mode) {
617 if (mode->crtc_hdisplay < 1920) {
618 mem_cfg = 1;
619 buffer_alloc = 2;
620 } else if (mode->crtc_hdisplay < 2560) {
621 mem_cfg = 2;
622 buffer_alloc = 2;
623 } else if (mode->crtc_hdisplay < 4096) {
624 mem_cfg = 0;
625 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
626 } else {
627 DRM_DEBUG_KMS("Mode too big for LB!\n");
628 mem_cfg = 0;
629 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
630 }
631 } else {
632 mem_cfg = 1;
633 buffer_alloc = 0;
634 }
635
636 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
637 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
638 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
639
640 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
641 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
642 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
643
644 for (i = 0; i < adev->usec_timeout; i++) {
645 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
646 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
647 break;
648 udelay(1);
649 }
650
651 if (amdgpu_crtc->base.enabled && mode) {
652 switch (mem_cfg) {
653 case 0:
654 default:
655 return 4096 * 2;
656 case 1:
657 return 1920 * 2;
658 case 2:
659 return 2560 * 2;
660 }
661 }
662
663 /* controller not enabled, so no lb used */
664 return 0;
665}
666
667/**
668 * cik_get_number_of_dram_channels - get the number of dram channels
669 *
670 * @adev: amdgpu_device pointer
671 *
672 * Look up the number of video ram channels (CIK).
673 * Used for display watermark bandwidth calculations
674 * Returns the number of dram channels
675 */
676static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
677{
678 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
679
680 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
681 case 0:
682 default:
683 return 1;
684 case 1:
685 return 2;
686 case 2:
687 return 4;
688 case 3:
689 return 8;
690 case 4:
691 return 3;
692 case 5:
693 return 6;
694 case 6:
695 return 10;
696 case 7:
697 return 12;
698 case 8:
699 return 16;
700 }
701}
702
703struct dce10_wm_params {
704 u32 dram_channels; /* number of dram channels */
705 u32 yclk; /* bandwidth per dram data pin in kHz */
706 u32 sclk; /* engine clock in kHz */
707 u32 disp_clk; /* display clock in kHz */
708 u32 src_width; /* viewport width */
709 u32 active_time; /* active display time in ns */
710 u32 blank_time; /* blank time in ns */
711 bool interlaced; /* mode is interlaced */
712 fixed20_12 vsc; /* vertical scale ratio */
713 u32 num_heads; /* number of active crtcs */
714 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
715 u32 lb_size; /* line buffer allocated to pipe */
716 u32 vtaps; /* vertical scaler taps */
717};
718
719/**
720 * dce_v11_0_dram_bandwidth - get the dram bandwidth
721 *
722 * @wm: watermark calculation data
723 *
724 * Calculate the raw dram bandwidth (CIK).
725 * Used for display watermark bandwidth calculations
726 * Returns the dram bandwidth in MBytes/s
727 */
728static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
729{
730 /* Calculate raw DRAM Bandwidth */
731 fixed20_12 dram_efficiency; /* 0.7 */
732 fixed20_12 yclk, dram_channels, bandwidth;
733 fixed20_12 a;
734
735 a.full = dfixed_const(1000);
736 yclk.full = dfixed_const(wm->yclk);
737 yclk.full = dfixed_div(yclk, a);
738 dram_channels.full = dfixed_const(wm->dram_channels * 4);
739 a.full = dfixed_const(10);
740 dram_efficiency.full = dfixed_const(7);
741 dram_efficiency.full = dfixed_div(dram_efficiency, a);
742 bandwidth.full = dfixed_mul(dram_channels, yclk);
743 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
744
745 return dfixed_trunc(bandwidth);
746}
747
748/**
749 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
750 *
751 * @wm: watermark calculation data
752 *
753 * Calculate the dram bandwidth used for display (CIK).
754 * Used for display watermark bandwidth calculations
755 * Returns the dram bandwidth for display in MBytes/s
756 */
757static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
758{
759 /* Calculate DRAM Bandwidth and the part allocated to display. */
760 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
761 fixed20_12 yclk, dram_channels, bandwidth;
762 fixed20_12 a;
763
764 a.full = dfixed_const(1000);
765 yclk.full = dfixed_const(wm->yclk);
766 yclk.full = dfixed_div(yclk, a);
767 dram_channels.full = dfixed_const(wm->dram_channels * 4);
768 a.full = dfixed_const(10);
769 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
770 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
771 bandwidth.full = dfixed_mul(dram_channels, yclk);
772 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
773
774 return dfixed_trunc(bandwidth);
775}
776
777/**
778 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
779 *
780 * @wm: watermark calculation data
781 *
782 * Calculate the data return bandwidth used for display (CIK).
783 * Used for display watermark bandwidth calculations
784 * Returns the data return bandwidth in MBytes/s
785 */
786static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
787{
788 /* Calculate the display Data return Bandwidth */
789 fixed20_12 return_efficiency; /* 0.8 */
790 fixed20_12 sclk, bandwidth;
791 fixed20_12 a;
792
793 a.full = dfixed_const(1000);
794 sclk.full = dfixed_const(wm->sclk);
795 sclk.full = dfixed_div(sclk, a);
796 a.full = dfixed_const(10);
797 return_efficiency.full = dfixed_const(8);
798 return_efficiency.full = dfixed_div(return_efficiency, a);
799 a.full = dfixed_const(32);
800 bandwidth.full = dfixed_mul(a, sclk);
801 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
802
803 return dfixed_trunc(bandwidth);
804}
805
806/**
807 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
808 *
809 * @wm: watermark calculation data
810 *
811 * Calculate the dmif bandwidth used for display (CIK).
812 * Used for display watermark bandwidth calculations
813 * Returns the dmif bandwidth in MBytes/s
814 */
815static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
816{
817 /* Calculate the DMIF Request Bandwidth */
818 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
819 fixed20_12 disp_clk, bandwidth;
820 fixed20_12 a, b;
821
822 a.full = dfixed_const(1000);
823 disp_clk.full = dfixed_const(wm->disp_clk);
824 disp_clk.full = dfixed_div(disp_clk, a);
825 a.full = dfixed_const(32);
826 b.full = dfixed_mul(a, disp_clk);
827
828 a.full = dfixed_const(10);
829 disp_clk_request_efficiency.full = dfixed_const(8);
830 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
831
832 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
833
834 return dfixed_trunc(bandwidth);
835}
836
837/**
838 * dce_v11_0_available_bandwidth - get the min available bandwidth
839 *
840 * @wm: watermark calculation data
841 *
842 * Calculate the min available bandwidth used for display (CIK).
843 * Used for display watermark bandwidth calculations
844 * Returns the min available bandwidth in MBytes/s
845 */
846static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
847{
848 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
849 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
850 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
851 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
852
853 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
854}
855
856/**
857 * dce_v11_0_average_bandwidth - get the average available bandwidth
858 *
859 * @wm: watermark calculation data
860 *
861 * Calculate the average available bandwidth used for display (CIK).
862 * Used for display watermark bandwidth calculations
863 * Returns the average available bandwidth in MBytes/s
864 */
865static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
866{
867 /* Calculate the display mode Average Bandwidth
868 * DisplayMode should contain the source and destination dimensions,
869 * timing, etc.
870 */
871 fixed20_12 bpp;
872 fixed20_12 line_time;
873 fixed20_12 src_width;
874 fixed20_12 bandwidth;
875 fixed20_12 a;
876
877 a.full = dfixed_const(1000);
878 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
879 line_time.full = dfixed_div(line_time, a);
880 bpp.full = dfixed_const(wm->bytes_per_pixel);
881 src_width.full = dfixed_const(wm->src_width);
882 bandwidth.full = dfixed_mul(src_width, bpp);
883 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
884 bandwidth.full = dfixed_div(bandwidth, line_time);
885
886 return dfixed_trunc(bandwidth);
887}
888
889/**
890 * dce_v11_0_latency_watermark - get the latency watermark
891 *
892 * @wm: watermark calculation data
893 *
894 * Calculate the latency watermark (CIK).
895 * Used for display watermark bandwidth calculations
896 * Returns the latency watermark in ns
897 */
898static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
899{
900 /* First calculate the latency in ns */
901 u32 mc_latency = 2000; /* 2000 ns. */
902 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
903 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
904 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
905 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
906 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
907 (wm->num_heads * cursor_line_pair_return_time);
908 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
909 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
910 u32 tmp, dmif_size = 12288;
911 fixed20_12 a, b, c;
912
913 if (wm->num_heads == 0)
914 return 0;
915
916 a.full = dfixed_const(2);
917 b.full = dfixed_const(1);
918 if ((wm->vsc.full > a.full) ||
919 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
920 (wm->vtaps >= 5) ||
921 ((wm->vsc.full >= a.full) && wm->interlaced))
922 max_src_lines_per_dst_line = 4;
923 else
924 max_src_lines_per_dst_line = 2;
925
926 a.full = dfixed_const(available_bandwidth);
927 b.full = dfixed_const(wm->num_heads);
928 a.full = dfixed_div(a, b);
929 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
930 tmp = min(dfixed_trunc(a), tmp);
931
932 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
933
934 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
935 b.full = dfixed_const(1000);
936 c.full = dfixed_const(lb_fill_bw);
937 b.full = dfixed_div(c, b);
938 a.full = dfixed_div(a, b);
939 line_fill_time = dfixed_trunc(a);
940
941 if (line_fill_time < wm->active_time)
942 return latency;
943 else
944 return latency + (line_fill_time - wm->active_time);
945
946}
947
948/**
949 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
950 * average and available dram bandwidth
951 *
952 * @wm: watermark calculation data
953 *
954 * Check if the display average bandwidth fits in the display
955 * dram bandwidth (CIK).
956 * Used for display watermark bandwidth calculations
957 * Returns true if the display fits, false if not.
958 */
959static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
960{
961 if (dce_v11_0_average_bandwidth(wm) <=
962 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
963 return true;
964 else
965 return false;
966}
967
968/**
969 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
970 * average and available bandwidth
971 *
972 * @wm: watermark calculation data
973 *
974 * Check if the display average bandwidth fits in the display
975 * available bandwidth (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns true if the display fits, false if not.
978 */
979static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
980{
981 if (dce_v11_0_average_bandwidth(wm) <=
982 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
983 return true;
984 else
985 return false;
986}
987
988/**
989 * dce_v11_0_check_latency_hiding - check latency hiding
990 *
991 * @wm: watermark calculation data
992 *
993 * Check latency hiding (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns true if the display fits, false if not.
996 */
997static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
998{
999 u32 lb_partitions = wm->lb_size / wm->src_width;
1000 u32 line_time = wm->active_time + wm->blank_time;
1001 u32 latency_tolerant_lines;
1002 u32 latency_hiding;
1003 fixed20_12 a;
1004
1005 a.full = dfixed_const(1);
1006 if (wm->vsc.full > a.full)
1007 latency_tolerant_lines = 1;
1008 else {
1009 if (lb_partitions <= (wm->vtaps + 1))
1010 latency_tolerant_lines = 1;
1011 else
1012 latency_tolerant_lines = 2;
1013 }
1014
1015 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1016
1017 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1018 return true;
1019 else
1020 return false;
1021}
1022
1023/**
1024 * dce_v11_0_program_watermarks - program display watermarks
1025 *
1026 * @adev: amdgpu_device pointer
1027 * @amdgpu_crtc: the selected display controller
1028 * @lb_size: line buffer size
1029 * @num_heads: number of display controllers in use
1030 *
1031 * Calculate and program the display watermarks for the
1032 * selected display controller (CIK).
1033 */
1034static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1035 struct amdgpu_crtc *amdgpu_crtc,
1036 u32 lb_size, u32 num_heads)
1037{
1038 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1039 struct dce10_wm_params wm_low, wm_high;
1040 u32 active_time;
1041 u32 line_time = 0;
1042 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1043 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1044
1045 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1046 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1047 (u32)mode->clock);
1048 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1049 (u32)mode->clock);
1050 line_time = min(line_time, (u32)65535);
1051
1052 /* watermark for high clocks */
1053 if (adev->pm.dpm_enabled) {
1054 wm_high.yclk =
1055 amdgpu_dpm_get_mclk(adev, false) * 10;
1056 wm_high.sclk =
1057 amdgpu_dpm_get_sclk(adev, false) * 10;
1058 } else {
1059 wm_high.yclk = adev->pm.current_mclk * 10;
1060 wm_high.sclk = adev->pm.current_sclk * 10;
1061 }
1062
1063 wm_high.disp_clk = mode->clock;
1064 wm_high.src_width = mode->crtc_hdisplay;
1065 wm_high.active_time = active_time;
1066 wm_high.blank_time = line_time - wm_high.active_time;
1067 wm_high.interlaced = false;
1068 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1069 wm_high.interlaced = true;
1070 wm_high.vsc = amdgpu_crtc->vsc;
1071 wm_high.vtaps = 1;
1072 if (amdgpu_crtc->rmx_type != RMX_OFF)
1073 wm_high.vtaps = 2;
1074 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1075 wm_high.lb_size = lb_size;
1076 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1077 wm_high.num_heads = num_heads;
1078
1079 /* set for high clocks */
1080 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1081
1082 /* possibly force display priority to high */
1083 /* should really do this at mode validation time... */
1084 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1085 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1086 !dce_v11_0_check_latency_hiding(&wm_high) ||
1087 (adev->mode_info.disp_priority == 2)) {
1088 DRM_DEBUG_KMS("force priority to high\n");
1089 }
1090
1091 /* watermark for low clocks */
1092 if (adev->pm.dpm_enabled) {
1093 wm_low.yclk =
1094 amdgpu_dpm_get_mclk(adev, true) * 10;
1095 wm_low.sclk =
1096 amdgpu_dpm_get_sclk(adev, true) * 10;
1097 } else {
1098 wm_low.yclk = adev->pm.current_mclk * 10;
1099 wm_low.sclk = adev->pm.current_sclk * 10;
1100 }
1101
1102 wm_low.disp_clk = mode->clock;
1103 wm_low.src_width = mode->crtc_hdisplay;
1104 wm_low.active_time = active_time;
1105 wm_low.blank_time = line_time - wm_low.active_time;
1106 wm_low.interlaced = false;
1107 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1108 wm_low.interlaced = true;
1109 wm_low.vsc = amdgpu_crtc->vsc;
1110 wm_low.vtaps = 1;
1111 if (amdgpu_crtc->rmx_type != RMX_OFF)
1112 wm_low.vtaps = 2;
1113 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1114 wm_low.lb_size = lb_size;
1115 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1116 wm_low.num_heads = num_heads;
1117
1118 /* set for low clocks */
1119 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1120
1121 /* possibly force display priority to high */
1122 /* should really do this at mode validation time... */
1123 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1124 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1125 !dce_v11_0_check_latency_hiding(&wm_low) ||
1126 (adev->mode_info.disp_priority == 2)) {
1127 DRM_DEBUG_KMS("force priority to high\n");
1128 }
1129 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1130 }
1131
1132 /* select wm A */
1133 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1134 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1135 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1136 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1137 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1138 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1139 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1140 /* select wm B */
1141 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1142 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1143 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1144 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1145 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1146 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1147 /* restore original selection */
1148 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1149
1150 /* save values for DPM */
1151 amdgpu_crtc->line_time = line_time;
1152 amdgpu_crtc->wm_high = latency_watermark_a;
1153 amdgpu_crtc->wm_low = latency_watermark_b;
1154 /* Save number of lines the linebuffer leads before the scanout */
1155 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1156}
1157
1158/**
1159 * dce_v11_0_bandwidth_update - program display watermarks
1160 *
1161 * @adev: amdgpu_device pointer
1162 *
1163 * Calculate and program the display watermarks and line
1164 * buffer allocation (CIK).
1165 */
1166static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1167{
1168 struct drm_display_mode *mode = NULL;
1169 u32 num_heads = 0, lb_size;
1170 int i;
1171
1172 amdgpu_display_update_priority(adev);
1173
1174 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1175 if (adev->mode_info.crtcs[i]->base.enabled)
1176 num_heads++;
1177 }
1178 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1179 mode = &adev->mode_info.crtcs[i]->base.mode;
1180 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1181 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1182 lb_size, num_heads);
1183 }
1184}
1185
1186static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1187{
1188 int i;
1189 u32 offset, tmp;
1190
1191 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1192 offset = adev->mode_info.audio.pin[i].offset;
1193 tmp = RREG32_AUDIO_ENDPT(offset,
1194 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1195 if (((tmp &
1196 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1197 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1198 adev->mode_info.audio.pin[i].connected = false;
1199 else
1200 adev->mode_info.audio.pin[i].connected = true;
1201 }
1202}
1203
1204static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1205{
1206 int i;
1207
1208 dce_v11_0_audio_get_connected_pins(adev);
1209
1210 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1211 if (adev->mode_info.audio.pin[i].connected)
1212 return &adev->mode_info.audio.pin[i];
1213 }
1214 DRM_ERROR("No connected audio pins found!\n");
1215 return NULL;
1216}
1217
1218static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1219{
1220 struct amdgpu_device *adev = encoder->dev->dev_private;
1221 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1222 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1223 u32 tmp;
1224
1225 if (!dig || !dig->afmt || !dig->afmt->pin)
1226 return;
1227
1228 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1229 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1230 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1231}
1232
1233static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1234 struct drm_display_mode *mode)
1235{
1236 struct amdgpu_device *adev = encoder->dev->dev_private;
1237 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1238 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1239 struct drm_connector *connector;
1240 struct amdgpu_connector *amdgpu_connector = NULL;
1241 u32 tmp;
1242 int interlace = 0;
1243
1244 if (!dig || !dig->afmt || !dig->afmt->pin)
1245 return;
1246
1247 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1248 if (connector->encoder == encoder) {
1249 amdgpu_connector = to_amdgpu_connector(connector);
1250 break;
1251 }
1252 }
1253
1254 if (!amdgpu_connector) {
1255 DRM_ERROR("Couldn't find encoder's connector\n");
1256 return;
1257 }
1258
1259 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1260 interlace = 1;
1261 if (connector->latency_present[interlace]) {
1262 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1264 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1265 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1266 } else {
1267 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1268 VIDEO_LIPSYNC, 0);
1269 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1270 AUDIO_LIPSYNC, 0);
1271 }
1272 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1273 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1274}
1275
1276static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1277{
1278 struct amdgpu_device *adev = encoder->dev->dev_private;
1279 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1280 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1281 struct drm_connector *connector;
1282 struct amdgpu_connector *amdgpu_connector = NULL;
1283 u32 tmp;
1284 u8 *sadb = NULL;
1285 int sad_count;
1286
1287 if (!dig || !dig->afmt || !dig->afmt->pin)
1288 return;
1289
1290 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1291 if (connector->encoder == encoder) {
1292 amdgpu_connector = to_amdgpu_connector(connector);
1293 break;
1294 }
1295 }
1296
1297 if (!amdgpu_connector) {
1298 DRM_ERROR("Couldn't find encoder's connector\n");
1299 return;
1300 }
1301
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1303 if (sad_count < 0) {
1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 sad_count = 0;
1306 }
1307
1308 /* program the speaker allocation */
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1310 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1311 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 DP_CONNECTION, 0);
1313 /* set HDMI mode */
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 HDMI_CONNECTION, 1);
1316 if (sad_count)
1317 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 SPEAKER_ALLOCATION, sadb[0]);
1319 else
1320 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1321 SPEAKER_ALLOCATION, 5); /* stereo */
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1323 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1324
1325 kfree(sadb);
1326}
1327
1328static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1329{
1330 struct amdgpu_device *adev = encoder->dev->dev_private;
1331 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1332 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1333 struct drm_connector *connector;
1334 struct amdgpu_connector *amdgpu_connector = NULL;
1335 struct cea_sad *sads;
1336 int i, sad_count;
1337
1338 static const u16 eld_reg_to_type[][2] = {
1339 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1340 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1341 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1342 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1351 };
1352
1353 if (!dig || !dig->afmt || !dig->afmt->pin)
1354 return;
1355
1356 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1357 if (connector->encoder == encoder) {
1358 amdgpu_connector = to_amdgpu_connector(connector);
1359 break;
1360 }
1361 }
1362
1363 if (!amdgpu_connector) {
1364 DRM_ERROR("Couldn't find encoder's connector\n");
1365 return;
1366 }
1367
1368 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1369 if (sad_count <= 0) {
1370 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1371 return;
1372 }
1373 BUG_ON(!sads);
1374
1375 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1376 u32 tmp = 0;
1377 u8 stereo_freqs = 0;
1378 int max_channels = -1;
1379 int j;
1380
1381 for (j = 0; j < sad_count; j++) {
1382 struct cea_sad *sad = &sads[j];
1383
1384 if (sad->format == eld_reg_to_type[i][1]) {
1385 if (sad->channels > max_channels) {
1386 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1387 MAX_CHANNELS, sad->channels);
1388 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1389 DESCRIPTOR_BYTE_2, sad->byte2);
1390 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391 SUPPORTED_FREQUENCIES, sad->freq);
1392 max_channels = sad->channels;
1393 }
1394
1395 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1396 stereo_freqs |= sad->freq;
1397 else
1398 break;
1399 }
1400 }
1401
1402 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1403 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1404 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1405 }
1406
1407 kfree(sads);
1408}
1409
1410static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1411 struct amdgpu_audio_pin *pin,
1412 bool enable)
1413{
1414 if (!pin)
1415 return;
1416
1417 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1418 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1419}
1420
1421static const u32 pin_offsets[] =
1422{
1423 AUD0_REGISTER_OFFSET,
1424 AUD1_REGISTER_OFFSET,
1425 AUD2_REGISTER_OFFSET,
1426 AUD3_REGISTER_OFFSET,
1427 AUD4_REGISTER_OFFSET,
1428 AUD5_REGISTER_OFFSET,
1429 AUD6_REGISTER_OFFSET,
1430 AUD7_REGISTER_OFFSET,
1431};
1432
1433static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1434{
1435 int i;
1436
1437 if (!amdgpu_audio)
1438 return 0;
1439
1440 adev->mode_info.audio.enabled = true;
1441
1442 switch (adev->asic_type) {
1443 case CHIP_CARRIZO:
1444 case CHIP_STONEY:
1445 adev->mode_info.audio.num_pins = 7;
1446 break;
1447 case CHIP_POLARIS10:
1448 adev->mode_info.audio.num_pins = 8;
1449 break;
1450 case CHIP_POLARIS11:
1451 case CHIP_POLARIS12:
1452 adev->mode_info.audio.num_pins = 6;
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1459 adev->mode_info.audio.pin[i].channels = -1;
1460 adev->mode_info.audio.pin[i].rate = -1;
1461 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1462 adev->mode_info.audio.pin[i].status_bits = 0;
1463 adev->mode_info.audio.pin[i].category_code = 0;
1464 adev->mode_info.audio.pin[i].connected = false;
1465 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1466 adev->mode_info.audio.pin[i].id = i;
1467 /* disable audio. it will be set up later */
1468 /* XXX remove once we switch to ip funcs */
1469 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1470 }
1471
1472 return 0;
1473}
1474
1475static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1476{
1477 int i;
1478
1479 if (!amdgpu_audio)
1480 return;
1481
1482 if (!adev->mode_info.audio.enabled)
1483 return;
1484
1485 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1486 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1487
1488 adev->mode_info.audio.enabled = false;
1489}
1490
1491/*
1492 * update the N and CTS parameters for a given pixel clock rate
1493 */
1494static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1495{
1496 struct drm_device *dev = encoder->dev;
1497 struct amdgpu_device *adev = dev->dev_private;
1498 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1499 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1500 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1501 u32 tmp;
1502
1503 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1504 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1505 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1506 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1507 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1508 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1509
1510 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1511 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1512 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1513 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1514 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1515 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1516
1517 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1518 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1519 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1520 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1521 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1522 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1523
1524}
1525
1526/*
1527 * build a HDMI Video Info Frame
1528 */
1529static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1530 void *buffer, size_t size)
1531{
1532 struct drm_device *dev = encoder->dev;
1533 struct amdgpu_device *adev = dev->dev_private;
1534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1535 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1536 uint8_t *frame = buffer + 3;
1537 uint8_t *header = buffer;
1538
1539 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1540 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1541 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1542 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1543 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1544 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1545 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1546 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1547}
1548
1549static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1550{
1551 struct drm_device *dev = encoder->dev;
1552 struct amdgpu_device *adev = dev->dev_private;
1553 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1554 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1555 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1556 u32 dto_phase = 24 * 1000;
1557 u32 dto_modulo = clock;
1558 u32 tmp;
1559
1560 if (!dig || !dig->afmt)
1561 return;
1562
1563 /* XXX two dtos; generally use dto0 for hdmi */
1564 /* Express [24MHz / target pixel clock] as an exact rational
1565 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1566 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1567 */
1568 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1569 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1570 amdgpu_crtc->crtc_id);
1571 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1572 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1573 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1574}
1575
1576/*
1577 * update the info frames with the data from the current display mode
1578 */
1579static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1580 struct drm_display_mode *mode)
1581{
1582 struct drm_device *dev = encoder->dev;
1583 struct amdgpu_device *adev = dev->dev_private;
1584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1585 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1586 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1587 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1588 struct hdmi_avi_infoframe frame;
1589 ssize_t err;
1590 u32 tmp;
1591 int bpc = 8;
1592
1593 if (!dig || !dig->afmt)
1594 return;
1595
1596 /* Silent, r600_hdmi_enable will raise WARN for us */
1597 if (!dig->afmt->enabled)
1598 return;
1599
1600 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1601 if (encoder->crtc) {
1602 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1603 bpc = amdgpu_crtc->bpc;
1604 }
1605
1606 /* disable audio prior to setting up hw */
1607 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1608 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1609
1610 dce_v11_0_audio_set_dto(encoder, mode->clock);
1611
1612 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1613 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1614 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1615
1616 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1617
1618 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1619 switch (bpc) {
1620 case 0:
1621 case 6:
1622 case 8:
1623 case 16:
1624 default:
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1627 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1628 connector->name, bpc);
1629 break;
1630 case 10:
1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1632 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1633 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1634 connector->name);
1635 break;
1636 case 12:
1637 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1638 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1639 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1640 connector->name);
1641 break;
1642 }
1643 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1644
1645 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1646 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1647 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1648 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1649 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1650
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1652 /* enable audio info frames (frames won't be set until audio is enabled) */
1653 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1654 /* required for audio info values to be updated */
1655 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1656 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1657
1658 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1659 /* required for audio info values to be updated */
1660 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1661 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1662
1663 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1664 /* anything other than 0 */
1665 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1666 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1667
1668 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1669
1670 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1671 /* set the default audio delay */
1672 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1673 /* should be suffient for all audio modes and small enough for all hblanks */
1674 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1675 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1676
1677 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1678 /* allow 60958 channel status fields to be updated */
1679 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1680 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1681
1682 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1683 if (bpc > 8)
1684 /* clear SW CTS value */
1685 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1686 else
1687 /* select SW CTS value */
1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1689 /* allow hw to sent ACR packets when required */
1690 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1691 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1692
1693 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1694
1695 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1696 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1697 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1698
1699 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1700 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1701 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1702
1703 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1704 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1705 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1706 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1707 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1708 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1709 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1710 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1711
1712 dce_v11_0_audio_write_speaker_allocation(encoder);
1713
1714 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1715 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1716
1717 dce_v11_0_afmt_audio_select_pin(encoder);
1718 dce_v11_0_audio_write_sad_regs(encoder);
1719 dce_v11_0_audio_write_latency_fields(encoder, mode);
1720
1721 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1722 if (err < 0) {
1723 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1724 return;
1725 }
1726
1727 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1728 if (err < 0) {
1729 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1730 return;
1731 }
1732
1733 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1734
1735 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1736 /* enable AVI info frames */
1737 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1738 /* required for audio info values to be updated */
1739 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1740 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1741
1742 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1743 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1744 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1745
1746 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1747 /* send audio packets */
1748 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1749 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1750
1751 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1752 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1753 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1754 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1755
1756 /* enable audio after to setting up hw */
1757 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1758}
1759
1760static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1761{
1762 struct drm_device *dev = encoder->dev;
1763 struct amdgpu_device *adev = dev->dev_private;
1764 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1765 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1766
1767 if (!dig || !dig->afmt)
1768 return;
1769
1770 /* Silent, r600_hdmi_enable will raise WARN for us */
1771 if (enable && dig->afmt->enabled)
1772 return;
1773 if (!enable && !dig->afmt->enabled)
1774 return;
1775
1776 if (!enable && dig->afmt->pin) {
1777 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1778 dig->afmt->pin = NULL;
1779 }
1780
1781 dig->afmt->enabled = enable;
1782
1783 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1784 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1785}
1786
1787static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1788{
1789 int i;
1790
1791 for (i = 0; i < adev->mode_info.num_dig; i++)
1792 adev->mode_info.afmt[i] = NULL;
1793
1794 /* DCE11 has audio blocks tied to DIG encoders */
1795 for (i = 0; i < adev->mode_info.num_dig; i++) {
1796 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1797 if (adev->mode_info.afmt[i]) {
1798 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1799 adev->mode_info.afmt[i]->id = i;
1800 } else {
1801 int j;
1802 for (j = 0; j < i; j++) {
1803 kfree(adev->mode_info.afmt[j]);
1804 adev->mode_info.afmt[j] = NULL;
1805 }
1806 return -ENOMEM;
1807 }
1808 }
1809 return 0;
1810}
1811
1812static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1813{
1814 int i;
1815
1816 for (i = 0; i < adev->mode_info.num_dig; i++) {
1817 kfree(adev->mode_info.afmt[i]);
1818 adev->mode_info.afmt[i] = NULL;
1819 }
1820}
1821
1822static const u32 vga_control_regs[6] =
1823{
1824 mmD1VGA_CONTROL,
1825 mmD2VGA_CONTROL,
1826 mmD3VGA_CONTROL,
1827 mmD4VGA_CONTROL,
1828 mmD5VGA_CONTROL,
1829 mmD6VGA_CONTROL,
1830};
1831
1832static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1833{
1834 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1835 struct drm_device *dev = crtc->dev;
1836 struct amdgpu_device *adev = dev->dev_private;
1837 u32 vga_control;
1838
1839 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1840 if (enable)
1841 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1842 else
1843 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1844}
1845
1846static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1847{
1848 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1849 struct drm_device *dev = crtc->dev;
1850 struct amdgpu_device *adev = dev->dev_private;
1851
1852 if (enable)
1853 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1854 else
1855 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1856}
1857
1858static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1859 struct drm_framebuffer *fb,
1860 int x, int y, int atomic)
1861{
1862 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1863 struct drm_device *dev = crtc->dev;
1864 struct amdgpu_device *adev = dev->dev_private;
1865 struct amdgpu_framebuffer *amdgpu_fb;
1866 struct drm_framebuffer *target_fb;
1867 struct drm_gem_object *obj;
1868 struct amdgpu_bo *abo;
1869 uint64_t fb_location, tiling_flags;
1870 uint32_t fb_format, fb_pitch_pixels;
1871 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1872 u32 pipe_config;
1873 u32 tmp, viewport_w, viewport_h;
1874 int r;
1875 bool bypass_lut = false;
1876 struct drm_format_name_buf format_name;
1877
1878 /* no fb bound */
1879 if (!atomic && !crtc->primary->fb) {
1880 DRM_DEBUG_KMS("No FB bound\n");
1881 return 0;
1882 }
1883
1884 if (atomic) {
1885 amdgpu_fb = to_amdgpu_framebuffer(fb);
1886 target_fb = fb;
1887 } else {
1888 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1889 target_fb = crtc->primary->fb;
1890 }
1891
1892 /* If atomic, assume fb object is pinned & idle & fenced and
1893 * just update base pointers
1894 */
1895 obj = amdgpu_fb->obj;
1896 abo = gem_to_amdgpu_bo(obj);
1897 r = amdgpu_bo_reserve(abo, false);
1898 if (unlikely(r != 0))
1899 return r;
1900
1901 if (atomic) {
1902 fb_location = amdgpu_bo_gpu_offset(abo);
1903 } else {
1904 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1905 if (unlikely(r != 0)) {
1906 amdgpu_bo_unreserve(abo);
1907 return -EINVAL;
1908 }
1909 }
1910
1911 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1912 amdgpu_bo_unreserve(abo);
1913
1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1915
1916 switch (target_fb->format->format) {
1917 case DRM_FORMAT_C8:
1918 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1919 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1920 break;
1921 case DRM_FORMAT_XRGB4444:
1922 case DRM_FORMAT_ARGB4444:
1923 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1924 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1925#ifdef __BIG_ENDIAN
1926 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1927 ENDIAN_8IN16);
1928#endif
1929 break;
1930 case DRM_FORMAT_XRGB1555:
1931 case DRM_FORMAT_ARGB1555:
1932 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1933 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1934#ifdef __BIG_ENDIAN
1935 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1936 ENDIAN_8IN16);
1937#endif
1938 break;
1939 case DRM_FORMAT_BGRX5551:
1940 case DRM_FORMAT_BGRA5551:
1941 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1942 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1943#ifdef __BIG_ENDIAN
1944 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1945 ENDIAN_8IN16);
1946#endif
1947 break;
1948 case DRM_FORMAT_RGB565:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 ENDIAN_8IN16);
1954#endif
1955 break;
1956 case DRM_FORMAT_XRGB8888:
1957 case DRM_FORMAT_ARGB8888:
1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1960#ifdef __BIG_ENDIAN
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1962 ENDIAN_8IN32);
1963#endif
1964 break;
1965 case DRM_FORMAT_XRGB2101010:
1966 case DRM_FORMAT_ARGB2101010:
1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1969#ifdef __BIG_ENDIAN
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1971 ENDIAN_8IN32);
1972#endif
1973 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1974 bypass_lut = true;
1975 break;
1976 case DRM_FORMAT_BGRX1010102:
1977 case DRM_FORMAT_BGRA1010102:
1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1980#ifdef __BIG_ENDIAN
1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1982 ENDIAN_8IN32);
1983#endif
1984 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1985 bypass_lut = true;
1986 break;
1987 default:
1988 DRM_ERROR("Unsupported screen format %s\n",
1989 drm_get_format_name(target_fb->format->format, &format_name));
1990 return -EINVAL;
1991 }
1992
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1995
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2001
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2004 ARRAY_2D_TILED_THIN1);
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2006 tile_split);
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2009 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2010 mtaspect);
2011 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2012 ADDR_SURF_MICRO_TILING_DISPLAY);
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2015 ARRAY_1D_TILED_THIN1);
2016 }
2017
2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2019 pipe_config);
2020
2021 dce_v11_0_vga_enable(crtc, false);
2022
2023 /* Make sure surface address is updated at vertical blank rather than
2024 * horizontal blank
2025 */
2026 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2027 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2028 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2029 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2030
2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2032 upper_32_bits(fb_location));
2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2034 upper_32_bits(fb_location));
2035 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2036 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2037 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2038 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2040 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2041
2042 /*
2043 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2044 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2045 * retain the full precision throughout the pipeline.
2046 */
2047 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2048 if (bypass_lut)
2049 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2050 else
2051 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2052 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2053
2054 if (bypass_lut)
2055 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2056
2057 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2058 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2059 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2060 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2061 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2062 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2063
2064 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2065 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2066
2067 dce_v11_0_grph_enable(crtc, true);
2068
2069 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2070 target_fb->height);
2071
2072 x &= ~3;
2073 y &= ~1;
2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2075 (x << 16) | y);
2076 viewport_w = crtc->mode.hdisplay;
2077 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2078 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2079 (viewport_w << 16) | viewport_h);
2080
2081 /* set pageflip to happen anywhere in vblank interval */
2082 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2083
2084 if (!atomic && fb && fb != crtc->primary->fb) {
2085 amdgpu_fb = to_amdgpu_framebuffer(fb);
2086 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2087 r = amdgpu_bo_reserve(abo, true);
2088 if (unlikely(r != 0))
2089 return r;
2090 amdgpu_bo_unpin(abo);
2091 amdgpu_bo_unreserve(abo);
2092 }
2093
2094 /* Bytes per pixel may have changed */
2095 dce_v11_0_bandwidth_update(adev);
2096
2097 return 0;
2098}
2099
2100static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2101 struct drm_display_mode *mode)
2102{
2103 struct drm_device *dev = crtc->dev;
2104 struct amdgpu_device *adev = dev->dev_private;
2105 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2106 u32 tmp;
2107
2108 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2109 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2110 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2111 else
2112 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2113 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2114}
2115
2116static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2117{
2118 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2119 struct drm_device *dev = crtc->dev;
2120 struct amdgpu_device *adev = dev->dev_private;
2121 u16 *r, *g, *b;
2122 int i;
2123 u32 tmp;
2124
2125 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2126
2127 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2128 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2129 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2130
2131 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2132 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2133 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2134
2135 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2136 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2137 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2138
2139 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2140
2141 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2142 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2143 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2144
2145 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2146 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2147 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2148
2149 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2150 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2151
2152 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2153 r = crtc->gamma_store;
2154 g = r + crtc->gamma_size;
2155 b = g + crtc->gamma_size;
2156 for (i = 0; i < 256; i++) {
2157 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2158 ((*r++ & 0xffc0) << 14) |
2159 ((*g++ & 0xffc0) << 4) |
2160 (*b++ >> 6));
2161 }
2162
2163 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2164 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2165 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2166 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2167 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2168
2169 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2170 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2171 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2172
2173 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2174 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2176
2177 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2178 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2179 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2180
2181 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2182 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2183 /* XXX this only needs to be programmed once per crtc at startup,
2184 * not sure where the best place for it is
2185 */
2186 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2187 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2188 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2189}
2190
2191static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2192{
2193 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2194 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2195
2196 switch (amdgpu_encoder->encoder_id) {
2197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2198 if (dig->linkb)
2199 return 1;
2200 else
2201 return 0;
2202 break;
2203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2204 if (dig->linkb)
2205 return 3;
2206 else
2207 return 2;
2208 break;
2209 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2210 if (dig->linkb)
2211 return 5;
2212 else
2213 return 4;
2214 break;
2215 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2216 return 6;
2217 break;
2218 default:
2219 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2220 return 0;
2221 }
2222}
2223
2224/**
2225 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2226 *
2227 * @crtc: drm crtc
2228 *
2229 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2230 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2231 * monitors a dedicated PPLL must be used. If a particular board has
2232 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2233 * as there is no need to program the PLL itself. If we are not able to
2234 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2235 * avoid messing up an existing monitor.
2236 *
2237 * Asic specific PLL information
2238 *
2239 * DCE 10.x
2240 * Tonga
2241 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2242 * CI
2243 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2244 *
2245 */
2246static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2247{
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 struct drm_device *dev = crtc->dev;
2250 struct amdgpu_device *adev = dev->dev_private;
2251 u32 pll_in_use;
2252 int pll;
2253
2254 if ((adev->asic_type == CHIP_POLARIS10) ||
2255 (adev->asic_type == CHIP_POLARIS11) ||
2256 (adev->asic_type == CHIP_POLARIS12)) {
2257 struct amdgpu_encoder *amdgpu_encoder =
2258 to_amdgpu_encoder(amdgpu_crtc->encoder);
2259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2260
2261 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2262 return ATOM_DP_DTO;
2263
2264 switch (amdgpu_encoder->encoder_id) {
2265 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2266 if (dig->linkb)
2267 return ATOM_COMBOPHY_PLL1;
2268 else
2269 return ATOM_COMBOPHY_PLL0;
2270 break;
2271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2272 if (dig->linkb)
2273 return ATOM_COMBOPHY_PLL3;
2274 else
2275 return ATOM_COMBOPHY_PLL2;
2276 break;
2277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2278 if (dig->linkb)
2279 return ATOM_COMBOPHY_PLL5;
2280 else
2281 return ATOM_COMBOPHY_PLL4;
2282 break;
2283 default:
2284 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2285 return ATOM_PPLL_INVALID;
2286 }
2287 }
2288
2289 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2290 if (adev->clock.dp_extclk)
2291 /* skip PPLL programming if using ext clock */
2292 return ATOM_PPLL_INVALID;
2293 else {
2294 /* use the same PPLL for all DP monitors */
2295 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2296 if (pll != ATOM_PPLL_INVALID)
2297 return pll;
2298 }
2299 } else {
2300 /* use the same PPLL for all monitors with the same clock */
2301 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2302 if (pll != ATOM_PPLL_INVALID)
2303 return pll;
2304 }
2305
2306 /* XXX need to determine what plls are available on each DCE11 part */
2307 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2308 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2309 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2310 return ATOM_PPLL1;
2311 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2312 return ATOM_PPLL0;
2313 DRM_ERROR("unable to allocate a PPLL\n");
2314 return ATOM_PPLL_INVALID;
2315 } else {
2316 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2317 return ATOM_PPLL2;
2318 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2319 return ATOM_PPLL1;
2320 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2321 return ATOM_PPLL0;
2322 DRM_ERROR("unable to allocate a PPLL\n");
2323 return ATOM_PPLL_INVALID;
2324 }
2325 return ATOM_PPLL_INVALID;
2326}
2327
2328static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2329{
2330 struct amdgpu_device *adev = crtc->dev->dev_private;
2331 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2332 uint32_t cur_lock;
2333
2334 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2335 if (lock)
2336 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2337 else
2338 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2339 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2340}
2341
2342static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2343{
2344 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2345 struct amdgpu_device *adev = crtc->dev->dev_private;
2346 u32 tmp;
2347
2348 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2349 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2350 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2351}
2352
2353static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2354{
2355 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2356 struct amdgpu_device *adev = crtc->dev->dev_private;
2357 u32 tmp;
2358
2359 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2360 upper_32_bits(amdgpu_crtc->cursor_addr));
2361 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2362 lower_32_bits(amdgpu_crtc->cursor_addr));
2363
2364 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2365 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2366 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2367 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2368}
2369
2370static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2371 int x, int y)
2372{
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374 struct amdgpu_device *adev = crtc->dev->dev_private;
2375 int xorigin = 0, yorigin = 0;
2376
2377 amdgpu_crtc->cursor_x = x;
2378 amdgpu_crtc->cursor_y = y;
2379
2380 /* avivo cursor are offset into the total surface */
2381 x += crtc->x;
2382 y += crtc->y;
2383 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2384
2385 if (x < 0) {
2386 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2387 x = 0;
2388 }
2389 if (y < 0) {
2390 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2391 y = 0;
2392 }
2393
2394 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2395 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2396 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2397 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2398
2399 return 0;
2400}
2401
2402static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2403 int x, int y)
2404{
2405 int ret;
2406
2407 dce_v11_0_lock_cursor(crtc, true);
2408 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2409 dce_v11_0_lock_cursor(crtc, false);
2410
2411 return ret;
2412}
2413
2414static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2415 struct drm_file *file_priv,
2416 uint32_t handle,
2417 uint32_t width,
2418 uint32_t height,
2419 int32_t hot_x,
2420 int32_t hot_y)
2421{
2422 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2423 struct drm_gem_object *obj;
2424 struct amdgpu_bo *aobj;
2425 int ret;
2426
2427 if (!handle) {
2428 /* turn off cursor */
2429 dce_v11_0_hide_cursor(crtc);
2430 obj = NULL;
2431 goto unpin;
2432 }
2433
2434 if ((width > amdgpu_crtc->max_cursor_width) ||
2435 (height > amdgpu_crtc->max_cursor_height)) {
2436 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2437 return -EINVAL;
2438 }
2439
2440 obj = drm_gem_object_lookup(file_priv, handle);
2441 if (!obj) {
2442 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2443 return -ENOENT;
2444 }
2445
2446 aobj = gem_to_amdgpu_bo(obj);
2447 ret = amdgpu_bo_reserve(aobj, false);
2448 if (ret != 0) {
2449 drm_gem_object_put_unlocked(obj);
2450 return ret;
2451 }
2452
2453 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2454 amdgpu_bo_unreserve(aobj);
2455 if (ret) {
2456 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2457 drm_gem_object_put_unlocked(obj);
2458 return ret;
2459 }
2460
2461 dce_v11_0_lock_cursor(crtc, true);
2462
2463 if (width != amdgpu_crtc->cursor_width ||
2464 height != amdgpu_crtc->cursor_height ||
2465 hot_x != amdgpu_crtc->cursor_hot_x ||
2466 hot_y != amdgpu_crtc->cursor_hot_y) {
2467 int x, y;
2468
2469 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2470 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2471
2472 dce_v11_0_cursor_move_locked(crtc, x, y);
2473
2474 amdgpu_crtc->cursor_width = width;
2475 amdgpu_crtc->cursor_height = height;
2476 amdgpu_crtc->cursor_hot_x = hot_x;
2477 amdgpu_crtc->cursor_hot_y = hot_y;
2478 }
2479
2480 dce_v11_0_show_cursor(crtc);
2481 dce_v11_0_lock_cursor(crtc, false);
2482
2483unpin:
2484 if (amdgpu_crtc->cursor_bo) {
2485 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2486 ret = amdgpu_bo_reserve(aobj, true);
2487 if (likely(ret == 0)) {
2488 amdgpu_bo_unpin(aobj);
2489 amdgpu_bo_unreserve(aobj);
2490 }
2491 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2492 }
2493
2494 amdgpu_crtc->cursor_bo = obj;
2495 return 0;
2496}
2497
2498static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2499{
2500 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2501
2502 if (amdgpu_crtc->cursor_bo) {
2503 dce_v11_0_lock_cursor(crtc, true);
2504
2505 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2506 amdgpu_crtc->cursor_y);
2507
2508 dce_v11_0_show_cursor(crtc);
2509
2510 dce_v11_0_lock_cursor(crtc, false);
2511 }
2512}
2513
2514static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2515 u16 *blue, uint32_t size,
2516 struct drm_modeset_acquire_ctx *ctx)
2517{
2518 dce_v11_0_crtc_load_lut(crtc);
2519
2520 return 0;
2521}
2522
2523static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2524{
2525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2526
2527 drm_crtc_cleanup(crtc);
2528 kfree(amdgpu_crtc);
2529}
2530
2531static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2532 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2533 .cursor_move = dce_v11_0_crtc_cursor_move,
2534 .gamma_set = dce_v11_0_crtc_gamma_set,
2535 .set_config = amdgpu_display_crtc_set_config,
2536 .destroy = dce_v11_0_crtc_destroy,
2537 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2538};
2539
2540static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2541{
2542 struct drm_device *dev = crtc->dev;
2543 struct amdgpu_device *adev = dev->dev_private;
2544 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2545 unsigned type;
2546
2547 switch (mode) {
2548 case DRM_MODE_DPMS_ON:
2549 amdgpu_crtc->enabled = true;
2550 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2551 dce_v11_0_vga_enable(crtc, true);
2552 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2553 dce_v11_0_vga_enable(crtc, false);
2554 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2555 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2556 amdgpu_crtc->crtc_id);
2557 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2558 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2559 drm_crtc_vblank_on(crtc);
2560 dce_v11_0_crtc_load_lut(crtc);
2561 break;
2562 case DRM_MODE_DPMS_STANDBY:
2563 case DRM_MODE_DPMS_SUSPEND:
2564 case DRM_MODE_DPMS_OFF:
2565 drm_crtc_vblank_off(crtc);
2566 if (amdgpu_crtc->enabled) {
2567 dce_v11_0_vga_enable(crtc, true);
2568 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2569 dce_v11_0_vga_enable(crtc, false);
2570 }
2571 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2572 amdgpu_crtc->enabled = false;
2573 break;
2574 }
2575 /* adjust pm to dpms */
2576 amdgpu_pm_compute_clocks(adev);
2577}
2578
2579static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2580{
2581 /* disable crtc pair power gating before programming */
2582 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2583 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2584 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2585}
2586
2587static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2588{
2589 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2590 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2591}
2592
2593static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2594{
2595 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2596 struct drm_device *dev = crtc->dev;
2597 struct amdgpu_device *adev = dev->dev_private;
2598 struct amdgpu_atom_ss ss;
2599 int i;
2600
2601 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2602 if (crtc->primary->fb) {
2603 int r;
2604 struct amdgpu_framebuffer *amdgpu_fb;
2605 struct amdgpu_bo *abo;
2606
2607 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2608 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2609 r = amdgpu_bo_reserve(abo, true);
2610 if (unlikely(r))
2611 DRM_ERROR("failed to reserve abo before unpin\n");
2612 else {
2613 amdgpu_bo_unpin(abo);
2614 amdgpu_bo_unreserve(abo);
2615 }
2616 }
2617 /* disable the GRPH */
2618 dce_v11_0_grph_enable(crtc, false);
2619
2620 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2621
2622 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2623 if (adev->mode_info.crtcs[i] &&
2624 adev->mode_info.crtcs[i]->enabled &&
2625 i != amdgpu_crtc->crtc_id &&
2626 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2627 /* one other crtc is using this pll don't turn
2628 * off the pll
2629 */
2630 goto done;
2631 }
2632 }
2633
2634 switch (amdgpu_crtc->pll_id) {
2635 case ATOM_PPLL0:
2636 case ATOM_PPLL1:
2637 case ATOM_PPLL2:
2638 /* disable the ppll */
2639 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2640 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2641 break;
2642 case ATOM_COMBOPHY_PLL0:
2643 case ATOM_COMBOPHY_PLL1:
2644 case ATOM_COMBOPHY_PLL2:
2645 case ATOM_COMBOPHY_PLL3:
2646 case ATOM_COMBOPHY_PLL4:
2647 case ATOM_COMBOPHY_PLL5:
2648 /* disable the ppll */
2649 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2650 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2651 break;
2652 default:
2653 break;
2654 }
2655done:
2656 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2657 amdgpu_crtc->adjusted_clock = 0;
2658 amdgpu_crtc->encoder = NULL;
2659 amdgpu_crtc->connector = NULL;
2660}
2661
2662static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2663 struct drm_display_mode *mode,
2664 struct drm_display_mode *adjusted_mode,
2665 int x, int y, struct drm_framebuffer *old_fb)
2666{
2667 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2668 struct drm_device *dev = crtc->dev;
2669 struct amdgpu_device *adev = dev->dev_private;
2670
2671 if (!amdgpu_crtc->adjusted_clock)
2672 return -EINVAL;
2673
2674 if ((adev->asic_type == CHIP_POLARIS10) ||
2675 (adev->asic_type == CHIP_POLARIS11) ||
2676 (adev->asic_type == CHIP_POLARIS12)) {
2677 struct amdgpu_encoder *amdgpu_encoder =
2678 to_amdgpu_encoder(amdgpu_crtc->encoder);
2679 int encoder_mode =
2680 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2681
2682 /* SetPixelClock calculates the plls and ss values now */
2683 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2684 amdgpu_crtc->pll_id,
2685 encoder_mode, amdgpu_encoder->encoder_id,
2686 adjusted_mode->clock, 0, 0, 0, 0,
2687 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2688 } else {
2689 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2690 }
2691 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2692 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2693 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2694 amdgpu_atombios_crtc_scaler_setup(crtc);
2695 dce_v11_0_cursor_reset(crtc);
2696 /* update the hw version fpr dpm */
2697 amdgpu_crtc->hw_mode = *adjusted_mode;
2698
2699 return 0;
2700}
2701
2702static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2703 const struct drm_display_mode *mode,
2704 struct drm_display_mode *adjusted_mode)
2705{
2706 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2707 struct drm_device *dev = crtc->dev;
2708 struct drm_encoder *encoder;
2709
2710 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2711 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2712 if (encoder->crtc == crtc) {
2713 amdgpu_crtc->encoder = encoder;
2714 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2715 break;
2716 }
2717 }
2718 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2719 amdgpu_crtc->encoder = NULL;
2720 amdgpu_crtc->connector = NULL;
2721 return false;
2722 }
2723 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2724 return false;
2725 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2726 return false;
2727 /* pick pll */
2728 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2729 /* if we can't get a PPLL for a non-DP encoder, fail */
2730 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2731 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2732 return false;
2733
2734 return true;
2735}
2736
2737static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2738 struct drm_framebuffer *old_fb)
2739{
2740 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2741}
2742
2743static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2744 struct drm_framebuffer *fb,
2745 int x, int y, enum mode_set_atomic state)
2746{
2747 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2748}
2749
2750static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2751 .dpms = dce_v11_0_crtc_dpms,
2752 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2753 .mode_set = dce_v11_0_crtc_mode_set,
2754 .mode_set_base = dce_v11_0_crtc_set_base,
2755 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2756 .prepare = dce_v11_0_crtc_prepare,
2757 .commit = dce_v11_0_crtc_commit,
2758 .disable = dce_v11_0_crtc_disable,
2759};
2760
2761static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2762{
2763 struct amdgpu_crtc *amdgpu_crtc;
2764
2765 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2766 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2767 if (amdgpu_crtc == NULL)
2768 return -ENOMEM;
2769
2770 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2771
2772 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2773 amdgpu_crtc->crtc_id = index;
2774 adev->mode_info.crtcs[index] = amdgpu_crtc;
2775
2776 amdgpu_crtc->max_cursor_width = 128;
2777 amdgpu_crtc->max_cursor_height = 128;
2778 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2779 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2780
2781 switch (amdgpu_crtc->crtc_id) {
2782 case 0:
2783 default:
2784 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2785 break;
2786 case 1:
2787 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2788 break;
2789 case 2:
2790 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2791 break;
2792 case 3:
2793 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2794 break;
2795 case 4:
2796 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2797 break;
2798 case 5:
2799 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2800 break;
2801 }
2802
2803 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2804 amdgpu_crtc->adjusted_clock = 0;
2805 amdgpu_crtc->encoder = NULL;
2806 amdgpu_crtc->connector = NULL;
2807 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2808
2809 return 0;
2810}
2811
2812static int dce_v11_0_early_init(void *handle)
2813{
2814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2815
2816 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2817 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2818
2819 dce_v11_0_set_display_funcs(adev);
2820
2821 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2822
2823 switch (adev->asic_type) {
2824 case CHIP_CARRIZO:
2825 adev->mode_info.num_hpd = 6;
2826 adev->mode_info.num_dig = 9;
2827 break;
2828 case CHIP_STONEY:
2829 adev->mode_info.num_hpd = 6;
2830 adev->mode_info.num_dig = 9;
2831 break;
2832 case CHIP_POLARIS10:
2833 adev->mode_info.num_hpd = 6;
2834 adev->mode_info.num_dig = 6;
2835 break;
2836 case CHIP_POLARIS11:
2837 case CHIP_POLARIS12:
2838 adev->mode_info.num_hpd = 5;
2839 adev->mode_info.num_dig = 5;
2840 break;
2841 default:
2842 /* FIXME: not supported yet */
2843 return -EINVAL;
2844 }
2845
2846 dce_v11_0_set_irq_funcs(adev);
2847
2848 return 0;
2849}
2850
2851static int dce_v11_0_sw_init(void *handle)
2852{
2853 int r, i;
2854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2855
2856 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2857 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2858 if (r)
2859 return r;
2860 }
2861
2862 for (i = 8; i < 20; i += 2) {
2863 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2864 if (r)
2865 return r;
2866 }
2867
2868 /* HPD hotplug */
2869 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2870 if (r)
2871 return r;
2872
2873 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2874
2875 adev->ddev->mode_config.async_page_flip = true;
2876
2877 adev->ddev->mode_config.max_width = 16384;
2878 adev->ddev->mode_config.max_height = 16384;
2879
2880 adev->ddev->mode_config.preferred_depth = 24;
2881 adev->ddev->mode_config.prefer_shadow = 1;
2882
2883 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2884
2885 r = amdgpu_display_modeset_create_props(adev);
2886 if (r)
2887 return r;
2888
2889 adev->ddev->mode_config.max_width = 16384;
2890 adev->ddev->mode_config.max_height = 16384;
2891
2892
2893 /* allocate crtcs */
2894 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2895 r = dce_v11_0_crtc_init(adev, i);
2896 if (r)
2897 return r;
2898 }
2899
2900 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2901 amdgpu_display_print_display_setup(adev->ddev);
2902 else
2903 return -EINVAL;
2904
2905 /* setup afmt */
2906 r = dce_v11_0_afmt_init(adev);
2907 if (r)
2908 return r;
2909
2910 r = dce_v11_0_audio_init(adev);
2911 if (r)
2912 return r;
2913
2914 drm_kms_helper_poll_init(adev->ddev);
2915
2916 adev->mode_info.mode_config_initialized = true;
2917 return 0;
2918}
2919
2920static int dce_v11_0_sw_fini(void *handle)
2921{
2922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2923
2924 kfree(adev->mode_info.bios_hardcoded_edid);
2925
2926 drm_kms_helper_poll_fini(adev->ddev);
2927
2928 dce_v11_0_audio_fini(adev);
2929
2930 dce_v11_0_afmt_fini(adev);
2931
2932 drm_mode_config_cleanup(adev->ddev);
2933 adev->mode_info.mode_config_initialized = false;
2934
2935 return 0;
2936}
2937
2938static int dce_v11_0_hw_init(void *handle)
2939{
2940 int i;
2941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2942
2943 dce_v11_0_init_golden_registers(adev);
2944
2945 /* disable vga render */
2946 dce_v11_0_set_vga_render_state(adev, false);
2947 /* init dig PHYs, disp eng pll */
2948 amdgpu_atombios_crtc_powergate_init(adev);
2949 amdgpu_atombios_encoder_init_dig(adev);
2950 if ((adev->asic_type == CHIP_POLARIS10) ||
2951 (adev->asic_type == CHIP_POLARIS11) ||
2952 (adev->asic_type == CHIP_POLARIS12)) {
2953 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2954 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2955 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2956 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
2957 } else {
2958 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2959 }
2960
2961 /* initialize hpd */
2962 dce_v11_0_hpd_init(adev);
2963
2964 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2965 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2966 }
2967
2968 dce_v11_0_pageflip_interrupt_init(adev);
2969
2970 return 0;
2971}
2972
2973static int dce_v11_0_hw_fini(void *handle)
2974{
2975 int i;
2976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2977
2978 dce_v11_0_hpd_fini(adev);
2979
2980 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2981 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2982 }
2983
2984 dce_v11_0_pageflip_interrupt_fini(adev);
2985
2986 return 0;
2987}
2988
2989static int dce_v11_0_suspend(void *handle)
2990{
2991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992
2993 adev->mode_info.bl_level =
2994 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2995
2996 return dce_v11_0_hw_fini(handle);
2997}
2998
2999static int dce_v11_0_resume(void *handle)
3000{
3001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3002 int ret;
3003
3004 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3005 adev->mode_info.bl_level);
3006
3007 ret = dce_v11_0_hw_init(handle);
3008
3009 /* turn on the BL */
3010 if (adev->mode_info.bl_encoder) {
3011 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3012 adev->mode_info.bl_encoder);
3013 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3014 bl_level);
3015 }
3016
3017 return ret;
3018}
3019
3020static bool dce_v11_0_is_idle(void *handle)
3021{
3022 return true;
3023}
3024
3025static int dce_v11_0_wait_for_idle(void *handle)
3026{
3027 return 0;
3028}
3029
3030static int dce_v11_0_soft_reset(void *handle)
3031{
3032 u32 srbm_soft_reset = 0, tmp;
3033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035 if (dce_v11_0_is_display_hung(adev))
3036 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3037
3038 if (srbm_soft_reset) {
3039 tmp = RREG32(mmSRBM_SOFT_RESET);
3040 tmp |= srbm_soft_reset;
3041 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3042 WREG32(mmSRBM_SOFT_RESET, tmp);
3043 tmp = RREG32(mmSRBM_SOFT_RESET);
3044
3045 udelay(50);
3046
3047 tmp &= ~srbm_soft_reset;
3048 WREG32(mmSRBM_SOFT_RESET, tmp);
3049 tmp = RREG32(mmSRBM_SOFT_RESET);
3050
3051 /* Wait a little for things to settle down */
3052 udelay(50);
3053 }
3054 return 0;
3055}
3056
3057static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3058 int crtc,
3059 enum amdgpu_interrupt_state state)
3060{
3061 u32 lb_interrupt_mask;
3062
3063 if (crtc >= adev->mode_info.num_crtc) {
3064 DRM_DEBUG("invalid crtc %d\n", crtc);
3065 return;
3066 }
3067
3068 switch (state) {
3069 case AMDGPU_IRQ_STATE_DISABLE:
3070 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3071 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3072 VBLANK_INTERRUPT_MASK, 0);
3073 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3074 break;
3075 case AMDGPU_IRQ_STATE_ENABLE:
3076 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3077 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3078 VBLANK_INTERRUPT_MASK, 1);
3079 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3080 break;
3081 default:
3082 break;
3083 }
3084}
3085
3086static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3087 int crtc,
3088 enum amdgpu_interrupt_state state)
3089{
3090 u32 lb_interrupt_mask;
3091
3092 if (crtc >= adev->mode_info.num_crtc) {
3093 DRM_DEBUG("invalid crtc %d\n", crtc);
3094 return;
3095 }
3096
3097 switch (state) {
3098 case AMDGPU_IRQ_STATE_DISABLE:
3099 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3100 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3101 VLINE_INTERRUPT_MASK, 0);
3102 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3103 break;
3104 case AMDGPU_IRQ_STATE_ENABLE:
3105 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3106 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3107 VLINE_INTERRUPT_MASK, 1);
3108 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3109 break;
3110 default:
3111 break;
3112 }
3113}
3114
3115static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3116 struct amdgpu_irq_src *source,
3117 unsigned hpd,
3118 enum amdgpu_interrupt_state state)
3119{
3120 u32 tmp;
3121
3122 if (hpd >= adev->mode_info.num_hpd) {
3123 DRM_DEBUG("invalid hdp %d\n", hpd);
3124 return 0;
3125 }
3126
3127 switch (state) {
3128 case AMDGPU_IRQ_STATE_DISABLE:
3129 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3130 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3131 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3132 break;
3133 case AMDGPU_IRQ_STATE_ENABLE:
3134 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3135 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3136 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3137 break;
3138 default:
3139 break;
3140 }
3141
3142 return 0;
3143}
3144
3145static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3146 struct amdgpu_irq_src *source,
3147 unsigned type,
3148 enum amdgpu_interrupt_state state)
3149{
3150 switch (type) {
3151 case AMDGPU_CRTC_IRQ_VBLANK1:
3152 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3153 break;
3154 case AMDGPU_CRTC_IRQ_VBLANK2:
3155 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3156 break;
3157 case AMDGPU_CRTC_IRQ_VBLANK3:
3158 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3159 break;
3160 case AMDGPU_CRTC_IRQ_VBLANK4:
3161 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3162 break;
3163 case AMDGPU_CRTC_IRQ_VBLANK5:
3164 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3165 break;
3166 case AMDGPU_CRTC_IRQ_VBLANK6:
3167 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3168 break;
3169 case AMDGPU_CRTC_IRQ_VLINE1:
3170 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3171 break;
3172 case AMDGPU_CRTC_IRQ_VLINE2:
3173 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3174 break;
3175 case AMDGPU_CRTC_IRQ_VLINE3:
3176 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3177 break;
3178 case AMDGPU_CRTC_IRQ_VLINE4:
3179 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3180 break;
3181 case AMDGPU_CRTC_IRQ_VLINE5:
3182 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3183 break;
3184 case AMDGPU_CRTC_IRQ_VLINE6:
3185 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3186 break;
3187 default:
3188 break;
3189 }
3190 return 0;
3191}
3192
3193static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3194 struct amdgpu_irq_src *src,
3195 unsigned type,
3196 enum amdgpu_interrupt_state state)
3197{
3198 u32 reg;
3199
3200 if (type >= adev->mode_info.num_crtc) {
3201 DRM_ERROR("invalid pageflip crtc %d\n", type);
3202 return -EINVAL;
3203 }
3204
3205 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3206 if (state == AMDGPU_IRQ_STATE_DISABLE)
3207 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3208 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3209 else
3210 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3211 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3212
3213 return 0;
3214}
3215
3216static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3217 struct amdgpu_irq_src *source,
3218 struct amdgpu_iv_entry *entry)
3219{
3220 unsigned long flags;
3221 unsigned crtc_id;
3222 struct amdgpu_crtc *amdgpu_crtc;
3223 struct amdgpu_flip_work *works;
3224
3225 crtc_id = (entry->src_id - 8) >> 1;
3226 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3227
3228 if (crtc_id >= adev->mode_info.num_crtc) {
3229 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3230 return -EINVAL;
3231 }
3232
3233 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3234 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3235 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3236 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3237
3238 /* IRQ could occur when in initial stage */
3239 if(amdgpu_crtc == NULL)
3240 return 0;
3241
3242 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3243 works = amdgpu_crtc->pflip_works;
3244 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3245 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3246 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3247 amdgpu_crtc->pflip_status,
3248 AMDGPU_FLIP_SUBMITTED);
3249 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3250 return 0;
3251 }
3252
3253 /* page flip completed. clean up */
3254 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3255 amdgpu_crtc->pflip_works = NULL;
3256
3257 /* wakeup usersapce */
3258 if(works->event)
3259 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3260
3261 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3262
3263 drm_crtc_vblank_put(&amdgpu_crtc->base);
3264 schedule_work(&works->unpin_work);
3265
3266 return 0;
3267}
3268
3269static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3270 int hpd)
3271{
3272 u32 tmp;
3273
3274 if (hpd >= adev->mode_info.num_hpd) {
3275 DRM_DEBUG("invalid hdp %d\n", hpd);
3276 return;
3277 }
3278
3279 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3280 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3281 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3282}
3283
3284static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3285 int crtc)
3286{
3287 u32 tmp;
3288
3289 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3290 DRM_DEBUG("invalid crtc %d\n", crtc);
3291 return;
3292 }
3293
3294 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3295 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3296 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3297}
3298
3299static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3300 int crtc)
3301{
3302 u32 tmp;
3303
3304 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3305 DRM_DEBUG("invalid crtc %d\n", crtc);
3306 return;
3307 }
3308
3309 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3310 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3311 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3312}
3313
3314static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3315 struct amdgpu_irq_src *source,
3316 struct amdgpu_iv_entry *entry)
3317{
3318 unsigned crtc = entry->src_id - 1;
3319 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3320 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3321 crtc);
3322
3323 switch (entry->src_data[0]) {
3324 case 0: /* vblank */
3325 if (disp_int & interrupt_status_offsets[crtc].vblank)
3326 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3327 else
3328 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3329
3330 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3331 drm_handle_vblank(adev->ddev, crtc);
3332 }
3333 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3334
3335 break;
3336 case 1: /* vline */
3337 if (disp_int & interrupt_status_offsets[crtc].vline)
3338 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3339 else
3340 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3341
3342 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3343
3344 break;
3345 default:
3346 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3347 break;
3348 }
3349
3350 return 0;
3351}
3352
3353static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3354 struct amdgpu_irq_src *source,
3355 struct amdgpu_iv_entry *entry)
3356{
3357 uint32_t disp_int, mask;
3358 unsigned hpd;
3359
3360 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3361 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3362 return 0;
3363 }
3364
3365 hpd = entry->src_data[0];
3366 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3367 mask = interrupt_status_offsets[hpd].hpd;
3368
3369 if (disp_int & mask) {
3370 dce_v11_0_hpd_int_ack(adev, hpd);
3371 schedule_work(&adev->hotplug_work);
3372 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3373 }
3374
3375 return 0;
3376}
3377
3378static int dce_v11_0_set_clockgating_state(void *handle,
3379 enum amd_clockgating_state state)
3380{
3381 return 0;
3382}
3383
3384static int dce_v11_0_set_powergating_state(void *handle,
3385 enum amd_powergating_state state)
3386{
3387 return 0;
3388}
3389
3390static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3391 .name = "dce_v11_0",
3392 .early_init = dce_v11_0_early_init,
3393 .late_init = NULL,
3394 .sw_init = dce_v11_0_sw_init,
3395 .sw_fini = dce_v11_0_sw_fini,
3396 .hw_init = dce_v11_0_hw_init,
3397 .hw_fini = dce_v11_0_hw_fini,
3398 .suspend = dce_v11_0_suspend,
3399 .resume = dce_v11_0_resume,
3400 .is_idle = dce_v11_0_is_idle,
3401 .wait_for_idle = dce_v11_0_wait_for_idle,
3402 .soft_reset = dce_v11_0_soft_reset,
3403 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3404 .set_powergating_state = dce_v11_0_set_powergating_state,
3405};
3406
3407static void
3408dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3409 struct drm_display_mode *mode,
3410 struct drm_display_mode *adjusted_mode)
3411{
3412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3413
3414 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3415
3416 /* need to call this here rather than in prepare() since we need some crtc info */
3417 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3418
3419 /* set scaler clears this on some chips */
3420 dce_v11_0_set_interleave(encoder->crtc, mode);
3421
3422 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3423 dce_v11_0_afmt_enable(encoder, true);
3424 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3425 }
3426}
3427
3428static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3429{
3430 struct amdgpu_device *adev = encoder->dev->dev_private;
3431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3432 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3433
3434 if ((amdgpu_encoder->active_device &
3435 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3436 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3437 ENCODER_OBJECT_ID_NONE)) {
3438 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3439 if (dig) {
3440 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3441 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3442 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3443 }
3444 }
3445
3446 amdgpu_atombios_scratch_regs_lock(adev, true);
3447
3448 if (connector) {
3449 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3450
3451 /* select the clock/data port if it uses a router */
3452 if (amdgpu_connector->router.cd_valid)
3453 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3454
3455 /* turn eDP panel on for mode set */
3456 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3457 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3458 ATOM_TRANSMITTER_ACTION_POWER_ON);
3459 }
3460
3461 /* this is needed for the pll/ss setup to work correctly in some cases */
3462 amdgpu_atombios_encoder_set_crtc_source(encoder);
3463 /* set up the FMT blocks */
3464 dce_v11_0_program_fmt(encoder);
3465}
3466
3467static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3468{
3469 struct drm_device *dev = encoder->dev;
3470 struct amdgpu_device *adev = dev->dev_private;
3471
3472 /* need to call this here as we need the crtc set up */
3473 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3474 amdgpu_atombios_scratch_regs_lock(adev, false);
3475}
3476
3477static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3478{
3479 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3480 struct amdgpu_encoder_atom_dig *dig;
3481
3482 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3483
3484 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3485 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3486 dce_v11_0_afmt_enable(encoder, false);
3487 dig = amdgpu_encoder->enc_priv;
3488 dig->dig_encoder = -1;
3489 }
3490 amdgpu_encoder->active_device = 0;
3491}
3492
3493/* these are handled by the primary encoders */
3494static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3495{
3496
3497}
3498
3499static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3500{
3501
3502}
3503
3504static void
3505dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3506 struct drm_display_mode *mode,
3507 struct drm_display_mode *adjusted_mode)
3508{
3509
3510}
3511
3512static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3513{
3514
3515}
3516
3517static void
3518dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3519{
3520
3521}
3522
3523static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3524 .dpms = dce_v11_0_ext_dpms,
3525 .prepare = dce_v11_0_ext_prepare,
3526 .mode_set = dce_v11_0_ext_mode_set,
3527 .commit = dce_v11_0_ext_commit,
3528 .disable = dce_v11_0_ext_disable,
3529 /* no detect for TMDS/LVDS yet */
3530};
3531
3532static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3533 .dpms = amdgpu_atombios_encoder_dpms,
3534 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3535 .prepare = dce_v11_0_encoder_prepare,
3536 .mode_set = dce_v11_0_encoder_mode_set,
3537 .commit = dce_v11_0_encoder_commit,
3538 .disable = dce_v11_0_encoder_disable,
3539 .detect = amdgpu_atombios_encoder_dig_detect,
3540};
3541
3542static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3543 .dpms = amdgpu_atombios_encoder_dpms,
3544 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3545 .prepare = dce_v11_0_encoder_prepare,
3546 .mode_set = dce_v11_0_encoder_mode_set,
3547 .commit = dce_v11_0_encoder_commit,
3548 .detect = amdgpu_atombios_encoder_dac_detect,
3549};
3550
3551static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3552{
3553 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3554 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3555 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3556 kfree(amdgpu_encoder->enc_priv);
3557 drm_encoder_cleanup(encoder);
3558 kfree(amdgpu_encoder);
3559}
3560
3561static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3562 .destroy = dce_v11_0_encoder_destroy,
3563};
3564
3565static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3566 uint32_t encoder_enum,
3567 uint32_t supported_device,
3568 u16 caps)
3569{
3570 struct drm_device *dev = adev->ddev;
3571 struct drm_encoder *encoder;
3572 struct amdgpu_encoder *amdgpu_encoder;
3573
3574 /* see if we already added it */
3575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3576 amdgpu_encoder = to_amdgpu_encoder(encoder);
3577 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3578 amdgpu_encoder->devices |= supported_device;
3579 return;
3580 }
3581
3582 }
3583
3584 /* add a new one */
3585 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3586 if (!amdgpu_encoder)
3587 return;
3588
3589 encoder = &amdgpu_encoder->base;
3590 switch (adev->mode_info.num_crtc) {
3591 case 1:
3592 encoder->possible_crtcs = 0x1;
3593 break;
3594 case 2:
3595 default:
3596 encoder->possible_crtcs = 0x3;
3597 break;
3598 case 3:
3599 encoder->possible_crtcs = 0x7;
3600 break;
3601 case 4:
3602 encoder->possible_crtcs = 0xf;
3603 break;
3604 case 5:
3605 encoder->possible_crtcs = 0x1f;
3606 break;
3607 case 6:
3608 encoder->possible_crtcs = 0x3f;
3609 break;
3610 }
3611
3612 amdgpu_encoder->enc_priv = NULL;
3613
3614 amdgpu_encoder->encoder_enum = encoder_enum;
3615 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3616 amdgpu_encoder->devices = supported_device;
3617 amdgpu_encoder->rmx_type = RMX_OFF;
3618 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3619 amdgpu_encoder->is_ext_encoder = false;
3620 amdgpu_encoder->caps = caps;
3621
3622 switch (amdgpu_encoder->encoder_id) {
3623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3624 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3625 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3626 DRM_MODE_ENCODER_DAC, NULL);
3627 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3628 break;
3629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3630 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3633 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3634 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3635 amdgpu_encoder->rmx_type = RMX_FULL;
3636 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3637 DRM_MODE_ENCODER_LVDS, NULL);
3638 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3639 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3640 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3641 DRM_MODE_ENCODER_DAC, NULL);
3642 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3643 } else {
3644 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3645 DRM_MODE_ENCODER_TMDS, NULL);
3646 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3647 }
3648 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3649 break;
3650 case ENCODER_OBJECT_ID_SI170B:
3651 case ENCODER_OBJECT_ID_CH7303:
3652 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3653 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3654 case ENCODER_OBJECT_ID_TITFP513:
3655 case ENCODER_OBJECT_ID_VT1623:
3656 case ENCODER_OBJECT_ID_HDMI_SI1930:
3657 case ENCODER_OBJECT_ID_TRAVIS:
3658 case ENCODER_OBJECT_ID_NUTMEG:
3659 /* these are handled by the primary encoders */
3660 amdgpu_encoder->is_ext_encoder = true;
3661 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3662 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3663 DRM_MODE_ENCODER_LVDS, NULL);
3664 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3665 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3666 DRM_MODE_ENCODER_DAC, NULL);
3667 else
3668 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3669 DRM_MODE_ENCODER_TMDS, NULL);
3670 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3671 break;
3672 }
3673}
3674
3675static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3676 .bandwidth_update = &dce_v11_0_bandwidth_update,
3677 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3678 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3679 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3680 .hpd_sense = &dce_v11_0_hpd_sense,
3681 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3682 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3683 .page_flip = &dce_v11_0_page_flip,
3684 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3685 .add_encoder = &dce_v11_0_encoder_add,
3686 .add_connector = &amdgpu_connector_add,
3687};
3688
3689static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3690{
3691 if (adev->mode_info.funcs == NULL)
3692 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3693}
3694
3695static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3696 .set = dce_v11_0_set_crtc_irq_state,
3697 .process = dce_v11_0_crtc_irq,
3698};
3699
3700static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3701 .set = dce_v11_0_set_pageflip_irq_state,
3702 .process = dce_v11_0_pageflip_irq,
3703};
3704
3705static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3706 .set = dce_v11_0_set_hpd_irq_state,
3707 .process = dce_v11_0_hpd_irq,
3708};
3709
3710static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3711{
3712 if (adev->mode_info.num_crtc > 0)
3713 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3714 else
3715 adev->crtc_irq.num_types = 0;
3716 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3717
3718 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3719 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3720
3721 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3722 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3723}
3724
3725const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3726{
3727 .type = AMD_IP_BLOCK_TYPE_DCE,
3728 .major = 11,
3729 .minor = 0,
3730 .rev = 0,
3731 .funcs = &dce_v11_0_ip_funcs,
3732};
3733
3734const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3735{
3736 .type = AMD_IP_BLOCK_TYPE_DCE,
3737 .major = 11,
3738 .minor = 2,
3739 .rev = 0,
3740 .funcs = &dce_v11_0_ip_funcs,
3741};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34#include "dce_v11_0.h"
35
36#include "dce/dce_11_0_d.h"
37#include "dce/dce_11_0_sh_mask.h"
38#include "dce/dce_11_0_enum.h"
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "gmc/gmc_8_1_sh_mask.h"
43
44static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46
47static const u32 crtc_offsets[] =
48{
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56};
57
58static const u32 hpd_offsets[] =
59{
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66};
67
68static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET,
76 DIG7_REGISTER_OFFSET,
77 DIG8_REGISTER_OFFSET
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static const u32 cz_golden_settings_a11[] =
119{
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
122};
123
124static const u32 cz_mgcg_cgcg_init[] =
125{
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128};
129
130static const u32 stoney_golden_settings_a11[] =
131{
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
134};
135
136static const u32 polaris11_golden_settings_a11[] =
137{
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
143};
144
145static const u32 polaris10_golden_settings_a11[] =
146{
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
151};
152
153static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154{
155 switch (adev->asic_type) {
156 case CHIP_CARRIZO:
157 amdgpu_program_register_sequence(adev,
158 cz_mgcg_cgcg_init,
159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
163 break;
164 case CHIP_STONEY:
165 amdgpu_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
168 break;
169 case CHIP_POLARIS11:
170 case CHIP_POLARIS12:
171 amdgpu_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
174 break;
175 case CHIP_POLARIS10:
176 amdgpu_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
179 break;
180 default:
181 break;
182 }
183}
184
185static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
187{
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195
196 return r;
197}
198
199static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
201{
202 unsigned long flags;
203
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208}
209
210static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
211{
212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
214 return true;
215 else
216 return false;
217}
218
219static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
220{
221 u32 pos1, pos2;
222
223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
225
226 if (pos1 != pos2)
227 return true;
228 else
229 return false;
230}
231
232/**
233 * dce_v11_0_vblank_wait - vblank wait asic callback.
234 *
235 * @adev: amdgpu_device pointer
236 * @crtc: crtc to wait for vblank on
237 *
238 * Wait for vblank on the requested crtc (evergreen+).
239 */
240static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
241{
242 unsigned i = 100;
243
244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
245 return;
246
247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 return;
249
250 /* depending on when we hit vblank, we may be close to active; if so,
251 * wait for another frame.
252 */
253 while (dce_v11_0_is_in_vblank(adev, crtc)) {
254 if (i++ == 100) {
255 i = 0;
256 if (!dce_v11_0_is_counter_moving(adev, crtc))
257 break;
258 }
259 }
260
261 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
262 if (i++ == 100) {
263 i = 0;
264 if (!dce_v11_0_is_counter_moving(adev, crtc))
265 break;
266 }
267 }
268}
269
270static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
271{
272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
273 return 0;
274 else
275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276}
277
278static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
279{
280 unsigned i;
281
282 /* Enable pflip interrupts */
283 for (i = 0; i < adev->mode_info.num_crtc; i++)
284 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285}
286
287static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
288{
289 unsigned i;
290
291 /* Disable pflip interrupts */
292 for (i = 0; i < adev->mode_info.num_crtc; i++)
293 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
294}
295
296/**
297 * dce_v11_0_page_flip - pageflip callback.
298 *
299 * @adev: amdgpu_device pointer
300 * @crtc_id: crtc to cleanup pageflip on
301 * @crtc_base: new address of the crtc (GPU MC address)
302 *
303 * Triggers the actual pageflip by updating the primary
304 * surface base address.
305 */
306static void dce_v11_0_page_flip(struct amdgpu_device *adev,
307 int crtc_id, u64 crtc_base, bool async)
308{
309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
310 u32 tmp;
311
312 /* flip immediate for async, default is vsync */
313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
317 /* update the scanout addresses */
318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
319 upper_32_bits(crtc_base));
320 /* writing to the low address triggers the update */
321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
322 lower_32_bits(crtc_base));
323 /* post the write */
324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
325}
326
327static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
328 u32 *vbl, u32 *position)
329{
330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
331 return -EINVAL;
332
333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
335
336 return 0;
337}
338
339/**
340 * dce_v11_0_hpd_sense - hpd sense callback.
341 *
342 * @adev: amdgpu_device pointer
343 * @hpd: hpd (hotplug detect) pin
344 *
345 * Checks if a digital monitor is connected (evergreen+).
346 * Returns true if connected, false if not connected.
347 */
348static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
349 enum amdgpu_hpd_id hpd)
350{
351 bool connected = false;
352
353 if (hpd >= adev->mode_info.num_hpd)
354 return connected;
355
356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
358 connected = true;
359
360 return connected;
361}
362
363/**
364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
365 *
366 * @adev: amdgpu_device pointer
367 * @hpd: hpd (hotplug detect) pin
368 *
369 * Set the polarity of the hpd pin (evergreen+).
370 */
371static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
372 enum amdgpu_hpd_id hpd)
373{
374 u32 tmp;
375 bool connected = dce_v11_0_hpd_sense(adev, hpd);
376
377 if (hpd >= adev->mode_info.num_hpd)
378 return;
379
380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
381 if (connected)
382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
383 else
384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
386}
387
388/**
389 * dce_v11_0_hpd_init - hpd setup callback.
390 *
391 * @adev: amdgpu_device pointer
392 *
393 * Setup the hpd pins used by the card (evergreen+).
394 * Enable the pin, set the polarity, and enable the hpd interrupts.
395 */
396static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
397{
398 struct drm_device *dev = adev->ddev;
399 struct drm_connector *connector;
400 u32 tmp;
401
402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
404
405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
406 continue;
407
408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
410 /* don't try to enable hpd on eDP or LVDS avoid breaking the
411 * aux dp channel on imac and help (but not completely fix)
412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
413 * also avoid interrupt storms during dpms.
414 */
415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
418 continue;
419 }
420
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
424
425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
427 DC_HPD_CONNECT_INT_DELAY,
428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
430 DC_HPD_DISCONNECT_INT_DELAY,
431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
433
434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
436 }
437}
438
439/**
440 * dce_v11_0_hpd_fini - hpd tear down callback.
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Tear down the hpd pins used by the card (evergreen+).
445 * Disable the hpd interrupts.
446 */
447static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
448{
449 struct drm_device *dev = adev->ddev;
450 struct drm_connector *connector;
451 u32 tmp;
452
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
455
456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
457 continue;
458
459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
462
463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
464 }
465}
466
467static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
468{
469 return mmDC_GPIO_HPD_A;
470}
471
472static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
473{
474 u32 crtc_hung = 0;
475 u32 crtc_status[6];
476 u32 i, j, tmp;
477
478 for (i = 0; i < adev->mode_info.num_crtc; i++) {
479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
482 crtc_hung |= (1 << i);
483 }
484 }
485
486 for (j = 0; j < 10; j++) {
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (crtc_hung & (1 << i)) {
489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 if (tmp != crtc_status[i])
491 crtc_hung &= ~(1 << i);
492 }
493 }
494 if (crtc_hung == 0)
495 return false;
496 udelay(100);
497 }
498
499 return true;
500}
501
502static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
503 struct amdgpu_mode_mc_save *save)
504{
505 u32 crtc_enabled, tmp;
506 int i;
507
508 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
509 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
510
511 /* disable VGA render */
512 tmp = RREG32(mmVGA_RENDER_CONTROL);
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
514 WREG32(mmVGA_RENDER_CONTROL, tmp);
515
516 /* blank the display controllers */
517 for (i = 0; i < adev->mode_info.num_crtc; i++) {
518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
519 CRTC_CONTROL, CRTC_MASTER_EN);
520 if (crtc_enabled) {
521#if 1
522 save->crtc_enabled[i] = true;
523 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
524 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
525 /*it is correct only for RGB ; black is 0*/
526 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
527 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
528 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
529 }
530#else
531 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
532 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
535 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 save->crtc_enabled[i] = false;
538 /* ***** */
539#endif
540 } else {
541 save->crtc_enabled[i] = false;
542 }
543 }
544}
545
546static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
547 struct amdgpu_mode_mc_save *save)
548{
549 u32 tmp;
550 int i;
551
552 /* update crtc base addresses */
553 for (i = 0; i < adev->mode_info.num_crtc; i++) {
554 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
555 upper_32_bits(adev->mc.vram_start));
556 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
557 (u32)adev->mc.vram_start);
558
559 if (save->crtc_enabled[i]) {
560 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
561 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
562 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
563 }
564 }
565
566 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
567 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
568
569 /* Unlock vga access */
570 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
571 mdelay(1);
572 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
573}
574
575static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
576 bool render)
577{
578 u32 tmp;
579
580 /* Lockout access through VGA aperture*/
581 tmp = RREG32(mmVGA_HDP_CONTROL);
582 if (render)
583 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
584 else
585 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
586 WREG32(mmVGA_HDP_CONTROL, tmp);
587
588 /* disable VGA render */
589 tmp = RREG32(mmVGA_RENDER_CONTROL);
590 if (render)
591 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
592 else
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
595}
596
597static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
598{
599 int num_crtc = 0;
600
601 switch (adev->asic_type) {
602 case CHIP_CARRIZO:
603 num_crtc = 3;
604 break;
605 case CHIP_STONEY:
606 num_crtc = 2;
607 break;
608 case CHIP_POLARIS10:
609 num_crtc = 6;
610 break;
611 case CHIP_POLARIS11:
612 case CHIP_POLARIS12:
613 num_crtc = 5;
614 break;
615 default:
616 num_crtc = 0;
617 }
618 return num_crtc;
619}
620
621void dce_v11_0_disable_dce(struct amdgpu_device *adev)
622{
623 /*Disable VGA render and enabled crtc, if has DCE engine*/
624 if (amdgpu_atombios_has_dce_engine_info(adev)) {
625 u32 tmp;
626 int crtc_enabled, i;
627
628 dce_v11_0_set_vga_render_state(adev, false);
629
630 /*Disable crtc*/
631 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
632 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
633 CRTC_CONTROL, CRTC_MASTER_EN);
634 if (crtc_enabled) {
635 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
636 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
637 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
638 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
639 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
640 }
641 }
642 }
643}
644
645static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
646{
647 struct drm_device *dev = encoder->dev;
648 struct amdgpu_device *adev = dev->dev_private;
649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
651 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
652 int bpc = 0;
653 u32 tmp = 0;
654 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
655
656 if (connector) {
657 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
658 bpc = amdgpu_connector_get_monitor_bpc(connector);
659 dither = amdgpu_connector->dither;
660 }
661
662 /* LVDS/eDP FMT is set up by atom */
663 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
664 return;
665
666 /* not needed for analog */
667 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
668 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
669 return;
670
671 if (bpc == 0)
672 return;
673
674 switch (bpc) {
675 case 6:
676 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
677 /* XXX sort out optimal dither settings */
678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
681 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
682 } else {
683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
684 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
685 }
686 break;
687 case 8:
688 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
689 /* XXX sort out optimal dither settings */
690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
694 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
695 } else {
696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
697 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
698 }
699 break;
700 case 10:
701 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
702 /* XXX sort out optimal dither settings */
703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
707 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
708 } else {
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
711 }
712 break;
713 default:
714 /* not needed */
715 break;
716 }
717
718 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
719}
720
721
722/* display watermark setup */
723/**
724 * dce_v11_0_line_buffer_adjust - Set up the line buffer
725 *
726 * @adev: amdgpu_device pointer
727 * @amdgpu_crtc: the selected display controller
728 * @mode: the current display mode on the selected display
729 * controller
730 *
731 * Setup up the line buffer allocation for
732 * the selected display controller (CIK).
733 * Returns the line buffer size in pixels.
734 */
735static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
736 struct amdgpu_crtc *amdgpu_crtc,
737 struct drm_display_mode *mode)
738{
739 u32 tmp, buffer_alloc, i, mem_cfg;
740 u32 pipe_offset = amdgpu_crtc->crtc_id;
741 /*
742 * Line Buffer Setup
743 * There are 6 line buffers, one for each display controllers.
744 * There are 3 partitions per LB. Select the number of partitions
745 * to enable based on the display width. For display widths larger
746 * than 4096, you need use to use 2 display controllers and combine
747 * them using the stereo blender.
748 */
749 if (amdgpu_crtc->base.enabled && mode) {
750 if (mode->crtc_hdisplay < 1920) {
751 mem_cfg = 1;
752 buffer_alloc = 2;
753 } else if (mode->crtc_hdisplay < 2560) {
754 mem_cfg = 2;
755 buffer_alloc = 2;
756 } else if (mode->crtc_hdisplay < 4096) {
757 mem_cfg = 0;
758 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
759 } else {
760 DRM_DEBUG_KMS("Mode too big for LB!\n");
761 mem_cfg = 0;
762 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
763 }
764 } else {
765 mem_cfg = 1;
766 buffer_alloc = 0;
767 }
768
769 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
770 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
771 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
772
773 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
774 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
775 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
776
777 for (i = 0; i < adev->usec_timeout; i++) {
778 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
779 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
780 break;
781 udelay(1);
782 }
783
784 if (amdgpu_crtc->base.enabled && mode) {
785 switch (mem_cfg) {
786 case 0:
787 default:
788 return 4096 * 2;
789 case 1:
790 return 1920 * 2;
791 case 2:
792 return 2560 * 2;
793 }
794 }
795
796 /* controller not enabled, so no lb used */
797 return 0;
798}
799
800/**
801 * cik_get_number_of_dram_channels - get the number of dram channels
802 *
803 * @adev: amdgpu_device pointer
804 *
805 * Look up the number of video ram channels (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the number of dram channels
808 */
809static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
810{
811 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
812
813 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
814 case 0:
815 default:
816 return 1;
817 case 1:
818 return 2;
819 case 2:
820 return 4;
821 case 3:
822 return 8;
823 case 4:
824 return 3;
825 case 5:
826 return 6;
827 case 6:
828 return 10;
829 case 7:
830 return 12;
831 case 8:
832 return 16;
833 }
834}
835
836struct dce10_wm_params {
837 u32 dram_channels; /* number of dram channels */
838 u32 yclk; /* bandwidth per dram data pin in kHz */
839 u32 sclk; /* engine clock in kHz */
840 u32 disp_clk; /* display clock in kHz */
841 u32 src_width; /* viewport width */
842 u32 active_time; /* active display time in ns */
843 u32 blank_time; /* blank time in ns */
844 bool interlaced; /* mode is interlaced */
845 fixed20_12 vsc; /* vertical scale ratio */
846 u32 num_heads; /* number of active crtcs */
847 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
848 u32 lb_size; /* line buffer allocated to pipe */
849 u32 vtaps; /* vertical scaler taps */
850};
851
852/**
853 * dce_v11_0_dram_bandwidth - get the dram bandwidth
854 *
855 * @wm: watermark calculation data
856 *
857 * Calculate the raw dram bandwidth (CIK).
858 * Used for display watermark bandwidth calculations
859 * Returns the dram bandwidth in MBytes/s
860 */
861static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
862{
863 /* Calculate raw DRAM Bandwidth */
864 fixed20_12 dram_efficiency; /* 0.7 */
865 fixed20_12 yclk, dram_channels, bandwidth;
866 fixed20_12 a;
867
868 a.full = dfixed_const(1000);
869 yclk.full = dfixed_const(wm->yclk);
870 yclk.full = dfixed_div(yclk, a);
871 dram_channels.full = dfixed_const(wm->dram_channels * 4);
872 a.full = dfixed_const(10);
873 dram_efficiency.full = dfixed_const(7);
874 dram_efficiency.full = dfixed_div(dram_efficiency, a);
875 bandwidth.full = dfixed_mul(dram_channels, yclk);
876 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
877
878 return dfixed_trunc(bandwidth);
879}
880
881/**
882 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the dram bandwidth used for display (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the dram bandwidth for display in MBytes/s
889 */
890static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
891{
892 /* Calculate DRAM Bandwidth and the part allocated to display. */
893 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
894 fixed20_12 yclk, dram_channels, bandwidth;
895 fixed20_12 a;
896
897 a.full = dfixed_const(1000);
898 yclk.full = dfixed_const(wm->yclk);
899 yclk.full = dfixed_div(yclk, a);
900 dram_channels.full = dfixed_const(wm->dram_channels * 4);
901 a.full = dfixed_const(10);
902 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
903 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
904 bandwidth.full = dfixed_mul(dram_channels, yclk);
905 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
906
907 return dfixed_trunc(bandwidth);
908}
909
910/**
911 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
912 *
913 * @wm: watermark calculation data
914 *
915 * Calculate the data return bandwidth used for display (CIK).
916 * Used for display watermark bandwidth calculations
917 * Returns the data return bandwidth in MBytes/s
918 */
919static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
920{
921 /* Calculate the display Data return Bandwidth */
922 fixed20_12 return_efficiency; /* 0.8 */
923 fixed20_12 sclk, bandwidth;
924 fixed20_12 a;
925
926 a.full = dfixed_const(1000);
927 sclk.full = dfixed_const(wm->sclk);
928 sclk.full = dfixed_div(sclk, a);
929 a.full = dfixed_const(10);
930 return_efficiency.full = dfixed_const(8);
931 return_efficiency.full = dfixed_div(return_efficiency, a);
932 a.full = dfixed_const(32);
933 bandwidth.full = dfixed_mul(a, sclk);
934 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
935
936 return dfixed_trunc(bandwidth);
937}
938
939/**
940 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
941 *
942 * @wm: watermark calculation data
943 *
944 * Calculate the dmif bandwidth used for display (CIK).
945 * Used for display watermark bandwidth calculations
946 * Returns the dmif bandwidth in MBytes/s
947 */
948static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
949{
950 /* Calculate the DMIF Request Bandwidth */
951 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
952 fixed20_12 disp_clk, bandwidth;
953 fixed20_12 a, b;
954
955 a.full = dfixed_const(1000);
956 disp_clk.full = dfixed_const(wm->disp_clk);
957 disp_clk.full = dfixed_div(disp_clk, a);
958 a.full = dfixed_const(32);
959 b.full = dfixed_mul(a, disp_clk);
960
961 a.full = dfixed_const(10);
962 disp_clk_request_efficiency.full = dfixed_const(8);
963 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
964
965 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
966
967 return dfixed_trunc(bandwidth);
968}
969
970/**
971 * dce_v11_0_available_bandwidth - get the min available bandwidth
972 *
973 * @wm: watermark calculation data
974 *
975 * Calculate the min available bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the min available bandwidth in MBytes/s
978 */
979static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
980{
981 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
982 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
983 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
984 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
985
986 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
987}
988
989/**
990 * dce_v11_0_average_bandwidth - get the average available bandwidth
991 *
992 * @wm: watermark calculation data
993 *
994 * Calculate the average available bandwidth used for display (CIK).
995 * Used for display watermark bandwidth calculations
996 * Returns the average available bandwidth in MBytes/s
997 */
998static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
999{
1000 /* Calculate the display mode Average Bandwidth
1001 * DisplayMode should contain the source and destination dimensions,
1002 * timing, etc.
1003 */
1004 fixed20_12 bpp;
1005 fixed20_12 line_time;
1006 fixed20_12 src_width;
1007 fixed20_12 bandwidth;
1008 fixed20_12 a;
1009
1010 a.full = dfixed_const(1000);
1011 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1012 line_time.full = dfixed_div(line_time, a);
1013 bpp.full = dfixed_const(wm->bytes_per_pixel);
1014 src_width.full = dfixed_const(wm->src_width);
1015 bandwidth.full = dfixed_mul(src_width, bpp);
1016 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1017 bandwidth.full = dfixed_div(bandwidth, line_time);
1018
1019 return dfixed_trunc(bandwidth);
1020}
1021
1022/**
1023 * dce_v11_0_latency_watermark - get the latency watermark
1024 *
1025 * @wm: watermark calculation data
1026 *
1027 * Calculate the latency watermark (CIK).
1028 * Used for display watermark bandwidth calculations
1029 * Returns the latency watermark in ns
1030 */
1031static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1032{
1033 /* First calculate the latency in ns */
1034 u32 mc_latency = 2000; /* 2000 ns. */
1035 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1036 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1037 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1038 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1039 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1040 (wm->num_heads * cursor_line_pair_return_time);
1041 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1042 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1043 u32 tmp, dmif_size = 12288;
1044 fixed20_12 a, b, c;
1045
1046 if (wm->num_heads == 0)
1047 return 0;
1048
1049 a.full = dfixed_const(2);
1050 b.full = dfixed_const(1);
1051 if ((wm->vsc.full > a.full) ||
1052 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1053 (wm->vtaps >= 5) ||
1054 ((wm->vsc.full >= a.full) && wm->interlaced))
1055 max_src_lines_per_dst_line = 4;
1056 else
1057 max_src_lines_per_dst_line = 2;
1058
1059 a.full = dfixed_const(available_bandwidth);
1060 b.full = dfixed_const(wm->num_heads);
1061 a.full = dfixed_div(a, b);
1062
1063 b.full = dfixed_const(mc_latency + 512);
1064 c.full = dfixed_const(wm->disp_clk);
1065 b.full = dfixed_div(b, c);
1066
1067 c.full = dfixed_const(dmif_size);
1068 b.full = dfixed_div(c, b);
1069
1070 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1071
1072 b.full = dfixed_const(1000);
1073 c.full = dfixed_const(wm->disp_clk);
1074 b.full = dfixed_div(c, b);
1075 c.full = dfixed_const(wm->bytes_per_pixel);
1076 b.full = dfixed_mul(b, c);
1077
1078 lb_fill_bw = min(tmp, dfixed_trunc(b));
1079
1080 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1081 b.full = dfixed_const(1000);
1082 c.full = dfixed_const(lb_fill_bw);
1083 b.full = dfixed_div(c, b);
1084 a.full = dfixed_div(a, b);
1085 line_fill_time = dfixed_trunc(a);
1086
1087 if (line_fill_time < wm->active_time)
1088 return latency;
1089 else
1090 return latency + (line_fill_time - wm->active_time);
1091
1092}
1093
1094/**
1095 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1096 * average and available dram bandwidth
1097 *
1098 * @wm: watermark calculation data
1099 *
1100 * Check if the display average bandwidth fits in the display
1101 * dram bandwidth (CIK).
1102 * Used for display watermark bandwidth calculations
1103 * Returns true if the display fits, false if not.
1104 */
1105static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1106{
1107 if (dce_v11_0_average_bandwidth(wm) <=
1108 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1109 return true;
1110 else
1111 return false;
1112}
1113
1114/**
1115 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1116 * average and available bandwidth
1117 *
1118 * @wm: watermark calculation data
1119 *
1120 * Check if the display average bandwidth fits in the display
1121 * available bandwidth (CIK).
1122 * Used for display watermark bandwidth calculations
1123 * Returns true if the display fits, false if not.
1124 */
1125static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1126{
1127 if (dce_v11_0_average_bandwidth(wm) <=
1128 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1129 return true;
1130 else
1131 return false;
1132}
1133
1134/**
1135 * dce_v11_0_check_latency_hiding - check latency hiding
1136 *
1137 * @wm: watermark calculation data
1138 *
1139 * Check latency hiding (CIK).
1140 * Used for display watermark bandwidth calculations
1141 * Returns true if the display fits, false if not.
1142 */
1143static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1144{
1145 u32 lb_partitions = wm->lb_size / wm->src_width;
1146 u32 line_time = wm->active_time + wm->blank_time;
1147 u32 latency_tolerant_lines;
1148 u32 latency_hiding;
1149 fixed20_12 a;
1150
1151 a.full = dfixed_const(1);
1152 if (wm->vsc.full > a.full)
1153 latency_tolerant_lines = 1;
1154 else {
1155 if (lb_partitions <= (wm->vtaps + 1))
1156 latency_tolerant_lines = 1;
1157 else
1158 latency_tolerant_lines = 2;
1159 }
1160
1161 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1162
1163 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1164 return true;
1165 else
1166 return false;
1167}
1168
1169/**
1170 * dce_v11_0_program_watermarks - program display watermarks
1171 *
1172 * @adev: amdgpu_device pointer
1173 * @amdgpu_crtc: the selected display controller
1174 * @lb_size: line buffer size
1175 * @num_heads: number of display controllers in use
1176 *
1177 * Calculate and program the display watermarks for the
1178 * selected display controller (CIK).
1179 */
1180static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1181 struct amdgpu_crtc *amdgpu_crtc,
1182 u32 lb_size, u32 num_heads)
1183{
1184 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1185 struct dce10_wm_params wm_low, wm_high;
1186 u32 pixel_period;
1187 u32 line_time = 0;
1188 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1189 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1190
1191 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1192 pixel_period = 1000000 / (u32)mode->clock;
1193 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1194
1195 /* watermark for high clocks */
1196 if (adev->pm.dpm_enabled) {
1197 wm_high.yclk =
1198 amdgpu_dpm_get_mclk(adev, false) * 10;
1199 wm_high.sclk =
1200 amdgpu_dpm_get_sclk(adev, false) * 10;
1201 } else {
1202 wm_high.yclk = adev->pm.current_mclk * 10;
1203 wm_high.sclk = adev->pm.current_sclk * 10;
1204 }
1205
1206 wm_high.disp_clk = mode->clock;
1207 wm_high.src_width = mode->crtc_hdisplay;
1208 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1209 wm_high.blank_time = line_time - wm_high.active_time;
1210 wm_high.interlaced = false;
1211 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1212 wm_high.interlaced = true;
1213 wm_high.vsc = amdgpu_crtc->vsc;
1214 wm_high.vtaps = 1;
1215 if (amdgpu_crtc->rmx_type != RMX_OFF)
1216 wm_high.vtaps = 2;
1217 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1218 wm_high.lb_size = lb_size;
1219 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1220 wm_high.num_heads = num_heads;
1221
1222 /* set for high clocks */
1223 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1224
1225 /* possibly force display priority to high */
1226 /* should really do this at mode validation time... */
1227 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1228 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1229 !dce_v11_0_check_latency_hiding(&wm_high) ||
1230 (adev->mode_info.disp_priority == 2)) {
1231 DRM_DEBUG_KMS("force priority to high\n");
1232 }
1233
1234 /* watermark for low clocks */
1235 if (adev->pm.dpm_enabled) {
1236 wm_low.yclk =
1237 amdgpu_dpm_get_mclk(adev, true) * 10;
1238 wm_low.sclk =
1239 amdgpu_dpm_get_sclk(adev, true) * 10;
1240 } else {
1241 wm_low.yclk = adev->pm.current_mclk * 10;
1242 wm_low.sclk = adev->pm.current_sclk * 10;
1243 }
1244
1245 wm_low.disp_clk = mode->clock;
1246 wm_low.src_width = mode->crtc_hdisplay;
1247 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1248 wm_low.blank_time = line_time - wm_low.active_time;
1249 wm_low.interlaced = false;
1250 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1251 wm_low.interlaced = true;
1252 wm_low.vsc = amdgpu_crtc->vsc;
1253 wm_low.vtaps = 1;
1254 if (amdgpu_crtc->rmx_type != RMX_OFF)
1255 wm_low.vtaps = 2;
1256 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1257 wm_low.lb_size = lb_size;
1258 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1259 wm_low.num_heads = num_heads;
1260
1261 /* set for low clocks */
1262 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1263
1264 /* possibly force display priority to high */
1265 /* should really do this at mode validation time... */
1266 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1267 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1268 !dce_v11_0_check_latency_hiding(&wm_low) ||
1269 (adev->mode_info.disp_priority == 2)) {
1270 DRM_DEBUG_KMS("force priority to high\n");
1271 }
1272 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1273 }
1274
1275 /* select wm A */
1276 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1277 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1278 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1279 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1280 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1281 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1282 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1283 /* select wm B */
1284 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1285 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1286 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1287 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1288 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1289 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1290 /* restore original selection */
1291 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1292
1293 /* save values for DPM */
1294 amdgpu_crtc->line_time = line_time;
1295 amdgpu_crtc->wm_high = latency_watermark_a;
1296 amdgpu_crtc->wm_low = latency_watermark_b;
1297 /* Save number of lines the linebuffer leads before the scanout */
1298 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1299}
1300
1301/**
1302 * dce_v11_0_bandwidth_update - program display watermarks
1303 *
1304 * @adev: amdgpu_device pointer
1305 *
1306 * Calculate and program the display watermarks and line
1307 * buffer allocation (CIK).
1308 */
1309static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1310{
1311 struct drm_display_mode *mode = NULL;
1312 u32 num_heads = 0, lb_size;
1313 int i;
1314
1315 amdgpu_update_display_priority(adev);
1316
1317 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1318 if (adev->mode_info.crtcs[i]->base.enabled)
1319 num_heads++;
1320 }
1321 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1322 mode = &adev->mode_info.crtcs[i]->base.mode;
1323 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1324 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1325 lb_size, num_heads);
1326 }
1327}
1328
1329static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1330{
1331 int i;
1332 u32 offset, tmp;
1333
1334 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1335 offset = adev->mode_info.audio.pin[i].offset;
1336 tmp = RREG32_AUDIO_ENDPT(offset,
1337 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1338 if (((tmp &
1339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1341 adev->mode_info.audio.pin[i].connected = false;
1342 else
1343 adev->mode_info.audio.pin[i].connected = true;
1344 }
1345}
1346
1347static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1348{
1349 int i;
1350
1351 dce_v11_0_audio_get_connected_pins(adev);
1352
1353 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1354 if (adev->mode_info.audio.pin[i].connected)
1355 return &adev->mode_info.audio.pin[i];
1356 }
1357 DRM_ERROR("No connected audio pins found!\n");
1358 return NULL;
1359}
1360
1361static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1362{
1363 struct amdgpu_device *adev = encoder->dev->dev_private;
1364 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1366 u32 tmp;
1367
1368 if (!dig || !dig->afmt || !dig->afmt->pin)
1369 return;
1370
1371 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1372 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1373 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1374}
1375
1376static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1377 struct drm_display_mode *mode)
1378{
1379 struct amdgpu_device *adev = encoder->dev->dev_private;
1380 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1381 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1382 struct drm_connector *connector;
1383 struct amdgpu_connector *amdgpu_connector = NULL;
1384 u32 tmp;
1385 int interlace = 0;
1386
1387 if (!dig || !dig->afmt || !dig->afmt->pin)
1388 return;
1389
1390 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1391 if (connector->encoder == encoder) {
1392 amdgpu_connector = to_amdgpu_connector(connector);
1393 break;
1394 }
1395 }
1396
1397 if (!amdgpu_connector) {
1398 DRM_ERROR("Couldn't find encoder's connector\n");
1399 return;
1400 }
1401
1402 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1403 interlace = 1;
1404 if (connector->latency_present[interlace]) {
1405 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1406 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1407 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1408 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1409 } else {
1410 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1411 VIDEO_LIPSYNC, 0);
1412 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1413 AUDIO_LIPSYNC, 0);
1414 }
1415 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1416 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1417}
1418
1419static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1420{
1421 struct amdgpu_device *adev = encoder->dev->dev_private;
1422 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1424 struct drm_connector *connector;
1425 struct amdgpu_connector *amdgpu_connector = NULL;
1426 u32 tmp;
1427 u8 *sadb = NULL;
1428 int sad_count;
1429
1430 if (!dig || !dig->afmt || !dig->afmt->pin)
1431 return;
1432
1433 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1434 if (connector->encoder == encoder) {
1435 amdgpu_connector = to_amdgpu_connector(connector);
1436 break;
1437 }
1438 }
1439
1440 if (!amdgpu_connector) {
1441 DRM_ERROR("Couldn't find encoder's connector\n");
1442 return;
1443 }
1444
1445 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1446 if (sad_count < 0) {
1447 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1448 sad_count = 0;
1449 }
1450
1451 /* program the speaker allocation */
1452 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1453 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1454 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1455 DP_CONNECTION, 0);
1456 /* set HDMI mode */
1457 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1458 HDMI_CONNECTION, 1);
1459 if (sad_count)
1460 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1461 SPEAKER_ALLOCATION, sadb[0]);
1462 else
1463 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1464 SPEAKER_ALLOCATION, 5); /* stereo */
1465 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1466 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1467
1468 kfree(sadb);
1469}
1470
1471static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1472{
1473 struct amdgpu_device *adev = encoder->dev->dev_private;
1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476 struct drm_connector *connector;
1477 struct amdgpu_connector *amdgpu_connector = NULL;
1478 struct cea_sad *sads;
1479 int i, sad_count;
1480
1481 static const u16 eld_reg_to_type[][2] = {
1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1493 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1494 };
1495
1496 if (!dig || !dig->afmt || !dig->afmt->pin)
1497 return;
1498
1499 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500 if (connector->encoder == encoder) {
1501 amdgpu_connector = to_amdgpu_connector(connector);
1502 break;
1503 }
1504 }
1505
1506 if (!amdgpu_connector) {
1507 DRM_ERROR("Couldn't find encoder's connector\n");
1508 return;
1509 }
1510
1511 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1512 if (sad_count <= 0) {
1513 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1514 return;
1515 }
1516 BUG_ON(!sads);
1517
1518 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1519 u32 tmp = 0;
1520 u8 stereo_freqs = 0;
1521 int max_channels = -1;
1522 int j;
1523
1524 for (j = 0; j < sad_count; j++) {
1525 struct cea_sad *sad = &sads[j];
1526
1527 if (sad->format == eld_reg_to_type[i][1]) {
1528 if (sad->channels > max_channels) {
1529 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1530 MAX_CHANNELS, sad->channels);
1531 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1532 DESCRIPTOR_BYTE_2, sad->byte2);
1533 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1534 SUPPORTED_FREQUENCIES, sad->freq);
1535 max_channels = sad->channels;
1536 }
1537
1538 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1539 stereo_freqs |= sad->freq;
1540 else
1541 break;
1542 }
1543 }
1544
1545 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1546 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1547 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1548 }
1549
1550 kfree(sads);
1551}
1552
1553static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1554 struct amdgpu_audio_pin *pin,
1555 bool enable)
1556{
1557 if (!pin)
1558 return;
1559
1560 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1561 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1562}
1563
1564static const u32 pin_offsets[] =
1565{
1566 AUD0_REGISTER_OFFSET,
1567 AUD1_REGISTER_OFFSET,
1568 AUD2_REGISTER_OFFSET,
1569 AUD3_REGISTER_OFFSET,
1570 AUD4_REGISTER_OFFSET,
1571 AUD5_REGISTER_OFFSET,
1572 AUD6_REGISTER_OFFSET,
1573 AUD7_REGISTER_OFFSET,
1574};
1575
1576static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1577{
1578 int i;
1579
1580 if (!amdgpu_audio)
1581 return 0;
1582
1583 adev->mode_info.audio.enabled = true;
1584
1585 switch (adev->asic_type) {
1586 case CHIP_CARRIZO:
1587 case CHIP_STONEY:
1588 adev->mode_info.audio.num_pins = 7;
1589 break;
1590 case CHIP_POLARIS10:
1591 adev->mode_info.audio.num_pins = 8;
1592 break;
1593 case CHIP_POLARIS11:
1594 case CHIP_POLARIS12:
1595 adev->mode_info.audio.num_pins = 6;
1596 break;
1597 default:
1598 return -EINVAL;
1599 }
1600
1601 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1602 adev->mode_info.audio.pin[i].channels = -1;
1603 adev->mode_info.audio.pin[i].rate = -1;
1604 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1605 adev->mode_info.audio.pin[i].status_bits = 0;
1606 adev->mode_info.audio.pin[i].category_code = 0;
1607 adev->mode_info.audio.pin[i].connected = false;
1608 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1609 adev->mode_info.audio.pin[i].id = i;
1610 /* disable audio. it will be set up later */
1611 /* XXX remove once we switch to ip funcs */
1612 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1613 }
1614
1615 return 0;
1616}
1617
1618static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1619{
1620 int i;
1621
1622 if (!amdgpu_audio)
1623 return;
1624
1625 if (!adev->mode_info.audio.enabled)
1626 return;
1627
1628 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1629 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1630
1631 adev->mode_info.audio.enabled = false;
1632}
1633
1634/*
1635 * update the N and CTS parameters for a given pixel clock rate
1636 */
1637static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1638{
1639 struct drm_device *dev = encoder->dev;
1640 struct amdgpu_device *adev = dev->dev_private;
1641 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1642 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1643 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1644 u32 tmp;
1645
1646 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1647 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1648 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1649 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1650 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1651 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1652
1653 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1654 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1655 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1656 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1657 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1658 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1659
1660 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1661 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1662 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1663 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1664 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1665 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1666
1667}
1668
1669/*
1670 * build a HDMI Video Info Frame
1671 */
1672static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1673 void *buffer, size_t size)
1674{
1675 struct drm_device *dev = encoder->dev;
1676 struct amdgpu_device *adev = dev->dev_private;
1677 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1678 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1679 uint8_t *frame = buffer + 3;
1680 uint8_t *header = buffer;
1681
1682 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1683 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1684 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1685 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1686 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1687 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1688 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1689 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1690}
1691
1692static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1693{
1694 struct drm_device *dev = encoder->dev;
1695 struct amdgpu_device *adev = dev->dev_private;
1696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1697 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1699 u32 dto_phase = 24 * 1000;
1700 u32 dto_modulo = clock;
1701 u32 tmp;
1702
1703 if (!dig || !dig->afmt)
1704 return;
1705
1706 /* XXX two dtos; generally use dto0 for hdmi */
1707 /* Express [24MHz / target pixel clock] as an exact rational
1708 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1709 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1710 */
1711 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1712 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1713 amdgpu_crtc->crtc_id);
1714 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1715 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1716 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1717}
1718
1719/*
1720 * update the info frames with the data from the current display mode
1721 */
1722static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1723 struct drm_display_mode *mode)
1724{
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1730 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1731 struct hdmi_avi_infoframe frame;
1732 ssize_t err;
1733 u32 tmp;
1734 int bpc = 8;
1735
1736 if (!dig || !dig->afmt)
1737 return;
1738
1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig->afmt->enabled)
1741 return;
1742
1743 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1744 if (encoder->crtc) {
1745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1746 bpc = amdgpu_crtc->bpc;
1747 }
1748
1749 /* disable audio prior to setting up hw */
1750 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1751 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1752
1753 dce_v11_0_audio_set_dto(encoder, mode->clock);
1754
1755 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1756 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1758
1759 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1760
1761 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1762 switch (bpc) {
1763 case 0:
1764 case 6:
1765 case 8:
1766 case 16:
1767 default:
1768 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1769 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1770 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1771 connector->name, bpc);
1772 break;
1773 case 10:
1774 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1775 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1776 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1777 connector->name);
1778 break;
1779 case 12:
1780 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1781 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1782 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1783 connector->name);
1784 break;
1785 }
1786 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1787
1788 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1789 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1791 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1792 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1793
1794 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1795 /* enable audio info frames (frames won't be set until audio is enabled) */
1796 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1797 /* required for audio info values to be updated */
1798 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1799 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1800
1801 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1802 /* required for audio info values to be updated */
1803 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1804 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1805
1806 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1807 /* anything other than 0 */
1808 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1809 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1810
1811 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1812
1813 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1814 /* set the default audio delay */
1815 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1816 /* should be suffient for all audio modes and small enough for all hblanks */
1817 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1818 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1819
1820 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1821 /* allow 60958 channel status fields to be updated */
1822 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1823 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1824
1825 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1826 if (bpc > 8)
1827 /* clear SW CTS value */
1828 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1829 else
1830 /* select SW CTS value */
1831 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1832 /* allow hw to sent ACR packets when required */
1833 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1834 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1835
1836 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1837
1838 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1839 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1840 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1841
1842 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1843 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1844 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1845
1846 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1847 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1848 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1849 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1850 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1851 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1852 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1853 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1854
1855 dce_v11_0_audio_write_speaker_allocation(encoder);
1856
1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1858 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1859
1860 dce_v11_0_afmt_audio_select_pin(encoder);
1861 dce_v11_0_audio_write_sad_regs(encoder);
1862 dce_v11_0_audio_write_latency_fields(encoder, mode);
1863
1864 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1865 if (err < 0) {
1866 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1867 return;
1868 }
1869
1870 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1871 if (err < 0) {
1872 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1873 return;
1874 }
1875
1876 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1877
1878 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1879 /* enable AVI info frames */
1880 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1881 /* required for audio info values to be updated */
1882 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1883 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1884
1885 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1886 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1887 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1888
1889 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1890 /* send audio packets */
1891 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1892 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1893
1894 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1895 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1896 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1897 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1898
1899 /* enable audio after to setting up hw */
1900 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1901}
1902
1903static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1904{
1905 struct drm_device *dev = encoder->dev;
1906 struct amdgpu_device *adev = dev->dev_private;
1907 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1908 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1909
1910 if (!dig || !dig->afmt)
1911 return;
1912
1913 /* Silent, r600_hdmi_enable will raise WARN for us */
1914 if (enable && dig->afmt->enabled)
1915 return;
1916 if (!enable && !dig->afmt->enabled)
1917 return;
1918
1919 if (!enable && dig->afmt->pin) {
1920 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1921 dig->afmt->pin = NULL;
1922 }
1923
1924 dig->afmt->enabled = enable;
1925
1926 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1927 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1928}
1929
1930static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1931{
1932 int i;
1933
1934 for (i = 0; i < adev->mode_info.num_dig; i++)
1935 adev->mode_info.afmt[i] = NULL;
1936
1937 /* DCE11 has audio blocks tied to DIG encoders */
1938 for (i = 0; i < adev->mode_info.num_dig; i++) {
1939 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1940 if (adev->mode_info.afmt[i]) {
1941 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1942 adev->mode_info.afmt[i]->id = i;
1943 } else {
1944 int j;
1945 for (j = 0; j < i; j++) {
1946 kfree(adev->mode_info.afmt[j]);
1947 adev->mode_info.afmt[j] = NULL;
1948 }
1949 return -ENOMEM;
1950 }
1951 }
1952 return 0;
1953}
1954
1955static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1956{
1957 int i;
1958
1959 for (i = 0; i < adev->mode_info.num_dig; i++) {
1960 kfree(adev->mode_info.afmt[i]);
1961 adev->mode_info.afmt[i] = NULL;
1962 }
1963}
1964
1965static const u32 vga_control_regs[6] =
1966{
1967 mmD1VGA_CONTROL,
1968 mmD2VGA_CONTROL,
1969 mmD3VGA_CONTROL,
1970 mmD4VGA_CONTROL,
1971 mmD5VGA_CONTROL,
1972 mmD6VGA_CONTROL,
1973};
1974
1975static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1976{
1977 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1978 struct drm_device *dev = crtc->dev;
1979 struct amdgpu_device *adev = dev->dev_private;
1980 u32 vga_control;
1981
1982 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1983 if (enable)
1984 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1985 else
1986 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1987}
1988
1989static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1990{
1991 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992 struct drm_device *dev = crtc->dev;
1993 struct amdgpu_device *adev = dev->dev_private;
1994
1995 if (enable)
1996 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1997 else
1998 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1999}
2000
2001static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2002 struct drm_framebuffer *fb,
2003 int x, int y, int atomic)
2004{
2005 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2008 struct amdgpu_framebuffer *amdgpu_fb;
2009 struct drm_framebuffer *target_fb;
2010 struct drm_gem_object *obj;
2011 struct amdgpu_bo *abo;
2012 uint64_t fb_location, tiling_flags;
2013 uint32_t fb_format, fb_pitch_pixels;
2014 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2015 u32 pipe_config;
2016 u32 tmp, viewport_w, viewport_h;
2017 int r;
2018 bool bypass_lut = false;
2019 struct drm_format_name_buf format_name;
2020
2021 /* no fb bound */
2022 if (!atomic && !crtc->primary->fb) {
2023 DRM_DEBUG_KMS("No FB bound\n");
2024 return 0;
2025 }
2026
2027 if (atomic) {
2028 amdgpu_fb = to_amdgpu_framebuffer(fb);
2029 target_fb = fb;
2030 } else {
2031 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2032 target_fb = crtc->primary->fb;
2033 }
2034
2035 /* If atomic, assume fb object is pinned & idle & fenced and
2036 * just update base pointers
2037 */
2038 obj = amdgpu_fb->obj;
2039 abo = gem_to_amdgpu_bo(obj);
2040 r = amdgpu_bo_reserve(abo, false);
2041 if (unlikely(r != 0))
2042 return r;
2043
2044 if (atomic) {
2045 fb_location = amdgpu_bo_gpu_offset(abo);
2046 } else {
2047 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2048 if (unlikely(r != 0)) {
2049 amdgpu_bo_unreserve(abo);
2050 return -EINVAL;
2051 }
2052 }
2053
2054 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2055 amdgpu_bo_unreserve(abo);
2056
2057 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2058
2059 switch (target_fb->pixel_format) {
2060 case DRM_FORMAT_C8:
2061 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2062 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2063 break;
2064 case DRM_FORMAT_XRGB4444:
2065 case DRM_FORMAT_ARGB4444:
2066 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2067 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2068#ifdef __BIG_ENDIAN
2069 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2070 ENDIAN_8IN16);
2071#endif
2072 break;
2073 case DRM_FORMAT_XRGB1555:
2074 case DRM_FORMAT_ARGB1555:
2075 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2076 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2077#ifdef __BIG_ENDIAN
2078 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2079 ENDIAN_8IN16);
2080#endif
2081 break;
2082 case DRM_FORMAT_BGRX5551:
2083 case DRM_FORMAT_BGRA5551:
2084 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2085 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2086#ifdef __BIG_ENDIAN
2087 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2088 ENDIAN_8IN16);
2089#endif
2090 break;
2091 case DRM_FORMAT_RGB565:
2092 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2093 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2094#ifdef __BIG_ENDIAN
2095 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2096 ENDIAN_8IN16);
2097#endif
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2102 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2103#ifdef __BIG_ENDIAN
2104 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2105 ENDIAN_8IN32);
2106#endif
2107 break;
2108 case DRM_FORMAT_XRGB2101010:
2109 case DRM_FORMAT_ARGB2101010:
2110 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2111 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2112#ifdef __BIG_ENDIAN
2113 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2114 ENDIAN_8IN32);
2115#endif
2116 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2117 bypass_lut = true;
2118 break;
2119 case DRM_FORMAT_BGRX1010102:
2120 case DRM_FORMAT_BGRA1010102:
2121 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2122 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2123#ifdef __BIG_ENDIAN
2124 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125 ENDIAN_8IN32);
2126#endif
2127 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2128 bypass_lut = true;
2129 break;
2130 default:
2131 DRM_ERROR("Unsupported screen format %s\n",
2132 drm_get_format_name(target_fb->pixel_format, &format_name));
2133 return -EINVAL;
2134 }
2135
2136 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2137 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2138
2139 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2140 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2141 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2142 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2143 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2144
2145 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2147 ARRAY_2D_TILED_THIN1);
2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2149 tile_split);
2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2153 mtaspect);
2154 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2155 ADDR_SURF_MICRO_TILING_DISPLAY);
2156 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2158 ARRAY_1D_TILED_THIN1);
2159 }
2160
2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2162 pipe_config);
2163
2164 dce_v11_0_vga_enable(crtc, false);
2165
2166 /* Make sure surface address is updated at vertical blank rather than
2167 * horizontal blank
2168 */
2169 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2170 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2171 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2172 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2173
2174 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2175 upper_32_bits(fb_location));
2176 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2177 upper_32_bits(fb_location));
2178 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2179 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2180 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2181 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2182 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2183 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2184
2185 /*
2186 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2187 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2188 * retain the full precision throughout the pipeline.
2189 */
2190 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2191 if (bypass_lut)
2192 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2193 else
2194 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2195 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2196
2197 if (bypass_lut)
2198 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2199
2200 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2201 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2202 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2203 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2204 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2205 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2206
2207 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2208 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2209
2210 dce_v11_0_grph_enable(crtc, true);
2211
2212 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2213 target_fb->height);
2214
2215 x &= ~3;
2216 y &= ~1;
2217 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2218 (x << 16) | y);
2219 viewport_w = crtc->mode.hdisplay;
2220 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2221 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2222 (viewport_w << 16) | viewport_h);
2223
2224 /* set pageflip to happen anywhere in vblank interval */
2225 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2226
2227 if (!atomic && fb && fb != crtc->primary->fb) {
2228 amdgpu_fb = to_amdgpu_framebuffer(fb);
2229 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2230 r = amdgpu_bo_reserve(abo, false);
2231 if (unlikely(r != 0))
2232 return r;
2233 amdgpu_bo_unpin(abo);
2234 amdgpu_bo_unreserve(abo);
2235 }
2236
2237 /* Bytes per pixel may have changed */
2238 dce_v11_0_bandwidth_update(adev);
2239
2240 return 0;
2241}
2242
2243static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2244 struct drm_display_mode *mode)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct amdgpu_device *adev = dev->dev_private;
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 u32 tmp;
2250
2251 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2252 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2253 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2254 else
2255 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2256 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2257}
2258
2259static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2260{
2261 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2262 struct drm_device *dev = crtc->dev;
2263 struct amdgpu_device *adev = dev->dev_private;
2264 int i;
2265 u32 tmp;
2266
2267 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2268
2269 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2270 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2271 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2272
2273 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2274 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2275 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2276
2277 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2278 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2279 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2280
2281 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2282
2283 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2284 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2285 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2286
2287 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2288 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2289 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2290
2291 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2292 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2293
2294 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2295 for (i = 0; i < 256; i++) {
2296 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2297 (amdgpu_crtc->lut_r[i] << 20) |
2298 (amdgpu_crtc->lut_g[i] << 10) |
2299 (amdgpu_crtc->lut_b[i] << 0));
2300 }
2301
2302 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2303 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2304 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2305 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2306 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2307
2308 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2309 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2310 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2311
2312 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2313 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2314 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2315
2316 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2317 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2318 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319
2320 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2321 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2322 /* XXX this only needs to be programmed once per crtc at startup,
2323 * not sure where the best place for it is
2324 */
2325 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2326 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2327 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2328}
2329
2330static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2331{
2332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2334
2335 switch (amdgpu_encoder->encoder_id) {
2336 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2337 if (dig->linkb)
2338 return 1;
2339 else
2340 return 0;
2341 break;
2342 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2343 if (dig->linkb)
2344 return 3;
2345 else
2346 return 2;
2347 break;
2348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2349 if (dig->linkb)
2350 return 5;
2351 else
2352 return 4;
2353 break;
2354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2355 return 6;
2356 break;
2357 default:
2358 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2359 return 0;
2360 }
2361}
2362
2363/**
2364 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2365 *
2366 * @crtc: drm crtc
2367 *
2368 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2369 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2370 * monitors a dedicated PPLL must be used. If a particular board has
2371 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2372 * as there is no need to program the PLL itself. If we are not able to
2373 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2374 * avoid messing up an existing monitor.
2375 *
2376 * Asic specific PLL information
2377 *
2378 * DCE 10.x
2379 * Tonga
2380 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2381 * CI
2382 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2383 *
2384 */
2385static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2386{
2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2388 struct drm_device *dev = crtc->dev;
2389 struct amdgpu_device *adev = dev->dev_private;
2390 u32 pll_in_use;
2391 int pll;
2392
2393 if ((adev->asic_type == CHIP_POLARIS10) ||
2394 (adev->asic_type == CHIP_POLARIS11) ||
2395 (adev->asic_type == CHIP_POLARIS12)) {
2396 struct amdgpu_encoder *amdgpu_encoder =
2397 to_amdgpu_encoder(amdgpu_crtc->encoder);
2398 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2399
2400 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2401 return ATOM_DP_DTO;
2402
2403 switch (amdgpu_encoder->encoder_id) {
2404 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2405 if (dig->linkb)
2406 return ATOM_COMBOPHY_PLL1;
2407 else
2408 return ATOM_COMBOPHY_PLL0;
2409 break;
2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2411 if (dig->linkb)
2412 return ATOM_COMBOPHY_PLL3;
2413 else
2414 return ATOM_COMBOPHY_PLL2;
2415 break;
2416 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2417 if (dig->linkb)
2418 return ATOM_COMBOPHY_PLL5;
2419 else
2420 return ATOM_COMBOPHY_PLL4;
2421 break;
2422 default:
2423 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2424 return ATOM_PPLL_INVALID;
2425 }
2426 }
2427
2428 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2429 if (adev->clock.dp_extclk)
2430 /* skip PPLL programming if using ext clock */
2431 return ATOM_PPLL_INVALID;
2432 else {
2433 /* use the same PPLL for all DP monitors */
2434 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2435 if (pll != ATOM_PPLL_INVALID)
2436 return pll;
2437 }
2438 } else {
2439 /* use the same PPLL for all monitors with the same clock */
2440 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2441 if (pll != ATOM_PPLL_INVALID)
2442 return pll;
2443 }
2444
2445 /* XXX need to determine what plls are available on each DCE11 part */
2446 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2447 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2448 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2449 return ATOM_PPLL1;
2450 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2451 return ATOM_PPLL0;
2452 DRM_ERROR("unable to allocate a PPLL\n");
2453 return ATOM_PPLL_INVALID;
2454 } else {
2455 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2456 return ATOM_PPLL2;
2457 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2458 return ATOM_PPLL1;
2459 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2460 return ATOM_PPLL0;
2461 DRM_ERROR("unable to allocate a PPLL\n");
2462 return ATOM_PPLL_INVALID;
2463 }
2464 return ATOM_PPLL_INVALID;
2465}
2466
2467static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2468{
2469 struct amdgpu_device *adev = crtc->dev->dev_private;
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471 uint32_t cur_lock;
2472
2473 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2474 if (lock)
2475 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2476 else
2477 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2478 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2479}
2480
2481static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2482{
2483 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2484 struct amdgpu_device *adev = crtc->dev->dev_private;
2485 u32 tmp;
2486
2487 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2488 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2489 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2490}
2491
2492static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2493{
2494 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2495 struct amdgpu_device *adev = crtc->dev->dev_private;
2496 u32 tmp;
2497
2498 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2499 upper_32_bits(amdgpu_crtc->cursor_addr));
2500 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2501 lower_32_bits(amdgpu_crtc->cursor_addr));
2502
2503 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2504 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2506 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2507}
2508
2509static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2510 int x, int y)
2511{
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513 struct amdgpu_device *adev = crtc->dev->dev_private;
2514 int xorigin = 0, yorigin = 0;
2515
2516 amdgpu_crtc->cursor_x = x;
2517 amdgpu_crtc->cursor_y = y;
2518
2519 /* avivo cursor are offset into the total surface */
2520 x += crtc->x;
2521 y += crtc->y;
2522 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2523
2524 if (x < 0) {
2525 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2526 x = 0;
2527 }
2528 if (y < 0) {
2529 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2530 y = 0;
2531 }
2532
2533 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2534 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2535 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2536 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2537
2538 return 0;
2539}
2540
2541static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2542 int x, int y)
2543{
2544 int ret;
2545
2546 dce_v11_0_lock_cursor(crtc, true);
2547 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2548 dce_v11_0_lock_cursor(crtc, false);
2549
2550 return ret;
2551}
2552
2553static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2554 struct drm_file *file_priv,
2555 uint32_t handle,
2556 uint32_t width,
2557 uint32_t height,
2558 int32_t hot_x,
2559 int32_t hot_y)
2560{
2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2562 struct drm_gem_object *obj;
2563 struct amdgpu_bo *aobj;
2564 int ret;
2565
2566 if (!handle) {
2567 /* turn off cursor */
2568 dce_v11_0_hide_cursor(crtc);
2569 obj = NULL;
2570 goto unpin;
2571 }
2572
2573 if ((width > amdgpu_crtc->max_cursor_width) ||
2574 (height > amdgpu_crtc->max_cursor_height)) {
2575 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2576 return -EINVAL;
2577 }
2578
2579 obj = drm_gem_object_lookup(file_priv, handle);
2580 if (!obj) {
2581 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2582 return -ENOENT;
2583 }
2584
2585 aobj = gem_to_amdgpu_bo(obj);
2586 ret = amdgpu_bo_reserve(aobj, false);
2587 if (ret != 0) {
2588 drm_gem_object_unreference_unlocked(obj);
2589 return ret;
2590 }
2591
2592 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2593 amdgpu_bo_unreserve(aobj);
2594 if (ret) {
2595 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2596 drm_gem_object_unreference_unlocked(obj);
2597 return ret;
2598 }
2599
2600 dce_v11_0_lock_cursor(crtc, true);
2601
2602 if (width != amdgpu_crtc->cursor_width ||
2603 height != amdgpu_crtc->cursor_height ||
2604 hot_x != amdgpu_crtc->cursor_hot_x ||
2605 hot_y != amdgpu_crtc->cursor_hot_y) {
2606 int x, y;
2607
2608 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2609 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2610
2611 dce_v11_0_cursor_move_locked(crtc, x, y);
2612
2613 amdgpu_crtc->cursor_width = width;
2614 amdgpu_crtc->cursor_height = height;
2615 amdgpu_crtc->cursor_hot_x = hot_x;
2616 amdgpu_crtc->cursor_hot_y = hot_y;
2617 }
2618
2619 dce_v11_0_show_cursor(crtc);
2620 dce_v11_0_lock_cursor(crtc, false);
2621
2622unpin:
2623 if (amdgpu_crtc->cursor_bo) {
2624 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2625 ret = amdgpu_bo_reserve(aobj, false);
2626 if (likely(ret == 0)) {
2627 amdgpu_bo_unpin(aobj);
2628 amdgpu_bo_unreserve(aobj);
2629 }
2630 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2631 }
2632
2633 amdgpu_crtc->cursor_bo = obj;
2634 return 0;
2635}
2636
2637static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2638{
2639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2640
2641 if (amdgpu_crtc->cursor_bo) {
2642 dce_v11_0_lock_cursor(crtc, true);
2643
2644 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2645 amdgpu_crtc->cursor_y);
2646
2647 dce_v11_0_show_cursor(crtc);
2648
2649 dce_v11_0_lock_cursor(crtc, false);
2650 }
2651}
2652
2653static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2654 u16 *blue, uint32_t size)
2655{
2656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2657 int i;
2658
2659 /* userspace palettes are always correct as is */
2660 for (i = 0; i < size; i++) {
2661 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2662 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2663 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2664 }
2665 dce_v11_0_crtc_load_lut(crtc);
2666
2667 return 0;
2668}
2669
2670static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2671{
2672 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2673
2674 drm_crtc_cleanup(crtc);
2675 kfree(amdgpu_crtc);
2676}
2677
2678static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2679 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2680 .cursor_move = dce_v11_0_crtc_cursor_move,
2681 .gamma_set = dce_v11_0_crtc_gamma_set,
2682 .set_config = amdgpu_crtc_set_config,
2683 .destroy = dce_v11_0_crtc_destroy,
2684 .page_flip_target = amdgpu_crtc_page_flip_target,
2685};
2686
2687static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2688{
2689 struct drm_device *dev = crtc->dev;
2690 struct amdgpu_device *adev = dev->dev_private;
2691 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2692 unsigned type;
2693
2694 switch (mode) {
2695 case DRM_MODE_DPMS_ON:
2696 amdgpu_crtc->enabled = true;
2697 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2698 dce_v11_0_vga_enable(crtc, true);
2699 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2700 dce_v11_0_vga_enable(crtc, false);
2701 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2702 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2703 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2704 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2705 drm_crtc_vblank_on(crtc);
2706 dce_v11_0_crtc_load_lut(crtc);
2707 break;
2708 case DRM_MODE_DPMS_STANDBY:
2709 case DRM_MODE_DPMS_SUSPEND:
2710 case DRM_MODE_DPMS_OFF:
2711 drm_crtc_vblank_off(crtc);
2712 if (amdgpu_crtc->enabled) {
2713 dce_v11_0_vga_enable(crtc, true);
2714 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2715 dce_v11_0_vga_enable(crtc, false);
2716 }
2717 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2718 amdgpu_crtc->enabled = false;
2719 break;
2720 }
2721 /* adjust pm to dpms */
2722 amdgpu_pm_compute_clocks(adev);
2723}
2724
2725static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2726{
2727 /* disable crtc pair power gating before programming */
2728 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2729 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2730 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2731}
2732
2733static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2734{
2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2736 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2737}
2738
2739static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2740{
2741 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2742 struct drm_device *dev = crtc->dev;
2743 struct amdgpu_device *adev = dev->dev_private;
2744 struct amdgpu_atom_ss ss;
2745 int i;
2746
2747 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2748 if (crtc->primary->fb) {
2749 int r;
2750 struct amdgpu_framebuffer *amdgpu_fb;
2751 struct amdgpu_bo *abo;
2752
2753 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2754 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2755 r = amdgpu_bo_reserve(abo, false);
2756 if (unlikely(r))
2757 DRM_ERROR("failed to reserve abo before unpin\n");
2758 else {
2759 amdgpu_bo_unpin(abo);
2760 amdgpu_bo_unreserve(abo);
2761 }
2762 }
2763 /* disable the GRPH */
2764 dce_v11_0_grph_enable(crtc, false);
2765
2766 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2767
2768 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2769 if (adev->mode_info.crtcs[i] &&
2770 adev->mode_info.crtcs[i]->enabled &&
2771 i != amdgpu_crtc->crtc_id &&
2772 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2773 /* one other crtc is using this pll don't turn
2774 * off the pll
2775 */
2776 goto done;
2777 }
2778 }
2779
2780 switch (amdgpu_crtc->pll_id) {
2781 case ATOM_PPLL0:
2782 case ATOM_PPLL1:
2783 case ATOM_PPLL2:
2784 /* disable the ppll */
2785 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2786 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2787 break;
2788 case ATOM_COMBOPHY_PLL0:
2789 case ATOM_COMBOPHY_PLL1:
2790 case ATOM_COMBOPHY_PLL2:
2791 case ATOM_COMBOPHY_PLL3:
2792 case ATOM_COMBOPHY_PLL4:
2793 case ATOM_COMBOPHY_PLL5:
2794 /* disable the ppll */
2795 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2796 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2797 break;
2798 default:
2799 break;
2800 }
2801done:
2802 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2803 amdgpu_crtc->adjusted_clock = 0;
2804 amdgpu_crtc->encoder = NULL;
2805 amdgpu_crtc->connector = NULL;
2806}
2807
2808static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2809 struct drm_display_mode *mode,
2810 struct drm_display_mode *adjusted_mode,
2811 int x, int y, struct drm_framebuffer *old_fb)
2812{
2813 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2814 struct drm_device *dev = crtc->dev;
2815 struct amdgpu_device *adev = dev->dev_private;
2816
2817 if (!amdgpu_crtc->adjusted_clock)
2818 return -EINVAL;
2819
2820 if ((adev->asic_type == CHIP_POLARIS10) ||
2821 (adev->asic_type == CHIP_POLARIS11) ||
2822 (adev->asic_type == CHIP_POLARIS12)) {
2823 struct amdgpu_encoder *amdgpu_encoder =
2824 to_amdgpu_encoder(amdgpu_crtc->encoder);
2825 int encoder_mode =
2826 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2827
2828 /* SetPixelClock calculates the plls and ss values now */
2829 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2830 amdgpu_crtc->pll_id,
2831 encoder_mode, amdgpu_encoder->encoder_id,
2832 adjusted_mode->clock, 0, 0, 0, 0,
2833 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2834 } else {
2835 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2836 }
2837 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2838 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2839 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2840 amdgpu_atombios_crtc_scaler_setup(crtc);
2841 dce_v11_0_cursor_reset(crtc);
2842 /* update the hw version fpr dpm */
2843 amdgpu_crtc->hw_mode = *adjusted_mode;
2844
2845 return 0;
2846}
2847
2848static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2849 const struct drm_display_mode *mode,
2850 struct drm_display_mode *adjusted_mode)
2851{
2852 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2853 struct drm_device *dev = crtc->dev;
2854 struct drm_encoder *encoder;
2855
2856 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2858 if (encoder->crtc == crtc) {
2859 amdgpu_crtc->encoder = encoder;
2860 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2861 break;
2862 }
2863 }
2864 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2865 amdgpu_crtc->encoder = NULL;
2866 amdgpu_crtc->connector = NULL;
2867 return false;
2868 }
2869 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2870 return false;
2871 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2872 return false;
2873 /* pick pll */
2874 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2875 /* if we can't get a PPLL for a non-DP encoder, fail */
2876 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2877 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2878 return false;
2879
2880 return true;
2881}
2882
2883static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2884 struct drm_framebuffer *old_fb)
2885{
2886 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2887}
2888
2889static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2890 struct drm_framebuffer *fb,
2891 int x, int y, enum mode_set_atomic state)
2892{
2893 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2894}
2895
2896static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2897 .dpms = dce_v11_0_crtc_dpms,
2898 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2899 .mode_set = dce_v11_0_crtc_mode_set,
2900 .mode_set_base = dce_v11_0_crtc_set_base,
2901 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2902 .prepare = dce_v11_0_crtc_prepare,
2903 .commit = dce_v11_0_crtc_commit,
2904 .load_lut = dce_v11_0_crtc_load_lut,
2905 .disable = dce_v11_0_crtc_disable,
2906};
2907
2908static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2909{
2910 struct amdgpu_crtc *amdgpu_crtc;
2911 int i;
2912
2913 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2914 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2915 if (amdgpu_crtc == NULL)
2916 return -ENOMEM;
2917
2918 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2919
2920 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2921 amdgpu_crtc->crtc_id = index;
2922 adev->mode_info.crtcs[index] = amdgpu_crtc;
2923
2924 amdgpu_crtc->max_cursor_width = 128;
2925 amdgpu_crtc->max_cursor_height = 128;
2926 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2927 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2928
2929 for (i = 0; i < 256; i++) {
2930 amdgpu_crtc->lut_r[i] = i << 2;
2931 amdgpu_crtc->lut_g[i] = i << 2;
2932 amdgpu_crtc->lut_b[i] = i << 2;
2933 }
2934
2935 switch (amdgpu_crtc->crtc_id) {
2936 case 0:
2937 default:
2938 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2939 break;
2940 case 1:
2941 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2942 break;
2943 case 2:
2944 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2945 break;
2946 case 3:
2947 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2948 break;
2949 case 4:
2950 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2951 break;
2952 case 5:
2953 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2954 break;
2955 }
2956
2957 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2958 amdgpu_crtc->adjusted_clock = 0;
2959 amdgpu_crtc->encoder = NULL;
2960 amdgpu_crtc->connector = NULL;
2961 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2962
2963 return 0;
2964}
2965
2966static int dce_v11_0_early_init(void *handle)
2967{
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969
2970 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2971 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2972
2973 dce_v11_0_set_display_funcs(adev);
2974 dce_v11_0_set_irq_funcs(adev);
2975
2976 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2977
2978 switch (adev->asic_type) {
2979 case CHIP_CARRIZO:
2980 adev->mode_info.num_hpd = 6;
2981 adev->mode_info.num_dig = 9;
2982 break;
2983 case CHIP_STONEY:
2984 adev->mode_info.num_hpd = 6;
2985 adev->mode_info.num_dig = 9;
2986 break;
2987 case CHIP_POLARIS10:
2988 adev->mode_info.num_hpd = 6;
2989 adev->mode_info.num_dig = 6;
2990 break;
2991 case CHIP_POLARIS11:
2992 case CHIP_POLARIS12:
2993 adev->mode_info.num_hpd = 5;
2994 adev->mode_info.num_dig = 5;
2995 break;
2996 default:
2997 /* FIXME: not supported yet */
2998 return -EINVAL;
2999 }
3000
3001 return 0;
3002}
3003
3004static int dce_v11_0_sw_init(void *handle)
3005{
3006 int r, i;
3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3008
3009 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3010 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3011 if (r)
3012 return r;
3013 }
3014
3015 for (i = 8; i < 20; i += 2) {
3016 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3017 if (r)
3018 return r;
3019 }
3020
3021 /* HPD hotplug */
3022 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3023 if (r)
3024 return r;
3025
3026 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3027
3028 adev->ddev->mode_config.async_page_flip = true;
3029
3030 adev->ddev->mode_config.max_width = 16384;
3031 adev->ddev->mode_config.max_height = 16384;
3032
3033 adev->ddev->mode_config.preferred_depth = 24;
3034 adev->ddev->mode_config.prefer_shadow = 1;
3035
3036 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3037
3038 r = amdgpu_modeset_create_props(adev);
3039 if (r)
3040 return r;
3041
3042 adev->ddev->mode_config.max_width = 16384;
3043 adev->ddev->mode_config.max_height = 16384;
3044
3045
3046 /* allocate crtcs */
3047 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3048 r = dce_v11_0_crtc_init(adev, i);
3049 if (r)
3050 return r;
3051 }
3052
3053 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3054 amdgpu_print_display_setup(adev->ddev);
3055 else
3056 return -EINVAL;
3057
3058 /* setup afmt */
3059 r = dce_v11_0_afmt_init(adev);
3060 if (r)
3061 return r;
3062
3063 r = dce_v11_0_audio_init(adev);
3064 if (r)
3065 return r;
3066
3067 drm_kms_helper_poll_init(adev->ddev);
3068
3069 adev->mode_info.mode_config_initialized = true;
3070 return 0;
3071}
3072
3073static int dce_v11_0_sw_fini(void *handle)
3074{
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076
3077 kfree(adev->mode_info.bios_hardcoded_edid);
3078
3079 drm_kms_helper_poll_fini(adev->ddev);
3080
3081 dce_v11_0_audio_fini(adev);
3082
3083 dce_v11_0_afmt_fini(adev);
3084
3085 drm_mode_config_cleanup(adev->ddev);
3086 adev->mode_info.mode_config_initialized = false;
3087
3088 return 0;
3089}
3090
3091static int dce_v11_0_hw_init(void *handle)
3092{
3093 int i;
3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3095
3096 dce_v11_0_init_golden_registers(adev);
3097
3098 /* init dig PHYs, disp eng pll */
3099 amdgpu_atombios_crtc_powergate_init(adev);
3100 amdgpu_atombios_encoder_init_dig(adev);
3101 if ((adev->asic_type == CHIP_POLARIS10) ||
3102 (adev->asic_type == CHIP_POLARIS11) ||
3103 (adev->asic_type == CHIP_POLARIS12)) {
3104 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3105 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3106 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3107 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3108 } else {
3109 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3110 }
3111
3112 /* initialize hpd */
3113 dce_v11_0_hpd_init(adev);
3114
3115 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3116 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3117 }
3118
3119 dce_v11_0_pageflip_interrupt_init(adev);
3120
3121 return 0;
3122}
3123
3124static int dce_v11_0_hw_fini(void *handle)
3125{
3126 int i;
3127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3128
3129 dce_v11_0_hpd_fini(adev);
3130
3131 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3132 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3133 }
3134
3135 dce_v11_0_pageflip_interrupt_fini(adev);
3136
3137 return 0;
3138}
3139
3140static int dce_v11_0_suspend(void *handle)
3141{
3142 return dce_v11_0_hw_fini(handle);
3143}
3144
3145static int dce_v11_0_resume(void *handle)
3146{
3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3148 int ret;
3149
3150 ret = dce_v11_0_hw_init(handle);
3151
3152 /* turn on the BL */
3153 if (adev->mode_info.bl_encoder) {
3154 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3155 adev->mode_info.bl_encoder);
3156 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3157 bl_level);
3158 }
3159
3160 return ret;
3161}
3162
3163static bool dce_v11_0_is_idle(void *handle)
3164{
3165 return true;
3166}
3167
3168static int dce_v11_0_wait_for_idle(void *handle)
3169{
3170 return 0;
3171}
3172
3173static int dce_v11_0_soft_reset(void *handle)
3174{
3175 u32 srbm_soft_reset = 0, tmp;
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3177
3178 if (dce_v11_0_is_display_hung(adev))
3179 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3180
3181 if (srbm_soft_reset) {
3182 tmp = RREG32(mmSRBM_SOFT_RESET);
3183 tmp |= srbm_soft_reset;
3184 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3185 WREG32(mmSRBM_SOFT_RESET, tmp);
3186 tmp = RREG32(mmSRBM_SOFT_RESET);
3187
3188 udelay(50);
3189
3190 tmp &= ~srbm_soft_reset;
3191 WREG32(mmSRBM_SOFT_RESET, tmp);
3192 tmp = RREG32(mmSRBM_SOFT_RESET);
3193
3194 /* Wait a little for things to settle down */
3195 udelay(50);
3196 }
3197 return 0;
3198}
3199
3200static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3201 int crtc,
3202 enum amdgpu_interrupt_state state)
3203{
3204 u32 lb_interrupt_mask;
3205
3206 if (crtc >= adev->mode_info.num_crtc) {
3207 DRM_DEBUG("invalid crtc %d\n", crtc);
3208 return;
3209 }
3210
3211 switch (state) {
3212 case AMDGPU_IRQ_STATE_DISABLE:
3213 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3214 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3215 VBLANK_INTERRUPT_MASK, 0);
3216 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3217 break;
3218 case AMDGPU_IRQ_STATE_ENABLE:
3219 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3220 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3221 VBLANK_INTERRUPT_MASK, 1);
3222 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3223 break;
3224 default:
3225 break;
3226 }
3227}
3228
3229static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3230 int crtc,
3231 enum amdgpu_interrupt_state state)
3232{
3233 u32 lb_interrupt_mask;
3234
3235 if (crtc >= adev->mode_info.num_crtc) {
3236 DRM_DEBUG("invalid crtc %d\n", crtc);
3237 return;
3238 }
3239
3240 switch (state) {
3241 case AMDGPU_IRQ_STATE_DISABLE:
3242 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3243 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3244 VLINE_INTERRUPT_MASK, 0);
3245 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3246 break;
3247 case AMDGPU_IRQ_STATE_ENABLE:
3248 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3249 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3250 VLINE_INTERRUPT_MASK, 1);
3251 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3252 break;
3253 default:
3254 break;
3255 }
3256}
3257
3258static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3259 struct amdgpu_irq_src *source,
3260 unsigned hpd,
3261 enum amdgpu_interrupt_state state)
3262{
3263 u32 tmp;
3264
3265 if (hpd >= adev->mode_info.num_hpd) {
3266 DRM_DEBUG("invalid hdp %d\n", hpd);
3267 return 0;
3268 }
3269
3270 switch (state) {
3271 case AMDGPU_IRQ_STATE_DISABLE:
3272 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3273 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3274 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3275 break;
3276 case AMDGPU_IRQ_STATE_ENABLE:
3277 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3278 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3279 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3280 break;
3281 default:
3282 break;
3283 }
3284
3285 return 0;
3286}
3287
3288static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *source,
3290 unsigned type,
3291 enum amdgpu_interrupt_state state)
3292{
3293 switch (type) {
3294 case AMDGPU_CRTC_IRQ_VBLANK1:
3295 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3296 break;
3297 case AMDGPU_CRTC_IRQ_VBLANK2:
3298 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3299 break;
3300 case AMDGPU_CRTC_IRQ_VBLANK3:
3301 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3302 break;
3303 case AMDGPU_CRTC_IRQ_VBLANK4:
3304 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3305 break;
3306 case AMDGPU_CRTC_IRQ_VBLANK5:
3307 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3308 break;
3309 case AMDGPU_CRTC_IRQ_VBLANK6:
3310 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3311 break;
3312 case AMDGPU_CRTC_IRQ_VLINE1:
3313 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3314 break;
3315 case AMDGPU_CRTC_IRQ_VLINE2:
3316 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3317 break;
3318 case AMDGPU_CRTC_IRQ_VLINE3:
3319 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3320 break;
3321 case AMDGPU_CRTC_IRQ_VLINE4:
3322 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3323 break;
3324 case AMDGPU_CRTC_IRQ_VLINE5:
3325 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3326 break;
3327 case AMDGPU_CRTC_IRQ_VLINE6:
3328 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3329 break;
3330 default:
3331 break;
3332 }
3333 return 0;
3334}
3335
3336static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3337 struct amdgpu_irq_src *src,
3338 unsigned type,
3339 enum amdgpu_interrupt_state state)
3340{
3341 u32 reg;
3342
3343 if (type >= adev->mode_info.num_crtc) {
3344 DRM_ERROR("invalid pageflip crtc %d\n", type);
3345 return -EINVAL;
3346 }
3347
3348 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3349 if (state == AMDGPU_IRQ_STATE_DISABLE)
3350 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3351 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3352 else
3353 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3354 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3355
3356 return 0;
3357}
3358
3359static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3360 struct amdgpu_irq_src *source,
3361 struct amdgpu_iv_entry *entry)
3362{
3363 unsigned long flags;
3364 unsigned crtc_id;
3365 struct amdgpu_crtc *amdgpu_crtc;
3366 struct amdgpu_flip_work *works;
3367
3368 crtc_id = (entry->src_id - 8) >> 1;
3369 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3370
3371 if (crtc_id >= adev->mode_info.num_crtc) {
3372 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3373 return -EINVAL;
3374 }
3375
3376 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3377 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3378 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3379 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3380
3381 /* IRQ could occur when in initial stage */
3382 if(amdgpu_crtc == NULL)
3383 return 0;
3384
3385 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3386 works = amdgpu_crtc->pflip_works;
3387 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3388 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3389 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3390 amdgpu_crtc->pflip_status,
3391 AMDGPU_FLIP_SUBMITTED);
3392 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3393 return 0;
3394 }
3395
3396 /* page flip completed. clean up */
3397 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3398 amdgpu_crtc->pflip_works = NULL;
3399
3400 /* wakeup usersapce */
3401 if(works->event)
3402 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3403
3404 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3405
3406 drm_crtc_vblank_put(&amdgpu_crtc->base);
3407 schedule_work(&works->unpin_work);
3408
3409 return 0;
3410}
3411
3412static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3413 int hpd)
3414{
3415 u32 tmp;
3416
3417 if (hpd >= adev->mode_info.num_hpd) {
3418 DRM_DEBUG("invalid hdp %d\n", hpd);
3419 return;
3420 }
3421
3422 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3423 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3424 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3425}
3426
3427static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3428 int crtc)
3429{
3430 u32 tmp;
3431
3432 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3433 DRM_DEBUG("invalid crtc %d\n", crtc);
3434 return;
3435 }
3436
3437 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3438 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3439 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3440}
3441
3442static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3443 int crtc)
3444{
3445 u32 tmp;
3446
3447 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3448 DRM_DEBUG("invalid crtc %d\n", crtc);
3449 return;
3450 }
3451
3452 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3453 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3454 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3455}
3456
3457static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3458 struct amdgpu_irq_src *source,
3459 struct amdgpu_iv_entry *entry)
3460{
3461 unsigned crtc = entry->src_id - 1;
3462 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3463 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3464
3465 switch (entry->src_data) {
3466 case 0: /* vblank */
3467 if (disp_int & interrupt_status_offsets[crtc].vblank)
3468 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3469 else
3470 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3471
3472 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3473 drm_handle_vblank(adev->ddev, crtc);
3474 }
3475 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3476
3477 break;
3478 case 1: /* vline */
3479 if (disp_int & interrupt_status_offsets[crtc].vline)
3480 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3481 else
3482 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3483
3484 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3485
3486 break;
3487 default:
3488 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3489 break;
3490 }
3491
3492 return 0;
3493}
3494
3495static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3496 struct amdgpu_irq_src *source,
3497 struct amdgpu_iv_entry *entry)
3498{
3499 uint32_t disp_int, mask;
3500 unsigned hpd;
3501
3502 if (entry->src_data >= adev->mode_info.num_hpd) {
3503 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3504 return 0;
3505 }
3506
3507 hpd = entry->src_data;
3508 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3509 mask = interrupt_status_offsets[hpd].hpd;
3510
3511 if (disp_int & mask) {
3512 dce_v11_0_hpd_int_ack(adev, hpd);
3513 schedule_work(&adev->hotplug_work);
3514 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3515 }
3516
3517 return 0;
3518}
3519
3520static int dce_v11_0_set_clockgating_state(void *handle,
3521 enum amd_clockgating_state state)
3522{
3523 return 0;
3524}
3525
3526static int dce_v11_0_set_powergating_state(void *handle,
3527 enum amd_powergating_state state)
3528{
3529 return 0;
3530}
3531
3532static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3533 .name = "dce_v11_0",
3534 .early_init = dce_v11_0_early_init,
3535 .late_init = NULL,
3536 .sw_init = dce_v11_0_sw_init,
3537 .sw_fini = dce_v11_0_sw_fini,
3538 .hw_init = dce_v11_0_hw_init,
3539 .hw_fini = dce_v11_0_hw_fini,
3540 .suspend = dce_v11_0_suspend,
3541 .resume = dce_v11_0_resume,
3542 .is_idle = dce_v11_0_is_idle,
3543 .wait_for_idle = dce_v11_0_wait_for_idle,
3544 .soft_reset = dce_v11_0_soft_reset,
3545 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3546 .set_powergating_state = dce_v11_0_set_powergating_state,
3547};
3548
3549static void
3550dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3551 struct drm_display_mode *mode,
3552 struct drm_display_mode *adjusted_mode)
3553{
3554 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3555
3556 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3557
3558 /* need to call this here rather than in prepare() since we need some crtc info */
3559 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3560
3561 /* set scaler clears this on some chips */
3562 dce_v11_0_set_interleave(encoder->crtc, mode);
3563
3564 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3565 dce_v11_0_afmt_enable(encoder, true);
3566 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3567 }
3568}
3569
3570static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3571{
3572 struct amdgpu_device *adev = encoder->dev->dev_private;
3573 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3574 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3575
3576 if ((amdgpu_encoder->active_device &
3577 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3578 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3579 ENCODER_OBJECT_ID_NONE)) {
3580 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3581 if (dig) {
3582 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3583 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3584 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3585 }
3586 }
3587
3588 amdgpu_atombios_scratch_regs_lock(adev, true);
3589
3590 if (connector) {
3591 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3592
3593 /* select the clock/data port if it uses a router */
3594 if (amdgpu_connector->router.cd_valid)
3595 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3596
3597 /* turn eDP panel on for mode set */
3598 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3599 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3600 ATOM_TRANSMITTER_ACTION_POWER_ON);
3601 }
3602
3603 /* this is needed for the pll/ss setup to work correctly in some cases */
3604 amdgpu_atombios_encoder_set_crtc_source(encoder);
3605 /* set up the FMT blocks */
3606 dce_v11_0_program_fmt(encoder);
3607}
3608
3609static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3610{
3611 struct drm_device *dev = encoder->dev;
3612 struct amdgpu_device *adev = dev->dev_private;
3613
3614 /* need to call this here as we need the crtc set up */
3615 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3616 amdgpu_atombios_scratch_regs_lock(adev, false);
3617}
3618
3619static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3620{
3621 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3622 struct amdgpu_encoder_atom_dig *dig;
3623
3624 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3625
3626 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3627 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3628 dce_v11_0_afmt_enable(encoder, false);
3629 dig = amdgpu_encoder->enc_priv;
3630 dig->dig_encoder = -1;
3631 }
3632 amdgpu_encoder->active_device = 0;
3633}
3634
3635/* these are handled by the primary encoders */
3636static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3637{
3638
3639}
3640
3641static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3642{
3643
3644}
3645
3646static void
3647dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3648 struct drm_display_mode *mode,
3649 struct drm_display_mode *adjusted_mode)
3650{
3651
3652}
3653
3654static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3655{
3656
3657}
3658
3659static void
3660dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3661{
3662
3663}
3664
3665static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3666 .dpms = dce_v11_0_ext_dpms,
3667 .prepare = dce_v11_0_ext_prepare,
3668 .mode_set = dce_v11_0_ext_mode_set,
3669 .commit = dce_v11_0_ext_commit,
3670 .disable = dce_v11_0_ext_disable,
3671 /* no detect for TMDS/LVDS yet */
3672};
3673
3674static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3675 .dpms = amdgpu_atombios_encoder_dpms,
3676 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3677 .prepare = dce_v11_0_encoder_prepare,
3678 .mode_set = dce_v11_0_encoder_mode_set,
3679 .commit = dce_v11_0_encoder_commit,
3680 .disable = dce_v11_0_encoder_disable,
3681 .detect = amdgpu_atombios_encoder_dig_detect,
3682};
3683
3684static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3685 .dpms = amdgpu_atombios_encoder_dpms,
3686 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3687 .prepare = dce_v11_0_encoder_prepare,
3688 .mode_set = dce_v11_0_encoder_mode_set,
3689 .commit = dce_v11_0_encoder_commit,
3690 .detect = amdgpu_atombios_encoder_dac_detect,
3691};
3692
3693static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3694{
3695 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3696 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3697 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3698 kfree(amdgpu_encoder->enc_priv);
3699 drm_encoder_cleanup(encoder);
3700 kfree(amdgpu_encoder);
3701}
3702
3703static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3704 .destroy = dce_v11_0_encoder_destroy,
3705};
3706
3707static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3708 uint32_t encoder_enum,
3709 uint32_t supported_device,
3710 u16 caps)
3711{
3712 struct drm_device *dev = adev->ddev;
3713 struct drm_encoder *encoder;
3714 struct amdgpu_encoder *amdgpu_encoder;
3715
3716 /* see if we already added it */
3717 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3718 amdgpu_encoder = to_amdgpu_encoder(encoder);
3719 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3720 amdgpu_encoder->devices |= supported_device;
3721 return;
3722 }
3723
3724 }
3725
3726 /* add a new one */
3727 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3728 if (!amdgpu_encoder)
3729 return;
3730
3731 encoder = &amdgpu_encoder->base;
3732 switch (adev->mode_info.num_crtc) {
3733 case 1:
3734 encoder->possible_crtcs = 0x1;
3735 break;
3736 case 2:
3737 default:
3738 encoder->possible_crtcs = 0x3;
3739 break;
3740 case 3:
3741 encoder->possible_crtcs = 0x7;
3742 break;
3743 case 4:
3744 encoder->possible_crtcs = 0xf;
3745 break;
3746 case 5:
3747 encoder->possible_crtcs = 0x1f;
3748 break;
3749 case 6:
3750 encoder->possible_crtcs = 0x3f;
3751 break;
3752 }
3753
3754 amdgpu_encoder->enc_priv = NULL;
3755
3756 amdgpu_encoder->encoder_enum = encoder_enum;
3757 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3758 amdgpu_encoder->devices = supported_device;
3759 amdgpu_encoder->rmx_type = RMX_OFF;
3760 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3761 amdgpu_encoder->is_ext_encoder = false;
3762 amdgpu_encoder->caps = caps;
3763
3764 switch (amdgpu_encoder->encoder_id) {
3765 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3767 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3768 DRM_MODE_ENCODER_DAC, NULL);
3769 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3770 break;
3771 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3772 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3775 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3776 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3777 amdgpu_encoder->rmx_type = RMX_FULL;
3778 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3779 DRM_MODE_ENCODER_LVDS, NULL);
3780 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3781 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3782 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3783 DRM_MODE_ENCODER_DAC, NULL);
3784 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3785 } else {
3786 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3787 DRM_MODE_ENCODER_TMDS, NULL);
3788 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3789 }
3790 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3791 break;
3792 case ENCODER_OBJECT_ID_SI170B:
3793 case ENCODER_OBJECT_ID_CH7303:
3794 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3795 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3796 case ENCODER_OBJECT_ID_TITFP513:
3797 case ENCODER_OBJECT_ID_VT1623:
3798 case ENCODER_OBJECT_ID_HDMI_SI1930:
3799 case ENCODER_OBJECT_ID_TRAVIS:
3800 case ENCODER_OBJECT_ID_NUTMEG:
3801 /* these are handled by the primary encoders */
3802 amdgpu_encoder->is_ext_encoder = true;
3803 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3804 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3805 DRM_MODE_ENCODER_LVDS, NULL);
3806 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3807 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3808 DRM_MODE_ENCODER_DAC, NULL);
3809 else
3810 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3811 DRM_MODE_ENCODER_TMDS, NULL);
3812 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3813 break;
3814 }
3815}
3816
3817static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3818 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3819 .bandwidth_update = &dce_v11_0_bandwidth_update,
3820 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3821 .vblank_wait = &dce_v11_0_vblank_wait,
3822 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3823 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3824 .hpd_sense = &dce_v11_0_hpd_sense,
3825 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3826 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3827 .page_flip = &dce_v11_0_page_flip,
3828 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3829 .add_encoder = &dce_v11_0_encoder_add,
3830 .add_connector = &amdgpu_connector_add,
3831 .stop_mc_access = &dce_v11_0_stop_mc_access,
3832 .resume_mc_access = &dce_v11_0_resume_mc_access,
3833};
3834
3835static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3836{
3837 if (adev->mode_info.funcs == NULL)
3838 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3839}
3840
3841static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3842 .set = dce_v11_0_set_crtc_irq_state,
3843 .process = dce_v11_0_crtc_irq,
3844};
3845
3846static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3847 .set = dce_v11_0_set_pageflip_irq_state,
3848 .process = dce_v11_0_pageflip_irq,
3849};
3850
3851static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3852 .set = dce_v11_0_set_hpd_irq_state,
3853 .process = dce_v11_0_hpd_irq,
3854};
3855
3856static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3857{
3858 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3859 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3860
3861 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3862 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3863
3864 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3865 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3866}
3867
3868const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3869{
3870 .type = AMD_IP_BLOCK_TYPE_DCE,
3871 .major = 11,
3872 .minor = 0,
3873 .rev = 0,
3874 .funcs = &dce_v11_0_ip_funcs,
3875};
3876
3877const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3878{
3879 .type = AMD_IP_BLOCK_TYPE_DCE,
3880 .major = 11,
3881 .minor = 2,
3882 .rev = 0,
3883 .funcs = &dce_v11_0_ip_funcs,
3884};