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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72 DRM_DEBUG("SMC\n");
73 amdgpu_ucode_print_common_hdr(hdr);
74
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80 } else {
81 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
82 }
83}
84
85void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
86{
87 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
88 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
89
90 DRM_DEBUG("GFX\n");
91 amdgpu_ucode_print_common_hdr(hdr);
92
93 if (version_major == 1) {
94 const struct gfx_firmware_header_v1_0 *gfx_hdr =
95 container_of(hdr, struct gfx_firmware_header_v1_0, header);
96
97 DRM_DEBUG("ucode_feature_version: %u\n",
98 le32_to_cpu(gfx_hdr->ucode_feature_version));
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
101 } else {
102 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
103 }
104}
105
106void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
107{
108 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
110
111 DRM_DEBUG("RLC\n");
112 amdgpu_ucode_print_common_hdr(hdr);
113
114 if (version_major == 1) {
115 const struct rlc_firmware_header_v1_0 *rlc_hdr =
116 container_of(hdr, struct rlc_firmware_header_v1_0, header);
117
118 DRM_DEBUG("ucode_feature_version: %u\n",
119 le32_to_cpu(rlc_hdr->ucode_feature_version));
120 DRM_DEBUG("save_and_restore_offset: %u\n",
121 le32_to_cpu(rlc_hdr->save_and_restore_offset));
122 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
124 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
126 DRM_DEBUG("master_pkt_description_offset: %u\n",
127 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
128 } else if (version_major == 2) {
129 const struct rlc_firmware_header_v2_0 *rlc_hdr =
130 container_of(hdr, struct rlc_firmware_header_v2_0, header);
131
132 DRM_DEBUG("ucode_feature_version: %u\n",
133 le32_to_cpu(rlc_hdr->ucode_feature_version));
134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
136 DRM_DEBUG("save_and_restore_offset: %u\n",
137 le32_to_cpu(rlc_hdr->save_and_restore_offset));
138 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
139 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
140 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
141 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
142 DRM_DEBUG("reg_restore_list_size: %u\n",
143 le32_to_cpu(rlc_hdr->reg_restore_list_size));
144 DRM_DEBUG("reg_list_format_start: %u\n",
145 le32_to_cpu(rlc_hdr->reg_list_format_start));
146 DRM_DEBUG("reg_list_format_separate_start: %u\n",
147 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
148 DRM_DEBUG("starting_offsets_start: %u\n",
149 le32_to_cpu(rlc_hdr->starting_offsets_start));
150 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
151 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
152 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
154 DRM_DEBUG("reg_list_size_bytes: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
156 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
157 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
158 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
160 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
166 } else {
167 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
168 }
169}
170
171void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
172{
173 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
174 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
175
176 DRM_DEBUG("SDMA\n");
177 amdgpu_ucode_print_common_hdr(hdr);
178
179 if (version_major == 1) {
180 const struct sdma_firmware_header_v1_0 *sdma_hdr =
181 container_of(hdr, struct sdma_firmware_header_v1_0, header);
182
183 DRM_DEBUG("ucode_feature_version: %u\n",
184 le32_to_cpu(sdma_hdr->ucode_feature_version));
185 DRM_DEBUG("ucode_change_version: %u\n",
186 le32_to_cpu(sdma_hdr->ucode_change_version));
187 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
188 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
189 if (version_minor >= 1) {
190 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
191 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
192 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
193 }
194 } else {
195 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
196 version_major, version_minor);
197 }
198}
199
200void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
201{
202 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
203 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
204
205 DRM_DEBUG("GPU_INFO\n");
206 amdgpu_ucode_print_common_hdr(hdr);
207
208 if (version_major == 1) {
209 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
210 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
211
212 DRM_DEBUG("version_major: %u\n",
213 le16_to_cpu(gpu_info_hdr->version_major));
214 DRM_DEBUG("version_minor: %u\n",
215 le16_to_cpu(gpu_info_hdr->version_minor));
216 } else {
217 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
218 }
219}
220
221int amdgpu_ucode_validate(const struct firmware *fw)
222{
223 const struct common_firmware_header *hdr =
224 (const struct common_firmware_header *)fw->data;
225
226 if (fw->size == le32_to_cpu(hdr->size_bytes))
227 return 0;
228
229 return -EINVAL;
230}
231
232bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
233 uint16_t hdr_major, uint16_t hdr_minor)
234{
235 if ((hdr->common.header_version_major == hdr_major) &&
236 (hdr->common.header_version_minor == hdr_minor))
237 return false;
238 return true;
239}
240
241enum amdgpu_firmware_load_type
242amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
243{
244 switch (adev->asic_type) {
245#ifdef CONFIG_DRM_AMDGPU_SI
246 case CHIP_TAHITI:
247 case CHIP_PITCAIRN:
248 case CHIP_VERDE:
249 case CHIP_OLAND:
250 return AMDGPU_FW_LOAD_DIRECT;
251#endif
252#ifdef CONFIG_DRM_AMDGPU_CIK
253 case CHIP_BONAIRE:
254 case CHIP_KAVERI:
255 case CHIP_KABINI:
256 case CHIP_HAWAII:
257 case CHIP_MULLINS:
258 return AMDGPU_FW_LOAD_DIRECT;
259#endif
260 case CHIP_TOPAZ:
261 case CHIP_TONGA:
262 case CHIP_FIJI:
263 case CHIP_CARRIZO:
264 case CHIP_STONEY:
265 case CHIP_POLARIS10:
266 case CHIP_POLARIS11:
267 case CHIP_POLARIS12:
268 if (!load_type)
269 return AMDGPU_FW_LOAD_DIRECT;
270 else
271 return AMDGPU_FW_LOAD_SMU;
272 case CHIP_VEGA10:
273 case CHIP_RAVEN:
274 case CHIP_VEGA12:
275 if (!load_type)
276 return AMDGPU_FW_LOAD_DIRECT;
277 else
278 return AMDGPU_FW_LOAD_PSP;
279 default:
280 DRM_ERROR("Unknown firmware load type\n");
281 }
282
283 return AMDGPU_FW_LOAD_DIRECT;
284}
285
286static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
287 struct amdgpu_firmware_info *ucode,
288 uint64_t mc_addr, void *kptr)
289{
290 const struct common_firmware_header *header = NULL;
291 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
292
293 if (NULL == ucode->fw)
294 return 0;
295
296 ucode->mc_addr = mc_addr;
297 ucode->kaddr = kptr;
298
299 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
300 return 0;
301
302 header = (const struct common_firmware_header *)ucode->fw->data;
303
304 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
305
306 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
307 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
308 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
309 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
310 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
311 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
312
313 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
314 le32_to_cpu(header->ucode_array_offset_bytes)),
315 ucode->ucode_size);
316 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
317 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
318 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
319 le32_to_cpu(cp_hdr->jt_size) * 4;
320
321 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
322 le32_to_cpu(header->ucode_array_offset_bytes)),
323 ucode->ucode_size);
324 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
325 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
326 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
327
328 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
329 le32_to_cpu(header->ucode_array_offset_bytes) +
330 le32_to_cpu(cp_hdr->jt_offset) * 4),
331 ucode->ucode_size);
332 }
333
334 return 0;
335}
336
337static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
338 uint64_t mc_addr, void *kptr)
339{
340 const struct gfx_firmware_header_v1_0 *header = NULL;
341 const struct common_firmware_header *comm_hdr = NULL;
342 uint8_t* src_addr = NULL;
343 uint8_t* dst_addr = NULL;
344
345 if (NULL == ucode->fw)
346 return 0;
347
348 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
349 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
350 dst_addr = ucode->kaddr +
351 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
352 PAGE_SIZE);
353 src_addr = (uint8_t *)ucode->fw->data +
354 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
355 (le32_to_cpu(header->jt_offset) * 4);
356 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
357
358 return 0;
359}
360
361int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
362{
363 uint64_t fw_offset = 0;
364 int i, err;
365 struct amdgpu_firmware_info *ucode = NULL;
366 const struct common_firmware_header *header = NULL;
367
368 if (!adev->firmware.fw_size) {
369 dev_warn(adev->dev, "No ip firmware need to load\n");
370 return 0;
371 }
372
373 if (!adev->in_gpu_reset) {
374 err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
375 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
376 &adev->firmware.fw_buf,
377 &adev->firmware.fw_buf_mc,
378 &adev->firmware.fw_buf_ptr);
379 if (err) {
380 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
381 goto failed;
382 }
383 }
384
385 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
386
387 /*
388 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
389 * ucode info here
390 */
391 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
392 if (amdgpu_sriov_vf(adev))
393 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
394 else
395 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
396 } else {
397 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
398 }
399
400 for (i = 0; i < adev->firmware.max_ucodes; i++) {
401 ucode = &adev->firmware.ucode[i];
402 if (ucode->fw) {
403 header = (const struct common_firmware_header *)ucode->fw->data;
404 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
405 adev->firmware.fw_buf_ptr + fw_offset);
406 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
407 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
408 const struct gfx_firmware_header_v1_0 *cp_hdr;
409 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
410 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
411 adev->firmware.fw_buf_ptr + fw_offset);
412 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
413 }
414 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
415 }
416 }
417 return 0;
418
419failed:
420 if (err)
421 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
422
423 return err;
424}
425
426int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
427{
428 int i;
429 struct amdgpu_firmware_info *ucode = NULL;
430
431 if (!adev->firmware.fw_size)
432 return 0;
433
434 for (i = 0; i < adev->firmware.max_ucodes; i++) {
435 ucode = &adev->firmware.ucode[i];
436 if (ucode->fw) {
437 ucode->mc_addr = 0;
438 ucode->kaddr = NULL;
439 }
440 }
441
442 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
443 &adev->firmware.fw_buf_mc,
444 &adev->firmware.fw_buf_ptr);
445
446 return 0;
447}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72 DRM_DEBUG("SMC\n");
73 amdgpu_ucode_print_common_hdr(hdr);
74
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80 } else {
81 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
82 }
83}
84
85void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
86{
87 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
88 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
89
90 DRM_DEBUG("GFX\n");
91 amdgpu_ucode_print_common_hdr(hdr);
92
93 if (version_major == 1) {
94 const struct gfx_firmware_header_v1_0 *gfx_hdr =
95 container_of(hdr, struct gfx_firmware_header_v1_0, header);
96
97 DRM_DEBUG("ucode_feature_version: %u\n",
98 le32_to_cpu(gfx_hdr->ucode_feature_version));
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
101 } else {
102 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
103 }
104}
105
106void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
107{
108 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
110
111 DRM_DEBUG("RLC\n");
112 amdgpu_ucode_print_common_hdr(hdr);
113
114 if (version_major == 1) {
115 const struct rlc_firmware_header_v1_0 *rlc_hdr =
116 container_of(hdr, struct rlc_firmware_header_v1_0, header);
117
118 DRM_DEBUG("ucode_feature_version: %u\n",
119 le32_to_cpu(rlc_hdr->ucode_feature_version));
120 DRM_DEBUG("save_and_restore_offset: %u\n",
121 le32_to_cpu(rlc_hdr->save_and_restore_offset));
122 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
124 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
126 DRM_DEBUG("master_pkt_description_offset: %u\n",
127 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
128 } else if (version_major == 2) {
129 const struct rlc_firmware_header_v2_0 *rlc_hdr =
130 container_of(hdr, struct rlc_firmware_header_v2_0, header);
131
132 DRM_DEBUG("ucode_feature_version: %u\n",
133 le32_to_cpu(rlc_hdr->ucode_feature_version));
134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
136 DRM_DEBUG("save_and_restore_offset: %u\n",
137 le32_to_cpu(rlc_hdr->save_and_restore_offset));
138 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
139 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
140 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
141 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
142 DRM_DEBUG("reg_restore_list_size: %u\n",
143 le32_to_cpu(rlc_hdr->reg_restore_list_size));
144 DRM_DEBUG("reg_list_format_start: %u\n",
145 le32_to_cpu(rlc_hdr->reg_list_format_start));
146 DRM_DEBUG("reg_list_format_separate_start: %u\n",
147 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
148 DRM_DEBUG("starting_offsets_start: %u\n",
149 le32_to_cpu(rlc_hdr->starting_offsets_start));
150 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
151 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
152 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
154 DRM_DEBUG("reg_list_size_bytes: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
156 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
157 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
158 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
160 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
166 } else {
167 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
168 }
169}
170
171void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
172{
173 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
174 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
175
176 DRM_DEBUG("SDMA\n");
177 amdgpu_ucode_print_common_hdr(hdr);
178
179 if (version_major == 1) {
180 const struct sdma_firmware_header_v1_0 *sdma_hdr =
181 container_of(hdr, struct sdma_firmware_header_v1_0, header);
182
183 DRM_DEBUG("ucode_feature_version: %u\n",
184 le32_to_cpu(sdma_hdr->ucode_feature_version));
185 DRM_DEBUG("ucode_change_version: %u\n",
186 le32_to_cpu(sdma_hdr->ucode_change_version));
187 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
188 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
189 if (version_minor >= 1) {
190 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
191 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
192 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
193 }
194 } else {
195 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
196 version_major, version_minor);
197 }
198}
199
200int amdgpu_ucode_validate(const struct firmware *fw)
201{
202 const struct common_firmware_header *hdr =
203 (const struct common_firmware_header *)fw->data;
204
205 if (fw->size == le32_to_cpu(hdr->size_bytes))
206 return 0;
207
208 return -EINVAL;
209}
210
211bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
212 uint16_t hdr_major, uint16_t hdr_minor)
213{
214 if ((hdr->common.header_version_major == hdr_major) &&
215 (hdr->common.header_version_minor == hdr_minor))
216 return false;
217 return true;
218}
219
220static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
221 uint64_t mc_addr, void *kptr)
222{
223 const struct common_firmware_header *header = NULL;
224
225 if (NULL == ucode->fw)
226 return 0;
227
228 ucode->mc_addr = mc_addr;
229 ucode->kaddr = kptr;
230
231 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
232 return 0;
233
234 header = (const struct common_firmware_header *)ucode->fw->data;
235 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
236 le32_to_cpu(header->ucode_array_offset_bytes)),
237 le32_to_cpu(header->ucode_size_bytes));
238
239 return 0;
240}
241
242static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
243 uint64_t mc_addr, void *kptr)
244{
245 const struct gfx_firmware_header_v1_0 *header = NULL;
246 const struct common_firmware_header *comm_hdr = NULL;
247 uint8_t* src_addr = NULL;
248 uint8_t* dst_addr = NULL;
249
250 if (NULL == ucode->fw)
251 return 0;
252
253 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
254 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
255 dst_addr = ucode->kaddr +
256 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
257 PAGE_SIZE);
258 src_addr = (uint8_t *)ucode->fw->data +
259 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
260 (le32_to_cpu(header->jt_offset) * 4);
261 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
262
263 return 0;
264}
265
266
267int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
268{
269 struct amdgpu_bo **bo = &adev->firmware.fw_buf;
270 uint64_t fw_mc_addr;
271 void *fw_buf_ptr = NULL;
272 uint64_t fw_offset = 0;
273 int i, err;
274 struct amdgpu_firmware_info *ucode = NULL;
275 const struct common_firmware_header *header = NULL;
276
277 err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
278 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
279 0, NULL, NULL, bo);
280 if (err) {
281 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
282 goto failed;
283 }
284
285 err = amdgpu_bo_reserve(*bo, false);
286 if (err) {
287 dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
288 goto failed_reserve;
289 }
290
291 err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
292 &fw_mc_addr);
293 if (err) {
294 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
295 goto failed_pin;
296 }
297
298 err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
299 if (err) {
300 dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
301 goto failed_kmap;
302 }
303
304 amdgpu_bo_unreserve(*bo);
305
306 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
307 ucode = &adev->firmware.ucode[i];
308 if (ucode->fw) {
309 header = (const struct common_firmware_header *)ucode->fw->data;
310 amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
311 fw_buf_ptr + fw_offset);
312 if (i == AMDGPU_UCODE_ID_CP_MEC1) {
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
315 amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
316 fw_buf_ptr + fw_offset);
317 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
318 }
319 fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
320 }
321 }
322 return 0;
323
324failed_kmap:
325 amdgpu_bo_unpin(*bo);
326failed_pin:
327 amdgpu_bo_unreserve(*bo);
328failed_reserve:
329 amdgpu_bo_unref(bo);
330failed:
331 adev->firmware.smu_load = false;
332
333 return err;
334}
335
336int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
337{
338 int i;
339 struct amdgpu_firmware_info *ucode = NULL;
340
341 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
342 ucode = &adev->firmware.ucode[i];
343 if (ucode->fw) {
344 ucode->mc_addr = 0;
345 ucode->kaddr = NULL;
346 }
347 }
348 amdgpu_bo_unref(&adev->firmware.fw_buf);
349 adev->firmware.fw_buf = NULL;
350
351 return 0;
352}