1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef _SPARC64_VISASM_H
 3#define _SPARC64_VISASM_H
 4
 5/* visasm.h:  FPU saving macros for VIS routines
 6 *
 7 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
 8 */
 9
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12
13/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
14
15#define VISEntry					\
16	rd		%fprs, %o5;			\
17	andcc		%o5, (FPRS_FEF|FPRS_DU), %g0;	\
18	be,pt		%icc, 297f;			\
19	 sethi		%hi(297f), %g7;			\
20	sethi		%hi(VISenter), %g1;		\
21	jmpl		%g1 + %lo(VISenter), %g0;	\
22	 or		%g7, %lo(297f), %g7;		\
23297:	wr		%g0, FPRS_FEF, %fprs;		\
24
25#define VISExit						\
26	wr		%g0, 0, %fprs;
27
28/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
29 * Must preserve %o5 between VISEntryHalf and VISExitHalf */
30
31#define VISEntryHalf					\
32	VISEntry
33
34#define VISExitHalf					\
35	VISExit
36
37#define VISEntryHalfFast(fail_label)			\
38	rd		%fprs, %o5;			\
39	andcc		%o5, FPRS_FEF, %g0;		\
40	be,pt		%icc, 297f;			\
41	 nop;						\
42	ba,a,pt		%xcc, fail_label;		\
43297:	wr		%o5, FPRS_FEF, %fprs;
44
45#define VISExitHalfFast					\
46	wr		%o5, 0, %fprs;
47
48#ifndef __ASSEMBLY__
49static inline void save_and_clear_fpu(void) {
50	__asm__ __volatile__ (
51"		rd %%fprs, %%o5\n"
52"		andcc %%o5, %0, %%g0\n"
53"		be,pt %%icc, 299f\n"
54"		 sethi %%hi(298f), %%g7\n"
55"		sethi %%hi(VISenter), %%g1\n"
56"		jmpl %%g1 + %%lo(VISenter), %%g0\n"
57"		 or %%g7, %%lo(298f), %%g7\n"
58"	298:	wr %%g0, 0, %%fprs\n"
59"	299:\n"
60"		" : : "i" (FPRS_FEF|FPRS_DU) :
61		"o5", "g1", "g2", "g3", "g7", "cc");
62}
63
64int vis_emul(struct pt_regs *, unsigned int);
65#endif
66
67#endif /* _SPARC64_ASI_H */

 
 1#ifndef _SPARC64_VISASM_H
 2#define _SPARC64_VISASM_H
 3
 4/* visasm.h:  FPU saving macros for VIS routines
 5 *
 6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
 7 */
 8
 9#include <asm/pstate.h>
10#include <asm/ptrace.h>
11
12/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
13
14#define VISEntry					\
15	rd		%fprs, %o5;			\
16	andcc		%o5, (FPRS_FEF|FPRS_DU), %g0;	\
17	be,pt		%icc, 297f;			\
18	 sethi		%hi(297f), %g7;			\
19	sethi		%hi(VISenter), %g1;		\
20	jmpl		%g1 + %lo(VISenter), %g0;	\
21	 or		%g7, %lo(297f), %g7;		\
22297:	wr		%g0, FPRS_FEF, %fprs;		\
23
24#define VISExit						\
25	wr		%g0, 0, %fprs;
26
27/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
28 * Must preserve %o5 between VISEntryHalf and VISExitHalf */
29
30#define VISEntryHalf					\
31	VISEntry
32
33#define VISExitHalf					\
34	VISExit
35
36#define VISEntryHalfFast(fail_label)			\
37	rd		%fprs, %o5;			\
38	andcc		%o5, FPRS_FEF, %g0;		\
39	be,pt		%icc, 297f;			\
40	 nop;						\
41	ba,a,pt		%xcc, fail_label;		\
42297:	wr		%o5, FPRS_FEF, %fprs;
43
44#define VISExitHalfFast					\
45	wr		%o5, 0, %fprs;
46
47#ifndef __ASSEMBLY__
48static inline void save_and_clear_fpu(void) {
49	__asm__ __volatile__ (
50"		rd %%fprs, %%o5\n"
51"		andcc %%o5, %0, %%g0\n"
52"		be,pt %%icc, 299f\n"
53"		 sethi %%hi(298f), %%g7\n"
54"		sethi %%hi(VISenter), %%g1\n"
55"		jmpl %%g1 + %%lo(VISenter), %%g0\n"
56"		 or %%g7, %%lo(298f), %%g7\n"
57"	298:	wr %%g0, 0, %%fprs\n"
58"	299:\n"
59"		" : : "i" (FPRS_FEF|FPRS_DU) :
60		"o5", "g1", "g2", "g3", "g7", "cc");
61}
62
63int vis_emul(struct pt_regs *, unsigned int);
64#endif
65
66#endif /* _SPARC64_ASI_H */