1/*
   2 *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   3 *  Copyright 2007-2010 Freescale Semiconductor, Inc.
   4 *
   5 *  This program is free software; you can redistribute it and/or
   6 *  modify it under the terms of the GNU General Public License
   7 *  as published by the Free Software Foundation; either version
   8 *  2 of the License, or (at your option) any later version.
   9 *
  10 *  Modified by Cort Dougan (cort@cs.nmt.edu)
  11 *  and Paul Mackerras (paulus@samba.org)
  12 */
  13
  14/*
  15 * This file handles the architecture-dependent parts of hardware exceptions
  16 */
  17
  18#include <linux/errno.h>
  19#include <linux/sched.h>
  20#include <linux/sched/debug.h>
  21#include <linux/kernel.h>
  22#include <linux/mm.h>
  23#include <linux/pkeys.h>
  24#include <linux/stddef.h>
  25#include <linux/unistd.h>
  26#include <linux/ptrace.h>
  27#include <linux/user.h>
  28#include <linux/interrupt.h>
  29#include <linux/init.h>
  30#include <linux/extable.h>
  31#include <linux/module.h>	/* print_modules */
  32#include <linux/prctl.h>
  33#include <linux/delay.h>
  34#include <linux/kprobes.h>
  35#include <linux/kexec.h>
  36#include <linux/backlight.h>
  37#include <linux/bug.h>
  38#include <linux/kdebug.h>
 
  39#include <linux/ratelimit.h>
  40#include <linux/context_tracking.h>
  41#include <linux/smp.h>
  42#include <linux/console.h>
  43#include <linux/kmsg_dump.h>
  44
  45#include <asm/emulated_ops.h>
  46#include <asm/pgtable.h>
  47#include <linux/uaccess.h>
  48#include <asm/debugfs.h>
  49#include <asm/io.h>
  50#include <asm/machdep.h>
  51#include <asm/rtas.h>
  52#include <asm/pmc.h>
  53#include <asm/reg.h>
  54#ifdef CONFIG_PMAC_BACKLIGHT
  55#include <asm/backlight.h>
  56#endif
  57#ifdef CONFIG_PPC64
  58#include <asm/firmware.h>
  59#include <asm/processor.h>
  60#include <asm/tm.h>
  61#endif
  62#include <asm/kexec.h>
  63#include <asm/ppc-opcode.h>
  64#include <asm/rio.h>
  65#include <asm/fadump.h>
  66#include <asm/switch_to.h>
  67#include <asm/tm.h>
  68#include <asm/debug.h>
  69#include <asm/asm-prototypes.h>
  70#include <asm/hmi.h>
  71#include <sysdev/fsl_pci.h>
  72#include <asm/kprobes.h>
  73
  74#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
  75int (*__debugger)(struct pt_regs *regs) __read_mostly;
  76int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
  77int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
  78int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
  79int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
  80int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
  81int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
  82
  83EXPORT_SYMBOL(__debugger);
  84EXPORT_SYMBOL(__debugger_ipi);
  85EXPORT_SYMBOL(__debugger_bpt);
  86EXPORT_SYMBOL(__debugger_sstep);
  87EXPORT_SYMBOL(__debugger_iabr_match);
  88EXPORT_SYMBOL(__debugger_break_match);
  89EXPORT_SYMBOL(__debugger_fault_handler);
  90#endif
  91
  92/* Transactional Memory trap debug */
  93#ifdef TM_DEBUG_SW
  94#define TM_DEBUG(x...) printk(KERN_INFO x)
  95#else
  96#define TM_DEBUG(x...) do { } while(0)
  97#endif
  98
  99/*
 100 * Trap & Exception support
 101 */
 102
 103#ifdef CONFIG_PMAC_BACKLIGHT
 104static void pmac_backlight_unblank(void)
 105{
 106	mutex_lock(&pmac_backlight_mutex);
 107	if (pmac_backlight) {
 108		struct backlight_properties *props;
 109
 110		props = &pmac_backlight->props;
 111		props->brightness = props->max_brightness;
 112		props->power = FB_BLANK_UNBLANK;
 113		backlight_update_status(pmac_backlight);
 114	}
 115	mutex_unlock(&pmac_backlight_mutex);
 116}
 117#else
 118static inline void pmac_backlight_unblank(void) { }
 119#endif
 120
 121/*
 122 * If oops/die is expected to crash the machine, return true here.
 123 *
 124 * This should not be expected to be 100% accurate, there may be
 125 * notifiers registered or other unexpected conditions that may bring
 126 * down the kernel. Or if the current process in the kernel is holding
 127 * locks or has other critical state, the kernel may become effectively
 128 * unusable anyway.
 129 */
 130bool die_will_crash(void)
 131{
 132	if (should_fadump_crash())
 133		return true;
 134	if (kexec_should_crash(current))
 135		return true;
 136	if (in_interrupt() || panic_on_oops ||
 137			!current->pid || is_global_init(current))
 138		return true;
 139
 140	return false;
 141}
 142
 143static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 144static int die_owner = -1;
 145static unsigned int die_nest_count;
 146static int die_counter;
 147
 148extern void panic_flush_kmsg_start(void)
 149{
 150	/*
 151	 * These are mostly taken from kernel/panic.c, but tries to do
 152	 * relatively minimal work. Don't use delay functions (TB may
 153	 * be broken), don't crash dump (need to set a firmware log),
 154	 * don't run notifiers. We do want to get some information to
 155	 * Linux console.
 156	 */
 157	console_verbose();
 158	bust_spinlocks(1);
 159}
 160
 161extern void panic_flush_kmsg_end(void)
 162{
 163	printk_safe_flush_on_panic();
 164	kmsg_dump(KMSG_DUMP_PANIC);
 165	bust_spinlocks(0);
 166	debug_locks_off();
 167	console_flush_on_panic();
 168}
 169
 170static unsigned long oops_begin(struct pt_regs *regs)
 171{
 172	int cpu;
 173	unsigned long flags;
 174
 175	oops_enter();
 176
 177	/* racy, but better than risking deadlock. */
 178	raw_local_irq_save(flags);
 179	cpu = smp_processor_id();
 180	if (!arch_spin_trylock(&die_lock)) {
 181		if (cpu == die_owner)
 182			/* nested oops. should stop eventually */;
 183		else
 184			arch_spin_lock(&die_lock);
 185	}
 186	die_nest_count++;
 187	die_owner = cpu;
 188	console_verbose();
 189	bust_spinlocks(1);
 190	if (machine_is(powermac))
 191		pmac_backlight_unblank();
 192	return flags;
 193}
 194NOKPROBE_SYMBOL(oops_begin);
 195
 196static void oops_end(unsigned long flags, struct pt_regs *regs,
 197			       int signr)
 198{
 199	bust_spinlocks(0);
 200	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 201	die_nest_count--;
 202	oops_exit();
 203	printk("\n");
 204	if (!die_nest_count) {
 205		/* Nest count reaches zero, release the lock. */
 206		die_owner = -1;
 207		arch_spin_unlock(&die_lock);
 208	}
 209	raw_local_irq_restore(flags);
 210
 211	/*
 212	 * system_reset_excption handles debugger, crash dump, panic, for 0x100
 213	 */
 214	if (TRAP(regs) == 0x100)
 215		return;
 216
 217	crash_fadump(regs, "die oops");
 218
 219	if (kexec_should_crash(current))
 
 
 
 
 220		crash_kexec(regs);
 221
 
 
 
 
 
 
 
 
 222	if (!signr)
 223		return;
 224
 225	/*
 226	 * While our oops output is serialised by a spinlock, output
 227	 * from panic() called below can race and corrupt it. If we
 228	 * know we are going to panic, delay for 1 second so we have a
 229	 * chance to get clean backtraces from all CPUs that are oopsing.
 230	 */
 231	if (in_interrupt() || panic_on_oops || !current->pid ||
 232	    is_global_init(current)) {
 233		mdelay(MSEC_PER_SEC);
 234	}
 235
 236	if (in_interrupt())
 237		panic("Fatal exception in interrupt");
 238	if (panic_on_oops)
 239		panic("Fatal exception");
 240	do_exit(signr);
 241}
 242NOKPROBE_SYMBOL(oops_end);
 243
 244static int __die(const char *str, struct pt_regs *regs, long err)
 245{
 246	printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
 247
 248	if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
 249		printk("LE ");
 250	else
 251		printk("BE ");
 252
 253	if (IS_ENABLED(CONFIG_PREEMPT))
 254		pr_cont("PREEMPT ");
 255
 256	if (IS_ENABLED(CONFIG_SMP))
 257		pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
 258
 259	if (debug_pagealloc_enabled())
 260		pr_cont("DEBUG_PAGEALLOC ");
 261
 262	if (IS_ENABLED(CONFIG_NUMA))
 263		pr_cont("NUMA ");
 264
 265	pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
 266
 267	if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
 268		return 1;
 269
 270	print_modules();
 271	show_regs(regs);
 272
 273	return 0;
 274}
 275NOKPROBE_SYMBOL(__die);
 276
 277void die(const char *str, struct pt_regs *regs, long err)
 278{
 279	unsigned long flags;
 280
 281	/*
 282	 * system_reset_excption handles debugger, crash dump, panic, for 0x100
 283	 */
 284	if (TRAP(regs) != 0x100) {
 285		if (debugger(regs))
 286			return;
 287	}
 288
 289	flags = oops_begin(regs);
 290	if (__die(str, regs, err))
 291		err = 0;
 292	oops_end(flags, regs, err);
 293}
 294NOKPROBE_SYMBOL(die);
 295
 296void user_single_step_siginfo(struct task_struct *tsk,
 297				struct pt_regs *regs, siginfo_t *info)
 298{
 299	memset(info, 0, sizeof(*info));
 300	info->si_signo = SIGTRAP;
 301	info->si_code = TRAP_TRACE;
 302	info->si_addr = (void __user *)regs->nip;
 303}
 304
 305
 306void _exception_pkey(int signr, struct pt_regs *regs, int code,
 307		unsigned long addr, int key)
 308{
 309	siginfo_t info;
 310	const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
 311			"at %08lx nip %08lx lr %08lx code %x\n";
 312	const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
 313			"at %016lx nip %016lx lr %016lx code %x\n";
 314
 315	if (!user_mode(regs)) {
 316		die("Exception in kernel mode", regs, signr);
 317		return;
 318	}
 319
 320	if (show_unhandled_signals && unhandled_signal(current, signr)) {
 321		printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
 322				   current->comm, current->pid, signr,
 323				   addr, regs->nip, regs->link, code);
 324	}
 325
 326	if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
 327		local_irq_enable();
 328
 329	current->thread.trap_nr = code;
 330
 331	/*
 332	 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
 333	 * to capture the content, if the task gets killed.
 334	 */
 335	thread_pkey_regs_save(&current->thread);
 336
 337	memset(&info, 0, sizeof(info));
 338	info.si_signo = signr;
 339	info.si_code = code;
 340	info.si_addr = (void __user *) addr;
 341	info.si_pkey = key;
 342
 343	force_sig_info(signr, &info, current);
 344}
 345
 346void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 347{
 348	_exception_pkey(signr, regs, code, addr, 0);
 349}
 350
 351void system_reset_exception(struct pt_regs *regs)
 352{
 353	/*
 354	 * Avoid crashes in case of nested NMI exceptions. Recoverability
 355	 * is determined by RI and in_nmi
 356	 */
 357	bool nested = in_nmi();
 358	if (!nested)
 359		nmi_enter();
 360
 361	__this_cpu_inc(irq_stat.sreset_irqs);
 362
 363	/* See if any machine dependent calls */
 364	if (ppc_md.system_reset_exception) {
 365		if (ppc_md.system_reset_exception(regs))
 366			goto out;
 367	}
 368
 369	if (debugger(regs))
 370		goto out;
 371
 372	/*
 373	 * A system reset is a request to dump, so we always send
 374	 * it through the crashdump code (if fadump or kdump are
 375	 * registered).
 376	 */
 377	crash_fadump(regs, "System Reset");
 378
 379	crash_kexec(regs);
 
 380
 381	/*
 382	 * We aren't the primary crash CPU. We need to send it
 383	 * to a holding pattern to avoid it ending up in the panic
 384	 * code.
 385	 */
 386	crash_kexec_secondary(regs);
 
 
 
 387
 388	/*
 389	 * No debugger or crash dump registered, print logs then
 390	 * panic.
 391	 */
 392	die("System Reset", regs, SIGABRT);
 393
 394	mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
 395	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 396	nmi_panic(regs, "System Reset");
 397
 398out:
 399#ifdef CONFIG_PPC_BOOK3S_64
 400	BUG_ON(get_paca()->in_nmi == 0);
 401	if (get_paca()->in_nmi > 1)
 402		nmi_panic(regs, "Unrecoverable nested System Reset");
 403#endif
 404	/* Must die if the interrupt is not recoverable */
 405	if (!(regs->msr & MSR_RI))
 406		nmi_panic(regs, "Unrecoverable System Reset");
 407
 408	if (!nested)
 409		nmi_exit();
 410
 411	/* What should we do here? We could issue a shutdown or hard reset. */
 
 
 
 
 
 412}
 413
 
 
 414/*
 415 * I/O accesses can cause machine checks on powermacs.
 416 * Check if the NIP corresponds to the address of a sync
 417 * instruction for which there is an entry in the exception
 418 * table.
 419 * Note that the 601 only takes a machine check on TEA
 420 * (transfer error ack) signal assertion, and does not
 421 * set any of the top 16 bits of SRR1.
 422 *  -- paulus.
 423 */
 424static inline int check_io_access(struct pt_regs *regs)
 425{
 426#ifdef CONFIG_PPC32
 427	unsigned long msr = regs->msr;
 428	const struct exception_table_entry *entry;
 429	unsigned int *nip = (unsigned int *)regs->nip;
 430
 431	if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 432	    && (entry = search_exception_tables(regs->nip)) != NULL) {
 433		/*
 434		 * Check that it's a sync instruction, or somewhere
 435		 * in the twi; isync; nop sequence that inb/inw/inl uses.
 436		 * As the address is in the exception table
 437		 * we should be able to read the instr there.
 438		 * For the debug message, we look at the preceding
 439		 * load or store.
 440		 */
 441		if (*nip == PPC_INST_NOP)
 442			nip -= 2;
 443		else if (*nip == PPC_INST_ISYNC)
 444			--nip;
 445		if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
 446			unsigned int rb;
 447
 448			--nip;
 449			rb = (*nip >> 11) & 0x1f;
 450			printk(KERN_DEBUG "%s bad port %lx at %p\n",
 451			       (*nip & 0x100)? "OUT to": "IN from",
 452			       regs->gpr[rb] - _IO_BASE, nip);
 453			regs->msr |= MSR_RI;
 454			regs->nip = extable_fixup(entry);
 455			return 1;
 456		}
 457	}
 458#endif /* CONFIG_PPC32 */
 459	return 0;
 460}
 461
 462#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 463/* On 4xx, the reason for the machine check or program exception
 464   is in the ESR. */
 465#define get_reason(regs)	((regs)->dsisr)
 
 
 
 
 
 466#define REASON_FP		ESR_FP
 467#define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
 468#define REASON_PRIVILEGED	ESR_PPR
 469#define REASON_TRAP		ESR_PTR
 470
 471/* single-step stuff */
 472#define single_stepping(regs)	(current->thread.debug.dbcr0 & DBCR0_IC)
 473#define clear_single_step(regs)	(current->thread.debug.dbcr0 &= ~DBCR0_IC)
 474#define clear_br_trace(regs)	do {} while(0)
 475#else
 476/* On non-4xx, the reason for the machine check or program
 477   exception is in the MSR. */
 478#define get_reason(regs)	((regs)->msr)
 479#define REASON_TM		SRR1_PROGTM
 480#define REASON_FP		SRR1_PROGFPE
 481#define REASON_ILLEGAL		SRR1_PROGILL
 482#define REASON_PRIVILEGED	SRR1_PROGPRIV
 483#define REASON_TRAP		SRR1_PROGTRAP
 
 484
 485#define single_stepping(regs)	((regs)->msr & MSR_SE)
 486#define clear_single_step(regs)	((regs)->msr &= ~MSR_SE)
 487#define clear_br_trace(regs)	((regs)->msr &= ~MSR_BE)
 488#endif
 489
 490#if defined(CONFIG_E500)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 491int machine_check_e500mc(struct pt_regs *regs)
 492{
 493	unsigned long mcsr = mfspr(SPRN_MCSR);
 494	unsigned long pvr = mfspr(SPRN_PVR);
 495	unsigned long reason = mcsr;
 496	int recoverable = 1;
 497
 498	if (reason & MCSR_LD) {
 499		recoverable = fsl_rio_mcheck_exception(regs);
 500		if (recoverable == 1)
 501			goto silent_out;
 502	}
 503
 504	printk("Machine check in kernel mode.\n");
 505	printk("Caused by (from MCSR=%lx): ", reason);
 506
 507	if (reason & MCSR_MCP)
 508		printk("Machine Check Signal\n");
 509
 510	if (reason & MCSR_ICPERR) {
 511		printk("Instruction Cache Parity Error\n");
 512
 513		/*
 514		 * This is recoverable by invalidating the i-cache.
 515		 */
 516		mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
 517		while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
 518			;
 519
 520		/*
 521		 * This will generally be accompanied by an instruction
 522		 * fetch error report -- only treat MCSR_IF as fatal
 523		 * if it wasn't due to an L1 parity error.
 524		 */
 525		reason &= ~MCSR_IF;
 526	}
 527
 528	if (reason & MCSR_DCPERR_MC) {
 529		printk("Data Cache Parity Error\n");
 530
 531		/*
 532		 * In write shadow mode we auto-recover from the error, but it
 533		 * may still get logged and cause a machine check.  We should
 534		 * only treat the non-write shadow case as non-recoverable.
 535		 */
 536		/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
 537		 * is not implemented but L1 data cache always runs in write
 538		 * shadow mode. Hence on data cache parity errors HW will
 539		 * automatically invalidate the L1 Data Cache.
 540		 */
 541		if (PVR_VER(pvr) != PVR_VER_E6500) {
 542			if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
 543				recoverable = 0;
 544		}
 545	}
 546
 547	if (reason & MCSR_L2MMU_MHIT) {
 548		printk("Hit on multiple TLB entries\n");
 549		recoverable = 0;
 550	}
 551
 552	if (reason & MCSR_NMI)
 553		printk("Non-maskable interrupt\n");
 554
 555	if (reason & MCSR_IF) {
 556		printk("Instruction Fetch Error Report\n");
 557		recoverable = 0;
 558	}
 559
 560	if (reason & MCSR_LD) {
 561		printk("Load Error Report\n");
 562		recoverable = 0;
 563	}
 564
 565	if (reason & MCSR_ST) {
 566		printk("Store Error Report\n");
 567		recoverable = 0;
 568	}
 569
 570	if (reason & MCSR_LDG) {
 571		printk("Guarded Load Error Report\n");
 572		recoverable = 0;
 573	}
 574
 575	if (reason & MCSR_TLBSYNC)
 576		printk("Simultaneous tlbsync operations\n");
 577
 578	if (reason & MCSR_BSL2_ERR) {
 579		printk("Level 2 Cache Error\n");
 580		recoverable = 0;
 581	}
 582
 583	if (reason & MCSR_MAV) {
 584		u64 addr;
 585
 586		addr = mfspr(SPRN_MCAR);
 587		addr |= (u64)mfspr(SPRN_MCARU) << 32;
 588
 589		printk("Machine Check %s Address: %#llx\n",
 590		       reason & MCSR_MEA ? "Effective" : "Physical", addr);
 591	}
 592
 593silent_out:
 594	mtspr(SPRN_MCSR, mcsr);
 595	return mfspr(SPRN_MCSR) == 0 && recoverable;
 596}
 597
 598int machine_check_e500(struct pt_regs *regs)
 599{
 600	unsigned long reason = mfspr(SPRN_MCSR);
 601
 602	if (reason & MCSR_BUS_RBERR) {
 603		if (fsl_rio_mcheck_exception(regs))
 604			return 1;
 605		if (fsl_pci_mcheck_exception(regs))
 606			return 1;
 607	}
 608
 609	printk("Machine check in kernel mode.\n");
 610	printk("Caused by (from MCSR=%lx): ", reason);
 611
 612	if (reason & MCSR_MCP)
 613		printk("Machine Check Signal\n");
 614	if (reason & MCSR_ICPERR)
 615		printk("Instruction Cache Parity Error\n");
 616	if (reason & MCSR_DCP_PERR)
 617		printk("Data Cache Push Parity Error\n");
 618	if (reason & MCSR_DCPERR)
 619		printk("Data Cache Parity Error\n");
 620	if (reason & MCSR_BUS_IAERR)
 621		printk("Bus - Instruction Address Error\n");
 622	if (reason & MCSR_BUS_RAERR)
 623		printk("Bus - Read Address Error\n");
 624	if (reason & MCSR_BUS_WAERR)
 625		printk("Bus - Write Address Error\n");
 626	if (reason & MCSR_BUS_IBERR)
 627		printk("Bus - Instruction Data Error\n");
 628	if (reason & MCSR_BUS_RBERR)
 629		printk("Bus - Read Data Bus Error\n");
 630	if (reason & MCSR_BUS_WBERR)
 631		printk("Bus - Write Data Bus Error\n");
 632	if (reason & MCSR_BUS_IPERR)
 633		printk("Bus - Instruction Parity Error\n");
 634	if (reason & MCSR_BUS_RPERR)
 635		printk("Bus - Read Parity Error\n");
 636
 637	return 0;
 638}
 639
 640int machine_check_generic(struct pt_regs *regs)
 641{
 642	return 0;
 643}
 644#elif defined(CONFIG_E200)
 645int machine_check_e200(struct pt_regs *regs)
 646{
 647	unsigned long reason = mfspr(SPRN_MCSR);
 648
 649	printk("Machine check in kernel mode.\n");
 650	printk("Caused by (from MCSR=%lx): ", reason);
 651
 652	if (reason & MCSR_MCP)
 653		printk("Machine Check Signal\n");
 654	if (reason & MCSR_CP_PERR)
 655		printk("Cache Push Parity Error\n");
 656	if (reason & MCSR_CPERR)
 657		printk("Cache Parity Error\n");
 658	if (reason & MCSR_EXCP_ERR)
 659		printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
 660	if (reason & MCSR_BUS_IRERR)
 661		printk("Bus - Read Bus Error on instruction fetch\n");
 662	if (reason & MCSR_BUS_DRERR)
 663		printk("Bus - Read Bus Error on data load\n");
 664	if (reason & MCSR_BUS_WRERR)
 665		printk("Bus - Write Bus Error on buffered store or cache line push\n");
 666
 667	return 0;
 668}
 669#elif defined(CONFIG_PPC32)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 670int machine_check_generic(struct pt_regs *regs)
 671{
 672	unsigned long reason = regs->msr;
 673
 674	printk("Machine check in kernel mode.\n");
 675	printk("Caused by (from SRR1=%lx): ", reason);
 676	switch (reason & 0x601F0000) {
 677	case 0x80000:
 678		printk("Machine check signal\n");
 679		break;
 680	case 0:		/* for 601 */
 681	case 0x40000:
 682	case 0x140000:	/* 7450 MSS error and TEA */
 683		printk("Transfer error ack signal\n");
 684		break;
 685	case 0x20000:
 686		printk("Data parity error signal\n");
 687		break;
 688	case 0x10000:
 689		printk("Address parity error signal\n");
 690		break;
 691	case 0x20000000:
 692		printk("L1 Data Cache error\n");
 693		break;
 694	case 0x40000000:
 695		printk("L1 Instruction Cache error\n");
 696		break;
 697	case 0x00100000:
 698		printk("L2 data cache parity error\n");
 699		break;
 700	default:
 701		printk("Unknown values in msr\n");
 702	}
 703	return 0;
 704}
 705#endif /* everything else */
 706
 707void machine_check_exception(struct pt_regs *regs)
 708{
 
 709	int recover = 0;
 710	bool nested = in_nmi();
 711	if (!nested)
 712		nmi_enter();
 713
 714	/* 64s accounts the mce in machine_check_early when in HVMODE */
 715	if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
 716		__this_cpu_inc(irq_stat.mce_exceptions);
 717
 718	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
 719
 720	/* See if any machine dependent calls. In theory, we would want
 721	 * to call the CPU first, and call the ppc_md. one if the CPU
 722	 * one returns a positive number. However there is existing code
 723	 * that assumes the board gets a first chance, so let's keep it
 724	 * that way for now and fix things later. --BenH.
 725	 */
 726	if (ppc_md.machine_check_exception)
 727		recover = ppc_md.machine_check_exception(regs);
 728	else if (cur_cpu_spec->machine_check)
 729		recover = cur_cpu_spec->machine_check(regs);
 730
 731	if (recover > 0)
 732		goto bail;
 733
 734	if (debugger_fault_handler(regs))
 735		goto bail;
 736
 737	if (check_io_access(regs))
 738		goto bail;
 739
 740	die("Machine check", regs, SIGBUS);
 741
 742	/* Must die if the interrupt is not recoverable */
 743	if (!(regs->msr & MSR_RI))
 744		nmi_panic(regs, "Unrecoverable Machine check");
 745
 746bail:
 747	if (!nested)
 748		nmi_exit();
 749}
 750
 751void SMIException(struct pt_regs *regs)
 752{
 753	die("System Management Interrupt", regs, SIGABRT);
 754}
 755
 756#ifdef CONFIG_VSX
 757static void p9_hmi_special_emu(struct pt_regs *regs)
 758{
 759	unsigned int ra, rb, t, i, sel, instr, rc;
 760	const void __user *addr;
 761	u8 vbuf[16], *vdst;
 762	unsigned long ea, msr, msr_mask;
 763	bool swap;
 764
 765	if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
 766		return;
 767
 768	/*
 769	 * lxvb16x	opcode: 0x7c0006d8
 770	 * lxvd2x	opcode: 0x7c000698
 771	 * lxvh8x	opcode: 0x7c000658
 772	 * lxvw4x	opcode: 0x7c000618
 773	 */
 774	if ((instr & 0xfc00073e) != 0x7c000618) {
 775		pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
 776			 " instr=%08x\n",
 777			 smp_processor_id(), current->comm, current->pid,
 778			 regs->nip, instr);
 779		return;
 780	}
 781
 782	/* Grab vector registers into the task struct */
 783	msr = regs->msr; /* Grab msr before we flush the bits */
 784	flush_vsx_to_thread(current);
 785	enable_kernel_altivec();
 786
 787	/*
 788	 * Is userspace running with a different endian (this is rare but
 789	 * not impossible)
 790	 */
 791	swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
 792
 793	/* Decode the instruction */
 794	ra = (instr >> 16) & 0x1f;
 795	rb = (instr >> 11) & 0x1f;
 796	t = (instr >> 21) & 0x1f;
 797	if (instr & 1)
 798		vdst = (u8 *)&current->thread.vr_state.vr[t];
 799	else
 800		vdst = (u8 *)&current->thread.fp_state.fpr[t][0];
 801
 802	/* Grab the vector address */
 803	ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
 804	if (is_32bit_task())
 805		ea &= 0xfffffffful;
 806	addr = (__force const void __user *)ea;
 807
 808	/* Check it */
 809	if (!access_ok(VERIFY_READ, addr, 16)) {
 810		pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
 811			 " instr=%08x addr=%016lx\n",
 812			 smp_processor_id(), current->comm, current->pid,
 813			 regs->nip, instr, (unsigned long)addr);
 814		return;
 815	}
 816
 817	/* Read the vector */
 818	rc = 0;
 819	if ((unsigned long)addr & 0xfUL)
 820		/* unaligned case */
 821		rc = __copy_from_user_inatomic(vbuf, addr, 16);
 822	else
 823		__get_user_atomic_128_aligned(vbuf, addr, rc);
 824	if (rc) {
 825		pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
 826			 " instr=%08x addr=%016lx\n",
 827			 smp_processor_id(), current->comm, current->pid,
 828			 regs->nip, instr, (unsigned long)addr);
 829		return;
 830	}
 831
 832	pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
 833		 " instr=%08x addr=%016lx\n",
 834		 smp_processor_id(), current->comm, current->pid, regs->nip,
 835		 instr, (unsigned long) addr);
 836
 837	/* Grab instruction "selector" */
 838	sel = (instr >> 6) & 3;
 839
 840	/*
 841	 * Check to make sure the facility is actually enabled. This
 842	 * could happen if we get a false positive hit.
 843	 *
 844	 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
 845	 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
 846	 */
 847	msr_mask = MSR_VSX;
 848	if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
 849		msr_mask = MSR_VEC;
 850	if (!(msr & msr_mask)) {
 851		pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
 852			 " instr=%08x msr:%016lx\n",
 853			 smp_processor_id(), current->comm, current->pid,
 854			 regs->nip, instr, msr);
 855		return;
 856	}
 857
 858	/* Do logging here before we modify sel based on endian */
 859	switch (sel) {
 860	case 0:	/* lxvw4x */
 861		PPC_WARN_EMULATED(lxvw4x, regs);
 862		break;
 863	case 1: /* lxvh8x */
 864		PPC_WARN_EMULATED(lxvh8x, regs);
 865		break;
 866	case 2: /* lxvd2x */
 867		PPC_WARN_EMULATED(lxvd2x, regs);
 868		break;
 869	case 3: /* lxvb16x */
 870		PPC_WARN_EMULATED(lxvb16x, regs);
 871		break;
 872	}
 873
 874#ifdef __LITTLE_ENDIAN__
 875	/*
 876	 * An LE kernel stores the vector in the task struct as an LE
 877	 * byte array (effectively swapping both the components and
 878	 * the content of the components). Those instructions expect
 879	 * the components to remain in ascending address order, so we
 880	 * swap them back.
 881	 *
 882	 * If we are running a BE user space, the expectation is that
 883	 * of a simple memcpy, so forcing the emulation to look like
 884	 * a lxvb16x should do the trick.
 885	 */
 886	if (swap)
 887		sel = 3;
 888
 889	switch (sel) {
 890	case 0:	/* lxvw4x */
 891		for (i = 0; i < 4; i++)
 892			((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
 893		break;
 894	case 1: /* lxvh8x */
 895		for (i = 0; i < 8; i++)
 896			((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
 897		break;
 898	case 2: /* lxvd2x */
 899		for (i = 0; i < 2; i++)
 900			((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
 901		break;
 902	case 3: /* lxvb16x */
 903		for (i = 0; i < 16; i++)
 904			vdst[i] = vbuf[15-i];
 905		break;
 906	}
 907#else /* __LITTLE_ENDIAN__ */
 908	/* On a big endian kernel, a BE userspace only needs a memcpy */
 909	if (!swap)
 910		sel = 3;
 911
 912	/* Otherwise, we need to swap the content of the components */
 913	switch (sel) {
 914	case 0:	/* lxvw4x */
 915		for (i = 0; i < 4; i++)
 916			((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
 917		break;
 918	case 1: /* lxvh8x */
 919		for (i = 0; i < 8; i++)
 920			((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
 921		break;
 922	case 2: /* lxvd2x */
 923		for (i = 0; i < 2; i++)
 924			((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
 925		break;
 926	case 3: /* lxvb16x */
 927		memcpy(vdst, vbuf, 16);
 928		break;
 929	}
 930#endif /* !__LITTLE_ENDIAN__ */
 931
 932	/* Go to next instruction */
 933	regs->nip += 4;
 934}
 935#endif /* CONFIG_VSX */
 936
 937void handle_hmi_exception(struct pt_regs *regs)
 938{
 939	struct pt_regs *old_regs;
 940
 941	old_regs = set_irq_regs(regs);
 942	irq_enter();
 943
 944#ifdef CONFIG_VSX
 945	/* Real mode flagged P9 special emu is needed */
 946	if (local_paca->hmi_p9_special_emu) {
 947		local_paca->hmi_p9_special_emu = 0;
 948
 949		/*
 950		 * We don't want to take page faults while doing the
 951		 * emulation, we just replay the instruction if necessary.
 952		 */
 953		pagefault_disable();
 954		p9_hmi_special_emu(regs);
 955		pagefault_enable();
 956	}
 957#endif /* CONFIG_VSX */
 958
 959	if (ppc_md.handle_hmi_exception)
 960		ppc_md.handle_hmi_exception(regs);
 961
 962	irq_exit();
 963	set_irq_regs(old_regs);
 964}
 965
 966void unknown_exception(struct pt_regs *regs)
 967{
 968	enum ctx_state prev_state = exception_enter();
 969
 970	printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
 971	       regs->nip, regs->msr, regs->trap);
 972
 973	_exception(SIGTRAP, regs, TRAP_FIXME, 0);
 974
 975	exception_exit(prev_state);
 976}
 977
 978void instruction_breakpoint_exception(struct pt_regs *regs)
 979{
 980	enum ctx_state prev_state = exception_enter();
 981
 982	if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
 983					5, SIGTRAP) == NOTIFY_STOP)
 984		goto bail;
 985	if (debugger_iabr_match(regs))
 986		goto bail;
 987	_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
 988
 989bail:
 990	exception_exit(prev_state);
 991}
 992
 993void RunModeException(struct pt_regs *regs)
 994{
 995	_exception(SIGTRAP, regs, TRAP_FIXME, 0);
 996}
 997
 998void single_step_exception(struct pt_regs *regs)
 999{
1000	enum ctx_state prev_state = exception_enter();
1001
1002	clear_single_step(regs);
1003	clear_br_trace(regs);
1004
1005	if (kprobe_post_handler(regs))
1006		return;
1007
1008	if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1009					5, SIGTRAP) == NOTIFY_STOP)
1010		goto bail;
1011	if (debugger_sstep(regs))
1012		goto bail;
1013
1014	_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1015
1016bail:
1017	exception_exit(prev_state);
1018}
1019NOKPROBE_SYMBOL(single_step_exception);
1020
1021/*
1022 * After we have successfully emulated an instruction, we have to
1023 * check if the instruction was being single-stepped, and if so,
1024 * pretend we got a single-step exception.  This was pointed out
1025 * by Kumar Gala.  -- paulus
1026 */
1027static void emulate_single_step(struct pt_regs *regs)
1028{
1029	if (single_stepping(regs))
1030		single_step_exception(regs);
1031}
1032
1033static inline int __parse_fpscr(unsigned long fpscr)
1034{
1035	int ret = FPE_FIXME;
1036
1037	/* Invalid operation */
1038	if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1039		ret = FPE_FLTINV;
1040
1041	/* Overflow */
1042	else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1043		ret = FPE_FLTOVF;
1044
1045	/* Underflow */
1046	else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1047		ret = FPE_FLTUND;
1048
1049	/* Divide by zero */
1050	else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1051		ret = FPE_FLTDIV;
1052
1053	/* Inexact result */
1054	else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1055		ret = FPE_FLTRES;
1056
1057	return ret;
1058}
1059
1060static void parse_fpe(struct pt_regs *regs)
1061{
1062	int code = 0;
1063
1064	flush_fp_to_thread(current);
1065
1066	code = __parse_fpscr(current->thread.fp_state.fpscr);
1067
1068	_exception(SIGFPE, regs, code, regs->nip);
1069}
1070
1071/*
1072 * Illegal instruction emulation support.  Originally written to
1073 * provide the PVR to user applications using the mfspr rd, PVR.
1074 * Return non-zero if we can't emulate, or -EFAULT if the associated
1075 * memory access caused an access fault.  Return zero on success.
1076 *
1077 * There are a couple of ways to do this, either "decode" the instruction
1078 * or directly match lots of bits.  In this case, matching lots of
1079 * bits is faster and easier.
1080 *
1081 */
1082static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1083{
1084	u8 rT = (instword >> 21) & 0x1f;
1085	u8 rA = (instword >> 16) & 0x1f;
1086	u8 NB_RB = (instword >> 11) & 0x1f;
1087	u32 num_bytes;
1088	unsigned long EA;
1089	int pos = 0;
1090
1091	/* Early out if we are an invalid form of lswx */
1092	if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1093		if ((rT == rA) || (rT == NB_RB))
1094			return -EINVAL;
1095
1096	EA = (rA == 0) ? 0 : regs->gpr[rA];
1097
1098	switch (instword & PPC_INST_STRING_MASK) {
1099		case PPC_INST_LSWX:
1100		case PPC_INST_STSWX:
1101			EA += NB_RB;
1102			num_bytes = regs->xer & 0x7f;
1103			break;
1104		case PPC_INST_LSWI:
1105		case PPC_INST_STSWI:
1106			num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1107			break;
1108		default:
1109			return -EINVAL;
1110	}
1111
1112	while (num_bytes != 0)
1113	{
1114		u8 val;
1115		u32 shift = 8 * (3 - (pos & 0x3));
1116
1117		/* if process is 32-bit, clear upper 32 bits of EA */
1118		if ((regs->msr & MSR_64BIT) == 0)
1119			EA &= 0xFFFFFFFF;
1120
1121		switch ((instword & PPC_INST_STRING_MASK)) {
1122			case PPC_INST_LSWX:
1123			case PPC_INST_LSWI:
1124				if (get_user(val, (u8 __user *)EA))
1125					return -EFAULT;
1126				/* first time updating this reg,
1127				 * zero it out */
1128				if (pos == 0)
1129					regs->gpr[rT] = 0;
1130				regs->gpr[rT] |= val << shift;
1131				break;
1132			case PPC_INST_STSWI:
1133			case PPC_INST_STSWX:
1134				val = regs->gpr[rT] >> shift;
1135				if (put_user(val, (u8 __user *)EA))
1136					return -EFAULT;
1137				break;
1138		}
1139		/* move EA to next address */
1140		EA += 1;
1141		num_bytes--;
1142
1143		/* manage our position within the register */
1144		if (++pos == 4) {
1145			pos = 0;
1146			if (++rT == 32)
1147				rT = 0;
1148		}
1149	}
1150
1151	return 0;
1152}
1153
1154static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1155{
1156	u32 ra,rs;
1157	unsigned long tmp;
1158
1159	ra = (instword >> 16) & 0x1f;
1160	rs = (instword >> 21) & 0x1f;
1161
1162	tmp = regs->gpr[rs];
1163	tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1164	tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1165	tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1166	regs->gpr[ra] = tmp;
1167
1168	return 0;
1169}
1170
1171static int emulate_isel(struct pt_regs *regs, u32 instword)
1172{
1173	u8 rT = (instword >> 21) & 0x1f;
1174	u8 rA = (instword >> 16) & 0x1f;
1175	u8 rB = (instword >> 11) & 0x1f;
1176	u8 BC = (instword >> 6) & 0x1f;
1177	u8 bit;
1178	unsigned long tmp;
1179
1180	tmp = (rA == 0) ? 0 : regs->gpr[rA];
1181	bit = (regs->ccr >> (31 - BC)) & 0x1;
1182
1183	regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1184
1185	return 0;
1186}
1187
1188#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1189static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1190{
1191        /* If we're emulating a load/store in an active transaction, we cannot
1192         * emulate it as the kernel operates in transaction suspended context.
1193         * We need to abort the transaction.  This creates a persistent TM
1194         * abort so tell the user what caused it with a new code.
1195	 */
1196	if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1197		tm_enable();
1198		tm_abort(cause);
1199		return true;
1200	}
1201	return false;
1202}
1203#else
1204static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1205{
1206	return false;
1207}
1208#endif
1209
1210static int emulate_instruction(struct pt_regs *regs)
1211{
1212	u32 instword;
1213	u32 rd;
1214
1215	if (!user_mode(regs))
1216		return -EINVAL;
1217	CHECK_FULL_REGS(regs);
1218
1219	if (get_user(instword, (u32 __user *)(regs->nip)))
1220		return -EFAULT;
1221
1222	/* Emulate the mfspr rD, PVR. */
1223	if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1224		PPC_WARN_EMULATED(mfpvr, regs);
1225		rd = (instword >> 21) & 0x1f;
1226		regs->gpr[rd] = mfspr(SPRN_PVR);
1227		return 0;
1228	}
1229
1230	/* Emulating the dcba insn is just a no-op.  */
1231	if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1232		PPC_WARN_EMULATED(dcba, regs);
1233		return 0;
1234	}
1235
1236	/* Emulate the mcrxr insn.  */
1237	if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1238		int shift = (instword >> 21) & 0x1c;
1239		unsigned long msk = 0xf0000000UL >> shift;
1240
1241		PPC_WARN_EMULATED(mcrxr, regs);
1242		regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1243		regs->xer &= ~0xf0000000UL;
1244		return 0;
1245	}
1246
1247	/* Emulate load/store string insn. */
1248	if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1249		if (tm_abort_check(regs,
1250				   TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1251			return -EINVAL;
1252		PPC_WARN_EMULATED(string, regs);
1253		return emulate_string_inst(regs, instword);
1254	}
1255
1256	/* Emulate the popcntb (Population Count Bytes) instruction. */
1257	if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1258		PPC_WARN_EMULATED(popcntb, regs);
1259		return emulate_popcntb_inst(regs, instword);
1260	}
1261
1262	/* Emulate isel (Integer Select) instruction */
1263	if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1264		PPC_WARN_EMULATED(isel, regs);
1265		return emulate_isel(regs, instword);
1266	}
1267
1268	/* Emulate sync instruction variants */
1269	if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1270		PPC_WARN_EMULATED(sync, regs);
1271		asm volatile("sync");
1272		return 0;
1273	}
1274
1275#ifdef CONFIG_PPC64
1276	/* Emulate the mfspr rD, DSCR. */
1277	if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1278		PPC_INST_MFSPR_DSCR_USER) ||
1279	     ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1280		PPC_INST_MFSPR_DSCR)) &&
1281			cpu_has_feature(CPU_FTR_DSCR)) {
1282		PPC_WARN_EMULATED(mfdscr, regs);
1283		rd = (instword >> 21) & 0x1f;
1284		regs->gpr[rd] = mfspr(SPRN_DSCR);
1285		return 0;
1286	}
1287	/* Emulate the mtspr DSCR, rD. */
1288	if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1289		PPC_INST_MTSPR_DSCR_USER) ||
1290	     ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1291		PPC_INST_MTSPR_DSCR)) &&
1292			cpu_has_feature(CPU_FTR_DSCR)) {
1293		PPC_WARN_EMULATED(mtdscr, regs);
1294		rd = (instword >> 21) & 0x1f;
1295		current->thread.dscr = regs->gpr[rd];
1296		current->thread.dscr_inherit = 1;
1297		mtspr(SPRN_DSCR, current->thread.dscr);
1298		return 0;
1299	}
1300#endif
1301
1302	return -EINVAL;
1303}
1304
1305int is_valid_bugaddr(unsigned long addr)
1306{
1307	return is_kernel_addr(addr);
1308}
1309
1310#ifdef CONFIG_MATH_EMULATION
1311static int emulate_math(struct pt_regs *regs)
1312{
1313	int ret;
1314	extern int do_mathemu(struct pt_regs *regs);
1315
1316	ret = do_mathemu(regs);
1317	if (ret >= 0)
1318		PPC_WARN_EMULATED(math, regs);
1319
1320	switch (ret) {
1321	case 0:
1322		emulate_single_step(regs);
1323		return 0;
1324	case 1: {
1325			int code = 0;
1326			code = __parse_fpscr(current->thread.fp_state.fpscr);
1327			_exception(SIGFPE, regs, code, regs->nip);
1328			return 0;
1329		}
1330	case -EFAULT:
1331		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1332		return 0;
1333	}
1334
1335	return -1;
1336}
1337#else
1338static inline int emulate_math(struct pt_regs *regs) { return -1; }
1339#endif
1340
1341void program_check_exception(struct pt_regs *regs)
1342{
1343	enum ctx_state prev_state = exception_enter();
1344	unsigned int reason = get_reason(regs);
1345
1346	/* We can now get here via a FP Unavailable exception if the core
1347	 * has no FPU, in that case the reason flags will be 0 */
1348
1349	if (reason & REASON_FP) {
1350		/* IEEE FP exception */
1351		parse_fpe(regs);
1352		goto bail;
1353	}
1354	if (reason & REASON_TRAP) {
1355		unsigned long bugaddr;
1356		/* Debugger is first in line to stop recursive faults in
1357		 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1358		if (debugger_bpt(regs))
1359			goto bail;
1360
1361		if (kprobe_handler(regs))
1362			goto bail;
1363
1364		/* trap exception */
1365		if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1366				== NOTIFY_STOP)
1367			goto bail;
1368
1369		bugaddr = regs->nip;
1370		/*
1371		 * Fixup bugaddr for BUG_ON() in real mode
1372		 */
1373		if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1374			bugaddr += PAGE_OFFSET;
1375
1376		if (!(regs->msr & MSR_PR) &&  /* not user-mode */
1377		    report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1378			regs->nip += 4;
1379			goto bail;
1380		}
1381		_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1382		goto bail;
1383	}
1384#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1385	if (reason & REASON_TM) {
1386		/* This is a TM "Bad Thing Exception" program check.
1387		 * This occurs when:
1388		 * -  An rfid/hrfid/mtmsrd attempts to cause an illegal
1389		 *    transition in TM states.
1390		 * -  A trechkpt is attempted when transactional.
1391		 * -  A treclaim is attempted when non transactional.
1392		 * -  A tend is illegally attempted.
1393		 * -  writing a TM SPR when transactional.
1394		 *
1395		 * If usermode caused this, it's done something illegal and
 
 
 
 
 
1396		 * gets a SIGILL slap on the wrist.  We call it an illegal
1397		 * operand to distinguish from the instruction just being bad
1398		 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1399		 * illegal /placement/ of a valid instruction.
1400		 */
1401		if (user_mode(regs)) {
1402			_exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1403			goto bail;
1404		} else {
1405			printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1406			       "at %lx (msr 0x%x)\n", regs->nip, reason);
1407			die("Unrecoverable exception", regs, SIGABRT);
1408		}
1409	}
1410#endif
1411
1412	/*
1413	 * If we took the program check in the kernel skip down to sending a
1414	 * SIGILL. The subsequent cases all relate to emulating instructions
1415	 * which we should only do for userspace. We also do not want to enable
1416	 * interrupts for kernel faults because that might lead to further
1417	 * faults, and loose the context of the original exception.
1418	 */
1419	if (!user_mode(regs))
1420		goto sigill;
1421
1422	/* We restore the interrupt state now */
1423	if (!arch_irq_disabled_regs(regs))
1424		local_irq_enable();
1425
1426	/* (reason & REASON_ILLEGAL) would be the obvious thing here,
1427	 * but there seems to be a hardware bug on the 405GP (RevD)
1428	 * that means ESR is sometimes set incorrectly - either to
1429	 * ESR_DST (!?) or 0.  In the process of chasing this with the
1430	 * hardware people - not sure if it can happen on any illegal
1431	 * instruction or only on FP instructions, whether there is a
1432	 * pattern to occurrences etc. -dgibson 31/Mar/2003
1433	 */
1434	if (!emulate_math(regs))
1435		goto bail;
1436
1437	/* Try to emulate it if we should. */
1438	if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1439		switch (emulate_instruction(regs)) {
1440		case 0:
1441			regs->nip += 4;
1442			emulate_single_step(regs);
1443			goto bail;
1444		case -EFAULT:
1445			_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1446			goto bail;
1447		}
1448	}
1449
1450sigill:
1451	if (reason & REASON_PRIVILEGED)
1452		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1453	else
1454		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1455
1456bail:
1457	exception_exit(prev_state);
1458}
1459NOKPROBE_SYMBOL(program_check_exception);
1460
1461/*
1462 * This occurs when running in hypervisor mode on POWER6 or later
1463 * and an illegal instruction is encountered.
1464 */
1465void emulation_assist_interrupt(struct pt_regs *regs)
1466{
1467	regs->msr |= REASON_ILLEGAL;
1468	program_check_exception(regs);
1469}
1470NOKPROBE_SYMBOL(emulation_assist_interrupt);
1471
1472void alignment_exception(struct pt_regs *regs)
1473{
1474	enum ctx_state prev_state = exception_enter();
1475	int sig, code, fixed = 0;
1476
1477	/* We restore the interrupt state now */
1478	if (!arch_irq_disabled_regs(regs))
1479		local_irq_enable();
1480
1481	if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1482		goto bail;
1483
1484	/* we don't implement logging of alignment exceptions */
1485	if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1486		fixed = fix_alignment(regs);
1487
1488	if (fixed == 1) {
1489		regs->nip += 4;	/* skip over emulated instruction */
1490		emulate_single_step(regs);
1491		goto bail;
1492	}
1493
1494	/* Operand address was bad */
1495	if (fixed == -EFAULT) {
1496		sig = SIGSEGV;
1497		code = SEGV_ACCERR;
1498	} else {
1499		sig = SIGBUS;
1500		code = BUS_ADRALN;
1501	}
1502	if (user_mode(regs))
1503		_exception(sig, regs, code, regs->dar);
1504	else
1505		bad_page_fault(regs, regs->dar, sig);
1506
1507bail:
1508	exception_exit(prev_state);
1509}
1510
 
 
 
 
 
 
 
 
 
 
 
 
1511void StackOverflow(struct pt_regs *regs)
1512{
1513	printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1514	       current, regs->gpr[1]);
1515	debugger(regs);
1516	show_regs(regs);
1517	panic("kernel stack overflow");
1518}
1519
1520void nonrecoverable_exception(struct pt_regs *regs)
1521{
1522	printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1523	       regs->nip, regs->msr);
1524	debugger(regs);
1525	die("nonrecoverable exception", regs, SIGKILL);
1526}
1527
1528void kernel_fp_unavailable_exception(struct pt_regs *regs)
1529{
1530	enum ctx_state prev_state = exception_enter();
1531
1532	printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1533			  "%lx at %lx\n", regs->trap, regs->nip);
1534	die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1535
1536	exception_exit(prev_state);
1537}
1538
1539void altivec_unavailable_exception(struct pt_regs *regs)
1540{
1541	enum ctx_state prev_state = exception_enter();
1542
1543	if (user_mode(regs)) {
1544		/* A user program has executed an altivec instruction,
1545		   but this kernel doesn't support altivec. */
1546		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1547		goto bail;
1548	}
1549
1550	printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1551			"%lx at %lx\n", regs->trap, regs->nip);
1552	die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1553
1554bail:
1555	exception_exit(prev_state);
1556}
1557
1558void vsx_unavailable_exception(struct pt_regs *regs)
1559{
1560	if (user_mode(regs)) {
1561		/* A user program has executed an vsx instruction,
1562		   but this kernel doesn't support vsx. */
1563		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1564		return;
1565	}
1566
1567	printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1568			"%lx at %lx\n", regs->trap, regs->nip);
1569	die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1570}
1571
1572#ifdef CONFIG_PPC64
1573static void tm_unavailable(struct pt_regs *regs)
1574{
1575#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1576	if (user_mode(regs)) {
1577		current->thread.load_tm++;
1578		regs->msr |= MSR_TM;
1579		tm_enable();
1580		tm_restore_sprs(&current->thread);
1581		return;
1582	}
1583#endif
1584	pr_emerg("Unrecoverable TM Unavailable Exception "
1585			"%lx at %lx\n", regs->trap, regs->nip);
1586	die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1587}
1588
1589void facility_unavailable_exception(struct pt_regs *regs)
1590{
1591	static char *facility_strings[] = {
1592		[FSCR_FP_LG] = "FPU",
1593		[FSCR_VECVSX_LG] = "VMX/VSX",
1594		[FSCR_DSCR_LG] = "DSCR",
1595		[FSCR_PM_LG] = "PMU SPRs",
1596		[FSCR_BHRB_LG] = "BHRB",
1597		[FSCR_TM_LG] = "TM",
1598		[FSCR_EBB_LG] = "EBB",
1599		[FSCR_TAR_LG] = "TAR",
1600		[FSCR_MSGP_LG] = "MSGP",
1601		[FSCR_SCV_LG] = "SCV",
1602	};
1603	char *facility = "unknown";
1604	u64 value;
1605	u32 instword, rd;
1606	u8 status;
1607	bool hv;
1608
1609	hv = (TRAP(regs) == 0xf80);
1610	if (hv)
1611		value = mfspr(SPRN_HFSCR);
1612	else
1613		value = mfspr(SPRN_FSCR);
1614
1615	status = value >> 56;
1616	if ((hv || status >= 2) &&
1617	    (status < ARRAY_SIZE(facility_strings)) &&
1618	    facility_strings[status])
1619		facility = facility_strings[status];
1620
1621	/* We should not have taken this interrupt in kernel */
1622	if (!user_mode(regs)) {
1623		pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1624			 facility, status, regs->nip);
1625		die("Unexpected facility unavailable exception", regs, SIGABRT);
1626	}
1627
1628	/* We restore the interrupt state now */
1629	if (!arch_irq_disabled_regs(regs))
1630		local_irq_enable();
1631
1632	if (status == FSCR_DSCR_LG) {
1633		/*
1634		 * User is accessing the DSCR register using the problem
1635		 * state only SPR number (0x03) either through a mfspr or
1636		 * a mtspr instruction. If it is a write attempt through
1637		 * a mtspr, then we set the inherit bit. This also allows
1638		 * the user to write or read the register directly in the
1639		 * future by setting via the FSCR DSCR bit. But in case it
1640		 * is a read DSCR attempt through a mfspr instruction, we
1641		 * just emulate the instruction instead. This code path will
1642		 * always emulate all the mfspr instructions till the user
1643		 * has attempted at least one mtspr instruction. This way it
1644		 * preserves the same behaviour when the user is accessing
1645		 * the DSCR through privilege level only SPR number (0x11)
1646		 * which is emulated through illegal instruction exception.
1647		 * We always leave HFSCR DSCR set.
1648		 */
1649		if (get_user(instword, (u32 __user *)(regs->nip))) {
1650			pr_err("Failed to fetch the user instruction\n");
1651			return;
1652		}
1653
1654		/* Write into DSCR (mtspr 0x03, RS) */
1655		if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1656				== PPC_INST_MTSPR_DSCR_USER) {
1657			rd = (instword >> 21) & 0x1f;
1658			current->thread.dscr = regs->gpr[rd];
1659			current->thread.dscr_inherit = 1;
1660			current->thread.fscr |= FSCR_DSCR;
1661			mtspr(SPRN_FSCR, current->thread.fscr);
1662		}
1663
1664		/* Read from DSCR (mfspr RT, 0x03) */
1665		if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1666				== PPC_INST_MFSPR_DSCR_USER) {
1667			if (emulate_instruction(regs)) {
1668				pr_err("DSCR based mfspr emulation failed\n");
1669				return;
1670			}
1671			regs->nip += 4;
1672			emulate_single_step(regs);
1673		}
1674		return;
1675	}
1676
1677	if (status == FSCR_TM_LG) {
1678		/*
1679		 * If we're here then the hardware is TM aware because it
1680		 * generated an exception with FSRM_TM set.
1681		 *
1682		 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1683		 * told us not to do TM, or the kernel is not built with TM
1684		 * support.
1685		 *
1686		 * If both of those things are true, then userspace can spam the
1687		 * console by triggering the printk() below just by continually
1688		 * doing tbegin (or any TM instruction). So in that case just
1689		 * send the process a SIGILL immediately.
1690		 */
1691		if (!cpu_has_feature(CPU_FTR_TM))
1692			goto out;
1693
1694		tm_unavailable(regs);
1695		return;
1696	}
1697
 
 
 
 
 
 
 
 
 
1698	pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1699		hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1700
1701out:
1702	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 
 
 
 
 
1703}
1704#endif
1705
1706#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1707
1708void fp_unavailable_tm(struct pt_regs *regs)
1709{
1710	/* Note:  This does not handle any kind of FP laziness. */
1711
1712	TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1713		 regs->nip, regs->msr);
1714
1715        /* We can only have got here if the task started using FP after
1716         * beginning the transaction.  So, the transactional regs are just a
1717         * copy of the checkpointed ones.  But, we still need to recheckpoint
1718         * as we're enabling FP for the process; it will return, abort the
1719         * transaction, and probably retry but now with FP enabled.  So the
1720         * checkpointed FP registers need to be loaded.
1721	 */
1722	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1723	/* Reclaim didn't save out any FPRs to transact_fprs. */
1724
1725	/* Enable FP for the task: */
1726	current->thread.load_fp = 1;
1727
1728	/* This loads and recheckpoints the FP registers from
1729	 * thread.fpr[].  They will remain in registers after the
1730	 * checkpoint so we don't need to reload them after.
1731	 * If VMX is in use, the VRs now hold checkpointed values,
1732	 * so we don't want to load the VRs from the thread_struct.
1733	 */
1734	tm_recheckpoint(&current->thread);
 
 
 
 
 
 
 
 
1735}
1736
1737void altivec_unavailable_tm(struct pt_regs *regs)
1738{
1739	/* See the comments in fp_unavailable_tm().  This function operates
1740	 * the same way.
1741	 */
1742
1743	TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1744		 "MSR=%lx\n",
1745		 regs->nip, regs->msr);
1746	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1747	current->thread.load_vec = 1;
1748	tm_recheckpoint(&current->thread);
1749	current->thread.used_vr = 1;
 
 
 
 
 
 
1750}
1751
1752void vsx_unavailable_tm(struct pt_regs *regs)
1753{
 
 
1754	/* See the comments in fp_unavailable_tm().  This works similarly,
1755	 * though we're loading both FP and VEC registers in here.
1756	 *
1757	 * If FP isn't in use, load FP regs.  If VEC isn't in use, load VEC
1758	 * regs.  Either way, set MSR_VSX.
1759	 */
1760
1761	TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1762		 "MSR=%lx\n",
1763		 regs->nip, regs->msr);
1764
1765	current->thread.used_vsr = 1;
1766
 
 
 
 
 
 
1767	/* This reclaims FP and/or VR regs if they're already enabled */
1768	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1769
1770	current->thread.load_vec = 1;
1771	current->thread.load_fp = 1;
1772
1773	tm_recheckpoint(&current->thread);
 
 
 
 
 
 
 
 
 
 
1774}
1775#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1776
1777void performance_monitor_exception(struct pt_regs *regs)
1778{
1779	__this_cpu_inc(irq_stat.pmu_irqs);
1780
1781	perf_irq(regs);
1782}
1783
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1784#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1785static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1786{
1787	int changed = 0;
1788	/*
1789	 * Determine the cause of the debug event, clear the
1790	 * event flags and send a trap to the handler. Torez
1791	 */
1792	if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1793		dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1794#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1795		current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1796#endif
1797		do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1798			     5);
1799		changed |= 0x01;
1800	}  else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1801		dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1802		do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1803			     6);
1804		changed |= 0x01;
1805	}  else if (debug_status & DBSR_IAC1) {
1806		current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1807		dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1808		do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1809			     1);
1810		changed |= 0x01;
1811	}  else if (debug_status & DBSR_IAC2) {
1812		current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1813		do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1814			     2);
1815		changed |= 0x01;
1816	}  else if (debug_status & DBSR_IAC3) {
1817		current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1818		dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1819		do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1820			     3);
1821		changed |= 0x01;
1822	}  else if (debug_status & DBSR_IAC4) {
1823		current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1824		do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1825			     4);
1826		changed |= 0x01;
1827	}
1828	/*
1829	 * At the point this routine was called, the MSR(DE) was turned off.
1830	 * Check all other debug flags and see if that bit needs to be turned
1831	 * back on or not.
1832	 */
1833	if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1834			       current->thread.debug.dbcr1))
1835		regs->msr |= MSR_DE;
1836	else
1837		/* Make sure the IDM flag is off */
1838		current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1839
1840	if (changed & 0x01)
1841		mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1842}
1843
1844void DebugException(struct pt_regs *regs, unsigned long debug_status)
1845{
1846	current->thread.debug.dbsr = debug_status;
1847
1848	/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1849	 * on server, it stops on the target of the branch. In order to simulate
1850	 * the server behaviour, we thus restart right away with a single step
1851	 * instead of stopping here when hitting a BT
1852	 */
1853	if (debug_status & DBSR_BT) {
1854		regs->msr &= ~MSR_DE;
1855
1856		/* Disable BT */
1857		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1858		/* Clear the BT event */
1859		mtspr(SPRN_DBSR, DBSR_BT);
1860
1861		/* Do the single step trick only when coming from userspace */
1862		if (user_mode(regs)) {
1863			current->thread.debug.dbcr0 &= ~DBCR0_BT;
1864			current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1865			regs->msr |= MSR_DE;
1866			return;
1867		}
1868
1869		if (kprobe_post_handler(regs))
1870			return;
1871
1872		if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1873			       5, SIGTRAP) == NOTIFY_STOP) {
1874			return;
1875		}
1876		if (debugger_sstep(regs))
1877			return;
1878	} else if (debug_status & DBSR_IC) { 	/* Instruction complete */
1879		regs->msr &= ~MSR_DE;
1880
1881		/* Disable instruction completion */
1882		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1883		/* Clear the instruction completion event */
1884		mtspr(SPRN_DBSR, DBSR_IC);
1885
1886		if (kprobe_post_handler(regs))
1887			return;
1888
1889		if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1890			       5, SIGTRAP) == NOTIFY_STOP) {
1891			return;
1892		}
1893
1894		if (debugger_sstep(regs))
1895			return;
1896
1897		if (user_mode(regs)) {
1898			current->thread.debug.dbcr0 &= ~DBCR0_IC;
1899			if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1900					       current->thread.debug.dbcr1))
1901				regs->msr |= MSR_DE;
1902			else
1903				/* Make sure the IDM bit is off */
1904				current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1905		}
1906
1907		_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1908	} else
1909		handle_debug(regs, debug_status);
1910}
1911NOKPROBE_SYMBOL(DebugException);
1912#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1913
1914#if !defined(CONFIG_TAU_INT)
1915void TAUException(struct pt_regs *regs)
1916{
1917	printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
1918	       regs->nip, regs->msr, regs->trap, print_tainted());
1919}
1920#endif /* CONFIG_INT_TAU */
1921
1922#ifdef CONFIG_ALTIVEC
1923void altivec_assist_exception(struct pt_regs *regs)
1924{
1925	int err;
1926
1927	if (!user_mode(regs)) {
1928		printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1929		       " at %lx\n", regs->nip);
1930		die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1931	}
1932
1933	flush_altivec_to_thread(current);
1934
1935	PPC_WARN_EMULATED(altivec, regs);
1936	err = emulate_altivec(regs);
1937	if (err == 0) {
1938		regs->nip += 4;		/* skip emulated instruction */
1939		emulate_single_step(regs);
1940		return;
1941	}
1942
1943	if (err == -EFAULT) {
1944		/* got an error reading the instruction */
1945		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1946	} else {
1947		/* didn't recognize the instruction */
1948		/* XXX quick hack for now: set the non-Java bit in the VSCR */
1949		printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1950				   "in %s at %lx\n", current->comm, regs->nip);
1951		current->thread.vr_state.vscr.u[3] |= 0x10000;
1952	}
1953}
1954#endif /* CONFIG_ALTIVEC */
1955
1956#ifdef CONFIG_FSL_BOOKE
1957void CacheLockingException(struct pt_regs *regs, unsigned long address,
1958			   unsigned long error_code)
1959{
1960	/* We treat cache locking instructions from the user
1961	 * as priv ops, in the future we could try to do
1962	 * something smarter
1963	 */
1964	if (error_code & (ESR_DLK|ESR_ILK))
1965		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1966	return;
1967}
1968#endif /* CONFIG_FSL_BOOKE */
1969
1970#ifdef CONFIG_SPE
1971void SPEFloatingPointException(struct pt_regs *regs)
1972{
1973	extern int do_spe_mathemu(struct pt_regs *regs);
1974	unsigned long spefscr;
1975	int fpexc_mode;
1976	int code = FPE_FIXME;
1977	int err;
1978
1979	flush_spe_to_thread(current);
1980
1981	spefscr = current->thread.spefscr;
1982	fpexc_mode = current->thread.fpexc_mode;
1983
1984	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1985		code = FPE_FLTOVF;
1986	}
1987	else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1988		code = FPE_FLTUND;
1989	}
1990	else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1991		code = FPE_FLTDIV;
1992	else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1993		code = FPE_FLTINV;
1994	}
1995	else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1996		code = FPE_FLTRES;
1997
1998	err = do_spe_mathemu(regs);
1999	if (err == 0) {
2000		regs->nip += 4;		/* skip emulated instruction */
2001		emulate_single_step(regs);
2002		return;
2003	}
2004
2005	if (err == -EFAULT) {
2006		/* got an error reading the instruction */
2007		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2008	} else if (err == -EINVAL) {
2009		/* didn't recognize the instruction */
2010		printk(KERN_ERR "unrecognized spe instruction "
2011		       "in %s at %lx\n", current->comm, regs->nip);
2012	} else {
2013		_exception(SIGFPE, regs, code, regs->nip);
2014	}
2015
2016	return;
2017}
2018
2019void SPEFloatingPointRoundException(struct pt_regs *regs)
2020{
2021	extern int speround_handler(struct pt_regs *regs);
2022	int err;
2023
2024	preempt_disable();
2025	if (regs->msr & MSR_SPE)
2026		giveup_spe(current);
2027	preempt_enable();
2028
2029	regs->nip -= 4;
2030	err = speround_handler(regs);
2031	if (err == 0) {
2032		regs->nip += 4;		/* skip emulated instruction */
2033		emulate_single_step(regs);
2034		return;
2035	}
2036
2037	if (err == -EFAULT) {
2038		/* got an error reading the instruction */
2039		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2040	} else if (err == -EINVAL) {
2041		/* didn't recognize the instruction */
2042		printk(KERN_ERR "unrecognized spe instruction "
2043		       "in %s at %lx\n", current->comm, regs->nip);
2044	} else {
2045		_exception(SIGFPE, regs, FPE_FIXME, regs->nip);
2046		return;
2047	}
2048}
2049#endif
2050
2051/*
2052 * We enter here if we get an unrecoverable exception, that is, one
2053 * that happened at a point where the RI (recoverable interrupt) bit
2054 * in the MSR is 0.  This indicates that SRR0/1 are live, and that
2055 * we therefore lost state by taking this exception.
2056 */
2057void unrecoverable_exception(struct pt_regs *regs)
2058{
2059	printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
2060	       regs->trap, regs->nip);
2061	die("Unrecoverable exception", regs, SIGABRT);
2062}
2063NOKPROBE_SYMBOL(unrecoverable_exception);
2064
2065#if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2066/*
2067 * Default handler for a Watchdog exception,
2068 * spins until a reboot occurs
2069 */
2070void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2071{
2072	/* Generic WatchdogHandler, implement your own */
2073	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2074	return;
2075}
2076
2077void WatchdogException(struct pt_regs *regs)
2078{
2079	printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2080	WatchdogHandler(regs);
2081}
2082#endif
2083
2084/*
2085 * We enter here if we discover during exception entry that we are
2086 * running in supervisor mode with a userspace value in the stack pointer.
2087 */
2088void kernel_bad_stack(struct pt_regs *regs)
2089{
2090	printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2091	       regs->gpr[1], regs->nip);
2092	die("Bad kernel stack pointer", regs, SIGABRT);
2093}
2094NOKPROBE_SYMBOL(kernel_bad_stack);
2095
2096void __init trap_init(void)
2097{
2098}
2099
2100
2101#ifdef CONFIG_PPC_EMULATED_STATS
2102
2103#define WARN_EMULATED_SETUP(type)	.type = { .name = #type }
2104
2105struct ppc_emulated ppc_emulated = {
2106#ifdef CONFIG_ALTIVEC
2107	WARN_EMULATED_SETUP(altivec),
2108#endif
2109	WARN_EMULATED_SETUP(dcba),
2110	WARN_EMULATED_SETUP(dcbz),
2111	WARN_EMULATED_SETUP(fp_pair),
2112	WARN_EMULATED_SETUP(isel),
2113	WARN_EMULATED_SETUP(mcrxr),
2114	WARN_EMULATED_SETUP(mfpvr),
2115	WARN_EMULATED_SETUP(multiple),
2116	WARN_EMULATED_SETUP(popcntb),
2117	WARN_EMULATED_SETUP(spe),
2118	WARN_EMULATED_SETUP(string),
2119	WARN_EMULATED_SETUP(sync),
2120	WARN_EMULATED_SETUP(unaligned),
2121#ifdef CONFIG_MATH_EMULATION
2122	WARN_EMULATED_SETUP(math),
2123#endif
2124#ifdef CONFIG_VSX
2125	WARN_EMULATED_SETUP(vsx),
2126#endif
2127#ifdef CONFIG_PPC64
2128	WARN_EMULATED_SETUP(mfdscr),
2129	WARN_EMULATED_SETUP(mtdscr),
2130	WARN_EMULATED_SETUP(lq_stq),
2131	WARN_EMULATED_SETUP(lxvw4x),
2132	WARN_EMULATED_SETUP(lxvh8x),
2133	WARN_EMULATED_SETUP(lxvd2x),
2134	WARN_EMULATED_SETUP(lxvb16x),
2135#endif
2136};
2137
2138u32 ppc_warn_emulated;
2139
2140void ppc_warn_emulated_print(const char *type)
2141{
2142	pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2143			    type);
2144}
2145
2146static int __init ppc_warn_emulated_init(void)
2147{
2148	struct dentry *dir, *d;
2149	unsigned int i;
2150	struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2151
2152	if (!powerpc_debugfs_root)
2153		return -ENODEV;
2154
2155	dir = debugfs_create_dir("emulated_instructions",
2156				 powerpc_debugfs_root);
2157	if (!dir)
2158		return -ENOMEM;
2159
2160	d = debugfs_create_u32("do_warn", 0644, dir,
2161			       &ppc_warn_emulated);
2162	if (!d)
2163		goto fail;
2164
2165	for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
2166		d = debugfs_create_u32(entries[i].name, 0644, dir,
2167				       (u32 *)&entries[i].val.counter);
2168		if (!d)
2169			goto fail;
2170	}
2171
2172	return 0;
2173
2174fail:
2175	debugfs_remove_recursive(dir);
2176	return -ENOMEM;
2177}
2178
2179device_initcall(ppc_warn_emulated_init);
2180
2181#endif /* CONFIG_PPC_EMULATED_STATS */