1/*
  2 * 
  3 * Common boot and setup code.
  4 *
  5 * Copyright (C) 2001 PPC64 Team, IBM Corp
  6 *
  7 *      This program is free software; you can redistribute it and/or
  8 *      modify it under the terms of the GNU General Public License
  9 *      as published by the Free Software Foundation; either version
 10 *      2 of the License, or (at your option) any later version.
 11 */
 12
 
 
 13#include <linux/export.h>
 14#include <linux/string.h>
 15#include <linux/sched.h>
 16#include <linux/init.h>
 17#include <linux/kernel.h>
 18#include <linux/reboot.h>
 19#include <linux/delay.h>
 20#include <linux/initrd.h>
 21#include <linux/seq_file.h>
 22#include <linux/ioport.h>
 23#include <linux/console.h>
 24#include <linux/utsname.h>
 25#include <linux/tty.h>
 26#include <linux/root_dev.h>
 27#include <linux/notifier.h>
 28#include <linux/cpu.h>
 29#include <linux/unistd.h>
 30#include <linux/serial.h>
 31#include <linux/serial_8250.h>
 32#include <linux/bootmem.h>
 33#include <linux/pci.h>
 34#include <linux/lockdep.h>
 35#include <linux/memblock.h>
 36#include <linux/memory.h>
 37#include <linux/nmi.h>
 38
 39#include <asm/debugfs.h>
 40#include <asm/io.h>
 41#include <asm/kdump.h>
 42#include <asm/prom.h>
 43#include <asm/processor.h>
 44#include <asm/pgtable.h>
 45#include <asm/smp.h>
 46#include <asm/elf.h>
 47#include <asm/machdep.h>
 48#include <asm/paca.h>
 49#include <asm/time.h>
 50#include <asm/cputable.h>
 51#include <asm/dt_cpu_ftrs.h>
 52#include <asm/sections.h>
 53#include <asm/btext.h>
 54#include <asm/nvram.h>
 55#include <asm/setup.h>
 56#include <asm/rtas.h>
 57#include <asm/iommu.h>
 58#include <asm/serial.h>
 59#include <asm/cache.h>
 60#include <asm/page.h>
 61#include <asm/mmu.h>
 62#include <asm/firmware.h>
 63#include <asm/xmon.h>
 64#include <asm/udbg.h>
 65#include <asm/kexec.h>
 66#include <asm/code-patching.h>
 67#include <asm/livepatch.h>
 68#include <asm/opal.h>
 69#include <asm/cputhreads.h>
 70#include <asm/hw_irq.h>
 71
 72#include "setup.h"
 73
 74#ifdef DEBUG
 75#define DBG(fmt...) udbg_printf(fmt)
 76#else
 77#define DBG(fmt...)
 78#endif
 79
 80int spinning_secondaries;
 81u64 ppc64_pft_size;
 82
 
 
 
 83struct ppc64_caches ppc64_caches = {
 84	.l1d = {
 85		.block_size = 0x40,
 86		.log_block_size = 6,
 87	},
 88	.l1i = {
 89		.block_size = 0x40,
 90		.log_block_size = 6
 91	},
 92};
 93EXPORT_SYMBOL_GPL(ppc64_caches);
 94
 
 
 
 
 
 
 
 
 95#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
 96void __init setup_tlb_core_data(void)
 97{
 98	int cpu;
 99
100	BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
101
102	for_each_possible_cpu(cpu) {
103		int first = cpu_first_thread_sibling(cpu);
104
105		/*
106		 * If we boot via kdump on a non-primary thread,
107		 * make sure we point at the thread that actually
108		 * set up this TLB.
109		 */
110		if (cpu_first_thread_sibling(boot_cpuid) == first)
111			first = boot_cpuid;
112
113		paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
114
115		/*
116		 * If we have threads, we need either tlbsrx.
117		 * or e6500 tablewalk mode, or else TLB handlers
118		 * will be racy and could produce duplicate entries.
119		 * Should we panic instead?
120		 */
121		WARN_ONCE(smt_enabled_at_boot >= 2 &&
122			  !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
123			  book3e_htw_mode != PPC_HTW_E6500,
124			  "%s: unsupported MMU configuration\n", __func__);
 
 
 
125	}
126}
127#endif
128
129#ifdef CONFIG_SMP
130
131static char *smt_enabled_cmdline;
132
133/* Look for ibm,smt-enabled OF option */
134void __init check_smt_enabled(void)
135{
136	struct device_node *dn;
137	const char *smt_option;
138
139	/* Default to enabling all threads */
140	smt_enabled_at_boot = threads_per_core;
141
142	/* Allow the command line to overrule the OF option */
143	if (smt_enabled_cmdline) {
144		if (!strcmp(smt_enabled_cmdline, "on"))
145			smt_enabled_at_boot = threads_per_core;
146		else if (!strcmp(smt_enabled_cmdline, "off"))
147			smt_enabled_at_boot = 0;
148		else {
149			int smt;
150			int rc;
151
152			rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
153			if (!rc)
154				smt_enabled_at_boot =
155					min(threads_per_core, smt);
156		}
157	} else {
158		dn = of_find_node_by_path("/options");
159		if (dn) {
160			smt_option = of_get_property(dn, "ibm,smt-enabled",
161						     NULL);
162
163			if (smt_option) {
164				if (!strcmp(smt_option, "on"))
165					smt_enabled_at_boot = threads_per_core;
166				else if (!strcmp(smt_option, "off"))
167					smt_enabled_at_boot = 0;
168			}
169
170			of_node_put(dn);
171		}
172	}
173}
174
175/* Look for smt-enabled= cmdline option */
176static int __init early_smt_enabled(char *p)
177{
178	smt_enabled_cmdline = p;
179	return 0;
180}
181early_param("smt-enabled", early_smt_enabled);
182
183#endif /* CONFIG_SMP */
184
185/** Fix up paca fields required for the boot cpu */
186static void __init fixup_boot_paca(void)
187{
188	/* The boot cpu is started */
189	get_paca()->cpu_start = 1;
190	/* Allow percpu accesses to work until we setup percpu data */
191	get_paca()->data_offset = 0;
192	/* Mark interrupts disabled in PACA */
193	irq_soft_mask_set(IRQS_DISABLED);
194}
195
196static void __init configure_exceptions(void)
197{
198	/*
199	 * Setup the trampolines from the lowmem exception vectors
200	 * to the kdump kernel when not using a relocatable kernel.
201	 */
202	setup_kdump_trampoline();
203
204	/* Under a PAPR hypervisor, we need hypercalls */
205	if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
206		/* Enable AIL if possible */
207		pseries_enable_reloc_on_exc();
208
209		/*
210		 * Tell the hypervisor that we want our exceptions to
211		 * be taken in little endian mode.
212		 *
213		 * We don't call this for big endian as our calling convention
214		 * makes us always enter in BE, and the call may fail under
215		 * some circumstances with kdump.
216		 */
217#ifdef __LITTLE_ENDIAN__
218		pseries_little_endian_exceptions();
219#endif
220	} else {
221		/* Set endian mode using OPAL */
222		if (firmware_has_feature(FW_FEATURE_OPAL))
223			opal_configure_cores();
224
225		/* AIL on native is done in cpu_ready_for_interrupts() */
226	}
227}
228
229static void cpu_ready_for_interrupts(void)
230{
231	/*
232	 * Enable AIL if supported, and we are in hypervisor mode. This
233	 * is called once for every processor.
234	 *
235	 * If we are not in hypervisor mode the job is done once for
236	 * the whole partition in configure_exceptions().
237	 */
238	if (cpu_has_feature(CPU_FTR_HVMODE) &&
239	    cpu_has_feature(CPU_FTR_ARCH_207S)) {
240		unsigned long lpcr = mfspr(SPRN_LPCR);
241		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
242	}
243
244	/*
245	 * Fixup HFSCR:TM based on CPU features. The bit is set by our
246	 * early asm init because at that point we haven't updated our
247	 * CPU features from firmware and device-tree. Here we have,
248	 * so let's do it.
249	 */
250	if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
251		mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
252
253	/* Set IR and DR in PACA MSR */
254	get_paca()->kernel_msr = MSR_KERNEL;
255}
256
257unsigned long spr_default_dscr = 0;
258
259void __init record_spr_defaults(void)
260{
261	if (early_cpu_has_feature(CPU_FTR_DSCR))
262		spr_default_dscr = mfspr(SPRN_DSCR);
263}
264
265/*
266 * Early initialization entry point. This is called by head.S
267 * with MMU translation disabled. We rely on the "feature" of
268 * the CPU that ignores the top 2 bits of the address in real
269 * mode so we can access kernel globals normally provided we
270 * only toy with things in the RMO region. From here, we do
271 * some early parsing of the device-tree to setup out MEMBLOCK
272 * data structures, and allocate & initialize the hash table
273 * and segment tables so we can start running with translation
274 * enabled.
275 *
276 * It is this function which will call the probe() callback of
277 * the various platform types and copy the matching one to the
278 * global ppc_md structure. Your platform can eventually do
279 * some very early initializations from the probe() routine, but
280 * this is not recommended, be very careful as, for example, the
281 * device-tree is not accessible via normal means at this point.
282 */
283
284void __init early_setup(unsigned long dt_ptr)
285{
286	static __initdata struct paca_struct boot_paca;
287
288	/* -------- printk is _NOT_ safe to use here ! ------- */
289
290	/* Try new device tree based feature discovery ... */
291	if (!dt_cpu_ftrs_init(__va(dt_ptr)))
292		/* Otherwise use the old style CPU table */
293		identify_cpu(0, mfspr(SPRN_PVR));
294
295	/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
296	initialise_paca(&boot_paca, 0);
297	setup_paca(&boot_paca);
298	fixup_boot_paca();
299
300	/* -------- printk is now safe to use ------- */
301
302	/* Enable early debugging if any specified (see udbg.h) */
303	udbg_early_init();
304
305 	DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
306
307	/*
308	 * Do early initialization using the flattened device
309	 * tree, such as retrieving the physical memory map or
310	 * calculating/retrieving the hash table size.
311	 */
312	early_init_devtree(__va(dt_ptr));
313
314	/* Now we know the logical id of our boot cpu, setup the paca. */
315	if (boot_cpuid != 0) {
316		/* Poison paca_ptrs[0] again if it's not the boot cpu */
317		memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
318	}
319	setup_paca(paca_ptrs[boot_cpuid]);
320	fixup_boot_paca();
321
322	/*
323	 * Configure exception handlers. This include setting up trampolines
324	 * if needed, setting exception endian mode, etc...
325	 */
326	configure_exceptions();
327
328	/* Apply all the dynamic patching */
329	apply_feature_fixups();
330	setup_feature_keys();
331
332	/* Initialize the hash table or TLB handling */
333	early_init_mmu();
334
335	/*
336	 * After firmware and early platform setup code has set things up,
337	 * we note the SPR values for configurable control/performance
338	 * registers, and use those as initial defaults.
339	 */
340	record_spr_defaults();
341
342	/*
343	 * At this point, we can let interrupts switch to virtual mode
344	 * (the MMU has been setup), so adjust the MSR in the PACA to
345	 * have IR and DR set and enable AIL if it exists
346	 */
347	cpu_ready_for_interrupts();
348
349	DBG(" <- early_setup()\n");
350
351#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
352	/*
353	 * This needs to be done *last* (after the above DBG() even)
354	 *
355	 * Right after we return from this function, we turn on the MMU
356	 * which means the real-mode access trick that btext does will
357	 * no longer work, it needs to switch to using a real MMU
358	 * mapping. This call will ensure that it does
359	 */
360	btext_map();
361#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
362}
363
364#ifdef CONFIG_SMP
365void early_setup_secondary(void)
366{
367	/* Mark interrupts disabled in PACA */
368	irq_soft_mask_set(IRQS_DISABLED);
369
370	/* Initialize the hash table or TLB handling */
371	early_init_mmu_secondary();
372
373	/*
374	 * At this point, we can let interrupts switch to virtual mode
375	 * (the MMU has been setup), so adjust the MSR in the PACA to
376	 * have IR and DR set.
377	 */
378	cpu_ready_for_interrupts();
379}
380
381#endif /* CONFIG_SMP */
382
383#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
384static bool use_spinloop(void)
385{
386	if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
387		/*
388		 * See comments in head_64.S -- not all platforms insert
389		 * secondaries at __secondary_hold and wait at the spin
390		 * loop.
391		 */
392		if (firmware_has_feature(FW_FEATURE_OPAL))
393			return false;
394		return true;
395	}
396
397	/*
398	 * When book3e boots from kexec, the ePAPR spin table does
399	 * not get used.
400	 */
401	return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
402}
403
404void smp_release_cpus(void)
405{
406	unsigned long *ptr;
407	int i;
408
409	if (!use_spinloop())
410		return;
411
412	DBG(" -> smp_release_cpus()\n");
413
414	/* All secondary cpus are spinning on a common spinloop, release them
415	 * all now so they can start to spin on their individual paca
416	 * spinloops. For non SMP kernels, the secondary cpus never get out
417	 * of the common spinloop.
418	 */
419
420	ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
421			- PHYSICAL_START);
422	*ptr = ppc_function_entry(generic_secondary_smp_init);
423
424	/* And wait a bit for them to catch up */
425	for (i = 0; i < 100000; i++) {
426		mb();
427		HMT_low();
428		if (spinning_secondaries == 0)
429			break;
430		udelay(1);
431	}
432	DBG("spinning_secondaries = %d\n", spinning_secondaries);
433
434	DBG(" <- smp_release_cpus()\n");
435}
436#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
437
438/*
439 * Initialize some remaining members of the ppc64_caches and systemcfg
440 * structures
441 * (at least until we get rid of them completely). This is mostly some
442 * cache informations about the CPU that will be used by cache flush
443 * routines and/or provided to userland
444 */
445
446static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
447			    u32 bsize, u32 sets)
448{
449	info->size = size;
450	info->sets = sets;
451	info->line_size = lsize;
452	info->block_size = bsize;
453	info->log_block_size = __ilog2(bsize);
454	if (bsize)
455		info->blocks_per_page = PAGE_SIZE / bsize;
456	else
457		info->blocks_per_page = 0;
458
459	if (sets == 0)
460		info->assoc = 0xffff;
461	else
462		info->assoc = size / (sets * lsize);
463}
464
465static bool __init parse_cache_info(struct device_node *np,
466				    bool icache,
467				    struct ppc_cache_info *info)
468{
469	static const char *ipropnames[] __initdata = {
470		"i-cache-size",
471		"i-cache-sets",
472		"i-cache-block-size",
473		"i-cache-line-size",
474	};
475	static const char *dpropnames[] __initdata = {
476		"d-cache-size",
477		"d-cache-sets",
478		"d-cache-block-size",
479		"d-cache-line-size",
480	};
481	const char **propnames = icache ? ipropnames : dpropnames;
482	const __be32 *sizep, *lsizep, *bsizep, *setsp;
483	u32 size, lsize, bsize, sets;
484	bool success = true;
485
486	size = 0;
487	sets = -1u;
488	lsize = bsize = cur_cpu_spec->dcache_bsize;
489	sizep = of_get_property(np, propnames[0], NULL);
490	if (sizep != NULL)
491		size = be32_to_cpu(*sizep);
492	setsp = of_get_property(np, propnames[1], NULL);
493	if (setsp != NULL)
494		sets = be32_to_cpu(*setsp);
495	bsizep = of_get_property(np, propnames[2], NULL);
496	lsizep = of_get_property(np, propnames[3], NULL);
497	if (bsizep == NULL)
498		bsizep = lsizep;
499	if (lsizep != NULL)
500		lsize = be32_to_cpu(*lsizep);
501	if (bsizep != NULL)
502		bsize = be32_to_cpu(*bsizep);
503	if (sizep == NULL || bsizep == NULL || lsizep == NULL)
504		success = false;
505
506	/*
507	 * OF is weird .. it represents fully associative caches
508	 * as "1 way" which doesn't make much sense and doesn't
509	 * leave room for direct mapped. We'll assume that 0
510	 * in OF means direct mapped for that reason.
511	 */
512	if (sets == 1)
513		sets = 0;
514	else if (sets == 0)
515		sets = 1;
516
517	init_cache_info(info, size, lsize, bsize, sets);
518
519	return success;
520}
521
522void __init initialize_cache_info(void)
523{
524	struct device_node *cpu = NULL, *l2, *l3 = NULL;
525	u32 pvr;
526
527	DBG(" -> initialize_cache_info()\n");
528
529	/*
530	 * All shipping POWER8 machines have a firmware bug that
531	 * puts incorrect information in the device-tree. This will
532	 * be (hopefully) fixed for future chips but for now hard
533	 * code the values if we are running on one of these
534	 */
535	pvr = PVR_VER(mfspr(SPRN_PVR));
536	if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
537	    pvr == PVR_POWER8NVL) {
538						/* size    lsize   blk  sets */
539		init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
540		init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
541		init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
542		init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
543	} else
544		cpu = of_find_node_by_type(NULL, "cpu");
545
546	/*
547	 * We're assuming *all* of the CPUs have the same
548	 * d-cache and i-cache sizes... -Peter
549	 */
550	if (cpu) {
551		if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
552			DBG("Argh, can't find dcache properties !\n");
553
554		if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
555			DBG("Argh, can't find icache properties !\n");
556
557		/*
558		 * Try to find the L2 and L3 if any. Assume they are
559		 * unified and use the D-side properties.
560		 */
561		l2 = of_find_next_cache_node(cpu);
562		of_node_put(cpu);
563		if (l2) {
564			parse_cache_info(l2, false, &ppc64_caches.l2);
565			l3 = of_find_next_cache_node(l2);
566			of_node_put(l2);
567		}
568		if (l3) {
569			parse_cache_info(l3, false, &ppc64_caches.l3);
570			of_node_put(l3);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
571		}
572	}
573
574	/* For use by binfmt_elf */
575	dcache_bsize = ppc64_caches.l1d.block_size;
576	icache_bsize = ppc64_caches.l1i.block_size;
577
578	cur_cpu_spec->dcache_bsize = dcache_bsize;
579	cur_cpu_spec->icache_bsize = icache_bsize;
580
581	DBG(" <- initialize_cache_info()\n");
582}
583
584/*
585 * This returns the limit below which memory accesses to the linear
586 * mapping are guarnateed not to cause an architectural exception (e.g.,
587 * TLB or SLB miss fault).
588 *
589 * This is used to allocate PACAs and various interrupt stacks that
590 * that are accessed early in interrupt handlers that must not cause
591 * re-entrant interrupts.
592 */
593__init u64 ppc64_bolted_size(void)
594{
595#ifdef CONFIG_PPC_BOOK3E
596	/* Freescale BookE bolts the entire linear mapping */
597	/* XXX: BookE ppc64_rma_limit setup seems to disagree? */
598	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
599		return linear_map_top;
600	/* Other BookE, we assume the first GB is bolted */
601	return 1ul << 30;
602#else
603	/* BookS radix, does not take faults on linear mapping */
604	if (early_radix_enabled())
605		return ULONG_MAX;
606
607	/* BookS hash, the first segment is bolted */
608	if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
609		return 1UL << SID_SHIFT_1T;
610	return 1UL << SID_SHIFT;
611#endif
612}
613
614static void *__init alloc_stack(unsigned long limit, int cpu)
615{
616	unsigned long pa;
617
618	pa = memblock_alloc_base_nid(THREAD_SIZE, THREAD_SIZE, limit,
619					early_cpu_to_node(cpu), MEMBLOCK_NONE);
620	if (!pa) {
621		pa = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
622		if (!pa)
623			panic("cannot allocate stacks");
624	}
625
626	return __va(pa);
627}
628
629void __init irqstack_early_init(void)
630{
631	u64 limit = ppc64_bolted_size();
632	unsigned int i;
633
634	/*
635	 * Interrupt stacks must be in the first segment since we
636	 * cannot afford to take SLB misses on them. They are not
637	 * accessed in realmode.
638	 */
639	for_each_possible_cpu(i) {
640		softirq_ctx[i] = alloc_stack(limit, i);
641		hardirq_ctx[i] = alloc_stack(limit, i);
 
 
 
 
642	}
643}
644
645#ifdef CONFIG_PPC_BOOK3E
646void __init exc_lvl_early_init(void)
647{
648	unsigned int i;
 
649
650	for_each_possible_cpu(i) {
651		void *sp;
652
653		sp = alloc_stack(ULONG_MAX, i);
654		critirq_ctx[i] = sp;
655		paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
656
657		sp = alloc_stack(ULONG_MAX, i);
658		dbgirq_ctx[i] = sp;
659		paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
660
661		sp = alloc_stack(ULONG_MAX, i);
662		mcheckirq_ctx[i] = sp;
663		paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
664	}
665
666	if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
667		patch_exception(0x040, exc_debug_debug_book3e);
668}
669#endif
670
671/*
672 * Emergency stacks are used for a range of things, from asynchronous
673 * NMIs (system reset, machine check) to synchronous, process context.
674 * We set preempt_count to zero, even though that isn't necessarily correct. To
675 * get the right value we'd need to copy it from the previous thread_info, but
676 * doing that might fault causing more problems.
677 * TODO: what to do with accounting?
678 */
679static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
680{
681	ti->task = NULL;
682	ti->cpu = cpu;
683	ti->preempt_count = 0;
684	ti->local_flags = 0;
685	ti->flags = 0;
686	klp_init_thread_info(ti);
687}
688
689/*
690 * Stack space used when we detect a bad kernel stack pointer, and
691 * early in SMP boots before relocation is enabled. Exclusive emergency
692 * stack for machine checks.
693 */
694void __init emergency_stack_init(void)
695{
696	u64 limit;
697	unsigned int i;
698
699	/*
700	 * Emergency stacks must be under 256MB, we cannot afford to take
701	 * SLB misses on them. The ABI also requires them to be 128-byte
702	 * aligned.
703	 *
704	 * Since we use these as temporary stacks during secondary CPU
705	 * bringup, machine check, system reset, and HMI, we need to get
706	 * at them in real mode. This means they must also be within the RMO
707	 * region.
708	 *
709	 * The IRQ stacks allocated elsewhere in this file are zeroed and
710	 * initialized in kernel/irq.c. These are initialized here in order
711	 * to have emergency stacks available as early as possible.
712	 */
713	limit = min(ppc64_bolted_size(), ppc64_rma_size);
714
715	for_each_possible_cpu(i) {
716		struct thread_info *ti;
717
718		ti = alloc_stack(limit, i);
719		memset(ti, 0, THREAD_SIZE);
720		emerg_stack_init_thread_info(ti, i);
721		paca_ptrs[i]->emergency_sp = (void *)ti + THREAD_SIZE;
722
723#ifdef CONFIG_PPC_BOOK3S_64
724		/* emergency stack for NMI exception handling. */
725		ti = alloc_stack(limit, i);
726		memset(ti, 0, THREAD_SIZE);
727		emerg_stack_init_thread_info(ti, i);
728		paca_ptrs[i]->nmi_emergency_sp = (void *)ti + THREAD_SIZE;
729
730		/* emergency stack for machine check exception handling. */
731		ti = alloc_stack(limit, i);
732		memset(ti, 0, THREAD_SIZE);
733		emerg_stack_init_thread_info(ti, i);
734		paca_ptrs[i]->mc_emergency_sp = (void *)ti + THREAD_SIZE;
735#endif
736	}
737}
738
739#ifdef CONFIG_SMP
740#define PCPU_DYN_SIZE		()
741
742static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
743{
744	return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
745				    __pa(MAX_DMA_ADDRESS));
746}
747
748static void __init pcpu_fc_free(void *ptr, size_t size)
749{
750	free_bootmem(__pa(ptr), size);
751}
752
753static int pcpu_cpu_distance(unsigned int from, unsigned int to)
754{
755	if (early_cpu_to_node(from) == early_cpu_to_node(to))
756		return LOCAL_DISTANCE;
757	else
758		return REMOTE_DISTANCE;
759}
760
761unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
762EXPORT_SYMBOL(__per_cpu_offset);
763
764void __init setup_per_cpu_areas(void)
765{
766	const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
767	size_t atom_size;
768	unsigned long delta;
769	unsigned int cpu;
770	int rc;
771
772	/*
773	 * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
774	 * to group units.  For larger mappings, use 1M atom which
775	 * should be large enough to contain a number of units.
776	 */
777	if (mmu_linear_psize == MMU_PAGE_4K)
778		atom_size = PAGE_SIZE;
779	else
780		atom_size = 1 << 20;
781
782	rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
783				    pcpu_fc_alloc, pcpu_fc_free);
784	if (rc < 0)
785		panic("cannot initialize percpu area (err=%d)", rc);
786
787	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
788	for_each_possible_cpu(cpu) {
789                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
790		paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
791	}
792}
793#endif
794
795#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
796unsigned long memory_block_size_bytes(void)
797{
798	if (ppc_md.memory_block_size)
799		return ppc_md.memory_block_size();
800
801	return MIN_MEMORY_BLOCK_SIZE;
802}
803#endif
804
805#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
806struct ppc_pci_io ppc_pci_io;
807EXPORT_SYMBOL(ppc_pci_io);
808#endif
809
810#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
811u64 hw_nmi_get_sample_period(int watchdog_thresh)
812{
813	return ppc_proc_freq * watchdog_thresh;
814}
815#endif
816
817/*
818 * The perf based hardlockup detector breaks PMU event based branches, so
819 * disable it by default. Book3S has a soft-nmi hardlockup detector based
820 * on the decrementer interrupt, so it does not suffer from this problem.
821 *
822 * It is likely to get false positives in VM guests, so disable it there
823 * by default too.
824 */
825static int __init disable_hardlockup_detector(void)
826{
827#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
828	hardlockup_detector_disable();
829#else
830	if (firmware_has_feature(FW_FEATURE_LPAR))
831		hardlockup_detector_disable();
832#endif
833
834	return 0;
835}
836early_initcall(disable_hardlockup_detector);
837
838#ifdef CONFIG_PPC_BOOK3S_64
839static enum l1d_flush_type enabled_flush_types;
840static void *l1d_flush_fallback_area;
841static bool no_rfi_flush;
842bool rfi_flush;
843
844static int __init handle_no_rfi_flush(char *p)
845{
846	pr_info("rfi-flush: disabled on command line.");
847	no_rfi_flush = true;
848	return 0;
849}
850early_param("no_rfi_flush", handle_no_rfi_flush);
851
852/*
853 * The RFI flush is not KPTI, but because users will see doco that says to use
854 * nopti we hijack that option here to also disable the RFI flush.
855 */
856static int __init handle_no_pti(char *p)
857{
858	pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
859	handle_no_rfi_flush(NULL);
860	return 0;
861}
862early_param("nopti", handle_no_pti);
863
864static void do_nothing(void *unused)
865{
866	/*
867	 * We don't need to do the flush explicitly, just enter+exit kernel is
868	 * sufficient, the RFI exit handlers will do the right thing.
869	 */
870}
871
872void rfi_flush_enable(bool enable)
873{
874	if (enable) {
875		do_rfi_flush_fixups(enabled_flush_types);
876		on_each_cpu(do_nothing, NULL, 1);
877	} else
878		do_rfi_flush_fixups(L1D_FLUSH_NONE);
879
880	rfi_flush = enable;
881}
882
883static void __ref init_fallback_flush(void)
884{
885	u64 l1d_size, limit;
886	int cpu;
887
888	/* Only allocate the fallback flush area once (at boot time). */
889	if (l1d_flush_fallback_area)
890		return;
891
892	l1d_size = ppc64_caches.l1d.size;
893
894	/*
895	 * If there is no d-cache-size property in the device tree, l1d_size
896	 * could be zero. That leads to the loop in the asm wrapping around to
897	 * 2^64-1, and then walking off the end of the fallback area and
898	 * eventually causing a page fault which is fatal. Just default to
899	 * something vaguely sane.
900	 */
901	if (!l1d_size)
902		l1d_size = (64 * 1024);
903
904	limit = min(ppc64_bolted_size(), ppc64_rma_size);
905
906	/*
907	 * Align to L1d size, and size it at 2x L1d size, to catch possible
908	 * hardware prefetch runoff. We don't have a recipe for load patterns to
909	 * reliably avoid the prefetcher.
910	 */
911	l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
912	memset(l1d_flush_fallback_area, 0, l1d_size * 2);
913
914	for_each_possible_cpu(cpu) {
915		struct paca_struct *paca = paca_ptrs[cpu];
916		paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
917		paca->l1d_flush_size = l1d_size;
918	}
919}
920
921void setup_rfi_flush(enum l1d_flush_type types, bool enable)
922{
923	if (types & L1D_FLUSH_FALLBACK) {
924		pr_info("rfi-flush: fallback displacement flush available\n");
925		init_fallback_flush();
926	}
927
928	if (types & L1D_FLUSH_ORI)
929		pr_info("rfi-flush: ori type flush available\n");
930
931	if (types & L1D_FLUSH_MTTRIG)
932		pr_info("rfi-flush: mttrig type flush available\n");
933
934	enabled_flush_types = types;
935
936	if (!no_rfi_flush)
937		rfi_flush_enable(enable);
938}
939
940#ifdef CONFIG_DEBUG_FS
941static int rfi_flush_set(void *data, u64 val)
942{
943	bool enable;
944
945	if (val == 1)
946		enable = true;
947	else if (val == 0)
948		enable = false;
949	else
950		return -EINVAL;
951
952	/* Only do anything if we're changing state */
953	if (enable != rfi_flush)
954		rfi_flush_enable(enable);
955
956	return 0;
957}
958
959static int rfi_flush_get(void *data, u64 *val)
960{
961	*val = rfi_flush ? 1 : 0;
962	return 0;
963}
964
965DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
966
967static __init int rfi_flush_debugfs_init(void)
968{
969	debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
970	return 0;
971}
972device_initcall(rfi_flush_debugfs_init);
973#endif
974#endif /* CONFIG_PPC_BOOK3S_64 */