1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * This file contains the 64-bit "server" PowerPC variant
   4 * of the low level exception handling including exception
   5 * vectors, exception return, part of the slb and stab
   6 * handling and other fixed offset specific things.
   7 *
   8 * This file is meant to be #included from head_64.S due to
   9 * position dependent assembly.
  10 *
  11 * Most of this originates from head_64.S and thus has the same
  12 * copyright history.
  13 *
  14 */
  15
  16#include <asm/hw_irq.h>
  17#include <asm/exception-64s.h>
  18#include <asm/ptrace.h>
  19#include <asm/cpuidle.h>
  20#include <asm/head-64.h>
  21
  22/*
  23 * There are a few constraints to be concerned with.
  24 * - Real mode exceptions code/data must be located at their physical location.
  25 * - Virtual mode exceptions must be mapped at their 0xc000... location.
  26 * - Fixed location code must not call directly beyond the __end_interrupts
  27 *   area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
  28 *   must be used.
  29 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
  30 *   virtual 0xc00...
  31 * - Conditional branch targets must be within +/-32K of caller.
  32 *
  33 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
  34 * therefore don't have to run in physically located code or rfid to
  35 * virtual mode kernel code. However on relocatable kernels they do have
  36 * to branch to KERNELBASE offset because the rest of the kernel (outside
  37 * the exception vectors) may be located elsewhere.
  38 *
  39 * Virtual exceptions correspond with physical, except their entry points
  40 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
  41 * offset applied. Virtual exceptions are enabled with the Alternate
  42 * Interrupt Location (AIL) bit set in the LPCR. However this does not
  43 * guarantee they will be delivered virtually. Some conditions (see the ISA)
  44 * cause exceptions to be delivered in real mode.
  45 *
  46 * It's impossible to receive interrupts below 0x300 via AIL.
  47 *
  48 * KVM: None of the virtual exceptions are from the guest. Anything that
  49 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
  50 *
  51 *
  52 * We layout physical memory as follows:
  53 * 0x0000 - 0x00ff : Secondary processor spin code
  54 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
  55 * 0x1900 - 0x3fff : Real mode trampolines
  56 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
  57 * 0x5900 - 0x6fff : Relon mode trampolines
  58 * 0x7000 - 0x7fff : FWNMI data area
  59 * 0x8000 -   .... : Common interrupt handlers, remaining early
  60 *                   setup code, rest of kernel.
  61 *
  62 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
  63 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
  64 * vectors there.
  65 */
  66OPEN_FIXED_SECTION(real_vectors,        0x0100, 0x1900)
  67OPEN_FIXED_SECTION(real_trampolines,    0x1900, 0x4000)
  68OPEN_FIXED_SECTION(virt_vectors,        0x4000, 0x5900)
  69OPEN_FIXED_SECTION(virt_trampolines,    0x5900, 0x7000)
  70#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
  71/*
  72 * Data area reserved for FWNMI option.
  73 * This address (0x7000) is fixed by the RPA.
  74 * pseries and powernv need to keep the whole page from
  75 * 0x7000 to 0x8000 free for use by the firmware
  76 */
  77ZERO_FIXED_SECTION(fwnmi_page,          0x7000, 0x8000)
  78OPEN_TEXT_SECTION(0x8000)
  79#else
  80OPEN_TEXT_SECTION(0x7000)
  81#endif
  82
  83USE_FIXED_SECTION(real_vectors)
  84
  85/*
  86 * This is the start of the interrupt handlers for pSeries
  87 * This code runs with relocation off.
  88 * Code from here to __end_interrupts gets copied down to real
  89 * address 0x100 when we are running a relocatable kernel.
  90 * Therefore any relative branches in this section must only
  91 * branch to labels in this section.
  92 */
  93	.globl __start_interrupts
  94__start_interrupts:
  95
  96/* No virt vectors corresponding with 0x0..0x100 */
  97EXC_VIRT_NONE(0x4000, 0x100)
  98
  99
 100#ifdef CONFIG_PPC_P7_NAP
 101	/*
 102	 * If running native on arch 2.06 or later, check if we are waking up
 103	 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
 104	 * bits 46:47. A non-0 value indicates that we are coming from a power
 105	 * saving state. The idle wakeup handler initially runs in real mode,
 106	 * but we branch to the 0xc000... address so we can turn on relocation
 107	 * with mtmsr.
 108	 */
 109#define IDLETEST(n)							\
 110	BEGIN_FTR_SECTION ;						\
 111	mfspr	r10,SPRN_SRR1 ;						\
 112	rlwinm.	r10,r10,47-31,30,31 ;					\
 113	beq-	1f ;							\
 114	cmpwi	cr3,r10,2 ;						\
 115	BRANCH_TO_C000(r10, system_reset_idle_common) ;			\
 1161:									\
 117	KVMTEST_PR(n) ;							\
 118	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 119#else
 120#define IDLETEST NOTEST
 121#endif
 122
 123EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
 124	SET_SCRATCH0(r13)
 125	/*
 126	 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
 127	 * being used, so a nested NMI exception would corrupt it.
 128	 */
 129	EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
 130				 IDLETEST, 0x100)
 131
 132EXC_REAL_END(system_reset, 0x100, 0x100)
 133EXC_VIRT_NONE(0x4100, 0x100)
 134TRAMP_KVM(PACA_EXNMI, 0x100)
 135
 136#ifdef CONFIG_PPC_P7_NAP
 137EXC_COMMON_BEGIN(system_reset_idle_common)
 138	mfspr	r12,SPRN_SRR1
 139	b	pnv_powersave_wakeup
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 140#endif
 141
 142/*
 143 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
 144 * the right thing. We do not want to reconcile because that goes
 145 * through irq tracing which we don't want in NMI.
 146 *
 147 * Save PACAIRQHAPPENED because some code will do a hard disable
 148 * (e.g., xmon). So we want to restore this back to where it was
 149 * when we return. DAR is unused in the stack, so save it there.
 150 */
 151#define ADD_RECONCILE_NMI						\
 152	li	r10,IRQS_ALL_DISABLED;					\
 153	stb	r10,PACAIRQSOFTMASK(r13);				\
 154	lbz	r10,PACAIRQHAPPENED(r13);				\
 155	std	r10,_DAR(r1)
 156
 157EXC_COMMON_BEGIN(system_reset_common)
 158	/*
 159	 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
 160	 * to recover, but nested NMI will notice in_nmi and not recover
 161	 * because of the use of the NMI stack. in_nmi reentrancy is tested in
 162	 * system_reset_exception.
 163	 */
 164	lhz	r10,PACA_IN_NMI(r13)
 165	addi	r10,r10,1
 166	sth	r10,PACA_IN_NMI(r13)
 167	li	r10,MSR_RI
 168	mtmsrd 	r10,1
 169
 170	mr	r10,r1
 171	ld	r1,PACA_NMI_EMERG_SP(r13)
 172	subi	r1,r1,INT_FRAME_SIZE
 173	EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
 174			system_reset, system_reset_exception,
 175			ADD_NVGPRS;ADD_RECONCILE_NMI)
 176
 177	/* This (and MCE) can be simplified with mtmsrd L=1 */
 178	/* Clear MSR_RI before setting SRR0 and SRR1. */
 179	li	r0,MSR_RI
 180	mfmsr	r9
 181	andc	r9,r9,r0
 182	mtmsrd	r9,1
 183
 184	/*
 185	 * MSR_RI is clear, now we can decrement paca->in_nmi.
 186	 */
 187	lhz	r10,PACA_IN_NMI(r13)
 188	subi	r10,r10,1
 189	sth	r10,PACA_IN_NMI(r13)
 190
 191	/*
 192	 * Restore soft mask settings.
 193	 */
 194	ld	r10,_DAR(r1)
 195	stb	r10,PACAIRQHAPPENED(r13)
 196	ld	r10,SOFTE(r1)
 197	stb	r10,PACAIRQSOFTMASK(r13)
 198
 199	/*
 200	 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
 201	 * Should share common bits...
 202	 */
 203
 204	/* Move original SRR0 and SRR1 into the respective regs */
 205	ld	r9,_MSR(r1)
 206	mtspr	SPRN_SRR1,r9
 207	ld	r3,_NIP(r1)
 208	mtspr	SPRN_SRR0,r3
 209	ld	r9,_CTR(r1)
 210	mtctr	r9
 211	ld	r9,_XER(r1)
 212	mtxer	r9
 213	ld	r9,_LINK(r1)
 214	mtlr	r9
 215	REST_GPR(0, r1)
 216	REST_8GPRS(2, r1)
 217	REST_GPR(10, r1)
 218	ld	r11,_CCR(r1)
 219	mtcr	r11
 220	REST_GPR(11, r1)
 221	REST_2GPRS(12, r1)
 222	/* restore original r1. */
 223	ld	r1,GPR1(r1)
 224	RFI_TO_USER_OR_KERNEL
 225
 226#ifdef CONFIG_PPC_PSERIES
 227/*
 228 * Vectors for the FWNMI option.  Share common code.
 229 */
 230TRAMP_REAL_BEGIN(system_reset_fwnmi)
 231	SET_SCRATCH0(r13)		/* save r13 */
 232	/* See comment at system_reset exception */
 233	EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
 234						EXC_STD, NOTEST, 0x100)
 235#endif /* CONFIG_PPC_PSERIES */
 236
 237
 238EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
 239	/* This is moved out of line as it can be patched by FW, but
 240	 * some code path might still want to branch into the original
 241	 * vector
 242	 */
 243	SET_SCRATCH0(r13)		/* save r13 */
 
 
 
 
 
 
 
 
 244	EXCEPTION_PROLOG_0(PACA_EXMC)
 245BEGIN_FTR_SECTION
 246	b	machine_check_powernv_early
 247FTR_SECTION_ELSE
 248	b	machine_check_pSeries_0
 249ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 250EXC_REAL_END(machine_check, 0x200, 0x100)
 251EXC_VIRT_NONE(0x4200, 0x100)
 252TRAMP_REAL_BEGIN(machine_check_powernv_early)
 253BEGIN_FTR_SECTION
 254	EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
 255	/*
 256	 * Register contents:
 257	 * R13		= PACA
 258	 * R9		= CR
 259	 * Original R9 to R13 is saved on PACA_EXMC
 260	 *
 261	 * Switch to mc_emergency stack and handle re-entrancy (we limit
 262	 * the nested MCE upto level 4 to avoid stack overflow).
 263	 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
 264	 *
 265	 * We use paca->in_mce to check whether this is the first entry or
 266	 * nested machine check. We increment paca->in_mce to track nested
 267	 * machine checks.
 268	 *
 269	 * If this is the first entry then set stack pointer to
 270	 * paca->mc_emergency_sp, otherwise r1 is already pointing to
 271	 * stack frame on mc_emergency stack.
 272	 *
 273	 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
 274	 * checkstop if we get another machine check exception before we do
 275	 * rfid with MSR_ME=1.
 276	 *
 277	 * This interrupt can wake directly from idle. If that is the case,
 278	 * the machine check is handled then the idle wakeup code is called
 279	 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
 280	 * is not applied in the early machine check code, which will cause
 281	 * bugs.
 282	 */
 283	mr	r11,r1			/* Save r1 */
 284	lhz	r10,PACA_IN_MCE(r13)
 285	cmpwi	r10,0			/* Are we in nested machine check */
 286	bne	0f			/* Yes, we are. */
 287	/* First machine check entry */
 288	ld	r1,PACAMCEMERGSP(r13)	/* Use MC emergency stack */
 2890:	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame */
 290	addi	r10,r10,1		/* increment paca->in_mce */
 291	sth	r10,PACA_IN_MCE(r13)
 292	/* Limit nested MCE to level 4 to avoid stack overflow */
 293	cmpwi	r10,MAX_MCE_DEPTH
 294	bgt	2f			/* Check if we hit limit of 4 */
 295	std	r11,GPR1(r1)		/* Save r1 on the stack. */
 296	std	r11,0(r1)		/* make stack chain pointer */
 297	mfspr	r11,SPRN_SRR0		/* Save SRR0 */
 298	std	r11,_NIP(r1)
 299	mfspr	r11,SPRN_SRR1		/* Save SRR1 */
 300	std	r11,_MSR(r1)
 301	mfspr	r11,SPRN_DAR		/* Save DAR */
 302	std	r11,_DAR(r1)
 303	mfspr	r11,SPRN_DSISR		/* Save DSISR */
 304	std	r11,_DSISR(r1)
 305	std	r9,_CCR(r1)		/* Save CR in stackframe */
 306	/* Save r9 through r13 from EXMC save area to stack frame. */
 307	EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
 308	mfmsr	r11			/* get MSR value */
 309	ori	r11,r11,MSR_ME		/* turn on ME bit */
 310	ori	r11,r11,MSR_RI		/* turn on RI bit */
 311	LOAD_HANDLER(r12, machine_check_handle_early)
 3121:	mtspr	SPRN_SRR0,r12
 313	mtspr	SPRN_SRR1,r11
 314	RFI_TO_KERNEL
 315	b	.	/* prevent speculative execution */
 3162:
 317	/* Stack overflow. Stay on emergency stack and panic.
 318	 * Keep the ME bit off while panic-ing, so that if we hit
 319	 * another machine check we checkstop.
 320	 */
 321	addi	r1,r1,INT_FRAME_SIZE	/* go back to previous stack frame */
 322	ld	r11,PACAKMSR(r13)
 323	LOAD_HANDLER(r12, unrecover_mce)
 324	li	r10,MSR_ME
 325	andc	r11,r11,r10		/* Turn off MSR_ME */
 326	b	1b
 327	b	.	/* prevent speculative execution */
 328END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 329
 330TRAMP_REAL_BEGIN(machine_check_pSeries)
 331	.globl machine_check_fwnmi
 332machine_check_fwnmi:
 333	SET_SCRATCH0(r13)		/* save r13 */
 334	EXCEPTION_PROLOG_0(PACA_EXMC)
 335machine_check_pSeries_0:
 336	EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
 337	/*
 338	 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
 339	 * nested machine check corrupts it. machine_check_common enables
 340	 * MSR_RI.
 
 341	 */
 342	EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
 
 
 
 
 
 
 
 
 343
 344TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
 345
 346EXC_COMMON_BEGIN(machine_check_common)
 347	/*
 348	 * Machine check is different because we use a different
 349	 * save area: PACA_EXMC instead of PACA_EXGEN.
 350	 */
 351	mfspr	r10,SPRN_DAR
 352	std	r10,PACA_EXMC+EX_DAR(r13)
 353	mfspr	r10,SPRN_DSISR
 354	stw	r10,PACA_EXMC+EX_DSISR(r13)
 355	EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 356	FINISH_NAP
 357	RECONCILE_IRQ_STATE(r10, r11)
 358	ld	r3,PACA_EXMC+EX_DAR(r13)
 359	lwz	r4,PACA_EXMC+EX_DSISR(r13)
 360	/* Enable MSR_RI when finished with PACA_EXMC */
 361	li	r10,MSR_RI
 362	mtmsrd 	r10,1
 363	std	r3,_DAR(r1)
 364	std	r4,_DSISR(r1)
 365	bl	save_nvgprs
 366	addi	r3,r1,STACK_FRAME_OVERHEAD
 367	bl	machine_check_exception
 368	b	ret_from_except
 369
 370#define MACHINE_CHECK_HANDLER_WINDUP			\
 371	/* Clear MSR_RI before setting SRR0 and SRR1. */\
 372	li	r0,MSR_RI;				\
 373	mfmsr	r9;		/* get MSR value */	\
 374	andc	r9,r9,r0;				\
 375	mtmsrd	r9,1;		/* Clear MSR_RI */	\
 376	/* Move original SRR0 and SRR1 into the respective regs */	\
 377	ld	r9,_MSR(r1);				\
 378	mtspr	SPRN_SRR1,r9;				\
 379	ld	r3,_NIP(r1);				\
 380	mtspr	SPRN_SRR0,r3;				\
 381	ld	r9,_CTR(r1);				\
 382	mtctr	r9;					\
 383	ld	r9,_XER(r1);				\
 384	mtxer	r9;					\
 385	ld	r9,_LINK(r1);				\
 386	mtlr	r9;					\
 387	REST_GPR(0, r1);				\
 388	REST_8GPRS(2, r1);				\
 389	REST_GPR(10, r1);				\
 390	ld	r11,_CCR(r1);				\
 391	mtcr	r11;					\
 392	/* Decrement paca->in_mce. */			\
 393	lhz	r12,PACA_IN_MCE(r13);			\
 394	subi	r12,r12,1;				\
 395	sth	r12,PACA_IN_MCE(r13);			\
 396	REST_GPR(11, r1);				\
 397	REST_2GPRS(12, r1);				\
 398	/* restore original r1. */			\
 399	ld	r1,GPR1(r1)
 400
 401#ifdef CONFIG_PPC_P7_NAP
 402/*
 403 * This is an idle wakeup. Low level machine check has already been
 404 * done. Queue the event then call the idle code to do the wake up.
 405 */
 406EXC_COMMON_BEGIN(machine_check_idle_common)
 407	bl	machine_check_queue_event
 408
 409	/*
 410	 * We have not used any non-volatile GPRs here, and as a rule
 411	 * most exception code including machine check does not.
 412	 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
 413	 * wakeup will restore volatile registers.
 414	 *
 415	 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
 416	 *
 417	 * Then decrement MCE nesting after finishing with the stack.
 418	 */
 419	ld	r3,_MSR(r1)
 420
 421	lhz	r11,PACA_IN_MCE(r13)
 422	subi	r11,r11,1
 423	sth	r11,PACA_IN_MCE(r13)
 424
 425	/* Turn off the RI bit because SRR1 is used by idle wakeup code. */
 426	/* Recoverability could be improved by reducing the use of SRR1. */
 427	li	r11,0
 428	mtmsrd	r11,1
 429
 430	b	pnv_powersave_wakeup_mce
 431#endif
 432	/*
 433	 * Handle machine check early in real mode. We come here with
 434	 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
 435	 */
 436EXC_COMMON_BEGIN(machine_check_handle_early)
 437	std	r0,GPR0(r1)	/* Save r0 */
 438	EXCEPTION_PROLOG_COMMON_3(0x200)
 439	bl	save_nvgprs
 440	addi	r3,r1,STACK_FRAME_OVERHEAD
 441	bl	machine_check_early
 442	std	r3,RESULT(r1)	/* Save result */
 443	ld	r12,_MSR(r1)
 444
 445#ifdef	CONFIG_PPC_P7_NAP
 446	/*
 447	 * Check if thread was in power saving mode. We come here when any
 448	 * of the following is true:
 449	 * a. thread wasn't in power saving mode
 450	 * b. thread was in power saving mode with no state loss,
 451	 *    supervisor state loss or hypervisor state loss.
 452	 *
 453	 * Go back to nap/sleep/winkle mode again if (b) is true.
 454	 */
 455	BEGIN_FTR_SECTION
 456	rlwinm.	r11,r12,47-31,30,31
 457	bne	machine_check_idle_common
 458	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 459#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 460
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 461	/*
 462	 * Check if we are coming from hypervisor userspace. If yes then we
 463	 * continue in host kernel in V mode to deliver the MC event.
 464	 */
 465	rldicl.	r11,r12,4,63		/* See if MC hit while in HV mode. */
 466	beq	5f
 467	andi.	r11,r12,MSR_PR		/* See if coming from user. */
 468	bne	9f			/* continue in V mode if we are. */
 469
 4705:
 471#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 472	/*
 473	 * We are coming from kernel context. Check if we are coming from
 474	 * guest. if yes, then we can continue. We will fall through
 475	 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
 476	 */
 477	lbz	r11,HSTATE_IN_GUEST(r13)
 478	cmpwi	r11,0			/* Check if coming from guest */
 479	bne	9f			/* continue if we are. */
 480#endif
 481	/*
 482	 * At this point we are not sure about what context we come from.
 483	 * Queue up the MCE event and return from the interrupt.
 484	 * But before that, check if this is an un-recoverable exception.
 485	 * If yes, then stay on emergency stack and panic.
 486	 */
 487	andi.	r11,r12,MSR_RI
 488	bne	2f
 4891:	mfspr	r11,SPRN_SRR0
 490	LOAD_HANDLER(r10,unrecover_mce)
 491	mtspr	SPRN_SRR0,r10
 492	ld	r10,PACAKMSR(r13)
 493	/*
 494	 * We are going down. But there are chances that we might get hit by
 495	 * another MCE during panic path and we may run into unstable state
 496	 * with no way out. Hence, turn ME bit off while going down, so that
 497	 * when another MCE is hit during panic path, system will checkstop
 498	 * and hypervisor will get restarted cleanly by SP.
 499	 */
 500	li	r3,MSR_ME
 501	andc	r10,r10,r3		/* Turn off MSR_ME */
 502	mtspr	SPRN_SRR1,r10
 503	RFI_TO_KERNEL
 504	b	.
 5052:
 506	/*
 507	 * Check if we have successfully handled/recovered from error, if not
 508	 * then stay on emergency stack and panic.
 509	 */
 510	ld	r3,RESULT(r1)	/* Load result */
 511	cmpdi	r3,0		/* see if we handled MCE successfully */
 512
 513	beq	1b		/* if !handled then panic */
 514	/*
 515	 * Return from MC interrupt.
 516	 * Queue up the MCE event so that we can log it later, while
 517	 * returning from kernel or opal call.
 518	 */
 519	bl	machine_check_queue_event
 520	MACHINE_CHECK_HANDLER_WINDUP
 521	RFI_TO_USER_OR_KERNEL
 5229:
 523	/* Deliver the machine check to host kernel in V mode. */
 524	MACHINE_CHECK_HANDLER_WINDUP
 525	b	machine_check_pSeries
 526
 527EXC_COMMON_BEGIN(unrecover_mce)
 528	/* Invoke machine_check_exception to print MCE event and panic. */
 529	addi	r3,r1,STACK_FRAME_OVERHEAD
 530	bl	machine_check_exception
 531	/*
 532	 * We will not reach here. Even if we did, there is no way out. Call
 533	 * unrecoverable_exception and die.
 534	 */
 5351:	addi	r3,r1,STACK_FRAME_OVERHEAD
 536	bl	unrecoverable_exception
 537	b	1b
 538
 539
 540EXC_REAL(data_access, 0x300, 0x80)
 541EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
 542TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
 543
 544EXC_COMMON_BEGIN(data_access_common)
 545	/*
 546	 * Here r13 points to the paca, r9 contains the saved CR,
 547	 * SRR0 and SRR1 are saved in r11 and r12,
 548	 * r9 - r13 are saved in paca->exgen.
 549	 */
 550	mfspr	r10,SPRN_DAR
 551	std	r10,PACA_EXGEN+EX_DAR(r13)
 552	mfspr	r10,SPRN_DSISR
 553	stw	r10,PACA_EXGEN+EX_DSISR(r13)
 554	EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
 555	RECONCILE_IRQ_STATE(r10, r11)
 556	ld	r12,_MSR(r1)
 557	ld	r3,PACA_EXGEN+EX_DAR(r13)
 558	lwz	r4,PACA_EXGEN+EX_DSISR(r13)
 559	li	r5,0x300
 560	std	r3,_DAR(r1)
 561	std	r4,_DSISR(r1)
 562BEGIN_MMU_FTR_SECTION
 563	b	do_hash_page		/* Try to handle as hpte fault */
 564MMU_FTR_SECTION_ELSE
 565	b	handle_page_fault
 566ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 567
 568
 569EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
 570	SET_SCRATCH0(r13)
 571	EXCEPTION_PROLOG_0(PACA_EXSLB)
 572	EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
 573	mr	r12,r3	/* save r3 */
 574	mfspr	r3,SPRN_DAR
 575	mfspr	r11,SPRN_SRR1
 576	crset	4*cr6+eq
 577	BRANCH_TO_COMMON(r10, slb_miss_common)
 578EXC_REAL_END(data_access_slb, 0x380, 0x80)
 
 
 
 
 
 
 
 
 
 
 
 
 579
 580EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
 581	SET_SCRATCH0(r13)
 582	EXCEPTION_PROLOG_0(PACA_EXSLB)
 583	EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
 584	mr	r12,r3	/* save r3 */
 585	mfspr	r3,SPRN_DAR
 586	mfspr	r11,SPRN_SRR1
 587	crset	4*cr6+eq
 588	BRANCH_TO_COMMON(r10, slb_miss_common)
 589EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
 
 
 
 
 
 
 
 
 
 
 
 
 590TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
 591
 592
 593EXC_REAL(instruction_access, 0x400, 0x80)
 594EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
 595TRAMP_KVM(PACA_EXGEN, 0x400)
 596
 597EXC_COMMON_BEGIN(instruction_access_common)
 598	EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
 599	RECONCILE_IRQ_STATE(r10, r11)
 600	ld	r12,_MSR(r1)
 601	ld	r3,_NIP(r1)
 602	andis.	r4,r12,DSISR_SRR1_MATCH_64S@h
 603	li	r5,0x400
 604	std	r3,_DAR(r1)
 605	std	r4,_DSISR(r1)
 606BEGIN_MMU_FTR_SECTION
 607	b	do_hash_page		/* Try to handle as hpte fault */
 608MMU_FTR_SECTION_ELSE
 609	b	handle_page_fault
 610ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 611
 612
 613EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
 614	SET_SCRATCH0(r13)
 615	EXCEPTION_PROLOG_0(PACA_EXSLB)
 616	EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
 617	mr	r12,r3	/* save r3 */
 618	mfspr	r3,SPRN_SRR0		/* SRR0 is faulting address */
 619	mfspr	r11,SPRN_SRR1
 620	crclr	4*cr6+eq
 621	BRANCH_TO_COMMON(r10, slb_miss_common)
 622EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
 
 
 
 
 
 
 
 623
 624EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
 625	SET_SCRATCH0(r13)
 626	EXCEPTION_PROLOG_0(PACA_EXSLB)
 627	EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
 628	mr	r12,r3	/* save r3 */
 629	mfspr	r3,SPRN_SRR0		/* SRR0 is faulting address */
 630	mfspr	r11,SPRN_SRR1
 631	crclr	4*cr6+eq
 632	BRANCH_TO_COMMON(r10, slb_miss_common)
 633EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
 
 
 
 
 
 
 
 634TRAMP_KVM(PACA_EXSLB, 0x480)
 635
 636
 637/*
 638 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
 639 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
 640 */
 641EXC_COMMON_BEGIN(slb_miss_common)
 642	/*
 643	 * r13 points to the PACA, r9 contains the saved CR,
 644	 * r12 contains the saved r3,
 645	 * r11 contain the saved SRR1, SRR0 is still ready for return
 646	 * r3 has the faulting address
 647	 * r9 - r13 are saved in paca->exslb.
 
 648 	 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
 649	 * We assume we aren't going to take any exceptions during this
 650	 * procedure.
 651	 */
 652	mflr	r10
 
 
 
 
 653	stw	r9,PACA_EXSLB+EX_CCR(r13)	/* save CR in exc. frame */
 654	std	r10,PACA_EXSLB+EX_LR(r13)	/* save LR */
 655
 656	andi.	r9,r11,MSR_PR	// Check for exception from userspace
 657	cmpdi	cr4,r9,MSR_PR	// And save the result in CR4 for later
 658
 659	/*
 660	 * Test MSR_RI before calling slb_allocate_realmode, because the
 661	 * MSR in r11 gets clobbered. However we still want to allocate
 662	 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
 663	 * recursive SLB faults. So use cr5 for this, which is preserved.
 664	 */
 665	andi.	r11,r11,MSR_RI	/* check for unrecoverable exception */
 666	cmpdi	cr5,r11,MSR_RI
 667
 668	crset	4*cr0+eq
 669#ifdef CONFIG_PPC_BOOK3S_64
 670BEGIN_MMU_FTR_SECTION
 671	bl	slb_allocate
 672END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 673#endif
 674
 675	ld	r10,PACA_EXSLB+EX_LR(r13)
 
 676	lwz	r9,PACA_EXSLB+EX_CCR(r13)	/* get saved CR */
 677	mtlr	r10
 678
 679	/*
 680	 * Large address, check whether we have to allocate new contexts.
 681	 */
 682	beq-	8f
 683
 684	bne-	cr5,2f		/* if unrecoverable exception, oops */
 
 685
 686	/* All done -- return from exception. */
 687
 688	bne	cr4,1f		/* returning to kernel */
 689
 690	mtcrf	0x80,r9
 691	mtcrf	0x08,r9		/* MSR[PR] indication is in cr4 */
 692	mtcrf	0x04,r9		/* MSR[RI] indication is in cr5 */
 693	mtcrf	0x02,r9		/* I/D indication is in cr6 */
 694	mtcrf	0x01,r9		/* slb_allocate uses cr0 and cr7 */
 695
 696	RESTORE_CTR(r9, PACA_EXSLB)
 697	RESTORE_PPR_PACA(PACA_EXSLB, r9)
 698	mr	r3,r12
 699	ld	r9,PACA_EXSLB+EX_R9(r13)
 700	ld	r10,PACA_EXSLB+EX_R10(r13)
 701	ld	r11,PACA_EXSLB+EX_R11(r13)
 702	ld	r12,PACA_EXSLB+EX_R12(r13)
 703	ld	r13,PACA_EXSLB+EX_R13(r13)
 704	RFI_TO_USER
 705	b	.	/* prevent speculative execution */
 7061:
 707	mtcrf	0x80,r9
 708	mtcrf	0x08,r9		/* MSR[PR] indication is in cr4 */
 709	mtcrf	0x04,r9		/* MSR[RI] indication is in cr5 */
 710	mtcrf	0x02,r9		/* I/D indication is in cr6 */
 711	mtcrf	0x01,r9		/* slb_allocate uses cr0 and cr7 */
 
 712
 713	RESTORE_CTR(r9, PACA_EXSLB)
 714	RESTORE_PPR_PACA(PACA_EXSLB, r9)
 715	mr	r3,r12
 716	ld	r9,PACA_EXSLB+EX_R9(r13)
 717	ld	r10,PACA_EXSLB+EX_R10(r13)
 718	ld	r11,PACA_EXSLB+EX_R11(r13)
 719	ld	r12,PACA_EXSLB+EX_R12(r13)
 720	ld	r13,PACA_EXSLB+EX_R13(r13)
 721	RFI_TO_KERNEL
 722	b	.	/* prevent speculative execution */
 723
 724
 7252:	std     r3,PACA_EXSLB+EX_DAR(r13)
 726	mr	r3,r12
 727	mfspr	r11,SPRN_SRR0
 728	mfspr	r12,SPRN_SRR1
 729	LOAD_HANDLER(r10,unrecov_slb)
 730	mtspr	SPRN_SRR0,r10
 731	ld	r10,PACAKMSR(r13)
 732	mtspr	SPRN_SRR1,r10
 733	RFI_TO_KERNEL
 734	b	.
 735
 7368:	std     r3,PACA_EXSLB+EX_DAR(r13)
 737	mr	r3,r12
 738	mfspr	r11,SPRN_SRR0
 739	mfspr	r12,SPRN_SRR1
 740	LOAD_HANDLER(r10, large_addr_slb)
 741	mtspr	SPRN_SRR0,r10
 742	ld	r10,PACAKMSR(r13)
 743	mtspr	SPRN_SRR1,r10
 744	RFI_TO_KERNEL
 745	b	.
 746
 747EXC_COMMON_BEGIN(unrecov_slb)
 748	EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
 749	RECONCILE_IRQ_STATE(r10, r11)
 750	bl	save_nvgprs
 7511:	addi	r3,r1,STACK_FRAME_OVERHEAD
 752	bl	unrecoverable_exception
 753	b	1b
 754
 755EXC_COMMON_BEGIN(large_addr_slb)
 756	EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
 757	RECONCILE_IRQ_STATE(r10, r11)
 758	ld	r3, PACA_EXSLB+EX_DAR(r13)
 759	std	r3, _DAR(r1)
 760	beq	cr6, 2f
 761	li	r10, 0x481		/* fix trap number for I-SLB miss */
 762	std	r10, _TRAP(r1)
 7632:	bl	save_nvgprs
 764	addi	r3, r1, STACK_FRAME_OVERHEAD
 765	bl	slb_miss_large_addr
 766	b	ret_from_except
 767
 768EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
 769	.globl hardware_interrupt_hv;
 770hardware_interrupt_hv:
 771	BEGIN_FTR_SECTION
 772		_MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 773					    EXC_HV, SOFTEN_TEST_HV,
 774					    IRQS_DISABLED)
 
 775	FTR_SECTION_ELSE
 776		_MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 777					    EXC_STD, SOFTEN_TEST_PR,
 778					    IRQS_DISABLED)
 
 779	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 780EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
 781
 782EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
 783	.globl hardware_interrupt_relon_hv;
 784hardware_interrupt_relon_hv:
 785	BEGIN_FTR_SECTION
 786		_MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 787						  EXC_HV, SOFTEN_TEST_HV,
 788						  IRQS_DISABLED)
 789	FTR_SECTION_ELSE
 790		_MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 791						  EXC_STD, SOFTEN_TEST_PR,
 792						  IRQS_DISABLED)
 793	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 794EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
 795
 796TRAMP_KVM(PACA_EXGEN, 0x500)
 797TRAMP_KVM_HV(PACA_EXGEN, 0x500)
 798EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
 799
 800
 801EXC_REAL(alignment, 0x600, 0x100)
 802EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
 803TRAMP_KVM(PACA_EXGEN, 0x600)
 804EXC_COMMON_BEGIN(alignment_common)
 805	mfspr	r10,SPRN_DAR
 806	std	r10,PACA_EXGEN+EX_DAR(r13)
 807	mfspr	r10,SPRN_DSISR
 808	stw	r10,PACA_EXGEN+EX_DSISR(r13)
 809	EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
 810	ld	r3,PACA_EXGEN+EX_DAR(r13)
 811	lwz	r4,PACA_EXGEN+EX_DSISR(r13)
 812	std	r3,_DAR(r1)
 813	std	r4,_DSISR(r1)
 814	bl	save_nvgprs
 815	RECONCILE_IRQ_STATE(r10, r11)
 816	addi	r3,r1,STACK_FRAME_OVERHEAD
 817	bl	alignment_exception
 818	b	ret_from_except
 819
 820
 821EXC_REAL(program_check, 0x700, 0x100)
 822EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
 823TRAMP_KVM(PACA_EXGEN, 0x700)
 824EXC_COMMON_BEGIN(program_check_common)
 825	/*
 826	 * It's possible to receive a TM Bad Thing type program check with
 827	 * userspace register values (in particular r1), but with SRR1 reporting
 828	 * that we came from the kernel. Normally that would confuse the bad
 829	 * stack logic, and we would report a bad kernel stack pointer. Instead
 830	 * we switch to the emergency stack if we're taking a TM Bad Thing from
 831	 * the kernel.
 832	 */
 833	li	r10,MSR_PR		/* Build a mask of MSR_PR ..	*/
 834	oris	r10,r10,0x200000@h	/* .. and SRR1_PROGTM		*/
 835	and	r10,r10,r12		/* Mask SRR1 with that.		*/
 836	srdi	r10,r10,8		/* Shift it so we can compare	*/
 837	cmpldi	r10,(0x200000 >> 8)	/* .. with an immediate.	*/
 838	bne 1f				/* If != go to normal path.	*/
 839
 840	/* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack	*/
 841	andi.	r10,r12,MSR_PR;		/* Set CR0 correctly for label	*/
 842					/* 3 in EXCEPTION_PROLOG_COMMON	*/
 843	mr	r10,r1			/* Save r1			*/
 844	ld	r1,PACAEMERGSP(r13)	/* Use emergency stack		*/
 845	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame		*/
 846	b 3f				/* Jump into the macro !!	*/
 8471:	EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
 848	bl	save_nvgprs
 849	RECONCILE_IRQ_STATE(r10, r11)
 850	addi	r3,r1,STACK_FRAME_OVERHEAD
 851	bl	program_check_exception
 852	b	ret_from_except
 853
 854
 855EXC_REAL(fp_unavailable, 0x800, 0x100)
 856EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
 857TRAMP_KVM(PACA_EXGEN, 0x800)
 858EXC_COMMON_BEGIN(fp_unavailable_common)
 859	EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
 860	bne	1f			/* if from user, just load it up */
 861	bl	save_nvgprs
 862	RECONCILE_IRQ_STATE(r10, r11)
 863	addi	r3,r1,STACK_FRAME_OVERHEAD
 864	bl	kernel_fp_unavailable_exception
 865	BUG_OPCODE
 8661:
 867#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 868BEGIN_FTR_SECTION
 869	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
 870	 * transaction), go do TM stuff
 871	 */
 872	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
 873	bne-	2f
 874END_FTR_SECTION_IFSET(CPU_FTR_TM)
 875#endif
 876	bl	load_up_fpu
 877	b	fast_exception_return
 878#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 8792:	/* User process was in a transaction */
 880	bl	save_nvgprs
 881	RECONCILE_IRQ_STATE(r10, r11)
 882	addi	r3,r1,STACK_FRAME_OVERHEAD
 883	bl	fp_unavailable_tm
 884	b	ret_from_except
 885#endif
 886
 887
 888EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
 889EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
 890TRAMP_KVM(PACA_EXGEN, 0x900)
 891EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
 892
 893
 894EXC_REAL_HV(hdecrementer, 0x980, 0x80)
 895EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
 896TRAMP_KVM_HV(PACA_EXGEN, 0x980)
 897EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
 898
 899
 900EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
 901EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
 902TRAMP_KVM(PACA_EXGEN, 0xa00)
 903#ifdef CONFIG_PPC_DOORBELL
 904EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
 905#else
 906EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
 907#endif
 908
 909
 910EXC_REAL(trap_0b, 0xb00, 0x100)
 911EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
 912TRAMP_KVM(PACA_EXGEN, 0xb00)
 913EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
 914
 915/*
 916 * system call / hypercall (0xc00, 0x4c00)
 917 *
 918 * The system call exception is invoked with "sc 0" and does not alter HV bit.
 919 * There is support for kernel code to invoke system calls but there are no
 920 * in-tree users.
 921 *
 922 * The hypercall is invoked with "sc 1" and sets HV=1.
 923 *
 924 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
 925 * 0x4c00 virtual mode.
 926 *
 927 * Call convention:
 928 *
 929 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
 930 *
 931 * For hypercalls, the register convention is as follows:
 932 * r0 volatile
 933 * r1-2 nonvolatile
 934 * r3 volatile parameter and return value for status
 935 * r4-r10 volatile input and output value
 936 * r11 volatile hypercall number and output value
 937 * r12 volatile input and output value
 938 * r13-r31 nonvolatile
 939 * LR nonvolatile
 940 * CTR volatile
 941 * XER volatile
 942 * CR0-1 CR5-7 volatile
 943 * CR2-4 nonvolatile
 944 * Other registers nonvolatile
 945 *
 946 * The intersection of volatile registers that don't contain possible
 947 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
 948 * without saving, though xer is not a good idea to use, as hardware may
 949 * interpret some bits so it may be costly to change them.
 950 */
 951#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 952	/*
 953	 * There is a little bit of juggling to get syscall and hcall
 954	 * working well. Save r13 in ctr to avoid using SPRG scratch
 955	 * register.
 956	 *
 957	 * Userspace syscalls have already saved the PPR, hcalls must save
 958	 * it before setting HMT_MEDIUM.
 959	 */
 960#define SYSCALL_KVMTEST							\
 961	mtctr	r13;							\
 962	GET_PACA(r13);							\
 963	std	r10,PACA_EXGEN+EX_R10(r13);				\
 964	INTERRUPT_TO_KERNEL;						\
 965	KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
 966	HMT_MEDIUM;							\
 967	mfctr	r9;
 968
 969#else
 970#define SYSCALL_KVMTEST							\
 971	HMT_MEDIUM;							\
 972	mr	r9,r13;							\
 973	GET_PACA(r13);							\
 974	INTERRUPT_TO_KERNEL;
 975#endif
 976	
 977#define LOAD_SYSCALL_HANDLER(reg)					\
 978	__LOAD_HANDLER(reg, system_call_common)
 979
 980/*
 981 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
 982 * and HMT_MEDIUM.
 983 */
 984#define SYSCALL_REAL	 					\
 
 
 
 985	mfspr	r11,SPRN_SRR0 ;					\
 
 
 
 986	mfspr	r12,SPRN_SRR1 ;					\
 987	LOAD_SYSCALL_HANDLER(r10) ; 				\
 988	mtspr	SPRN_SRR0,r10 ; 				\
 989	ld	r10,PACAKMSR(r13) ;				\
 990	mtspr	SPRN_SRR1,r10 ; 				\
 991	RFI_TO_KERNEL ;						\
 992	b	. ;	/* prevent speculative execution */
 993
 994#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
 995#define SYSCALL_FASTENDIAN_TEST					\
 996BEGIN_FTR_SECTION						\
 997	cmpdi	r0,0x1ebe ; 					\
 998	beq-	1f ;						\
 999END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)				\
1000
1001#define SYSCALL_FASTENDIAN					\
1002	/* Fast LE/BE switch system call */			\
10031:	mfspr	r12,SPRN_SRR1 ;					\
1004	xori	r12,r12,MSR_LE ;				\
1005	mtspr	SPRN_SRR1,r12 ;					\
1006	mr	r13,r9 ;					\
1007	RFI_TO_USER ;	/* return to userspace */		\
1008	b	. ;	/* prevent speculative execution */
1009#else
1010#define SYSCALL_FASTENDIAN_TEST
1011#define SYSCALL_FASTENDIAN
1012#endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */
1013
1014#if defined(CONFIG_RELOCATABLE)
1015	/*
1016	 * We can't branch directly so we do it via the CTR which
1017	 * is volatile across system calls.
1018	 */
1019#define SYSCALL_VIRT						\
1020	LOAD_SYSCALL_HANDLER(r10) ;				\
1021	mtctr	r10 ;						\
1022	mfspr	r11,SPRN_SRR0 ;					\
1023	mfspr	r12,SPRN_SRR1 ;					\
1024	li	r10,MSR_RI ;					\
1025	mtmsrd 	r10,1 ;						\
1026	bctr ;
1027#else
1028	/* We can branch directly */
1029#define SYSCALL_VIRT						\
1030	mfspr	r11,SPRN_SRR0 ;					\
1031	mfspr	r12,SPRN_SRR1 ;					\
1032	li	r10,MSR_RI ;					\
1033	mtmsrd 	r10,1 ;			/* Set RI (EE=0) */	\
1034	b	system_call_common ;
1035#endif
1036
1037EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1038	SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1039	SYSCALL_FASTENDIAN_TEST
1040	SYSCALL_REAL
1041	SYSCALL_FASTENDIAN
1042EXC_REAL_END(system_call, 0xc00, 0x100)
1043
1044EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1045	SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1046	SYSCALL_FASTENDIAN_TEST
1047	SYSCALL_VIRT
1048	SYSCALL_FASTENDIAN
1049EXC_VIRT_END(system_call, 0x4c00, 0x100)
1050
1051#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1052	/*
1053	 * This is a hcall, so register convention is as above, with these
1054	 * differences:
1055	 * r13 = PACA
1056	 * ctr = orig r13
1057	 * orig r10 saved in PACA
1058	 */
1059TRAMP_KVM_BEGIN(do_kvm_0xc00)
1060	 /*
1061	  * Save the PPR (on systems that support it) before changing to
1062	  * HMT_MEDIUM. That allows the KVM code to save that value into the
1063	  * guest state (it is the guest's PPR value).
 
 
1064	  */
1065	OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1066	HMT_MEDIUM
1067	OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1068	mfctr	r10
1069	SET_SCRATCH0(r10)
1070	std	r9,PACA_EXGEN+EX_R9(r13)
 
 
 
 
1071	mfcr	r9
1072	KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
 
 
 
1073#endif
 
 
 
 
1074
 
 
 
 
 
 
 
 
1075
1076EXC_REAL(single_step, 0xd00, 0x100)
1077EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
 
1078TRAMP_KVM(PACA_EXGEN, 0xd00)
1079EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1080
1081EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1082EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1083TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1084EXC_COMMON_BEGIN(h_data_storage_common)
1085	mfspr   r10,SPRN_HDAR
1086	std     r10,PACA_EXGEN+EX_DAR(r13)
1087	mfspr   r10,SPRN_HDSISR
1088	stw     r10,PACA_EXGEN+EX_DSISR(r13)
1089	EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1090	bl      save_nvgprs
1091	RECONCILE_IRQ_STATE(r10, r11)
1092	addi    r3,r1,STACK_FRAME_OVERHEAD
1093	bl      unknown_exception
1094	b       ret_from_except
1095
1096
1097EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1098EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1099TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1100EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1101
1102
1103EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1104EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1105TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1106EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1107
1108
1109/*
1110 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1111 * first, and then eventaully from there to the trampoline to get into virtual
1112 * mode.
1113 */
1114__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1115__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1116EXC_VIRT_NONE(0x4e60, 0x20)
1117TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1118TRAMP_REAL_BEGIN(hmi_exception_early)
1119	EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1120	mr	r10,r1			/* Save r1 */
1121	ld	r1,PACAEMERGSP(r13)	/* Use emergency stack for realmode */
1122	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame		*/
 
1123	mfspr	r11,SPRN_HSRR0		/* Save HSRR0 */
1124	mfspr	r12,SPRN_HSRR1		/* Save HSRR1 */
1125	EXCEPTION_PROLOG_COMMON_1()
 
 
 
 
1126	EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1127	EXCEPTION_PROLOG_COMMON_3(0xe60)
1128	addi	r3,r1,STACK_FRAME_OVERHEAD
1129	BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1130	cmpdi	cr0,r3,0
1131
1132	/* Windup the stack. */
1133	/* Move original HSRR0 and HSRR1 into the respective regs */
1134	ld	r9,_MSR(r1)
1135	mtspr	SPRN_HSRR1,r9
1136	ld	r3,_NIP(r1)
1137	mtspr	SPRN_HSRR0,r3
1138	ld	r9,_CTR(r1)
1139	mtctr	r9
1140	ld	r9,_XER(r1)
1141	mtxer	r9
1142	ld	r9,_LINK(r1)
1143	mtlr	r9
1144	REST_GPR(0, r1)
1145	REST_8GPRS(2, r1)
1146	REST_GPR(10, r1)
1147	ld	r11,_CCR(r1)
1148	REST_2GPRS(12, r1)
1149	bne	1f
1150	mtcr	r11
1151	REST_GPR(11, r1)
1152	ld	r1,GPR1(r1)
1153	HRFI_TO_USER_OR_KERNEL
1154
11551:	mtcr	r11
1156	REST_GPR(11, r1)
1157	ld	r1,GPR1(r1)
1158
1159	/*
1160	 * Go to virtual mode and pull the HMI event information from
1161	 * firmware.
1162	 */
1163	.globl hmi_exception_after_realmode
1164hmi_exception_after_realmode:
1165	SET_SCRATCH0(r13)
1166	EXCEPTION_PROLOG_0(PACA_EXGEN)
1167	b	tramp_real_hmi_exception
1168
1169EXC_COMMON_BEGIN(hmi_exception_common)
1170EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception,
1171        ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON)
1172
1173EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1174EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1175TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1176#ifdef CONFIG_PPC_DOORBELL
1177EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1178#else
1179EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1180#endif
1181
1182
1183EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1184EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1185TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1186EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1187
1188
1189EXC_REAL_NONE(0xec0, 0x20)
1190EXC_VIRT_NONE(0x4ec0, 0x20)
1191EXC_REAL_NONE(0xee0, 0x20)
1192EXC_VIRT_NONE(0x4ee0, 0x20)
1193
1194
1195EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1196EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1197TRAMP_KVM(PACA_EXGEN, 0xf00)
1198EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1199
1200
1201EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1202EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1203TRAMP_KVM(PACA_EXGEN, 0xf20)
1204EXC_COMMON_BEGIN(altivec_unavailable_common)
1205	EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1206#ifdef CONFIG_ALTIVEC
1207BEGIN_FTR_SECTION
1208	beq	1f
1209#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1210  BEGIN_FTR_SECTION_NESTED(69)
1211	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1212	 * transaction), go do TM stuff
1213	 */
1214	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
1215	bne-	2f
1216  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1217#endif
1218	bl	load_up_altivec
1219	b	fast_exception_return
1220#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
12212:	/* User process was in a transaction */
1222	bl	save_nvgprs
1223	RECONCILE_IRQ_STATE(r10, r11)
1224	addi	r3,r1,STACK_FRAME_OVERHEAD
1225	bl	altivec_unavailable_tm
1226	b	ret_from_except
1227#endif
12281:
1229END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1230#endif
1231	bl	save_nvgprs
1232	RECONCILE_IRQ_STATE(r10, r11)
1233	addi	r3,r1,STACK_FRAME_OVERHEAD
1234	bl	altivec_unavailable_exception
1235	b	ret_from_except
1236
1237
1238EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1239EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1240TRAMP_KVM(PACA_EXGEN, 0xf40)
1241EXC_COMMON_BEGIN(vsx_unavailable_common)
1242	EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1243#ifdef CONFIG_VSX
1244BEGIN_FTR_SECTION
1245	beq	1f
1246#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1247  BEGIN_FTR_SECTION_NESTED(69)
1248	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1249	 * transaction), go do TM stuff
1250	 */
1251	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
1252	bne-	2f
1253  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1254#endif
1255	b	load_up_vsx
1256#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
12572:	/* User process was in a transaction */
1258	bl	save_nvgprs
1259	RECONCILE_IRQ_STATE(r10, r11)
1260	addi	r3,r1,STACK_FRAME_OVERHEAD
1261	bl	vsx_unavailable_tm
1262	b	ret_from_except
1263#endif
12641:
1265END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1266#endif
1267	bl	save_nvgprs
1268	RECONCILE_IRQ_STATE(r10, r11)
1269	addi	r3,r1,STACK_FRAME_OVERHEAD
1270	bl	vsx_unavailable_exception
1271	b	ret_from_except
1272
1273
1274EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1275EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1276TRAMP_KVM(PACA_EXGEN, 0xf60)
1277EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1278
1279
1280EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1281EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1282TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1283EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1284
1285
1286EXC_REAL_NONE(0xfa0, 0x20)
1287EXC_VIRT_NONE(0x4fa0, 0x20)
1288EXC_REAL_NONE(0xfc0, 0x20)
1289EXC_VIRT_NONE(0x4fc0, 0x20)
1290EXC_REAL_NONE(0xfe0, 0x20)
1291EXC_VIRT_NONE(0x4fe0, 0x20)
1292
1293EXC_REAL_NONE(0x1000, 0x100)
1294EXC_VIRT_NONE(0x5000, 0x100)
1295EXC_REAL_NONE(0x1100, 0x100)
1296EXC_VIRT_NONE(0x5100, 0x100)
1297
1298#ifdef CONFIG_CBE_RAS
1299EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1300EXC_VIRT_NONE(0x5200, 0x100)
1301TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1302EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1303#else /* CONFIG_CBE_RAS */
1304EXC_REAL_NONE(0x1200, 0x100)
1305EXC_VIRT_NONE(0x5200, 0x100)
1306#endif
1307
1308
1309EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1310EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1311TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1312EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1313
1314EXC_REAL_NONE(0x1400, 0x100)
1315EXC_VIRT_NONE(0x5400, 0x100)
1316
1317EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1318	mtspr	SPRN_SPRG_HSCRATCH0,r13
1319	EXCEPTION_PROLOG_0(PACA_EXGEN)
1320	EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1321
1322#ifdef CONFIG_PPC_DENORMALISATION
1323	mfspr	r10,SPRN_HSRR1
1324	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
1325	andis.	r10,r10,(HSRR1_DENORM)@h /* denorm? */
1326	addi	r11,r11,-4		/* HSRR0 is next instruction */
1327	bne+	denorm_assist
1328#endif
1329
1330	KVMTEST_HV(0x1500)
1331	EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1332EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1333
1334#ifdef CONFIG_PPC_DENORMALISATION
1335EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1336	b	exc_real_0x1500_denorm_exception_hv
1337EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1338#else
1339EXC_VIRT_NONE(0x5500, 0x100)
1340#endif
1341
1342TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
1343
1344#ifdef CONFIG_PPC_DENORMALISATION
1345TRAMP_REAL_BEGIN(denorm_assist)
1346BEGIN_FTR_SECTION
1347/*
1348 * To denormalise we need to move a copy of the register to itself.
1349 * For POWER6 do that here for all FP regs.
1350 */
1351	mfmsr	r10
1352	ori	r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1353	xori	r10,r10,(MSR_FE0|MSR_FE1)
1354	mtmsrd	r10
1355	sync
1356
1357#define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
1358#define FMR4(n)  FMR2(n) ; FMR2(n+2)
1359#define FMR8(n)  FMR4(n) ; FMR4(n+4)
1360#define FMR16(n) FMR8(n) ; FMR8(n+8)
1361#define FMR32(n) FMR16(n) ; FMR16(n+16)
1362	FMR32(0)
1363
1364FTR_SECTION_ELSE
1365/*
1366 * To denormalise we need to move a copy of the register to itself.
1367 * For POWER7 do that here for the first 32 VSX registers only.
1368 */
1369	mfmsr	r10
1370	oris	r10,r10,MSR_VSX@h
1371	mtmsrd	r10
1372	sync
1373
1374#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1375#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1376#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1377#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1378#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1379	XVCPSGNDP32(0)
1380
1381ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1382
1383BEGIN_FTR_SECTION
1384	b	denorm_done
1385END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1386/*
1387 * To denormalise we need to move a copy of the register to itself.
1388 * For POWER8 we need to do that for all 64 VSX registers
1389 */
1390	XVCPSGNDP32(32)
1391denorm_done:
1392	mtspr	SPRN_HSRR0,r11
1393	mtcrf	0x80,r9
1394	ld	r9,PACA_EXGEN+EX_R9(r13)
1395	RESTORE_PPR_PACA(PACA_EXGEN, r10)
1396BEGIN_FTR_SECTION
1397	ld	r10,PACA_EXGEN+EX_CFAR(r13)
1398	mtspr	SPRN_CFAR,r10
1399END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1400	ld	r10,PACA_EXGEN+EX_R10(r13)
1401	ld	r11,PACA_EXGEN+EX_R11(r13)
1402	ld	r12,PACA_EXGEN+EX_R12(r13)
1403	ld	r13,PACA_EXGEN+EX_R13(r13)
1404	HRFI_TO_UNKNOWN
1405	b	.
1406#endif
1407
1408EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1409
1410
1411#ifdef CONFIG_CBE_RAS
1412EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1413EXC_VIRT_NONE(0x5600, 0x100)
1414TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1415EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1416#else /* CONFIG_CBE_RAS */
1417EXC_REAL_NONE(0x1600, 0x100)
1418EXC_VIRT_NONE(0x5600, 0x100)
1419#endif
1420
1421
1422EXC_REAL(altivec_assist, 0x1700, 0x100)
1423EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1424TRAMP_KVM(PACA_EXGEN, 0x1700)
1425#ifdef CONFIG_ALTIVEC
1426EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1427#else
1428EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1429#endif
1430
1431
1432#ifdef CONFIG_CBE_RAS
1433EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1434EXC_VIRT_NONE(0x5800, 0x100)
1435TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1436EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1437#else /* CONFIG_CBE_RAS */
1438EXC_REAL_NONE(0x1800, 0x100)
1439EXC_VIRT_NONE(0x5800, 0x100)
1440#endif
1441
1442#ifdef CONFIG_PPC_WATCHDOG
1443
1444#define MASKED_DEC_HANDLER_LABEL 3f
1445
1446#define MASKED_DEC_HANDLER(_H)				\
14473: /* soft-nmi */					\
1448	std	r12,PACA_EXGEN+EX_R12(r13);		\
1449	GET_SCRATCH0(r10);				\
1450	std	r10,PACA_EXGEN+EX_R13(r13);		\
1451	EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1452
1453/*
1454 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1455 * stack is one that is usable by maskable interrupts so long as MSR_EE
1456 * remains off. It is used for recovery when something has corrupted the
1457 * normal kernel stack, for example. The "soft NMI" must not use the process
1458 * stack because we want irq disabled sections to avoid touching the stack
1459 * at all (other than PMU interrupts), so use the emergency stack for this,
1460 * and run it entirely with interrupts hard disabled.
1461 */
1462EXC_COMMON_BEGIN(soft_nmi_common)
1463	mr	r10,r1
1464	ld	r1,PACAEMERGSP(r13)
1465	subi	r1,r1,INT_FRAME_SIZE
1466	EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1467			system_reset, soft_nmi_interrupt,
1468			ADD_NVGPRS;ADD_RECONCILE)
1469	b	ret_from_except
1470
1471#else /* CONFIG_PPC_WATCHDOG */
1472#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1473#define MASKED_DEC_HANDLER(_H)
1474#endif /* CONFIG_PPC_WATCHDOG */
1475
1476/*
1477 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1478 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1479 * - If it was a doorbell we return immediately since doorbells are edge
1480 *   triggered and won't automatically refire.
1481 * - If it was a HMI we return immediately since we handled it in realmode
1482 *   and it won't refire.
1483 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1484 * This is called with r10 containing the value to OR to the paca field.
1485 */
1486#define MASKED_INTERRUPT(_H)				\
1487masked_##_H##interrupt:					\
1488	std	r11,PACA_EXGEN+EX_R11(r13);		\
1489	lbz	r11,PACAIRQHAPPENED(r13);		\
1490	or	r11,r11,r10;				\
1491	stb	r11,PACAIRQHAPPENED(r13);		\
1492	cmpwi	r10,PACA_IRQ_DEC;			\
1493	bne	1f;					\
1494	lis	r10,0x7fff;				\
1495	ori	r10,r10,0xffff;				\
1496	mtspr	SPRN_DEC,r10;				\
1497	b	MASKED_DEC_HANDLER_LABEL;		\
14981:	andi.	r10,r10,PACA_IRQ_MUST_HARD_MASK;	\
 
 
1499	beq	2f;					\
1500	mfspr	r10,SPRN_##_H##SRR1;			\
1501	xori	r10,r10,MSR_EE; /* clear MSR_EE */	\
 
1502	mtspr	SPRN_##_H##SRR1,r10;			\
15032:	mtcrf	0x80,r9;				\
1504	ld	r9,PACA_EXGEN+EX_R9(r13);		\
1505	ld	r10,PACA_EXGEN+EX_R10(r13);		\
1506	ld	r11,PACA_EXGEN+EX_R11(r13);		\
1507	/* returns to kernel where r13 must be set up, so don't restore it */ \
1508	##_H##RFI_TO_KERNEL;				\
1509	b	.;					\
1510	MASKED_DEC_HANDLER(_H)
1511
1512TRAMP_REAL_BEGIN(stf_barrier_fallback)
1513	std	r9,PACA_EXRFI+EX_R9(r13)
1514	std	r10,PACA_EXRFI+EX_R10(r13)
1515	sync
1516	ld	r9,PACA_EXRFI+EX_R9(r13)
1517	ld	r10,PACA_EXRFI+EX_R10(r13)
1518	ori	31,31,0
1519	.rept 14
1520	b	1f
15211:
1522	.endr
1523	blr
1524
1525TRAMP_REAL_BEGIN(rfi_flush_fallback)
1526	SET_SCRATCH0(r13);
1527	GET_PACA(r13);
1528	std	r9,PACA_EXRFI+EX_R9(r13)
1529	std	r10,PACA_EXRFI+EX_R10(r13)
1530	std	r11,PACA_EXRFI+EX_R11(r13)
1531	mfctr	r9
1532	ld	r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1533	ld	r11,PACA_L1D_FLUSH_SIZE(r13)
1534	srdi	r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1535	mtctr	r11
1536	DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1537
1538	/* order ld/st prior to dcbt stop all streams with flushing */
1539	sync
1540
1541	/*
1542	 * The load adresses are at staggered offsets within cachelines,
1543	 * which suits some pipelines better (on others it should not
1544	 * hurt).
1545	 */
15461:
1547	ld	r11,(0x80 + 8)*0(r10)
1548	ld	r11,(0x80 + 8)*1(r10)
1549	ld	r11,(0x80 + 8)*2(r10)
1550	ld	r11,(0x80 + 8)*3(r10)
1551	ld	r11,(0x80 + 8)*4(r10)
1552	ld	r11,(0x80 + 8)*5(r10)
1553	ld	r11,(0x80 + 8)*6(r10)
1554	ld	r11,(0x80 + 8)*7(r10)
1555	addi	r10,r10,0x80*8
1556	bdnz	1b
1557
1558	mtctr	r9
1559	ld	r9,PACA_EXRFI+EX_R9(r13)
1560	ld	r10,PACA_EXRFI+EX_R10(r13)
1561	ld	r11,PACA_EXRFI+EX_R11(r13)
1562	GET_SCRATCH0(r13);
1563	rfid
1564
1565TRAMP_REAL_BEGIN(hrfi_flush_fallback)
1566	SET_SCRATCH0(r13);
1567	GET_PACA(r13);
1568	std	r9,PACA_EXRFI+EX_R9(r13)
1569	std	r10,PACA_EXRFI+EX_R10(r13)
1570	std	r11,PACA_EXRFI+EX_R11(r13)
1571	mfctr	r9
1572	ld	r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1573	ld	r11,PACA_L1D_FLUSH_SIZE(r13)
1574	srdi	r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1575	mtctr	r11
1576	DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1577
1578	/* order ld/st prior to dcbt stop all streams with flushing */
1579	sync
1580
1581	/*
1582	 * The load adresses are at staggered offsets within cachelines,
1583	 * which suits some pipelines better (on others it should not
1584	 * hurt).
1585	 */
15861:
1587	ld	r11,(0x80 + 8)*0(r10)
1588	ld	r11,(0x80 + 8)*1(r10)
1589	ld	r11,(0x80 + 8)*2(r10)
1590	ld	r11,(0x80 + 8)*3(r10)
1591	ld	r11,(0x80 + 8)*4(r10)
1592	ld	r11,(0x80 + 8)*5(r10)
1593	ld	r11,(0x80 + 8)*6(r10)
1594	ld	r11,(0x80 + 8)*7(r10)
1595	addi	r10,r10,0x80*8
1596	bdnz	1b
1597
1598	mtctr	r9
1599	ld	r9,PACA_EXRFI+EX_R9(r13)
1600	ld	r10,PACA_EXRFI+EX_R10(r13)
1601	ld	r11,PACA_EXRFI+EX_R11(r13)
1602	GET_SCRATCH0(r13);
1603	hrfid
1604
1605/*
1606 * Real mode exceptions actually use this too, but alternate
1607 * instruction code patches (which end up in the common .text area)
1608 * cannot reach these if they are put there.
1609 */
1610USE_FIXED_SECTION(virt_trampolines)
1611	MASKED_INTERRUPT()
1612	MASKED_INTERRUPT(H)
1613
1614#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1615TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1616	/*
1617	 * Here all GPRs are unchanged from when the interrupt happened
1618	 * except for r13, which is saved in SPRG_SCRATCH0.
1619	 */
1620	mfspr	r13, SPRN_SRR0
1621	addi	r13, r13, 4
1622	mtspr	SPRN_SRR0, r13
1623	GET_SCRATCH0(r13)
1624	RFI_TO_KERNEL
1625	b	.
1626
1627TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1628	/*
1629	 * Here all GPRs are unchanged from when the interrupt happened
1630	 * except for r13, which is saved in SPRG_SCRATCH0.
1631	 */
1632	mfspr	r13, SPRN_HSRR0
1633	addi	r13, r13, 4
1634	mtspr	SPRN_HSRR0, r13
1635	GET_SCRATCH0(r13)
1636	HRFI_TO_KERNEL
1637	b	.
1638#endif
1639
1640/*
1641 * Ensure that any handlers that get invoked from the exception prologs
1642 * above are below the first 64KB (0x10000) of the kernel image because
1643 * the prologs assemble the addresses of these handlers using the
1644 * LOAD_HANDLER macro, which uses an ori instruction.
1645 */
1646
1647/*** Common interrupt handlers ***/
1648
1649
1650	/*
1651	 * Relocation-on interrupts: A subset of the interrupts can be delivered
1652	 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1653	 * it.  Addresses are the same as the original interrupt addresses, but
1654	 * offset by 0xc000000000004000.
1655	 * It's impossible to receive interrupts below 0x300 via this mechanism.
1656	 * KVM: None of these traps are from the guest ; anything that escalated
1657	 * to HV=1 from HV=0 is delivered via real mode handlers.
1658	 */
1659
1660	/*
1661	 * This uses the standard macro, since the original 0x300 vector
1662	 * only has extra guff for STAB-based processors -- which never
1663	 * come here.
1664	 */
1665
1666EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1667	b	__ppc64_runlatch_on
1668
1669USE_FIXED_SECTION(virt_trampolines)
1670	/*
1671	 * The __end_interrupts marker must be past the out-of-line (OOL)
1672	 * handlers, so that they are copied to real address 0x100 when running
1673	 * a relocatable kernel. This ensures they can be reached from the short
1674	 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1675	 * directly, without using LOAD_HANDLER().
1676	 */
1677	.align	7
1678	.globl	__end_interrupts
1679__end_interrupts:
1680DEFINE_FIXED_SYMBOL(__end_interrupts)
1681
1682#ifdef CONFIG_PPC_970_NAP
1683EXC_COMMON_BEGIN(power4_fixup_nap)
1684	andc	r9,r9,r10
1685	std	r9,TI_LOCAL_FLAGS(r11)
1686	ld	r10,_LINK(r1)		/* make idle task do the */
1687	std	r10,_NIP(r1)		/* equivalent of a blr */
1688	blr
1689#endif
1690
1691CLOSE_FIXED_SECTION(real_vectors);
1692CLOSE_FIXED_SECTION(real_trampolines);
1693CLOSE_FIXED_SECTION(virt_vectors);
1694CLOSE_FIXED_SECTION(virt_trampolines);
1695
1696USE_TEXT_SECTION()
1697
1698/*
1699 * Hash table stuff
1700 */
1701	.balign	IFETCH_ALIGN_BYTES
1702do_hash_page:
1703#ifdef CONFIG_PPC_BOOK3S_64
1704	lis	r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
1705	ori	r0,r0,DSISR_BAD_FAULT_64S@l
1706	and.	r0,r4,r0		/* weird error? */
1707	bne-	handle_page_fault	/* if not, try to insert a HPTE */
 
 
1708	CURRENT_THREAD_INFO(r11, r1)
1709	lwz	r0,TI_PREEMPT(r11)	/* If we're in an "NMI" */
1710	andis.	r0,r0,NMI_MASK@h	/* (i.e. an irq when soft-disabled) */
1711	bne	77f			/* then don't call hash_page now */
1712
1713	/*
1714	 * r3 contains the faulting address
1715	 * r4 msr
1716	 * r5 contains the trap number
1717	 * r6 contains dsisr
1718	 *
1719	 * at return r3 = 0 for success, 1 for page fault, negative for error
1720	 */
1721        mr 	r4,r12
1722	ld      r6,_DSISR(r1)
1723	bl	__hash_page		/* build HPTE if possible */
1724        cmpdi	r3,0			/* see if __hash_page succeeded */
1725
1726	/* Success */
1727	beq	fast_exc_return_irq	/* Return from exception on success */
1728
1729	/* Error */
1730	blt-	13f
1731
1732	/* Reload DSISR into r4 for the DABR check below */
1733	ld      r4,_DSISR(r1)
1734#endif /* CONFIG_PPC_BOOK3S_64 */
1735
1736/* Here we have a page fault that hash_page can't handle. */
1737handle_page_fault:
173811:	andis.  r0,r4,DSISR_DABRMATCH@h
1739	bne-    handle_dabr_fault
1740	ld	r4,_DAR(r1)
1741	ld	r5,_DSISR(r1)
1742	addi	r3,r1,STACK_FRAME_OVERHEAD
1743	bl	do_page_fault
1744	cmpdi	r3,0
1745	beq+	12f
1746	bl	save_nvgprs
1747	mr	r5,r3
1748	addi	r3,r1,STACK_FRAME_OVERHEAD
1749	lwz	r4,_DAR(r1)
1750	bl	bad_page_fault
1751	b	ret_from_except
1752
1753/* We have a data breakpoint exception - handle it */
1754handle_dabr_fault:
1755	bl	save_nvgprs
1756	ld      r4,_DAR(r1)
1757	ld      r5,_DSISR(r1)
1758	addi    r3,r1,STACK_FRAME_OVERHEAD
1759	bl      do_break
176012:	b       ret_from_except_lite
1761
1762
1763#ifdef CONFIG_PPC_BOOK3S_64
1764/* We have a page fault that hash_page could handle but HV refused
1765 * the PTE insertion
1766 */
176713:	bl	save_nvgprs
1768	mr	r5,r3
1769	addi	r3,r1,STACK_FRAME_OVERHEAD
1770	ld	r4,_DAR(r1)
1771	bl	low_hash_fault
1772	b	ret_from_except
1773#endif
1774
1775/*
1776 * We come here as a result of a DSI at a point where we don't want
1777 * to call hash_page, such as when we are accessing memory (possibly
1778 * user memory) inside a PMU interrupt that occurred while interrupts
1779 * were soft-disabled.  We want to invoke the exception handler for
1780 * the access, or panic if there isn't a handler.
1781 */
178277:	bl	save_nvgprs
1783	mr	r4,r3
1784	addi	r3,r1,STACK_FRAME_OVERHEAD
1785	li	r5,SIGSEGV
1786	bl	bad_page_fault
1787	b	ret_from_except
1788
1789/*
1790 * Here we have detected that the kernel stack pointer is bad.
1791 * R9 contains the saved CR, r13 points to the paca,
1792 * r10 contains the (bad) kernel stack pointer,
1793 * r11 and r12 contain the saved SRR0 and SRR1.
1794 * We switch to using an emergency stack, save the registers there,
1795 * and call kernel_bad_stack(), which panics.
1796 */
1797bad_stack:
1798	ld	r1,PACAEMERGSP(r13)
1799	subi	r1,r1,64+INT_FRAME_SIZE
1800	std	r9,_CCR(r1)
1801	std	r10,GPR1(r1)
1802	std	r11,_NIP(r1)
1803	std	r12,_MSR(r1)
1804	mfspr	r11,SPRN_DAR
1805	mfspr	r12,SPRN_DSISR
1806	std	r11,_DAR(r1)
1807	std	r12,_DSISR(r1)
1808	mflr	r10
1809	mfctr	r11
1810	mfxer	r12
1811	std	r10,_LINK(r1)
1812	std	r11,_CTR(r1)
1813	std	r12,_XER(r1)
1814	SAVE_GPR(0,r1)
1815	SAVE_GPR(2,r1)
1816	ld	r10,EX_R3(r3)
1817	std	r10,GPR3(r1)
1818	SAVE_GPR(4,r1)
1819	SAVE_4GPRS(5,r1)
1820	ld	r9,EX_R9(r3)
1821	ld	r10,EX_R10(r3)
1822	SAVE_2GPRS(9,r1)
1823	ld	r9,EX_R11(r3)
1824	ld	r10,EX_R12(r3)
1825	ld	r11,EX_R13(r3)
1826	std	r9,GPR11(r1)
1827	std	r10,GPR12(r1)
1828	std	r11,GPR13(r1)
1829BEGIN_FTR_SECTION
1830	ld	r10,EX_CFAR(r3)
1831	std	r10,ORIG_GPR3(r1)
1832END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1833	SAVE_8GPRS(14,r1)
1834	SAVE_10GPRS(22,r1)
1835	lhz	r12,PACA_TRAP_SAVE(r13)
1836	std	r12,_TRAP(r1)
1837	addi	r11,r1,INT_FRAME_SIZE
1838	std	r11,0(r1)
1839	li	r12,0
1840	std	r12,0(r11)
1841	ld	r2,PACATOC(r13)
1842	ld	r11,exception_marker@toc(r2)
1843	std	r12,RESULT(r1)
1844	std	r11,STACK_FRAME_OVERHEAD-16(r1)
18451:	addi	r3,r1,STACK_FRAME_OVERHEAD
1846	bl	kernel_bad_stack
1847	b	1b
1848_ASM_NOKPROBE_SYMBOL(bad_stack);
1849
1850/*
1851 * When doorbell is triggered from system reset wakeup, the message is
1852 * not cleared, so it would fire again when EE is enabled.
1853 *
1854 * When coming from local_irq_enable, there may be the same problem if
1855 * we were hard disabled.
1856 *
1857 * Execute msgclr to clear pending exceptions before handling it.
1858 */
1859h_doorbell_common_msgclr:
1860	LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1861	PPC_MSGCLR(3)
1862	b 	h_doorbell_common
1863
1864doorbell_super_common_msgclr:
1865	LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1866	PPC_MSGCLRP(3)
1867	b 	doorbell_super_common
1868
1869/*
1870 * Called from arch_local_irq_enable when an interrupt needs
1871 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1872 * which kind of interrupt. MSR:EE is already off. We generate a
1873 * stackframe like if a real interrupt had happened.
1874 *
1875 * Note: While MSR:EE is off, we need to make sure that _MSR
1876 * in the generated frame has EE set to 1 or the exception
1877 * handler will not properly re-enable them.
1878 *
1879 * Note that we don't specify LR as the NIP (return address) for
1880 * the interrupt because that would unbalance the return branch
1881 * predictor.
1882 */
1883_GLOBAL(__replay_interrupt)
1884	/* We are going to jump to the exception common code which
1885	 * will retrieve various register values from the PACA which
1886	 * we don't give a damn about, so we don't bother storing them.
1887	 */
1888	mfmsr	r12
1889	LOAD_REG_ADDR(r11, replay_interrupt_return)
1890	mfcr	r9
1891	ori	r12,r12,MSR_EE
1892	cmpwi	r3,0x900
1893	beq	decrementer_common
1894	cmpwi	r3,0x500
1895BEGIN_FTR_SECTION
1896	beq	h_virt_irq_common
1897FTR_SECTION_ELSE
1898	beq	hardware_interrupt_common
1899ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1900	cmpwi	r3,0xf00
1901	beq	performance_monitor_common
1902BEGIN_FTR_SECTION
1903	cmpwi	r3,0xa00
1904	beq	h_doorbell_common_msgclr
 
 
1905	cmpwi	r3,0xe60
1906	beq	hmi_exception_common
1907FTR_SECTION_ELSE
1908	cmpwi	r3,0xa00
1909	beq	doorbell_super_common_msgclr
1910ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1911replay_interrupt_return:
1912	blr
1913
1914_ASM_NOKPROBE_SYMBOL(__replay_interrupt)