1/*
  2 * The file intends to implement PE based on the information from
  3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
  4 * All the PEs should be organized as hierarchy tree. The first level
  5 * of the tree will be associated to existing PHBs since the particular
  6 * PE is only meaningful in one PHB domain.
  7 *
  8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
  9 *
 10 * This program is free software; you can redistribute it and/or modify
 11 * it under the terms of the GNU General Public License as published by
 12 * the Free Software Foundation; either version 2 of the License, or
 13 * (at your option) any later version.
 14 *
 15 * This program is distributed in the hope that it will be useful,
 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18 * GNU General Public License for more details.
 19 *
 20 * You should have received a copy of the GNU General Public License
 21 * along with this program; if not, write to the Free Software
 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 23 */
 24
 25#include <linux/delay.h>
 26#include <linux/export.h>
 27#include <linux/gfp.h>
 28#include <linux/kernel.h>
 29#include <linux/pci.h>
 30#include <linux/string.h>
 31
 32#include <asm/pci-bridge.h>
 33#include <asm/ppc-pci.h>
 34
 35static int eeh_pe_aux_size = 0;
 36static LIST_HEAD(eeh_phb_pe);
 37
 38/**
 39 * eeh_set_pe_aux_size - Set PE auxillary data size
 40 * @size: PE auxillary data size
 41 *
 42 * Set PE auxillary data size
 43 */
 44void eeh_set_pe_aux_size(int size)
 45{
 46	if (size < 0)
 47		return;
 48
 49	eeh_pe_aux_size = size;
 50}
 51
 52/**
 53 * eeh_pe_alloc - Allocate PE
 54 * @phb: PCI controller
 55 * @type: PE type
 56 *
 57 * Allocate PE instance dynamically.
 58 */
 59static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
 60{
 61	struct eeh_pe *pe;
 62	size_t alloc_size;
 63
 64	alloc_size = sizeof(struct eeh_pe);
 65	if (eeh_pe_aux_size) {
 66		alloc_size = ALIGN(alloc_size, cache_line_size());
 67		alloc_size += eeh_pe_aux_size;
 68	}
 69
 70	/* Allocate PHB PE */
 71	pe = kzalloc(alloc_size, GFP_KERNEL);
 72	if (!pe) return NULL;
 73
 74	/* Initialize PHB PE */
 75	pe->type = type;
 76	pe->phb = phb;
 77	INIT_LIST_HEAD(&pe->child_list);
 78	INIT_LIST_HEAD(&pe->child);
 79	INIT_LIST_HEAD(&pe->edevs);
 80
 81	pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
 82				      cache_line_size());
 83	return pe;
 84}
 85
 86/**
 87 * eeh_phb_pe_create - Create PHB PE
 88 * @phb: PCI controller
 89 *
 90 * The function should be called while the PHB is detected during
 91 * system boot or PCI hotplug in order to create PHB PE.
 92 */
 93int eeh_phb_pe_create(struct pci_controller *phb)
 94{
 95	struct eeh_pe *pe;
 96
 97	/* Allocate PHB PE */
 98	pe = eeh_pe_alloc(phb, EEH_PE_PHB);
 99	if (!pe) {
100		pr_err("%s: out of memory!\n", __func__);
101		return -ENOMEM;
102	}
103
104	/* Put it into the list */
105	list_add_tail(&pe->child, &eeh_phb_pe);
106
107	pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
108
109	return 0;
110}
111
112/**
113 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
114 * @phb: PCI controller
115 *
116 * The overall PEs form hierarchy tree. The first layer of the
117 * hierarchy tree is composed of PHB PEs. The function is used
118 * to retrieve the corresponding PHB PE according to the given PHB.
119 */
120struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
121{
122	struct eeh_pe *pe;
123
124	list_for_each_entry(pe, &eeh_phb_pe, child) {
125		/*
126		 * Actually, we needn't check the type since
127		 * the PE for PHB has been determined when that
128		 * was created.
129		 */
130		if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
131			return pe;
132	}
133
134	return NULL;
135}
136
137/**
138 * eeh_pe_next - Retrieve the next PE in the tree
139 * @pe: current PE
140 * @root: root PE
141 *
142 * The function is used to retrieve the next PE in the
143 * hierarchy PE tree.
144 */
145static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
146				  struct eeh_pe *root)
147{
148	struct list_head *next = pe->child_list.next;
149
150	if (next == &pe->child_list) {
151		while (1) {
152			if (pe == root)
153				return NULL;
154			next = pe->child.next;
155			if (next != &pe->parent->child_list)
156				break;
157			pe = pe->parent;
158		}
159	}
160
161	return list_entry(next, struct eeh_pe, child);
162}
163
164/**
165 * eeh_pe_traverse - Traverse PEs in the specified PHB
166 * @root: root PE
167 * @fn: callback
168 * @flag: extra parameter to callback
169 *
170 * The function is used to traverse the specified PE and its
171 * child PEs. The traversing is to be terminated once the
172 * callback returns something other than NULL, or no more PEs
173 * to be traversed.
174 */
175void *eeh_pe_traverse(struct eeh_pe *root,
176		      eeh_traverse_func fn, void *flag)
177{
178	struct eeh_pe *pe;
179	void *ret;
180
181	for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
182		ret = fn(pe, flag);
183		if (ret) return ret;
184	}
185
186	return NULL;
187}
188
189/**
190 * eeh_pe_dev_traverse - Traverse the devices from the PE
191 * @root: EEH PE
192 * @fn: function callback
193 * @flag: extra parameter to callback
194 *
195 * The function is used to traverse the devices of the specified
196 * PE and its child PEs.
197 */
198void *eeh_pe_dev_traverse(struct eeh_pe *root,
199		eeh_traverse_func fn, void *flag)
200{
201	struct eeh_pe *pe;
202	struct eeh_dev *edev, *tmp;
203	void *ret;
204
205	if (!root) {
206		pr_warn("%s: Invalid PE %p\n",
207			__func__, root);
208		return NULL;
209	}
210
211	/* Traverse root PE */
212	for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
213		eeh_pe_for_each_dev(pe, edev, tmp) {
214			ret = fn(edev, flag);
215			if (ret)
216				return ret;
217		}
218	}
219
220	return NULL;
221}
222
223/**
224 * __eeh_pe_get - Check the PE address
225 * @data: EEH PE
226 * @flag: EEH device
227 *
228 * For one particular PE, it can be identified by PE address
229 * or tranditional BDF address. BDF address is composed of
230 * Bus/Device/Function number. The extra data referred by flag
231 * indicates which type of address should be used.
232 */
233struct eeh_pe_get_flag {
234	int pe_no;
235	int config_addr;
236};
237
238static void *__eeh_pe_get(void *data, void *flag)
239{
240	struct eeh_pe *pe = (struct eeh_pe *)data;
241	struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
242
243	/* Unexpected PHB PE */
244	if (pe->type & EEH_PE_PHB)
245		return NULL;
246
247	/*
248	 * We prefer PE address. For most cases, we should
249	 * have non-zero PE address
250	 */
251	if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
252		if (tmp->pe_no == pe->addr)
253			return pe;
254	} else {
255		if (tmp->pe_no &&
256		    (tmp->pe_no == pe->addr))
257			return pe;
258	}
259
260	/* Try BDF address */
261	if (tmp->config_addr &&
262	   (tmp->config_addr == pe->config_addr))
263		return pe;
264
265	return NULL;
266}
267
268/**
269 * eeh_pe_get - Search PE based on the given address
270 * @phb: PCI controller
271 * @pe_no: PE number
272 * @config_addr: Config address
273 *
274 * Search the corresponding PE based on the specified address which
275 * is included in the eeh device. The function is used to check if
276 * the associated PE has been created against the PE address. It's
277 * notable that the PE address has 2 format: traditional PE address
278 * which is composed of PCI bus/device/function number, or unified
279 * PE address.
280 */
281struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
282		int pe_no, int config_addr)
283{
284	struct eeh_pe *root = eeh_phb_pe_get(phb);
285	struct eeh_pe_get_flag tmp = { pe_no, config_addr };
286	struct eeh_pe *pe;
287
288	pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
289
290	return pe;
291}
292
293/**
294 * eeh_pe_get_parent - Retrieve the parent PE
295 * @edev: EEH device
296 *
297 * The whole PEs existing in the system are organized as hierarchy
298 * tree. The function is used to retrieve the parent PE according
299 * to the parent EEH device.
300 */
301static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
302{
303	struct eeh_dev *parent;
304	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
305
306	/*
307	 * It might have the case for the indirect parent
308	 * EEH device already having associated PE, but
309	 * the direct parent EEH device doesn't have yet.
310	 */
311	if (edev->physfn)
312		pdn = pci_get_pdn(edev->physfn);
313	else
314		pdn = pdn ? pdn->parent : NULL;
315	while (pdn) {
316		/* We're poking out of PCI territory */
317		parent = pdn_to_eeh_dev(pdn);
318		if (!parent)
319			return NULL;
320
321		if (parent->pe)
322			return parent->pe;
323
324		pdn = pdn->parent;
325	}
326
327	return NULL;
328}
329
330/**
331 * eeh_add_to_parent_pe - Add EEH device to parent PE
332 * @edev: EEH device
333 *
334 * Add EEH device to the parent PE. If the parent PE already
335 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
336 * we have to create new PE to hold the EEH device and the new
337 * PE will be linked to its parent PE as well.
338 */
339int eeh_add_to_parent_pe(struct eeh_dev *edev)
340{
341	struct eeh_pe *pe, *parent;
342	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
343	int config_addr = (pdn->busno << 8) | (pdn->devfn);
344
345	/* Check if the PE number is valid */
346	if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
347		pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
348		       __func__, config_addr, pdn->phb->global_number);
349		return -EINVAL;
350	}
351
352	/*
353	 * Search the PE has been existing or not according
354	 * to the PE address. If that has been existing, the
355	 * PE should be composed of PCI bus and its subordinate
356	 * components.
357	 */
358	pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
359	if (pe && !(pe->type & EEH_PE_INVALID)) {
360		/* Mark the PE as type of PCI bus */
361		pe->type = EEH_PE_BUS;
362		edev->pe = pe;
363
364		/* Put the edev to PE */
365		list_add_tail(&edev->list, &pe->edevs);
366		pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
367			 pdn->phb->global_number,
368			 pdn->busno,
369			 PCI_SLOT(pdn->devfn),
370			 PCI_FUNC(pdn->devfn),
371			 pe->addr);
372		return 0;
373	} else if (pe && (pe->type & EEH_PE_INVALID)) {
374		list_add_tail(&edev->list, &pe->edevs);
375		edev->pe = pe;
376		/*
377		 * We're running to here because of PCI hotplug caused by
378		 * EEH recovery. We need clear EEH_PE_INVALID until the top.
379		 */
380		parent = pe;
381		while (parent) {
382			if (!(parent->type & EEH_PE_INVALID))
383				break;
384			parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
385			parent = parent->parent;
386		}
387
388		pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
389			 "PE#%x, Parent PE#%x\n",
390			 pdn->phb->global_number,
391			 pdn->busno,
392			 PCI_SLOT(pdn->devfn),
393			 PCI_FUNC(pdn->devfn),
394			 pe->addr, pe->parent->addr);
395		return 0;
396	}
397
398	/* Create a new EEH PE */
399	if (edev->physfn)
400		pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
401	else
402		pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
403	if (!pe) {
404		pr_err("%s: out of memory!\n", __func__);
405		return -ENOMEM;
406	}
407	pe->addr	= edev->pe_config_addr;
408	pe->config_addr	= config_addr;
409
410	/*
411	 * Put the new EEH PE into hierarchy tree. If the parent
412	 * can't be found, the newly created PE will be attached
413	 * to PHB directly. Otherwise, we have to associate the
414	 * PE with its parent.
415	 */
416	parent = eeh_pe_get_parent(edev);
417	if (!parent) {
418		parent = eeh_phb_pe_get(pdn->phb);
419		if (!parent) {
420			pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
421				__func__, pdn->phb->global_number);
422			edev->pe = NULL;
423			kfree(pe);
424			return -EEXIST;
425		}
426	}
427	pe->parent = parent;
428
429	/*
430	 * Put the newly created PE into the child list and
431	 * link the EEH device accordingly.
432	 */
433	list_add_tail(&pe->child, &parent->child_list);
434	list_add_tail(&edev->list, &pe->edevs);
435	edev->pe = pe;
436	pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
437		 "Device PE#%x, Parent PE#%x\n",
438		 pdn->phb->global_number,
439		 pdn->busno,
440		 PCI_SLOT(pdn->devfn),
441		 PCI_FUNC(pdn->devfn),
442		 pe->addr, pe->parent->addr);
443
444	return 0;
445}
446
447/**
448 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
449 * @edev: EEH device
450 *
451 * The PE hierarchy tree might be changed when doing PCI hotplug.
452 * Also, the PCI devices or buses could be removed from the system
453 * during EEH recovery. So we have to call the function remove the
454 * corresponding PE accordingly if necessary.
455 */
456int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
457{
458	struct eeh_pe *pe, *parent, *child;
459	int cnt;
460	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
461
462	if (!edev->pe) {
463		pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
464			 __func__,  pdn->phb->global_number,
465			 pdn->busno,
466			 PCI_SLOT(pdn->devfn),
467			 PCI_FUNC(pdn->devfn));
468		return -EEXIST;
469	}
470
471	/* Remove the EEH device */
472	pe = eeh_dev_to_pe(edev);
473	edev->pe = NULL;
474	list_del(&edev->list);
475
476	/*
477	 * Check if the parent PE includes any EEH devices.
478	 * If not, we should delete that. Also, we should
479	 * delete the parent PE if it doesn't have associated
480	 * child PEs and EEH devices.
481	 */
482	while (1) {
483		parent = pe->parent;
484		if (pe->type & EEH_PE_PHB)
485			break;
486
487		if (!(pe->state & EEH_PE_KEEP)) {
488			if (list_empty(&pe->edevs) &&
489			    list_empty(&pe->child_list)) {
490				list_del(&pe->child);
491				kfree(pe);
492			} else {
493				break;
494			}
495		} else {
496			if (list_empty(&pe->edevs)) {
497				cnt = 0;
498				list_for_each_entry(child, &pe->child_list, child) {
499					if (!(child->type & EEH_PE_INVALID)) {
500						cnt++;
501						break;
502					}
503				}
504
505				if (!cnt)
506					pe->type |= EEH_PE_INVALID;
507				else
508					break;
509			}
510		}
511
512		pe = parent;
513	}
514
515	return 0;
516}
517
518/**
519 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
520 * @pe: EEH PE
521 *
522 * We have time stamp for each PE to trace its time of getting
523 * frozen in last hour. The function should be called to update
524 * the time stamp on first error of the specific PE. On the other
525 * handle, we needn't account for errors happened in last hour.
526 */
527void eeh_pe_update_time_stamp(struct eeh_pe *pe)
528{
529	time64_t tstamp;
530
531	if (!pe) return;
532
533	if (pe->freeze_count <= 0) {
534		pe->freeze_count = 0;
535		pe->tstamp = ktime_get_seconds();
536	} else {
537		tstamp = ktime_get_seconds();
538		if (tstamp - pe->tstamp > 3600) {
539			pe->tstamp = tstamp;
540			pe->freeze_count = 0;
541		}
542	}
543}
544
545/**
546 * __eeh_pe_state_mark - Mark the state for the PE
547 * @data: EEH PE
548 * @flag: state
549 *
550 * The function is used to mark the indicated state for the given
551 * PE. Also, the associated PCI devices will be put into IO frozen
552 * state as well.
553 */
554static void *__eeh_pe_state_mark(void *data, void *flag)
555{
556	struct eeh_pe *pe = (struct eeh_pe *)data;
557	int state = *((int *)flag);
558	struct eeh_dev *edev, *tmp;
559	struct pci_dev *pdev;
560
561	/* Keep the state of permanently removed PE intact */
562	if (pe->state & EEH_PE_REMOVED)
563		return NULL;
564
565	pe->state |= state;
566
567	/* Offline PCI devices if applicable */
568	if (!(state & EEH_PE_ISOLATED))
569		return NULL;
570
571	eeh_pe_for_each_dev(pe, edev, tmp) {
572		pdev = eeh_dev_to_pci_dev(edev);
573		if (pdev)
574			pdev->error_state = pci_channel_io_frozen;
575	}
576
577	/* Block PCI config access if required */
578	if (pe->state & EEH_PE_CFG_RESTRICTED)
579		pe->state |= EEH_PE_CFG_BLOCKED;
580
581	return NULL;
582}
583
584/**
585 * eeh_pe_state_mark - Mark specified state for PE and its associated device
586 * @pe: EEH PE
587 *
588 * EEH error affects the current PE and its child PEs. The function
589 * is used to mark appropriate state for the affected PEs and the
590 * associated devices.
591 */
592void eeh_pe_state_mark(struct eeh_pe *pe, int state)
593{
594	eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
595}
596EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
597
598static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
599{
600	struct eeh_dev *edev = data;
601	int mode = *((int *)flag);
602
603	edev->mode |= mode;
604
605	return NULL;
606}
607
608/**
609 * eeh_pe_dev_state_mark - Mark state for all device under the PE
610 * @pe: EEH PE
611 *
612 * Mark specific state for all child devices of the PE.
613 */
614void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
615{
616	eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
617}
618
619/**
620 * __eeh_pe_state_clear - Clear state for the PE
621 * @data: EEH PE
622 * @flag: state
623 *
624 * The function is used to clear the indicated state from the
625 * given PE. Besides, we also clear the check count of the PE
626 * as well.
627 */
628static void *__eeh_pe_state_clear(void *data, void *flag)
629{
630	struct eeh_pe *pe = (struct eeh_pe *)data;
631	int state = *((int *)flag);
632	struct eeh_dev *edev, *tmp;
633	struct pci_dev *pdev;
634
635	/* Keep the state of permanently removed PE intact */
636	if (pe->state & EEH_PE_REMOVED)
637		return NULL;
638
639	pe->state &= ~state;
640
641	/*
642	 * Special treatment on clearing isolated state. Clear
643	 * check count since last isolation and put all affected
644	 * devices to normal state.
645	 */
646	if (!(state & EEH_PE_ISOLATED))
647		return NULL;
648
649	pe->check_count = 0;
650	eeh_pe_for_each_dev(pe, edev, tmp) {
651		pdev = eeh_dev_to_pci_dev(edev);
652		if (!pdev)
653			continue;
654
655		pdev->error_state = pci_channel_io_normal;
656	}
657
658	/* Unblock PCI config access if required */
659	if (pe->state & EEH_PE_CFG_RESTRICTED)
660		pe->state &= ~EEH_PE_CFG_BLOCKED;
661
662	return NULL;
663}
664
665/**
666 * eeh_pe_state_clear - Clear state for the PE and its children
667 * @pe: PE
668 * @state: state to be cleared
669 *
670 * When the PE and its children has been recovered from error,
671 * we need clear the error state for that. The function is used
672 * for the purpose.
673 */
674void eeh_pe_state_clear(struct eeh_pe *pe, int state)
675{
676	eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
677}
678
679/**
680 * eeh_pe_state_mark_with_cfg - Mark PE state with unblocked config space
681 * @pe: PE
682 * @state: PE state to be set
683 *
684 * Set specified flag to PE and its child PEs. The PCI config space
685 * of some PEs is blocked automatically when EEH_PE_ISOLATED is set,
686 * which isn't needed in some situations. The function allows to set
687 * the specified flag to indicated PEs without blocking their PCI
688 * config space.
689 */
690void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
691{
692	eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
693	if (!(state & EEH_PE_ISOLATED))
694		return;
695
696	/* Clear EEH_PE_CFG_BLOCKED, which might be set just now */
697	state = EEH_PE_CFG_BLOCKED;
698	eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
699}
700
701/*
702 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
703 * buses assigned explicitly by firmware, and we probably have
704 * lost that after reset. So we have to delay the check until
705 * the PCI-CFG registers have been restored for the parent
706 * bridge.
707 *
708 * Don't use normal PCI-CFG accessors, which probably has been
709 * blocked on normal path during the stage. So we need utilize
710 * eeh operations, which is always permitted.
711 */
712static void eeh_bridge_check_link(struct eeh_dev *edev)
713{
714	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
715	int cap;
716	uint32_t val;
717	int timeout = 0;
718
719	/*
720	 * We only check root port and downstream ports of
721	 * PCIe switches
722	 */
723	if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
724		return;
725
726	pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
727		 __func__, pdn->phb->global_number,
728		 pdn->busno,
729		 PCI_SLOT(pdn->devfn),
730		 PCI_FUNC(pdn->devfn));
731
732	/* Check slot status */
733	cap = edev->pcie_cap;
734	eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
735	if (!(val & PCI_EXP_SLTSTA_PDS)) {
736		pr_debug("  No card in the slot (0x%04x) !\n", val);
737		return;
738	}
739
740	/* Check power status if we have the capability */
741	eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
742	if (val & PCI_EXP_SLTCAP_PCP) {
743		eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
744		if (val & PCI_EXP_SLTCTL_PCC) {
745			pr_debug("  In power-off state, power it on ...\n");
746			val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
747			val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
748			eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
749			msleep(2 * 1000);
750		}
751	}
752
753	/* Enable link */
754	eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
755	val &= ~PCI_EXP_LNKCTL_LD;
756	eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
757
758	/* Check link */
759	eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
760	if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
761		pr_debug("  No link reporting capability (0x%08x) \n", val);
762		msleep(1000);
763		return;
764	}
765
766	/* Wait the link is up until timeout (5s) */
767	timeout = 0;
768	while (timeout < 5000) {
769		msleep(20);
770		timeout += 20;
771
772		eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
773		if (val & PCI_EXP_LNKSTA_DLLLA)
774			break;
775	}
776
777	if (val & PCI_EXP_LNKSTA_DLLLA)
778		pr_debug("  Link up (%s)\n",
779			 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
780	else
781		pr_debug("  Link not ready (0x%04x)\n", val);
782}
783
784#define BYTE_SWAP(OFF)	(8*((OFF)/4)+3-(OFF))
785#define SAVED_BYTE(OFF)	(((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
786
787static void eeh_restore_bridge_bars(struct eeh_dev *edev)
788{
789	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
790	int i;
791
792	/*
793	 * Device BARs: 0x10 - 0x18
794	 * Bus numbers and windows: 0x18 - 0x30
795	 */
796	for (i = 4; i < 13; i++)
797		eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
798	/* Rom: 0x38 */
799	eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
800
801	/* Cache line & Latency timer: 0xC 0xD */
802	eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
803                SAVED_BYTE(PCI_CACHE_LINE_SIZE));
804        eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
805                SAVED_BYTE(PCI_LATENCY_TIMER));
806	/* Max latency, min grant, interrupt ping and line: 0x3C */
807	eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
808
809	/* PCI Command: 0x4 */
810	eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
811			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
812
813	/* Check the PCIe link is ready */
814	eeh_bridge_check_link(edev);
815}
816
817static void eeh_restore_device_bars(struct eeh_dev *edev)
818{
819	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
820	int i;
821	u32 cmd;
822
823	for (i = 4; i < 10; i++)
824		eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
825	/* 12 == Expansion ROM Address */
826	eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
827
828	eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
829		SAVED_BYTE(PCI_CACHE_LINE_SIZE));
830	eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
831		SAVED_BYTE(PCI_LATENCY_TIMER));
832
833	/* max latency, min grant, interrupt pin and line */
834	eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
835
836	/*
837	 * Restore PERR & SERR bits, some devices require it,
838	 * don't touch the other command bits
839	 */
840	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
841	if (edev->config_space[1] & PCI_COMMAND_PARITY)
842		cmd |= PCI_COMMAND_PARITY;
843	else
844		cmd &= ~PCI_COMMAND_PARITY;
845	if (edev->config_space[1] & PCI_COMMAND_SERR)
846		cmd |= PCI_COMMAND_SERR;
847	else
848		cmd &= ~PCI_COMMAND_SERR;
849	eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
850}
851
852/**
853 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
854 * @data: EEH device
855 * @flag: Unused
856 *
857 * Loads the PCI configuration space base address registers,
858 * the expansion ROM base address, the latency timer, and etc.
859 * from the saved values in the device node.
860 */
861static void *eeh_restore_one_device_bars(void *data, void *flag)
862{
863	struct eeh_dev *edev = (struct eeh_dev *)data;
864	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
865
866	/* Do special restore for bridges */
867	if (edev->mode & EEH_DEV_BRIDGE)
868		eeh_restore_bridge_bars(edev);
869	else
870		eeh_restore_device_bars(edev);
871
872	if (eeh_ops->restore_config && pdn)
873		eeh_ops->restore_config(pdn);
874
875	return NULL;
876}
877
878/**
879 * eeh_pe_restore_bars - Restore the PCI config space info
880 * @pe: EEH PE
881 *
882 * This routine performs a recursive walk to the children
883 * of this device as well.
884 */
885void eeh_pe_restore_bars(struct eeh_pe *pe)
886{
887	/*
888	 * We needn't take the EEH lock since eeh_pe_dev_traverse()
889	 * will take that.
890	 */
891	eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
892}
893
894/**
895 * eeh_pe_loc_get - Retrieve location code binding to the given PE
896 * @pe: EEH PE
897 *
898 * Retrieve the location code of the given PE. If the primary PE bus
899 * is root bus, we will grab location code from PHB device tree node
900 * or root port. Otherwise, the upstream bridge's device tree node
901 * of the primary PE bus will be checked for the location code.
902 */
903const char *eeh_pe_loc_get(struct eeh_pe *pe)
904{
905	struct pci_bus *bus = eeh_pe_bus_get(pe);
906	struct device_node *dn;
907	const char *loc = NULL;
908
909	while (bus) {
910		dn = pci_bus_to_OF_node(bus);
911		if (!dn) {
912			bus = bus->parent;
913			continue;
914		}
915
916		if (pci_is_root_bus(bus))
917			loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
918		else
919			loc = of_get_property(dn, "ibm,slot-location-code",
920					      NULL);
921
922		if (loc)
923			return loc;
924
925		bus = bus->parent;
926	}
927
928	return "N/A";
929}
930
931/**
932 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
933 * @pe: EEH PE
934 *
935 * Retrieve the PCI bus according to the given PE. Basically,
936 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
937 * primary PCI bus will be retrieved. The parent bus will be
938 * returned for BUS PE. However, we don't have associated PCI
939 * bus for DEVICE PE.
940 */
941struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
942{
943	struct eeh_dev *edev;
944	struct pci_dev *pdev;
945
946	if (pe->type & EEH_PE_PHB)
947		return pe->phb->bus;
948
949	/* The primary bus might be cached during probe time */
950	if (pe->state & EEH_PE_PRI_BUS)
951		return pe->bus;
952
953	/* Retrieve the parent PCI bus of first (top) PCI device */
954	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
955	pdev = eeh_dev_to_pci_dev(edev);
956	if (pdev)
957		return pdev->bus;
958
959	return NULL;
960}