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1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
22#include <linux/mman.h>
23#include <linux/mm.h>
24#include <linux/suspend.h>
25#include <linux/hrtimer.h>
26#ifdef CONFIG_PPC64
27#include <linux/time.h>
28#include <linux/hardirq.h>
29#endif
30#include <linux/kbuild.h>
31
32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
36#include <asm/cputable.h>
37#include <asm/thread_info.h>
38#include <asm/rtas.h>
39#include <asm/vdso_datapage.h>
40#include <asm/dbell.h>
41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
44#include <asm/cache.h>
45#include <asm/compat.h>
46#include <asm/mmu.h>
47#include <asm/hvcall.h>
48#include <asm/xics.h>
49#endif
50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
54#include <linux/kvm_host.h>
55#endif
56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
58#include <asm/kvm_ppc.h>
59#endif
60
61#ifdef CONFIG_PPC32
62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
65#endif
66
67#if defined(CONFIG_PPC_FSL_BOOK3E)
68#include "../mm/mmu_decl.h"
69#endif
70
71#ifdef CONFIG_PPC_8xx
72#include <asm/fixmap.h>
73#endif
74
75#define STACK_PT_REGS_OFFSET(sym, val) \
76 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
77
78int main(void)
79{
80 OFFSET(THREAD, task_struct, thread);
81 OFFSET(MM, task_struct, mm);
82 OFFSET(MMCONTEXTID, mm_struct, context.id);
83#ifdef CONFIG_PPC64
84 DEFINE(SIGSEGV, SIGSEGV);
85 DEFINE(NMI_MASK, NMI_MASK);
86 OFFSET(TASKTHREADPPR, task_struct, thread.ppr);
87#else
88 OFFSET(THREAD_INFO, task_struct, stack);
89 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
90 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
91#endif /* CONFIG_PPC64 */
92
93#ifdef CONFIG_LIVEPATCH
94 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
95#endif
96
97 OFFSET(KSP, thread_struct, ksp);
98 OFFSET(PT_REGS, thread_struct, regs);
99#ifdef CONFIG_BOOKE
100 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
101#endif
102 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
103 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
104 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
105 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
106 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
107#ifdef CONFIG_ALTIVEC
108 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
109 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
110 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
111 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
112 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
113 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
114#endif /* CONFIG_ALTIVEC */
115#ifdef CONFIG_VSX
116 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
117#endif /* CONFIG_VSX */
118#ifdef CONFIG_PPC64
119 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
120#else /* CONFIG_PPC64 */
121 OFFSET(PGDIR, thread_struct, pgdir);
122#ifdef CONFIG_SPE
123 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
124 OFFSET(THREAD_ACC, thread_struct, acc);
125 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
126 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
127#endif /* CONFIG_SPE */
128#endif /* CONFIG_PPC64 */
129#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
130 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
131#endif
132#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
133 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
134#endif
135#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
136 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
137#endif
138
139#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
140 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
141 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
142 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
143 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
144 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
145 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
146 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
147 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
148 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
149 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
150 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
151 /* Local pt_regs on stack for Transactional Memory funcs. */
152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
153 sizeof(struct pt_regs) + 16);
154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
155
156 OFFSET(TI_FLAGS, thread_info, flags);
157 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
158 OFFSET(TI_PREEMPT, thread_info, preempt_count);
159 OFFSET(TI_TASK, thread_info, task);
160 OFFSET(TI_CPU, thread_info, cpu);
161
162#ifdef CONFIG_PPC64
163 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
164 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
165 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
166 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
167 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
168 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
169 /* paca */
170 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
171 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
172 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
173 OFFSET(PACAKSAVE, paca_struct, kstack);
174 OFFSET(PACACURRENT, paca_struct, __current);
175 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
176 OFFSET(PACASTABRR, paca_struct, stab_rr);
177 OFFSET(PACAR1, paca_struct, saved_r1);
178 OFFSET(PACATOC, paca_struct, kernel_toc);
179 OFFSET(PACAKBASE, paca_struct, kernelbase);
180 OFFSET(PACAKMSR, paca_struct, kernel_msr);
181 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
182 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
183#ifdef CONFIG_PPC_BOOK3S
184 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
185#ifdef CONFIG_PPC_MM_SLICES
186 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
187 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
188 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
189 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
190#endif /* CONFIG_PPC_MM_SLICES */
191#endif
192
193#ifdef CONFIG_PPC_BOOK3E
194 OFFSET(PACAPGD, paca_struct, pgd);
195 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
196 OFFSET(PACA_EXGEN, paca_struct, exgen);
197 OFFSET(PACA_EXTLB, paca_struct, extlb);
198 OFFSET(PACA_EXMC, paca_struct, exmc);
199 OFFSET(PACA_EXCRIT, paca_struct, excrit);
200 OFFSET(PACA_EXDBG, paca_struct, exdbg);
201 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
202 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
203 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
204 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
205
206 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
207 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
208 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
209#endif /* CONFIG_PPC_BOOK3E */
210
211#ifdef CONFIG_PPC_BOOK3S_64
212 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
213 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
214 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
215#ifdef CONFIG_PPC_MM_SLICES
216 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
217#else
218 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
219#endif /* CONFIG_PPC_MM_SLICES */
220 OFFSET(PACA_EXGEN, paca_struct, exgen);
221 OFFSET(PACA_EXMC, paca_struct, exmc);
222 OFFSET(PACA_EXSLB, paca_struct, exslb);
223 OFFSET(PACA_EXNMI, paca_struct, exnmi);
224#ifdef CONFIG_PPC_PSERIES
225 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
226#endif
227 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
228 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
229 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
230 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
231 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
232#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
233 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
234#endif
235 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
236 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
237 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
238#endif /* CONFIG_PPC_BOOK3S_64 */
239 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
240#ifdef CONFIG_PPC_BOOK3S_64
241 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
242 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
243 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
244 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
245 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
246 OFFSET(PACA_EXRFI, paca_struct, exrfi);
247 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
248
249#endif
250 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
251 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
252 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
253 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
254 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
255 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
256 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
257 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
258 OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost);
259 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
260#else /* CONFIG_PPC64 */
261#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
262 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
263 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
264 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
265 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
266#endif
267#endif /* CONFIG_PPC64 */
268
269 /* RTAS */
270 OFFSET(RTASBASE, rtas_t, base);
271 OFFSET(RTASENTRY, rtas_t, entry);
272
273 /* Interrupt register frame */
274 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
275 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
276#ifdef CONFIG_PPC64
277 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
278 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
279 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
280#endif /* CONFIG_PPC64 */
281 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
282 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
283 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
284 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
285 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
286 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
287 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
288 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
289 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
290 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
291 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
292 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
293 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
294 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
295#ifndef CONFIG_PPC64
296 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
297#endif /* CONFIG_PPC64 */
298 /*
299 * Note: these symbols include _ because they overlap with special
300 * register names
301 */
302 STACK_PT_REGS_OFFSET(_NIP, nip);
303 STACK_PT_REGS_OFFSET(_MSR, msr);
304 STACK_PT_REGS_OFFSET(_CTR, ctr);
305 STACK_PT_REGS_OFFSET(_LINK, link);
306 STACK_PT_REGS_OFFSET(_CCR, ccr);
307 STACK_PT_REGS_OFFSET(_XER, xer);
308 STACK_PT_REGS_OFFSET(_DAR, dar);
309 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
310 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
311 STACK_PT_REGS_OFFSET(RESULT, result);
312 STACK_PT_REGS_OFFSET(_TRAP, trap);
313#ifndef CONFIG_PPC64
314 /*
315 * The PowerPC 400-class & Book-E processors have neither the DAR
316 * nor the DSISR SPRs. Hence, we overload them to hold the similar
317 * DEAR and ESR SPRs for such processors. For critical interrupts
318 * we use them to hold SRR0 and SRR1.
319 */
320 STACK_PT_REGS_OFFSET(_DEAR, dar);
321 STACK_PT_REGS_OFFSET(_ESR, dsisr);
322#else /* CONFIG_PPC64 */
323 STACK_PT_REGS_OFFSET(SOFTE, softe);
324
325 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
326 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
327 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
328#endif /* CONFIG_PPC64 */
329
330#if defined(CONFIG_PPC32)
331#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
332 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
333 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
334 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
335 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
336 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
337 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
338 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
339 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
340 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
341 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
342 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
343 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
344 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
345 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
346 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
347 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
348#endif
349#endif
350
351#ifndef CONFIG_PPC64
352 OFFSET(MM_PGD, mm_struct, pgd);
353#endif /* ! CONFIG_PPC64 */
354
355 /* About the CPU features table */
356 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
357 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
358 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
359
360 OFFSET(pbe_address, pbe, address);
361 OFFSET(pbe_orig_address, pbe, orig_address);
362 OFFSET(pbe_next, pbe, next);
363
364#ifndef CONFIG_PPC64
365 DEFINE(TASK_SIZE, TASK_SIZE);
366 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
367#endif /* ! CONFIG_PPC64 */
368
369 /* datapage offsets for use by vdso */
370 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
371 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
372 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
373 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
374 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
375 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
376 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
377 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
378 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
379 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
380 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
381 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
382 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
383 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
384 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
385#ifdef CONFIG_PPC64
386 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
387 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
388 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
389 OFFSET(TVAL32_TV_SEC, compat_timeval, tv_sec);
390 OFFSET(TVAL32_TV_USEC, compat_timeval, tv_usec);
391 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
392 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
393 OFFSET(TSPC32_TV_SEC, compat_timespec, tv_sec);
394 OFFSET(TSPC32_TV_NSEC, compat_timespec, tv_nsec);
395#else
396 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
397 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
398 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
399 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
400#endif
401 /* timeval/timezone offsets for use by vdso */
402 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
403 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
404
405 /* Other bits used by the vdso */
406 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
407 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
408 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
409 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
410 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
411 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
412
413#ifdef CONFIG_BUG
414 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
415#endif
416
417#ifdef CONFIG_PPC_BOOK3S_64
418 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
419#else
420 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
421#endif
422 DEFINE(PTE_SIZE, sizeof(pte_t));
423
424#ifdef CONFIG_KVM
425 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
426 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
427 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
428 OFFSET(VCPU_GPRS, kvm_vcpu, arch.gpr);
429 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
430 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
431#ifdef CONFIG_ALTIVEC
432 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
433#endif
434 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
435 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
436 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
437#ifdef CONFIG_PPC_BOOK3S
438 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
439#endif
440 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
441 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
442#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
443 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
444 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
445 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
446 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
447 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
448 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
449 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
450#endif
451#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
452 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
453 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
454 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
455 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
456 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
457 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
458 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
459 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
460 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
461 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
462 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
463#endif
464 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
465 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
466 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
467 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
468 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
469 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
470 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
471 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
472 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
473 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
474#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
475 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
476#endif
477
478 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
479 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
480 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
481 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
482 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
483 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
484
485 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
486 OFFSET(KVM_LPID, kvm, arch.lpid);
487
488 /* book3s */
489#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
490 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
491 OFFSET(KVM_SDR1, kvm, arch.sdr1);
492 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
493 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
494 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
495 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
496 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
497 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
498 OFFSET(KVM_RADIX, kvm, arch.radix);
499 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
500 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
501 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
502 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
503 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
504 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
505 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
506 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
507#endif
508#ifdef CONFIG_PPC_BOOK3S
509 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
510 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
511 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
512 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
513 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
514 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
515 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
516 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
517 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
518 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
519 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
520 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
521 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
522 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
523 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
524 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
525 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
526 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
527 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
528 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
529 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
530 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
531 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
532 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
533 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
534 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
535 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
536 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
537 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
538 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
539 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
540 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
541 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
542 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
543 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
544 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
545 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
546 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
547 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
548 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
549 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
550 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
551 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
552 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
553 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
554 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
555 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
556 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
557 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
558 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
559 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
560 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
561 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
562 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
563 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
564 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
565 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
566 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
567 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
568 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
569 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
570 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
571 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
572 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
573#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
574 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
575 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
576 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
577 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
578 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
579 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
580 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
581 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
582 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
583 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
584 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
585 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
586 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
587 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
588 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
589 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
590#endif
591
592#ifdef CONFIG_PPC_BOOK3S_64
593#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
594 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
595# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
596#else
597# define SVCPU_FIELD(x, f)
598#endif
599# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
600#else /* 32-bit */
601# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
602# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
603#endif
604
605 SVCPU_FIELD(SVCPU_CR, cr);
606 SVCPU_FIELD(SVCPU_XER, xer);
607 SVCPU_FIELD(SVCPU_CTR, ctr);
608 SVCPU_FIELD(SVCPU_LR, lr);
609 SVCPU_FIELD(SVCPU_PC, pc);
610 SVCPU_FIELD(SVCPU_R0, gpr[0]);
611 SVCPU_FIELD(SVCPU_R1, gpr[1]);
612 SVCPU_FIELD(SVCPU_R2, gpr[2]);
613 SVCPU_FIELD(SVCPU_R3, gpr[3]);
614 SVCPU_FIELD(SVCPU_R4, gpr[4]);
615 SVCPU_FIELD(SVCPU_R5, gpr[5]);
616 SVCPU_FIELD(SVCPU_R6, gpr[6]);
617 SVCPU_FIELD(SVCPU_R7, gpr[7]);
618 SVCPU_FIELD(SVCPU_R8, gpr[8]);
619 SVCPU_FIELD(SVCPU_R9, gpr[9]);
620 SVCPU_FIELD(SVCPU_R10, gpr[10]);
621 SVCPU_FIELD(SVCPU_R11, gpr[11]);
622 SVCPU_FIELD(SVCPU_R12, gpr[12]);
623 SVCPU_FIELD(SVCPU_R13, gpr[13]);
624 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
625 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
626 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
627 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
628#ifdef CONFIG_PPC_BOOK3S_32
629 SVCPU_FIELD(SVCPU_SR, sr);
630#endif
631#ifdef CONFIG_PPC64
632 SVCPU_FIELD(SVCPU_SLB, slb);
633 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
634 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
635#endif
636
637 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
638 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
639 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
640 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
641 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
642 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
643 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
644 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
645 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
646 HSTATE_FIELD(HSTATE_NAPPING, napping);
647
648#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
649 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
650 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
651 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
652 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
653 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
654 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
655 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
656 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
657 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
658 HSTATE_FIELD(HSTATE_PTID, ptid);
659 HSTATE_FIELD(HSTATE_TID, tid);
660 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
661 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
662 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
663 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
664 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
665 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
666 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
667 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
668 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
669 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
670 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
671 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
672 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
673 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
674 HSTATE_FIELD(HSTATE_PURR, host_purr);
675 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
676 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
677 HSTATE_FIELD(HSTATE_DABR, dabr);
678 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
679 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
680 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
681 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
682 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
683 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
684 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
685 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
686 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
687 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
688#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
689
690#ifdef CONFIG_PPC_BOOK3S_64
691 HSTATE_FIELD(HSTATE_CFAR, cfar);
692 HSTATE_FIELD(HSTATE_PPR, ppr);
693 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
694#endif /* CONFIG_PPC_BOOK3S_64 */
695
696#else /* CONFIG_PPC_BOOK3S */
697 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
698 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
699 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
700 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
701 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
702 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
703 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
704 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
705 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
706 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
707#endif /* CONFIG_PPC_BOOK3S */
708#endif /* CONFIG_KVM */
709
710#ifdef CONFIG_KVM_GUEST
711 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
712 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
713 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
714 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
715 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
716 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
717 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
718#endif
719
720#ifdef CONFIG_44x
721 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
722 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
723#endif
724#ifdef CONFIG_PPC_FSL_BOOK3E
725 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
726 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
727 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
728 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
729 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
730 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
731#endif
732
733#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
734 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
735 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
736 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
737 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
738#endif
739
740#ifdef CONFIG_KVM_BOOKE_HV
741 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
742 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
743#endif
744
745#ifdef CONFIG_KVM_XICS
746 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
747 arch.xive_saved_state));
748 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
749 arch.xive_cam_word));
750 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
751 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
752 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
753 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
754#endif
755
756#ifdef CONFIG_KVM_EXIT_TIMING
757 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
758 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
759 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
760 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
761#endif
762
763#ifdef CONFIG_PPC_POWERNV
764 OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr);
765 OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state);
766 OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask);
767 OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask);
768 OFFSET(PACA_SIBLING_PACA_PTRS, paca_struct, thread_sibling_pacas);
769 OFFSET(PACA_REQ_PSSCR, paca_struct, requested_psscr);
770 OFFSET(PACA_DONT_STOP, paca_struct, dont_stop);
771#define STOP_SPR(x, f) OFFSET(x, paca_struct, stop_sprs.f)
772 STOP_SPR(STOP_PID, pid);
773 STOP_SPR(STOP_LDBAR, ldbar);
774 STOP_SPR(STOP_FSCR, fscr);
775 STOP_SPR(STOP_HFSCR, hfscr);
776 STOP_SPR(STOP_MMCR1, mmcr1);
777 STOP_SPR(STOP_MMCR2, mmcr2);
778 STOP_SPR(STOP_MMCRA, mmcra);
779#endif
780
781 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
782 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
783
784#ifdef CONFIG_PPC_8xx
785 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
786#endif
787
788 return 0;
789}
1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
22#include <linux/mman.h>
23#include <linux/mm.h>
24#include <linux/suspend.h>
25#include <linux/hrtimer.h>
26#ifdef CONFIG_PPC64
27#include <linux/time.h>
28#include <linux/hardirq.h>
29#endif
30#include <linux/kbuild.h>
31
32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
36#include <asm/cputable.h>
37#include <asm/thread_info.h>
38#include <asm/rtas.h>
39#include <asm/vdso_datapage.h>
40#include <asm/dbell.h>
41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
44#include <asm/cache.h>
45#include <asm/compat.h>
46#include <asm/mmu.h>
47#include <asm/hvcall.h>
48#include <asm/xics.h>
49#endif
50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
54#include <linux/kvm_host.h>
55#endif
56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
58#include <asm/kvm_ppc.h>
59#endif
60
61#ifdef CONFIG_PPC32
62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
65#endif
66
67#if defined(CONFIG_PPC_FSL_BOOK3E)
68#include "../mm/mmu_decl.h"
69#endif
70
71#ifdef CONFIG_PPC_8xx
72#include <asm/fixmap.h>
73#endif
74
75int main(void)
76{
77 DEFINE(THREAD, offsetof(struct task_struct, thread));
78 DEFINE(MM, offsetof(struct task_struct, mm));
79 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
80#ifdef CONFIG_PPC64
81 DEFINE(SIGSEGV, SIGSEGV);
82 DEFINE(NMI_MASK, NMI_MASK);
83 DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr));
84#else
85 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
86 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
87 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
88#endif /* CONFIG_PPC64 */
89
90#ifdef CONFIG_LIVEPATCH
91 DEFINE(TI_livepatch_sp, offsetof(struct thread_info, livepatch_sp));
92#endif
93
94 DEFINE(KSP, offsetof(struct thread_struct, ksp));
95 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
96#ifdef CONFIG_BOOKE
97 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
98#endif
99 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
100 DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fp_state));
101 DEFINE(THREAD_FPSAVEAREA, offsetof(struct thread_struct, fp_save_area));
102 DEFINE(FPSTATE_FPSCR, offsetof(struct thread_fp_state, fpscr));
103 DEFINE(THREAD_LOAD_FP, offsetof(struct thread_struct, load_fp));
104#ifdef CONFIG_ALTIVEC
105 DEFINE(THREAD_VRSTATE, offsetof(struct thread_struct, vr_state));
106 DEFINE(THREAD_VRSAVEAREA, offsetof(struct thread_struct, vr_save_area));
107 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
108 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
109 DEFINE(VRSTATE_VSCR, offsetof(struct thread_vr_state, vscr));
110 DEFINE(THREAD_LOAD_VEC, offsetof(struct thread_struct, load_vec));
111#endif /* CONFIG_ALTIVEC */
112#ifdef CONFIG_VSX
113 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr));
114#endif /* CONFIG_VSX */
115#ifdef CONFIG_PPC64
116 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
117#else /* CONFIG_PPC64 */
118 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
119#ifdef CONFIG_SPE
120 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
121 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
122 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr));
123 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
124#endif /* CONFIG_SPE */
125#endif /* CONFIG_PPC64 */
126#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
127 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
128#endif
129#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
130 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
131#endif
132#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
133 DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu));
134#endif
135
136#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
137 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
138 DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
139 DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
140 DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
141 DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
142 DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
143 DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
144 DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
145 DEFINE(THREAD_CKVRSTATE, offsetof(struct thread_struct,
146 ckvr_state));
147 DEFINE(THREAD_CKVRSAVE, offsetof(struct thread_struct,
148 ckvrsave));
149 DEFINE(THREAD_CKFPSTATE, offsetof(struct thread_struct,
150 ckfp_state));
151 /* Local pt_regs on stack for Transactional Memory funcs. */
152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
153 sizeof(struct pt_regs) + 16);
154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
155
156 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
157 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
158 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
159 DEFINE(TI_TASK, offsetof(struct thread_info, task));
160 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
161
162#ifdef CONFIG_PPC64
163 DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));
164 DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));
165 DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));
166 DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));
167 DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));
168 DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));
169 /* paca */
170 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
171 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
172 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start));
173 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
174 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
175 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
176 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
177 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
178 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
179 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
180 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
181 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
182 DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened));
183#ifdef CONFIG_PPC_BOOK3S
184 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, mm_ctx_id));
185#ifdef CONFIG_PPC_MM_SLICES
186 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
187 mm_ctx_low_slices_psize));
188 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
189 mm_ctx_high_slices_psize));
190 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
191#endif /* CONFIG_PPC_MM_SLICES */
192#endif
193
194#ifdef CONFIG_PPC_BOOK3E
195 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
196 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
197 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
198 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
199 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
200 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
201 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
202 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
203 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
204 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
205 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
206
207 DEFINE(TCD_ESEL_NEXT,
208 offsetof(struct tlb_core_data, esel_next));
209 DEFINE(TCD_ESEL_MAX,
210 offsetof(struct tlb_core_data, esel_max));
211 DEFINE(TCD_ESEL_FIRST,
212 offsetof(struct tlb_core_data, esel_first));
213#endif /* CONFIG_PPC_BOOK3E */
214
215#ifdef CONFIG_PPC_STD_MMU_64
216 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
217 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
218 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
219#ifdef CONFIG_PPC_MM_SLICES
220 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
221#else
222 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, mm_ctx_sllp));
223#endif /* CONFIG_PPC_MM_SLICES */
224 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
225 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
226 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
227 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
228 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
229 DEFINE(SLBSHADOW_STACKVSID,
230 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
231 DEFINE(SLBSHADOW_STACKESID,
232 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid));
233 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
234 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use));
235 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx));
236 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
237 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
238#endif /* CONFIG_PPC_STD_MMU_64 */
239 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
240#ifdef CONFIG_PPC_BOOK3S_64
241 DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp));
242 DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce));
243#endif
244 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
245 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
246 DEFINE(PACA_DSCR_DEFAULT, offsetof(struct paca_struct, dscr_default));
247 DEFINE(ACCOUNT_STARTTIME,
248 offsetof(struct paca_struct, accounting.starttime));
249 DEFINE(ACCOUNT_STARTTIME_USER,
250 offsetof(struct paca_struct, accounting.starttime_user));
251 DEFINE(ACCOUNT_USER_TIME,
252 offsetof(struct paca_struct, accounting.user_time));
253 DEFINE(ACCOUNT_SYSTEM_TIME,
254 offsetof(struct paca_struct, accounting.system_time));
255 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
256 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
257 DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
258#else /* CONFIG_PPC64 */
259#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
260 DEFINE(ACCOUNT_STARTTIME,
261 offsetof(struct thread_info, accounting.starttime));
262 DEFINE(ACCOUNT_STARTTIME_USER,
263 offsetof(struct thread_info, accounting.starttime_user));
264 DEFINE(ACCOUNT_USER_TIME,
265 offsetof(struct thread_info, accounting.user_time));
266 DEFINE(ACCOUNT_SYSTEM_TIME,
267 offsetof(struct thread_info, accounting.system_time));
268#endif
269#endif /* CONFIG_PPC64 */
270
271 /* RTAS */
272 DEFINE(RTASBASE, offsetof(struct rtas_t, base));
273 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
274
275 /* Interrupt register frame */
276 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
277 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
278#ifdef CONFIG_PPC64
279 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
280 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
281 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
282#endif /* CONFIG_PPC64 */
283 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0]));
284 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1]));
285 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2]));
286 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3]));
287 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4]));
288 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5]));
289 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6]));
290 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7]));
291 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8]));
292 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9]));
293 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10]));
294 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11]));
295 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12]));
296 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13]));
297#ifndef CONFIG_PPC64
298 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14]));
299#endif /* CONFIG_PPC64 */
300 /*
301 * Note: these symbols include _ because they overlap with special
302 * register names
303 */
304 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip));
305 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr));
306 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr));
307 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link));
308 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr));
309 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
310 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
311 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
312 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3));
313 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result));
314 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap));
315#ifndef CONFIG_PPC64
316 /*
317 * The PowerPC 400-class & Book-E processors have neither the DAR
318 * nor the DSISR SPRs. Hence, we overload them to hold the similar
319 * DEAR and ESR SPRs for such processors. For critical interrupts
320 * we use them to hold SRR0 and SRR1.
321 */
322 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
323 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
324#else /* CONFIG_PPC64 */
325 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe));
326
327 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
328 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
329 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
330#endif /* CONFIG_PPC64 */
331
332#if defined(CONFIG_PPC32)
333#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
334 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
335 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
336 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
337 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
338 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
339 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
340 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
341 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
342 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
343 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
344 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
345 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
346 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
347 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
348 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
349 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
350#endif
351#endif
352
353#ifndef CONFIG_PPC64
354 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd));
355#endif /* ! CONFIG_PPC64 */
356
357 /* About the CPU features table */
358 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
359 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
360 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
361
362 DEFINE(pbe_address, offsetof(struct pbe, address));
363 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
364 DEFINE(pbe_next, offsetof(struct pbe, next));
365
366#ifndef CONFIG_PPC64
367 DEFINE(TASK_SIZE, TASK_SIZE);
368 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
369#endif /* ! CONFIG_PPC64 */
370
371 /* datapage offsets for use by vdso */
372 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp));
373 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec));
374 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs));
375 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count));
376 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest));
377 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
378 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32));
379 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
380 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
381 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
382 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
383 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
384 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
385 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
386 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size));
387#ifdef CONFIG_PPC64
388 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64));
389 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec));
390 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec));
391 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec));
392 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec));
393 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec));
394 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec));
395 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec));
396 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec));
397#else
398 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec));
399 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec));
400 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec));
401 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec));
402#endif
403 /* timeval/timezone offsets for use by vdso */
404 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
405 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
406
407 /* Other bits used by the vdso */
408 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
409 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
410 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
411 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
412
413#ifdef CONFIG_BUG
414 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
415#endif
416
417#ifdef MAX_PGD_TABLE_SIZE
418 DEFINE(PGD_TABLE_SIZE, MAX_PGD_TABLE_SIZE);
419#else
420 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
421#endif
422 DEFINE(PTE_SIZE, sizeof(pte_t));
423
424#ifdef CONFIG_KVM
425 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack));
426 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
427 DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
428 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
429 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
430 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr));
431#ifdef CONFIG_ALTIVEC
432 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr));
433#endif
434 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
435 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
436 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
437#ifdef CONFIG_PPC_BOOK3S
438 DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar));
439#endif
440 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
441 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
442#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
443 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr));
444 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0));
445 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1));
446 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0));
447 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1));
448 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
449 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
450#endif
451#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
452 DEFINE(VCPU_TB_RMENTRY, offsetof(struct kvm_vcpu, arch.rm_entry));
453 DEFINE(VCPU_TB_RMINTR, offsetof(struct kvm_vcpu, arch.rm_intr));
454 DEFINE(VCPU_TB_RMEXIT, offsetof(struct kvm_vcpu, arch.rm_exit));
455 DEFINE(VCPU_TB_GUEST, offsetof(struct kvm_vcpu, arch.guest_time));
456 DEFINE(VCPU_TB_CEDE, offsetof(struct kvm_vcpu, arch.cede_time));
457 DEFINE(VCPU_CUR_ACTIVITY, offsetof(struct kvm_vcpu, arch.cur_activity));
458 DEFINE(VCPU_ACTIVITY_START, offsetof(struct kvm_vcpu, arch.cur_tb_start));
459 DEFINE(TAS_SEQCOUNT, offsetof(struct kvmhv_tb_accumulator, seqcount));
460 DEFINE(TAS_TOTAL, offsetof(struct kvmhv_tb_accumulator, tb_total));
461 DEFINE(TAS_MIN, offsetof(struct kvmhv_tb_accumulator, tb_min));
462 DEFINE(TAS_MAX, offsetof(struct kvmhv_tb_accumulator, tb_max));
463#endif
464 DEFINE(VCPU_SHARED_SPRG3, offsetof(struct kvm_vcpu_arch_shared, sprg3));
465 DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4));
466 DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5));
467 DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6));
468 DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7));
469 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
470 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
471 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
472 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
473 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
474#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
475 DEFINE(VCPU_SHAREDBE, offsetof(struct kvm_vcpu, arch.shared_big_endian));
476#endif
477
478 DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0));
479 DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1));
480 DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2));
481 DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3));
482 DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4));
483 DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6));
484
485 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
486 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
487
488 /* book3s */
489#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
490 DEFINE(KVM_TLB_SETS, offsetof(struct kvm, arch.tlb_sets));
491 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
492 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
493 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
494 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1));
495 DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits));
496 DEFINE(KVM_ENABLED_HCALLS, offsetof(struct kvm, arch.enabled_hcalls));
497 DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v));
498 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
499 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
500 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
501 DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
502 DEFINE(VCPU_HEIR, offsetof(struct kvm_vcpu, arch.emul_inst));
503 DEFINE(VCPU_CPU, offsetof(struct kvm_vcpu, cpu));
504 DEFINE(VCPU_THREAD_CPU, offsetof(struct kvm_vcpu, arch.thread_cpu));
505#endif
506#ifdef CONFIG_PPC_BOOK3S
507 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
508 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
509 DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic));
510 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
511 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
512 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
513 DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr));
514 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
515 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
516 DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx));
517 DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr));
518 DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx));
519 DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr));
520 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
521 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
522 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
523 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions));
524 DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded));
525 DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded));
526 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
527 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
528 DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc));
529 DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar));
530 DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar));
531 DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier));
532 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
533 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
534 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
535 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
536 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
537 DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr));
538 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
539 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
540 DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
541 DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
542 DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
543 DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
544 DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
545 DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
546 DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
547 DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr));
548 DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr));
549 DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr));
550 DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop));
551 DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort));
552 DEFINE(VCPU_TID, offsetof(struct kvm_vcpu, arch.tid));
553 DEFINE(VCPU_PSSCR, offsetof(struct kvm_vcpu, arch.psscr));
554 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_map));
555 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
556 DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads));
557 DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm));
558 DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset));
559 DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr));
560 DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr));
561 DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes));
562 DEFINE(VCORE_VTB, offsetof(struct kvmppc_vcore, vtb));
563 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
564 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
565 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
566#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
567 DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
568 DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
569 DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
570 DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
571 DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
572 DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
573 DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
574 DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
575 DEFINE(VCPU_XER_TM, offsetof(struct kvm_vcpu, arch.xer_tm));
576 DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
577 DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
578 DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
579 DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
580 DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
581 DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
582#endif
583
584#ifdef CONFIG_PPC_BOOK3S_64
585#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
586 DEFINE(PACA_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
587# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
588#else
589# define SVCPU_FIELD(x, f)
590#endif
591# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
592#else /* 32-bit */
593# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
594# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
595#endif
596
597 SVCPU_FIELD(SVCPU_CR, cr);
598 SVCPU_FIELD(SVCPU_XER, xer);
599 SVCPU_FIELD(SVCPU_CTR, ctr);
600 SVCPU_FIELD(SVCPU_LR, lr);
601 SVCPU_FIELD(SVCPU_PC, pc);
602 SVCPU_FIELD(SVCPU_R0, gpr[0]);
603 SVCPU_FIELD(SVCPU_R1, gpr[1]);
604 SVCPU_FIELD(SVCPU_R2, gpr[2]);
605 SVCPU_FIELD(SVCPU_R3, gpr[3]);
606 SVCPU_FIELD(SVCPU_R4, gpr[4]);
607 SVCPU_FIELD(SVCPU_R5, gpr[5]);
608 SVCPU_FIELD(SVCPU_R6, gpr[6]);
609 SVCPU_FIELD(SVCPU_R7, gpr[7]);
610 SVCPU_FIELD(SVCPU_R8, gpr[8]);
611 SVCPU_FIELD(SVCPU_R9, gpr[9]);
612 SVCPU_FIELD(SVCPU_R10, gpr[10]);
613 SVCPU_FIELD(SVCPU_R11, gpr[11]);
614 SVCPU_FIELD(SVCPU_R12, gpr[12]);
615 SVCPU_FIELD(SVCPU_R13, gpr[13]);
616 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
617 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
618 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
619 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
620#ifdef CONFIG_PPC_BOOK3S_32
621 SVCPU_FIELD(SVCPU_SR, sr);
622#endif
623#ifdef CONFIG_PPC64
624 SVCPU_FIELD(SVCPU_SLB, slb);
625 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
626 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
627#endif
628
629 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
630 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
631 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
632 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
633 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
634 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
635 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
636 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
637 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
638 HSTATE_FIELD(HSTATE_NAPPING, napping);
639
640#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
641 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
642 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
643 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
644 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
645 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
646 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
647 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
648 HSTATE_FIELD(HSTATE_PTID, ptid);
649 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
650 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
651 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
652 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
653 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
654 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
655 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
656 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
657 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
658 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
659 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
660 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
661 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
662 HSTATE_FIELD(HSTATE_PURR, host_purr);
663 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
664 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
665 HSTATE_FIELD(HSTATE_DABR, dabr);
666 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
667 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
668 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
669 DEFINE(KVM_SPLIT_RPR, offsetof(struct kvm_split_mode, rpr));
670 DEFINE(KVM_SPLIT_PMMAR, offsetof(struct kvm_split_mode, pmmar));
671 DEFINE(KVM_SPLIT_LDBAR, offsetof(struct kvm_split_mode, ldbar));
672 DEFINE(KVM_SPLIT_DO_NAP, offsetof(struct kvm_split_mode, do_nap));
673 DEFINE(KVM_SPLIT_NAPPED, offsetof(struct kvm_split_mode, napped));
674#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
675
676#ifdef CONFIG_PPC_BOOK3S_64
677 HSTATE_FIELD(HSTATE_CFAR, cfar);
678 HSTATE_FIELD(HSTATE_PPR, ppr);
679 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
680#endif /* CONFIG_PPC_BOOK3S_64 */
681
682#else /* CONFIG_PPC_BOOK3S */
683 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
684 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
685 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
686 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
687 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
688 DEFINE(VCPU_SPRG9, offsetof(struct kvm_vcpu, arch.sprg9));
689 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
690 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
691 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
692 DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save));
693#endif /* CONFIG_PPC_BOOK3S */
694#endif /* CONFIG_KVM */
695
696#ifdef CONFIG_KVM_GUEST
697 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared,
698 scratch1));
699 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared,
700 scratch2));
701 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared,
702 scratch3));
703 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared,
704 int_pending));
705 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
706 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
707 critical));
708 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
709#endif
710
711#ifdef CONFIG_44x
712 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
713 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
714#endif
715#ifdef CONFIG_PPC_FSL_BOOK3E
716 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
717 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
718 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
719 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
720 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
721 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
722#endif
723
724#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
725 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0]));
726 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc));
727 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr));
728 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr));
729#endif
730
731#ifdef CONFIG_KVM_BOOKE_HV
732 DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4));
733 DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6));
734#endif
735
736#ifdef CONFIG_KVM_EXIT_TIMING
737 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
738 arch.timing_exit.tv32.tbu));
739 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu,
740 arch.timing_exit.tv32.tbl));
741 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
742 arch.timing_last_enter.tv32.tbu));
743 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
744 arch.timing_last_enter.tv32.tbl));
745#endif
746
747#ifdef CONFIG_PPC_POWERNV
748 DEFINE(PACA_CORE_IDLE_STATE_PTR,
749 offsetof(struct paca_struct, core_idle_state_ptr));
750 DEFINE(PACA_THREAD_IDLE_STATE,
751 offsetof(struct paca_struct, thread_idle_state));
752 DEFINE(PACA_THREAD_MASK,
753 offsetof(struct paca_struct, thread_mask));
754 DEFINE(PACA_SUBCORE_SIBLING_MASK,
755 offsetof(struct paca_struct, subcore_sibling_mask));
756#endif
757
758 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
759
760#ifdef CONFIG_PPC_8xx
761 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
762#endif
763
764 return 0;
765}