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1// SPDX-License-Identifier: GPL-2.0
2
3/ {
4 #address-cells = <1>;
5 #size-cells = <1>;
6
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 cpu@0 {
12 device_type = "cpu";
13 reg = <0>;
14 model = "ti,c64x+";
15 };
16 cpu@1 {
17 device_type = "cpu";
18 reg = <1>;
19 model = "ti,c64x+";
20 };
21 cpu@2 {
22 device_type = "cpu";
23 reg = <2>;
24 model = "ti,c64x+";
25 };
26 cpu@3 {
27 device_type = "cpu";
28 reg = <3>;
29 model = "ti,c64x+";
30 };
31 cpu@4 {
32 device_type = "cpu";
33 reg = <4>;
34 model = "ti,c64x+";
35 };
36 cpu@5 {
37 device_type = "cpu";
38 reg = <5>;
39 model = "ti,c64x+";
40 };
41 };
42
43 soc {
44 compatible = "simple-bus";
45 model = "tms320c6472";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 core_pic: interrupt-controller {
51 compatible = "ti,c64x+core-pic";
52 interrupt-controller;
53 #interrupt-cells = <1>;
54 };
55
56 megamod_pic: interrupt-controller@1800000 {
57 compatible = "ti,c64x+megamod-pic";
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 reg = <0x1800000 0x1000>;
61 interrupt-parent = <&core_pic>;
62 };
63
64 cache-controller@1840000 {
65 compatible = "ti,c64x+cache";
66 reg = <0x01840000 0x8400>;
67 };
68
69 timer0: timer@25e0000 {
70 compatible = "ti,c64x+timer64";
71 ti,core-mask = < 0x01 >;
72 reg = <0x25e0000 0x40>;
73 };
74
75 timer1: timer@25f0000 {
76 compatible = "ti,c64x+timer64";
77 ti,core-mask = < 0x02 >;
78 reg = <0x25f0000 0x40>;
79 };
80
81 timer2: timer@2600000 {
82 compatible = "ti,c64x+timer64";
83 ti,core-mask = < 0x04 >;
84 reg = <0x2600000 0x40>;
85 };
86
87 timer3: timer@2610000 {
88 compatible = "ti,c64x+timer64";
89 ti,core-mask = < 0x08 >;
90 reg = <0x2610000 0x40>;
91 };
92
93 timer4: timer@2620000 {
94 compatible = "ti,c64x+timer64";
95 ti,core-mask = < 0x10 >;
96 reg = <0x2620000 0x40>;
97 };
98
99 timer5: timer@2630000 {
100 compatible = "ti,c64x+timer64";
101 ti,core-mask = < 0x20 >;
102 reg = <0x2630000 0x40>;
103 };
104
105 clock-controller@29a0000 {
106 compatible = "ti,c6472-pll", "ti,c64x+pll";
107 reg = <0x029a0000 0x200>;
108 ti,c64x+pll-bypass-delay = <200>;
109 ti,c64x+pll-reset-delay = <12000>;
110 ti,c64x+pll-lock-delay = <80000>;
111 };
112
113 device-state-controller@2a80000 {
114 compatible = "ti,c64x+dscr";
115 reg = <0x02a80000 0x1000>;
116
117 ti,dscr-devstat = <0>;
118 ti,dscr-silicon-rev = <0x70c 16 0xff>;
119
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
121 0x704 5 6 0 0>;
122
123 ti,dscr-rmii-resets = <0x208 1
124 0x20c 1>;
125
126 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
127 0x40c 0x420 0xbea7
128 0x41c 0x420 0xbea7>;
129
130 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
131
132 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
133 };
134 };
135};
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 cpu@3 {
26 device_type = "cpu";
27 reg = <3>;
28 model = "ti,c64x+";
29 };
30 cpu@4 {
31 device_type = "cpu";
32 reg = <4>;
33 model = "ti,c64x+";
34 };
35 cpu@5 {
36 device_type = "cpu";
37 reg = <5>;
38 model = "ti,c64x+";
39 };
40 };
41
42 soc {
43 compatible = "simple-bus";
44 model = "tms320c6472";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 core_pic: interrupt-controller {
50 compatible = "ti,c64x+core-pic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 };
54
55 megamod_pic: interrupt-controller@1800000 {
56 compatible = "ti,c64x+megamod-pic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x1800000 0x1000>;
60 interrupt-parent = <&core_pic>;
61 };
62
63 cache-controller@1840000 {
64 compatible = "ti,c64x+cache";
65 reg = <0x01840000 0x8400>;
66 };
67
68 timer0: timer@25e0000 {
69 compatible = "ti,c64x+timer64";
70 ti,core-mask = < 0x01 >;
71 reg = <0x25e0000 0x40>;
72 };
73
74 timer1: timer@25f0000 {
75 compatible = "ti,c64x+timer64";
76 ti,core-mask = < 0x02 >;
77 reg = <0x25f0000 0x40>;
78 };
79
80 timer2: timer@2600000 {
81 compatible = "ti,c64x+timer64";
82 ti,core-mask = < 0x04 >;
83 reg = <0x2600000 0x40>;
84 };
85
86 timer3: timer@2610000 {
87 compatible = "ti,c64x+timer64";
88 ti,core-mask = < 0x08 >;
89 reg = <0x2610000 0x40>;
90 };
91
92 timer4: timer@2620000 {
93 compatible = "ti,c64x+timer64";
94 ti,core-mask = < 0x10 >;
95 reg = <0x2620000 0x40>;
96 };
97
98 timer5: timer@2630000 {
99 compatible = "ti,c64x+timer64";
100 ti,core-mask = < 0x20 >;
101 reg = <0x2630000 0x40>;
102 };
103
104 clock-controller@29a0000 {
105 compatible = "ti,c6472-pll", "ti,c64x+pll";
106 reg = <0x029a0000 0x200>;
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
110 };
111
112 device-state-controller@2a80000 {
113 compatible = "ti,c64x+dscr";
114 reg = <0x02a80000 0x1000>;
115
116 ti,dscr-devstat = <0>;
117 ti,dscr-silicon-rev = <0x70c 16 0xff>;
118
119 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
120 0x704 5 6 0 0>;
121
122 ti,dscr-rmii-resets = <0x208 1
123 0x20c 1>;
124
125 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
126 0x40c 0x420 0xbea7
127 0x41c 0x420 0xbea7>;
128
129 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
130
131 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
132 };
133 };
134};