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1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44#include "armv7-m.dtsi"
45#include <dt-bindings/clock/stm32fx-clock.h>
46#include <dt-bindings/mfd/stm32f7-rcc.h>
47
48/ {
49 clocks {
50 clk_hse: clk-hse {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
54 };
55
56 clk-lse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
60 };
61
62 clk-lsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32000>;
66 };
67
68 clk_i2s_ckin: clk-i2s-ckin {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <48000000>;
72 };
73 };
74
75 soc {
76 timer2: timer@40000000 {
77 compatible = "st,stm32-timer";
78 reg = <0x40000000 0x400>;
79 interrupts = <28>;
80 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
81 status = "disabled";
82 };
83
84 timers2: timers@40000000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 compatible = "st,stm32-timers";
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
90 clock-names = "int";
91 status = "disabled";
92
93 pwm {
94 compatible = "st,stm32-pwm";
95 status = "disabled";
96 };
97
98 timer@1 {
99 compatible = "st,stm32-timer-trigger";
100 reg = <1>;
101 status = "disabled";
102 };
103 };
104
105 timer3: timer@40000400 {
106 compatible = "st,stm32-timer";
107 reg = <0x40000400 0x400>;
108 interrupts = <29>;
109 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
110 status = "disabled";
111 };
112
113 timers3: timers@40000400 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "st,stm32-timers";
117 reg = <0x40000400 0x400>;
118 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
119 clock-names = "int";
120 status = "disabled";
121
122 pwm {
123 compatible = "st,stm32-pwm";
124 status = "disabled";
125 };
126
127 timer@2 {
128 compatible = "st,stm32-timer-trigger";
129 reg = <2>;
130 status = "disabled";
131 };
132 };
133
134 timer4: timer@40000800 {
135 compatible = "st,stm32-timer";
136 reg = <0x40000800 0x400>;
137 interrupts = <30>;
138 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
139 status = "disabled";
140 };
141
142 timers4: timers@40000800 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "st,stm32-timers";
146 reg = <0x40000800 0x400>;
147 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
148 clock-names = "int";
149 status = "disabled";
150
151 pwm {
152 compatible = "st,stm32-pwm";
153 status = "disabled";
154 };
155
156 timer@3 {
157 compatible = "st,stm32-timer-trigger";
158 reg = <3>;
159 status = "disabled";
160 };
161 };
162
163 timer5: timer@40000c00 {
164 compatible = "st,stm32-timer";
165 reg = <0x40000c00 0x400>;
166 interrupts = <50>;
167 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
168 };
169
170 timers5: timers@40000c00 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "st,stm32-timers";
174 reg = <0x40000C00 0x400>;
175 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
176 clock-names = "int";
177 status = "disabled";
178
179 pwm {
180 compatible = "st,stm32-pwm";
181 status = "disabled";
182 };
183
184 timer@4 {
185 compatible = "st,stm32-timer-trigger";
186 reg = <4>;
187 status = "disabled";
188 };
189 };
190
191 timer6: timer@40001000 {
192 compatible = "st,stm32-timer";
193 reg = <0x40001000 0x400>;
194 interrupts = <54>;
195 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
196 status = "disabled";
197 };
198
199 timers6: timers@40001000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "st,stm32-timers";
203 reg = <0x40001000 0x400>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
205 clock-names = "int";
206 status = "disabled";
207
208 timer@5 {
209 compatible = "st,stm32-timer-trigger";
210 reg = <5>;
211 status = "disabled";
212 };
213 };
214
215 timer7: timer@40001400 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001400 0x400>;
218 interrupts = <55>;
219 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
220 status = "disabled";
221 };
222
223 timers7: timers@40001400 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001400 0x400>;
228 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
229 clock-names = "int";
230 status = "disabled";
231
232 timer@6 {
233 compatible = "st,stm32-timer-trigger";
234 reg = <6>;
235 status = "disabled";
236 };
237 };
238
239 timers12: timers@40001800 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "st,stm32-timers";
243 reg = <0x40001800 0x400>;
244 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
245 clock-names = "int";
246 status = "disabled";
247
248 pwm {
249 compatible = "st,stm32-pwm";
250 status = "disabled";
251 };
252
253 timer@11 {
254 compatible = "st,stm32-timer-trigger";
255 reg = <11>;
256 status = "disabled";
257 };
258 };
259
260 timers13: timers@40001c00 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "st,stm32-timers";
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
266 clock-names = "int";
267 status = "disabled";
268
269 pwm {
270 compatible = "st,stm32-pwm";
271 status = "disabled";
272 };
273 };
274
275 timers14: timers@40002000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "st,stm32-timers";
279 reg = <0x40002000 0x400>;
280 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
281 clock-names = "int";
282 status = "disabled";
283
284 pwm {
285 compatible = "st,stm32-pwm";
286 status = "disabled";
287 };
288 };
289
290 rtc: rtc@40002800 {
291 compatible = "st,stm32-rtc";
292 reg = <0x40002800 0x400>;
293 clocks = <&rcc 1 CLK_RTC>;
294 clock-names = "ck_rtc";
295 assigned-clocks = <&rcc 1 CLK_RTC>;
296 assigned-clock-parents = <&rcc 1 CLK_LSE>;
297 interrupt-parent = <&exti>;
298 interrupts = <17 1>;
299 interrupt-names = "alarm";
300 st,syscfg = <&pwrcfg>;
301 status = "disabled";
302 };
303
304 usart2: serial@40004400 {
305 compatible = "st,stm32f7-uart";
306 reg = <0x40004400 0x400>;
307 interrupts = <38>;
308 clocks = <&rcc 1 CLK_USART2>;
309 status = "disabled";
310 };
311
312 usart3: serial@40004800 {
313 compatible = "st,stm32f7-uart";
314 reg = <0x40004800 0x400>;
315 interrupts = <39>;
316 clocks = <&rcc 1 CLK_USART3>;
317 status = "disabled";
318 };
319
320 usart4: serial@40004c00 {
321 compatible = "st,stm32f7-uart";
322 reg = <0x40004c00 0x400>;
323 interrupts = <52>;
324 clocks = <&rcc 1 CLK_UART4>;
325 status = "disabled";
326 };
327
328 usart5: serial@40005000 {
329 compatible = "st,stm32f7-uart";
330 reg = <0x40005000 0x400>;
331 interrupts = <53>;
332 clocks = <&rcc 1 CLK_UART5>;
333 status = "disabled";
334 };
335
336 i2c1: i2c@40005400 {
337 compatible = "st,stm32f7-i2c";
338 reg = <0x40005400 0x400>;
339 interrupts = <31>,
340 <32>;
341 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
342 clocks = <&rcc 1 CLK_I2C1>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 cec: cec@40006c00 {
349 compatible = "st,stm32-cec";
350 reg = <0x40006C00 0x400>;
351 interrupts = <94>;
352 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
353 clock-names = "cec", "hdmi-cec";
354 status = "disabled";
355 };
356
357 usart7: serial@40007800 {
358 compatible = "st,stm32f7-uart";
359 reg = <0x40007800 0x400>;
360 interrupts = <82>;
361 clocks = <&rcc 1 CLK_UART7>;
362 status = "disabled";
363 };
364
365 usart8: serial@40007c00 {
366 compatible = "st,stm32f7-uart";
367 reg = <0x40007c00 0x400>;
368 interrupts = <83>;
369 clocks = <&rcc 1 CLK_UART8>;
370 status = "disabled";
371 };
372
373 timers1: timers@40010000 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 compatible = "st,stm32-timers";
377 reg = <0x40010000 0x400>;
378 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
379 clock-names = "int";
380 status = "disabled";
381
382 pwm {
383 compatible = "st,stm32-pwm";
384 status = "disabled";
385 };
386
387 timer@0 {
388 compatible = "st,stm32-timer-trigger";
389 reg = <0>;
390 status = "disabled";
391 };
392 };
393
394 timers8: timers@40010400 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 compatible = "st,stm32-timers";
398 reg = <0x40010400 0x400>;
399 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
400 clock-names = "int";
401 status = "disabled";
402
403 pwm {
404 compatible = "st,stm32-pwm";
405 status = "disabled";
406 };
407
408 timer@7 {
409 compatible = "st,stm32-timer-trigger";
410 reg = <7>;
411 status = "disabled";
412 };
413 };
414
415 usart1: serial@40011000 {
416 compatible = "st,stm32f7-uart";
417 reg = <0x40011000 0x400>;
418 interrupts = <37>;
419 clocks = <&rcc 1 CLK_USART1>;
420 status = "disabled";
421 };
422
423 usart6: serial@40011400 {
424 compatible = "st,stm32f7-uart";
425 reg = <0x40011400 0x400>;
426 interrupts = <71>;
427 clocks = <&rcc 1 CLK_USART6>;
428 status = "disabled";
429 };
430
431 sdio2: sdio2@40011c00 {
432 compatible = "arm,pl180", "arm,primecell";
433 arm,primecell-periphid = <0x00880180>;
434 reg = <0x40011c00 0x400>;
435 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
436 clock-names = "apb_pclk";
437 interrupts = <103>;
438 max-frequency = <48000000>;
439 status = "disabled";
440 };
441
442 sdio1: sdio1@40012c00 {
443 compatible = "arm,pl180", "arm,primecell";
444 arm,primecell-periphid = <0x00880180>;
445 reg = <0x40012c00 0x400>;
446 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
447 clock-names = "apb_pclk";
448 interrupts = <49>;
449 max-frequency = <48000000>;
450 status = "disabled";
451 };
452
453 syscfg: system-config@40013800 {
454 compatible = "syscon";
455 reg = <0x40013800 0x400>;
456 };
457
458 exti: interrupt-controller@40013c00 {
459 compatible = "st,stm32-exti";
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 reg = <0x40013C00 0x400>;
463 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
464 };
465
466 timers9: timers@40014000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "st,stm32-timers";
470 reg = <0x40014000 0x400>;
471 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
472 clock-names = "int";
473 status = "disabled";
474
475 pwm {
476 compatible = "st,stm32-pwm";
477 status = "disabled";
478 };
479
480 timer@8 {
481 compatible = "st,stm32-timer-trigger";
482 reg = <8>;
483 status = "disabled";
484 };
485 };
486
487 timers10: timers@40014400 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "st,stm32-timers";
491 reg = <0x40014400 0x400>;
492 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
493 clock-names = "int";
494 status = "disabled";
495
496 pwm {
497 compatible = "st,stm32-pwm";
498 status = "disabled";
499 };
500 };
501
502 timers11: timers@40014800 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "st,stm32-timers";
506 reg = <0x40014800 0x400>;
507 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
508 clock-names = "int";
509 status = "disabled";
510
511 pwm {
512 compatible = "st,stm32-pwm";
513 status = "disabled";
514 };
515 };
516
517 pwrcfg: power-config@40007000 {
518 compatible = "syscon";
519 reg = <0x40007000 0x400>;
520 };
521
522 crc: crc@40023000 {
523 compatible = "st,stm32f7-crc";
524 reg = <0x40023000 0x400>;
525 clocks = <&rcc 0 12>;
526 status = "disabled";
527 };
528
529 rcc: rcc@40023800 {
530 #reset-cells = <1>;
531 #clock-cells = <2>;
532 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
533 reg = <0x40023800 0x400>;
534 clocks = <&clk_hse>, <&clk_i2s_ckin>;
535 st,syscfg = <&pwrcfg>;
536 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
537 assigned-clock-rates = <1000000>;
538 };
539
540 dma1: dma@40026000 {
541 compatible = "st,stm32-dma";
542 reg = <0x40026000 0x400>;
543 interrupts = <11>,
544 <12>,
545 <13>,
546 <14>,
547 <15>,
548 <16>,
549 <17>,
550 <47>;
551 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
552 #dma-cells = <4>;
553 status = "disabled";
554 };
555
556 dma2: dma@40026400 {
557 compatible = "st,stm32-dma";
558 reg = <0x40026400 0x400>;
559 interrupts = <56>,
560 <57>,
561 <58>,
562 <59>,
563 <60>,
564 <68>,
565 <69>,
566 <70>;
567 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
568 #dma-cells = <4>;
569 st,mem2mem;
570 status = "disabled";
571 };
572
573 usbotg_hs: usb@40040000 {
574 compatible = "st,stm32f7-hsotg";
575 reg = <0x40040000 0x40000>;
576 interrupts = <77>;
577 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
578 clock-names = "otg";
579 g-rx-fifo-size = <256>;
580 g-np-tx-fifo-size = <32>;
581 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
582 status = "disabled";
583 };
584
585 usbotg_fs: usb@50000000 {
586 compatible = "st,stm32f4x9-fsotg";
587 reg = <0x50000000 0x40000>;
588 interrupts = <67>;
589 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
590 clock-names = "otg";
591 status = "disabled";
592 };
593 };
594};
595
596&systick {
597 clocks = <&rcc 1 0>;
598 status = "okay";
599};
1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44#include "armv7-m.dtsi"
45#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
46
47/ {
48 clocks {
49 clk_hse: clk-hse {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <0>;
53 };
54 };
55
56 soc {
57 timer2: timer@40000000 {
58 compatible = "st,stm32-timer";
59 reg = <0x40000000 0x400>;
60 interrupts = <28>;
61 clocks = <&rcc 0 128>;
62 status = "disabled";
63 };
64
65 timer3: timer@40000400 {
66 compatible = "st,stm32-timer";
67 reg = <0x40000400 0x400>;
68 interrupts = <29>;
69 clocks = <&rcc 0 129>;
70 status = "disabled";
71 };
72
73 timer4: timer@40000800 {
74 compatible = "st,stm32-timer";
75 reg = <0x40000800 0x400>;
76 interrupts = <30>;
77 clocks = <&rcc 0 130>;
78 status = "disabled";
79 };
80
81 timer5: timer@40000c00 {
82 compatible = "st,stm32-timer";
83 reg = <0x40000c00 0x400>;
84 interrupts = <50>;
85 clocks = <&rcc 0 131>;
86 };
87
88 timer6: timer@40001000 {
89 compatible = "st,stm32-timer";
90 reg = <0x40001000 0x400>;
91 interrupts = <54>;
92 clocks = <&rcc 0 132>;
93 status = "disabled";
94 };
95
96 timer7: timer@40001400 {
97 compatible = "st,stm32-timer";
98 reg = <0x40001400 0x400>;
99 interrupts = <55>;
100 clocks = <&rcc 0 133>;
101 status = "disabled";
102 };
103
104 usart2: serial@40004400 {
105 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
106 reg = <0x40004400 0x400>;
107 interrupts = <38>;
108 clocks = <&rcc 0 145>;
109 status = "disabled";
110 };
111
112 usart3: serial@40004800 {
113 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
114 reg = <0x40004800 0x400>;
115 interrupts = <39>;
116 clocks = <&rcc 0 146>;
117 status = "disabled";
118 };
119
120 usart4: serial@40004c00 {
121 compatible = "st,stm32f7-uart";
122 reg = <0x40004c00 0x400>;
123 interrupts = <52>;
124 clocks = <&rcc 0 147>;
125 status = "disabled";
126 };
127
128 usart5: serial@40005000 {
129 compatible = "st,stm32f7-uart";
130 reg = <0x40005000 0x400>;
131 interrupts = <53>;
132 clocks = <&rcc 0 148>;
133 status = "disabled";
134 };
135
136 usart7: serial@40007800 {
137 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
138 reg = <0x40007800 0x400>;
139 interrupts = <82>;
140 clocks = <&rcc 0 158>;
141 status = "disabled";
142 };
143
144 usart8: serial@40007c00 {
145 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
146 reg = <0x40007c00 0x400>;
147 interrupts = <83>;
148 clocks = <&rcc 0 159>;
149 status = "disabled";
150 };
151
152 usart1: serial@40011000 {
153 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
154 reg = <0x40011000 0x400>;
155 interrupts = <37>;
156 clocks = <&rcc 0 164>;
157 status = "disabled";
158 };
159
160 usart6: serial@40011400 {
161 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
162 reg = <0x40011400 0x400>;
163 interrupts = <71>;
164 clocks = <&rcc 0 165>;
165 status = "disabled";
166 };
167
168 syscfg: system-config@40013800 {
169 compatible = "syscon";
170 reg = <0x40013800 0x400>;
171 };
172
173 exti: interrupt-controller@40013c00 {
174 compatible = "st,stm32-exti";
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 reg = <0x40013C00 0x400>;
178 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
179 };
180
181 pin-controller {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 compatible = "st,stm32f746-pinctrl";
185 ranges = <0 0x40020000 0x3000>;
186 interrupt-parent = <&exti>;
187 st,syscfg = <&syscfg 0x8>;
188 pins-are-numbered;
189
190 gpioa: gpio@40020000 {
191 gpio-controller;
192 #gpio-cells = <2>;
193 reg = <0x0 0x400>;
194 clocks = <&rcc 0 256>;
195 st,bank-name = "GPIOA";
196 };
197
198 gpiob: gpio@40020400 {
199 gpio-controller;
200 #gpio-cells = <2>;
201 reg = <0x400 0x400>;
202 clocks = <&rcc 0 257>;
203 st,bank-name = "GPIOB";
204 };
205
206 gpioc: gpio@40020800 {
207 gpio-controller;
208 #gpio-cells = <2>;
209 reg = <0x800 0x400>;
210 clocks = <&rcc 0 258>;
211 st,bank-name = "GPIOC";
212 };
213
214 gpiod: gpio@40020c00 {
215 gpio-controller;
216 #gpio-cells = <2>;
217 reg = <0xc00 0x400>;
218 clocks = <&rcc 0 259>;
219 st,bank-name = "GPIOD";
220 };
221
222 gpioe: gpio@40021000 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 reg = <0x1000 0x400>;
226 clocks = <&rcc 0 260>;
227 st,bank-name = "GPIOE";
228 };
229
230 gpiof: gpio@40021400 {
231 gpio-controller;
232 #gpio-cells = <2>;
233 reg = <0x1400 0x400>;
234 clocks = <&rcc 0 261>;
235 st,bank-name = "GPIOF";
236 };
237
238 gpiog: gpio@40021800 {
239 gpio-controller;
240 #gpio-cells = <2>;
241 reg = <0x1800 0x400>;
242 clocks = <&rcc 0 262>;
243 st,bank-name = "GPIOG";
244 };
245
246 gpioh: gpio@40021c00 {
247 gpio-controller;
248 #gpio-cells = <2>;
249 reg = <0x1c00 0x400>;
250 clocks = <&rcc 0 263>;
251 st,bank-name = "GPIOH";
252 };
253
254 gpioi: gpio@40022000 {
255 gpio-controller;
256 #gpio-cells = <2>;
257 reg = <0x2000 0x400>;
258 clocks = <&rcc 0 264>;
259 st,bank-name = "GPIOI";
260 };
261
262 gpioj: gpio@40022400 {
263 gpio-controller;
264 #gpio-cells = <2>;
265 reg = <0x2400 0x400>;
266 clocks = <&rcc 0 265>;
267 st,bank-name = "GPIOJ";
268 };
269
270 gpiok: gpio@40022800 {
271 gpio-controller;
272 #gpio-cells = <2>;
273 reg = <0x2800 0x400>;
274 clocks = <&rcc 0 266>;
275 st,bank-name = "GPIOK";
276 };
277
278 usart1_pins_a: usart1@0 {
279 pins1 {
280 pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
281 bias-disable;
282 drive-push-pull;
283 slew-rate = <0>;
284 };
285 pins2 {
286 pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
287 bias-disable;
288 };
289 };
290 };
291
292 rcc: rcc@40023800 {
293 #clock-cells = <2>;
294 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
295 reg = <0x40023800 0x400>;
296 clocks = <&clk_hse>;
297 };
298 };
299};
300
301&systick {
302 clocks = <&rcc 1 0>;
303 status = "okay";
304};